IS61WV2568EDBLL [ISSI]
256K x 8 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH ECC;
| 型号： | IS61WV2568EDBLL |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 256K x 8 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH ECC |
| 文件： | 总14页 (文件大小：657K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS61WV2568EDBLL
IS64WV2568EDBLL
256K x 8 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH ECC
DECEMBER 2011
DESCRIPTION
FEATURES
Theꢀ ISSIꢀ IS61/64WV2568EDBLLꢀ isꢀ aꢀ ꢀ high-speed,ꢀ
2,097,152-bitꢀstaticꢀRAMsꢀorganizedꢀasꢀ262,144ꢀwordsꢀbyꢀ
8ꢀbits.ꢀItꢀisꢀfabricatedꢀusingꢀISSI'sꢀhigh-performanceꢀCMOSꢀ
technology.ꢀThisꢀhighlyꢀreliableꢀprocessꢀcoupledꢀwithꢀinno-
vativeꢀcircuitꢀdesignꢀtechniques,ꢀyieldsꢀhigh-performanceꢀ
andꢀlowꢀpowerꢀconsumptionꢀdevices.
•ꢀ High-speedꢀaccessꢀtime:ꢀ8,ꢀ10ꢀns
•ꢀ LowꢀActiveꢀPower:ꢀ85ꢀmWꢀ(typical)
•ꢀ LowꢀStandbyꢀPower:ꢀ7ꢀmWꢀ(typical)ꢀ
CMOSꢀstandby
•ꢀ Singleꢀpowerꢀsupply
ꢀ —ꢀꢀVddꢀ2.4Vꢀtoꢀ3.6Vꢀ(10ꢀns)
—ꢀꢀVddꢀ3.3Vꢀ ꢀ10%ꢀ(8ꢀns)
WhenꢀCEꢀisꢀHIGHꢀ(deselected),ꢀtheꢀdeviceꢀassumesꢀaꢀ
standbyꢀmodeꢀatꢀwhichꢀtheꢀpowerꢀdissipationꢀcanꢀbeꢀre-
ducedꢀdownꢀwithꢀCMOSꢀinputꢀlevels.
•ꢀ Fullyꢀstaticꢀoperation:ꢀnoꢀclockꢀorꢀrefreshꢀꢀ
required
EasyꢀmemoryꢀexpansionꢀisꢀprovidedꢀbyꢀusingꢀChipꢀEnableꢀ
andꢀOutputꢀEnableꢀinputs,ꢀCEꢀandꢀOE.ꢀTheꢀactiveꢀLOWꢀ
WriteꢀEnableꢀ(WE)ꢀcontrolsꢀbothꢀwritingꢀandꢀreadingꢀofꢀ
theꢀmemory.ꢀꢀ
•ꢀ Threeꢀstateꢀoutputs
•ꢀ IndustrialꢀandꢀAutomotiveꢀtemperatureꢀsupport
•ꢀ Lead-freeꢀavailable
•ꢀ ErrorꢀDetectionꢀandꢀErrorꢀCorrection
TheꢀIS61/64WV2568EDBLLꢀisꢀꢀpackagedꢀinꢀtheꢀJEDECꢀ
standardꢀ44-pinꢀTSOP-II,ꢀ36-pinꢀSOJꢀandꢀ36-pinꢀMiniꢀBGAꢀ
(6mmꢀxꢀ8mm).
FUNCTIONAL BLOCK DIAGRAM
ECC Array
(256Kx4)
Memory Array
(256Kx8)
A0-A17
Decoder
8
4
8
8
12
I/O Data
Circuit
ECC
IO0-7
Column I/O
/CE
/OE
/WE
Control
Circuit
Copyrightꢀ©ꢀ2011ꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀꢀAllꢀrightsꢀreserved.ꢀꢀISSIꢀreservesꢀtheꢀrightꢀtoꢀmakeꢀchangesꢀtoꢀthisꢀspecificationꢀandꢀitsꢀproductsꢀatꢀanyꢀtimeꢀwithoutꢀ
notice.ꢀꢀꢀISSIꢀassumesꢀnoꢀliabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀtheꢀlat-
estꢀversionꢀofꢀthisꢀdeviceꢀspecificationꢀbeforeꢀrelyingꢀonꢀanyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.
IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀreason-
ablyꢀbeꢀexpectedꢀtoꢀcauseꢀfailureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsignificantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀapplicationsꢀ
unlessꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀreceivesꢀwrittenꢀassuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:
a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;
b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand
c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstancesꢀꢀ
Integrated Silicon Solution, Inc. — www.issi.comꢀ
1
Rev. A
11/08/2011
IS61/64WV2568EDBLL
PIN CONFIGURATION
44-Pin TSOP (Type II)
36 mini BGA
1
2
3
4
5
6
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
2
3
4
A17
A16
A15
A14
OE
I/O7
I/O6
GND
5
6
A
B
C
D
E
F
A0
A1
A2
NC
WE
NC
A3
A4
A5
A6
A7
A8
7
I/O4
I/O5
GND
I/O0
I/O1
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
V
DD
V
DD
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
V
DD
V
DD
GND
I/O2
I/O3
A14
I/O5
I/O4
A13
A12
A11
A10
NC
NC
NC
NC
I/O6
I/O7
A9
NC
CE
A17
A16
A12
OE
A15
A13
G
H
A10
A11
NC
NC
36-Pin SOJ
PIN DESCRIPTIONS
A0
A1
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A0-A17ꢀ ꢀ
AddressꢀInputs
2
A17
A16
A15
A14
OE
CEꢀꢀ
OEꢀꢀ
WEꢀꢀ
ꢀ
ꢀ
ꢀ
ChipꢀEnableꢀInput
A2
3
OutputꢀEnableꢀInputꢀ
WriteꢀEnableꢀInput
BidirectionalꢀPorts
Power
A3
4
A4
5
CE
I/O0
I/O1
6
I/O0-I/O7ꢀ
7
I/O7
I/O6
GND
Vddꢀ
GNDꢀ
NCꢀ
ꢀ
ꢀ
ꢀ
8
Ground
VDD
9
NoꢀConnection
GND
I/O2
I/O3
WE
A5
10
11
12
13
14
15
16
17
18
VDD
I/O5
I/O4
A13
A12
A11
A10
NC
A6
A7
A8
A9
NC
2ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
11/08/2011
IS61/64WV2568EDBLL
ABSOLUTE MAXIMUM RATINGS(1)
1
Symbol Parameter
Value
–0.5ꢀtoꢀVddꢀ+ꢀ0.5ꢀ
–0.3ꢀtoꢀ4.0ꢀ
–65ꢀtoꢀ+150ꢀ
1.0ꢀ
Unit
V
V
°C
W
Vtermꢀ
Vddꢀ
tstgꢀ
Ptꢀ
TerminalꢀVoltageꢀwithꢀRespectꢀtoꢀGNDꢀ
VddꢀRelatesꢀtoꢀGNDꢀ
StorageꢀTemperatureꢀ
ꢀ
ꢀ
ꢀ
2
PowerꢀDissipationꢀ
Notes:
1.ꢀꢀStressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀ
theꢀdevice.ꢀThisꢀisꢀaꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀ
aboveꢀthoseꢀindicatedꢀinꢀtheꢀoperationalꢀsectionsꢀofꢀthisꢀspecificationꢀisꢀnotꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀ
maximumꢀratingꢀconditionsꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀreliability.ꢀ
3
CAPACITANCE(1,2)
4
Symbol
Cinꢀ
Parameter
Conditions
Vinꢀ=ꢀ0Vꢀ
Max.
6ꢀ
Unit
pF
InputꢀCapacitanceꢀ
Input/OutputꢀCapacitanceꢀ
ꢀ
Ci/Oꢀ
VOutꢀ=ꢀ0Vꢀ
8ꢀ
pF
5
Notes:
1.ꢀꢀTestedꢀinitiallyꢀandꢀafterꢀanyꢀdesignꢀorꢀprocessꢀchangesꢀthatꢀmayꢀaffectꢀtheseꢀparameters.
2.ꢀ Testꢀconditions:ꢀTaꢀ=ꢀ25°C,ꢀfꢀ=ꢀ1ꢀMHz,ꢀVddꢀ=ꢀ3.3V.
6
ERROR DETECTION AND ERROR CORRECTION
•ꢀ IndependentꢀECCꢀwithꢀhammingꢀcodeꢀforꢀeachꢀbyte
•ꢀ Detectꢀandꢀcorrectꢀoneꢀbitꢀerrorꢀperꢀbyte
•ꢀ Betterꢀreliabilityꢀthanꢀparityꢀcodeꢀschemesꢀwhichꢀcanꢀonlyꢀdetectꢀanꢀerrorꢀbutꢀnotꢀcorrectꢀanꢀerror
•ꢀ BackwardꢀCompatible:ꢀDropꢀinꢀreplacementꢀtoꢀcurrentꢀinꢀindustryꢀstandardꢀdevicesꢀ(withoutꢀECC)
7
8
TRUTH TABLE
Mode
CE
WE OE I/O Operation VDD Current
9
NotꢀSelectedꢀ Hꢀ
(Power-down)ꢀ
Xꢀ
Xꢀ
High-Zꢀ
isb1,ꢀisb2
ꢀ
ꢀ
ꢀ
ꢀ
OutputꢀDisabledꢀLꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
High-Zꢀ
dOutꢀ
dinꢀ
iCC
iCC
iCC
10
11
12
Readꢀ
Writeꢀ
Lꢀ
Lꢀ
Xꢀ
OPERATING RANGE (VDD)1
Range
Ambient Temperature
IS61WV2568EDBLL
IS64WV2568EDBLL
VDD (8, 10nS)
2.4V-3.6Vꢀ(10ns)ꢀ
3.3Vꢀ ꢀ10%ꢀ(8ns)
VDD (10nS)
Industrialꢀ
–40°Cꢀtoꢀ+85°Cꢀ
ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢀ
ꢀ Automotiveꢀ(A1)ꢀ
Automotiveꢀ(A3)ꢀ –40°Cꢀtoꢀ+125°Cꢀ
–40°Cꢀtoꢀ+85°Cꢀ
—ꢀ
—ꢀ
2.4V-3.6V
2.4V-3.6V
Note:
1.ꢀꢀContactꢀSRAM@issi.comꢀforꢀ1.8Vꢀoption
Integrated Silicon Solution, Inc. — www.issi.comꢀ
3
Rev. A
11/08/2011
IS61/64WV2568EDBLL
DC ELECTRICAL CHARACTERISTICS (OverꢀOperatingꢀRange)
VDD = 3.3V + 10%
Symbol Parameter
Test Conditions
Vddꢀ=ꢀMin.,ꢀiOhꢀ=ꢀ–4.0ꢀmAꢀ
Min.
2.4ꢀ
—ꢀ
2ꢀ
–0.3ꢀ
–1ꢀ
Max.
—ꢀ
0.4ꢀ
Unit
V
V
V
V
VOhꢀ
VOlꢀ
Vihꢀ
Vilꢀ
OutputꢀHIGHꢀVoltageꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
OutputꢀLOWꢀVoltageꢀ
InputꢀHIGHꢀVoltageꢀ
InputꢀLOWꢀVoltage(1)ꢀ
InputꢀLeakageꢀ
Vddꢀ=ꢀMin.,ꢀiOlꢀ=ꢀ8.0ꢀmAꢀ
ꢀ
ꢀ
Vddꢀ+ꢀ0.3ꢀ
0.8ꢀ
ꢀ
iliꢀ
GNDꢀ≤ꢀVinꢀ≤ꢀVdd
1ꢀ
1ꢀ
µA
µA
ilOꢀ
OutputꢀLeakageꢀ
GNDꢀ≤ꢀVOutꢀ≤ꢀVdd,ꢀOutputsꢀDisabledꢀ
–1ꢀ
Note:
1.ꢀꢀVilꢀ(min.)ꢀ=ꢀ–0.3VꢀDC;ꢀVilꢀ(min.)ꢀ=ꢀ–2.0VꢀACꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
ꢀ
Vihꢀ(max.)ꢀ=ꢀVddꢀ+ꢀ0.3VꢀdC;ꢀVihꢀ(max.)ꢀ=ꢀVddꢀ+ꢀ2.0VꢀaCꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
DC ELECTRICAL CHARACTERISTICS (OverꢀOperatingꢀRange)
VDD = 2.4V-3.6Vꢀ
ꢀ
ꢀ
ꢀ
Symbol Parameter
Test Conditions
Min.
1.8ꢀ
—ꢀ
Max.
—ꢀ
Unit
V
VOhꢀ
VOlꢀ
Vihꢀ
Vilꢀ
iliꢀ
OutputꢀHIGHꢀVoltageꢀ
OutputꢀLOWꢀVoltageꢀ
InputꢀHIGHꢀVoltageꢀ
InputꢀLOWꢀVoltage(1)ꢀ
InputꢀLeakageꢀ
Vddꢀ=ꢀMin.,ꢀiOhꢀ=ꢀ–1.0ꢀmAꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Vddꢀ=ꢀMin.,ꢀiOlꢀ=ꢀ1.0ꢀmAꢀ
0.4ꢀ
V
ꢀ
ꢀ
2.0ꢀ
–0.3ꢀ
–1ꢀ
Vddꢀ+ꢀ0.3ꢀ
0.8ꢀ
V
V
ꢀ
GNDꢀ≤ꢀꢀVinꢀ≤ ꢀVdd
1ꢀ
µA
µA
ilOꢀ
OutputꢀLeakageꢀ
GNDꢀ≤ꢀꢀVOutꢀ≤ ꢀVdd,ꢀOutputsꢀDisabledꢀ
–1ꢀ
1ꢀ
Note:
1.ꢀꢀVilꢀ(min.)ꢀ=ꢀ–0.3VꢀDC;ꢀVilꢀ(min.)ꢀ=ꢀ–2.0VꢀACꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
ꢀ
Vihꢀ(max.)ꢀ=ꢀVddꢀ+ꢀ0.3VꢀdC;ꢀVihꢀ(max.)ꢀ=ꢀVddꢀ+ꢀ2.0VꢀaCꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
POWER SUPPLY CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
-8
-10
Min. Max.
-20
Min. Max.
Symbol Parameter
Test Conditions
Min. Max.
Unit
ꢀ iCCꢀ
ꢀ ꢀ
ꢀ ꢀ
VddꢀDynamicꢀOperatingꢀ Vddꢀ=ꢀMax.,ꢀꢀ
Com.ꢀ ꢀ —ꢀ ꢀ 40ꢀ
Ind.ꢀ ꢀ —ꢀ ꢀ 45ꢀ
Auto.ꢀ ꢀ —ꢀ ꢀ —ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
30ꢀ
35ꢀ
50ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
25ꢀ
30ꢀ
45ꢀ
mA
ꢀ
ꢀ
SupplyꢀCurrentꢀ
iOutꢀ=ꢀ0ꢀmA,ꢀfꢀ=ꢀfmaxꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢀ
typ.(2)
ꢀ
ꢀ
ꢀ 21ꢀ ꢀ
21
ꢀ iCC1ꢀ
ꢀ ꢀ
ꢀ ꢀ
Operatingꢀ
SupplyꢀCurrentꢀ
ꢀ
Vddꢀ=ꢀMax.,ꢀꢀ
iOutꢀ=ꢀ0ꢀmA,ꢀfꢀ=ꢀ0ꢀ
ꢀ
Com.ꢀ ꢀ —ꢀ ꢀ 20ꢀ
Ind.ꢀ ꢀ —ꢀ ꢀ 25ꢀ
Auto.ꢀ ꢀ —ꢀ ꢀ —ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
20ꢀ
25ꢀ
40ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
20ꢀ
25ꢀ
40ꢀ
mA
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ isb1ꢀ
ꢀ ꢀ
ꢀ ꢀ
TTLꢀStandbyꢀCurrentꢀ
(TTLꢀInputs)ꢀ
ꢀ
Vddꢀ=ꢀMax.,ꢀꢀ
Vinꢀ=ꢀVihꢀorꢀVilꢀ
CEꢀ≥ꢀVih,ꢀfꢀ=ꢀ0ꢀ
Com.ꢀ ꢀ —ꢀ ꢀ 10ꢀ
Ind.ꢀ ꢀ —ꢀ ꢀ 15ꢀ
Auto.ꢀ ꢀ —ꢀ ꢀ —ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
10ꢀ
15ꢀ
30ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
10ꢀ
15
30
mA
mA
ꢀ isb2ꢀ
ꢀ ꢀ
ꢀ ꢀ
CMOSꢀStandbyꢀ
Currentꢀ(CMOSꢀInputs)ꢀ CEꢀ≥ꢀVddꢀ–ꢀ0.2V,ꢀ
ꢀ
ꢀ
Vddꢀ=ꢀMax.,ꢀꢀ
Com.ꢀ ꢀ —ꢀ ꢀ 5ꢀ
Ind.ꢀ ꢀ —ꢀ ꢀ 6ꢀ
Auto.ꢀ ꢀ —ꢀ ꢀ —ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
5ꢀ
6ꢀ
15ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
5ꢀ
6
15
Vinꢀ≥ꢀVddꢀ–ꢀ0.2V,ꢀorꢀ
Vinꢀ≤ ꢀ0.2V,ꢀfꢀ=ꢀ0ꢀ
ꢀ ꢀ
typ.(2)
ꢀ
ꢀ
ꢀ 1.5ꢀ ꢀ
1.5
Note:
1.ꢀꢀAtꢀfꢀ=ꢀfmax,ꢀaddressꢀandꢀdataꢀinputsꢀareꢀcyclingꢀatꢀtheꢀmaximumꢀfrequency,ꢀfꢀ=ꢀ0ꢀmeansꢀnoꢀinputꢀlinesꢀchange.
2.ꢀTypicalꢀvaluesꢀareꢀmeasuredꢀatꢀVddꢀ=ꢀ3.0V,ꢀTaꢀ=ꢀ25oCꢀandꢀnotꢀ100%ꢀtested.
4ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
11/08/2011
IS61/64WV2568EDBLL
AC TEST CONDITIONS
Parameter
Unit
1
(2.4V-3.6V)
0.4VꢀtoꢀVdd-0.3V
1V/ꢀns
InputꢀPulseꢀLevelꢀ
ꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
ꢀ
ꢀ
InputꢀandꢀOutputꢀTimingꢀ
andꢀReferenceꢀLevelꢀ(VRef
Vdd/2
2
)
ꢀ
OutputꢀLoadꢀ
SeeꢀFiguresꢀ1ꢀandꢀ2
3
AC TEST LOADS
319 Ω
4
3.3V
ZO
= 50Ω
50Ω
1.5V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
5
353 Ω
5 pF
Including
jig and
scope
6
Figure 1.
Figure 2.
7
READ CYCLE SWITCHING CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
8
-8
-10
-20
Symbol
ꢀ ꢀ trC
ꢀ ꢀ taa
ꢀ ꢀ tOha
Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ꢀ
ReadꢀCycleꢀTimeꢀ
AddressꢀAccessꢀTimeꢀ
OutputꢀHoldꢀTimeꢀ
CEꢀAccessꢀTimeꢀ
OEꢀAccessꢀTimeꢀ
OEꢀtoꢀHigh-ZꢀOutputꢀ
OEꢀtoꢀLow-ZꢀOutputꢀ
CEꢀtoꢀHigh-ZꢀOutputꢀ
CEꢀtoꢀLow-ZꢀOutputꢀ
PowerꢀUpꢀTimeꢀ
8ꢀ ꢀ —ꢀ
—ꢀ ꢀ 8ꢀ
2.0ꢀ ꢀ —ꢀ
—ꢀ ꢀ 8ꢀ
—ꢀ ꢀ 4.5ꢀ
—ꢀ ꢀ 3ꢀ
0ꢀ ꢀ —ꢀ
0ꢀ ꢀ 3ꢀꢀ
3ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
—ꢀ ꢀ 8ꢀ
10ꢀ ꢀ —ꢀ
—ꢀ ꢀ 10ꢀ
2.0ꢀ ꢀ —ꢀ
—ꢀ ꢀ 10ꢀ
—ꢀ ꢀ 4.5ꢀ
—ꢀ ꢀ 4ꢀ
0ꢀ ꢀ —ꢀ
0ꢀ ꢀ 4ꢀ
20ꢀ ꢀ —ꢀ
—ꢀ ꢀ 20ꢀ
2.5ꢀ ꢀ —ꢀ
—ꢀ ꢀ 20ꢀ
—ꢀ ꢀ 8ꢀ
—ꢀ ꢀ 8ꢀ
0ꢀ ꢀ —ꢀ
0ꢀ ꢀ 8ꢀ
ꢀ
9
ꢀ
ꢀ
ꢀ ꢀ taCe
ꢀ
ꢀ ꢀ tdOe
ꢀ ꢀ thzOe(2)ꢀ
ꢀ ꢀ tlzOe(2)ꢀ
ꢀ ꢀ thzCe(2ꢀ
ꢀ ꢀ tlzCe(2)ꢀ
10
11
12
3ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
—ꢀ ꢀ 10ꢀ
3ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
—ꢀ ꢀ 20ꢀ
ꢀ ꢀ tPu
ꢀ ꢀ tPd
ꢀ
ꢀ
PowerꢀDownꢀTimeꢀ
Notes:ꢀ
1.ꢀ TestꢀconditionsꢀandꢀoutputꢀloadingꢀconditionsꢀareꢀspecifiedꢀinꢀtheꢀACꢀTestꢀConditionsꢀandꢀACꢀTestꢀLoadsꢀ(Figureꢀ1).
2.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ2.ꢀꢀTransitionꢀisꢀmeasuredꢀ 500ꢀmVꢀfromꢀsteady-stateꢀvoltage.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
5
Rev. A
11/08/2011
IS61/64WV2568EDBLL
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (AddressꢀControlled)ꢀ(CEꢀ=ꢀOEꢀ=ꢀVil)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3) (CEꢀandꢀOEꢀControlled)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
t
LZOE
ACE
CE
t
HZCE
t
LZCE
HIGH-Z
DOUT
DATA VALID
CE_RD2.eps
Notes:ꢀ
1.ꢀ WEꢀisꢀHIGHꢀforꢀaꢀReadꢀCycle.
2.ꢀ Theꢀdeviceꢀisꢀcontinuouslyꢀselected.ꢀOE,ꢀCEꢀ=ꢀVil.
3.ꢀ AddressꢀisꢀvalidꢀpriorꢀtoꢀorꢀcoincidentꢀwithꢀCEꢀLOWꢀtransitions.
6ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
11/08/2011
3
4
ꢀ ꢀ thd
ꢀ
0ꢀ
IS61/64WV2568EDBLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (OverꢀOperatingꢀRange)
1
-8
-10
Min. Max.
-20
Min. Max.
Symbol
Parameter
Min. Max.
Unit
ns
ꢀ ꢀ twC
ꢀ
WriteꢀCycleꢀTimeꢀ
CEꢀtoꢀWriteꢀEndꢀ
ꢀ
ꢀ
ꢀ
8ꢀ ꢀ —ꢀ
6.5ꢀ ꢀ —ꢀ
6.5ꢀ ꢀ —ꢀ
ꢀ 10ꢀ ꢀ —ꢀ
20ꢀ
12ꢀ
12ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ ꢀ tsCe
ꢀ
ꢀ
ꢀ
8ꢀ ꢀ —ꢀ
8ꢀ ꢀ —ꢀ
ns
2
ꢀ ꢀ taw
ꢀ
AddressꢀSetupꢀTimeꢀꢀ
toꢀWriteꢀEnd
ns
ꢀ ꢀ ꢀ
ꢀ ꢀ tha
ꢀ
AddressꢀHoldꢀfromꢀWriteꢀEndꢀ
AddressꢀSetupꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
6.5ꢀ ꢀ —ꢀ
8.0ꢀ ꢀ —ꢀ
5ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
—ꢀ ꢀ 3.5ꢀ
2ꢀ ꢀ —ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
8ꢀ ꢀ —ꢀ
0ꢀ
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
9ꢀ
ns
ns
ns
ns
ns
ns
ns
ns
ꢀ ꢀ tsa
ꢀ
ꢀ ꢀ tPwe1ꢀ
ꢀ ꢀ tPwe2ꢀ
WEꢀPulseꢀWidthꢀ
12ꢀ
17ꢀ
9ꢀ
WEꢀPulseꢀWidthꢀꢀ(OEꢀ=ꢀLOW)ꢀ
DataꢀSetupꢀtoꢀWriteꢀEndꢀ
DataꢀHoldꢀfromꢀWriteꢀEndꢀ
WEꢀLOWꢀtoꢀHigh-ZꢀOutputꢀ
WEꢀHIGHꢀtoꢀLow-ZꢀOutputꢀ
ꢀ 10ꢀ ꢀ —ꢀ
ꢀ ꢀ tsd
ꢀ
ꢀ
ꢀ
6ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
ꢀ ꢀ thzwe(2)ꢀ
ꢀ ꢀ tlzwe(2)ꢀ
Notes:ꢀ
ꢀ —ꢀ ꢀ 5ꢀ
2ꢀ ꢀ —ꢀ
—ꢀ
2ꢀ
ꢀ
—ꢀ
5
1.ꢀ TestꢀconditionsꢀandꢀoutputꢀloadingꢀconditionsꢀareꢀspecifiedꢀinꢀtheꢀACꢀTestꢀConditionsꢀandꢀACꢀTestꢀLoadsꢀ(Figureꢀ1).
2.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ2.ꢀꢀTransitionꢀisꢀmeasuredꢀ 500ꢀmVꢀfromꢀsteady-stateꢀvoltage.ꢀNotꢀ100%ꢀtested.
3.ꢀ TheꢀinternalꢀwriteꢀtimeꢀisꢀdefinedꢀbyꢀtheꢀoverlapꢀofꢀCEꢀLOW,ꢀandꢀWEꢀLOW.ꢀꢀAllꢀsignalsꢀmustꢀbeꢀinꢀvalidꢀstatesꢀtoꢀinitiateꢀaꢀ
Write,ꢀbutꢀanyꢀoneꢀcanꢀgoꢀinactiveꢀtoꢀterminateꢀtheꢀWrite.ꢀꢀTheꢀDataꢀInputꢀSetupꢀandꢀHoldꢀtimingꢀareꢀreferencedꢀtoꢀtheꢀrisingꢀ
orꢀfallingꢀedgeꢀofꢀtheꢀsignalꢀthatꢀterminatesꢀtheꢀwrite.ꢀShadedꢀareaꢀproductꢀinꢀdevelopmentꢀ
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.comꢀ
7
Rev. A
11/08/2011
IS61/64WV2568EDBLL
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CEꢀControlled,ꢀOEꢀ=ꢀHIGHꢀorꢀLOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
t
SA
t
t
HA
CE
t
AW
t
tPPWWEE21
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR1.eps
8ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
11/08/2011
IS61/64WV2568EDBLL
WRITE CYCLE NO. 2(1,2) (WEꢀControlled:ꢀOEꢀisꢀHIGHꢀDuringꢀWriteꢀCycle)
t
WC
1
ADDRESS
VALID ADDRESS
t
HA
OE
2
LOW
CE
3
t
AW
t
PWE1
WE
4
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
5
t
SD
t
HD
DATAIN VALID
DIN
CE_WR2.eps
6
Notes:ꢀ
1.ꢀ TheꢀinternalꢀwriteꢀtimeꢀisꢀdefinedꢀbyꢀtheꢀoverlapꢀofꢀCEꢀLOWꢀandꢀWEꢀLOW.ꢀꢀAllꢀsignalsꢀmustꢀbeꢀinꢀvalidꢀstatesꢀtoꢀinitiateꢀaꢀWrite,ꢀ
butꢀanyꢀoneꢀcanꢀgoꢀinactiveꢀtoꢀterminateꢀtheꢀWrite.ꢀꢀTheꢀDataꢀInputꢀSetupꢀandꢀHoldꢀtimingꢀareꢀreferencedꢀtoꢀtheꢀrisingꢀorꢀfallingꢀ
edgeꢀofꢀtheꢀsignalꢀthatꢀterminatesꢀtheꢀWrite.
2.ꢀ I/OꢀwillꢀassumeꢀtheꢀHigh-ZꢀstateꢀifꢀOEꢀ >ꢀVih.
7
WRITE CYCLE NO. 3 (WEꢀControlled:ꢀOEꢀisꢀLOWꢀDuringꢀWriteꢀCycle)
t
WC
8
ADDRESS
VALID ADDRESS
t
HA
9
LOW
LOW
OE
CE
10
11
12
t
t
AW
t
PWE2
WE
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR3.eps
Integrated Silicon Solution, Inc. — www.issi.comꢀ
9
Rev. A
11/08/2011
IS61/64WV2568EDBLL
HIGH SPEED
DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V)
Symbol
ꢀ ꢀ Vdrꢀ
Parameter
Test Condition
Options
Min.
2.0ꢀ
—ꢀ
Typ.(1)
—ꢀ
Max.
3.6ꢀ
5ꢀ
Unit
V
VddꢀforꢀDataꢀRetentionꢀ
DataꢀRetentionꢀCurrentꢀ
SeeꢀDataꢀRetentionꢀWaveformꢀ
Vddꢀ=ꢀ2.0V,ꢀCEꢀ≥ꢀVddꢀ–ꢀ0.2Vꢀ
ꢀ
ꢀ ꢀ idrꢀ
Com.ꢀ
0.5ꢀ
mA
ꢀ
ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Ind.ꢀ
Auto.ꢀ
—ꢀ
ꢀ
—ꢀ
ꢀ
6ꢀ
ꢀ
15
ꢀ ꢀ tsdrꢀ
ꢀ ꢀ trdrꢀ
DataꢀRetentionꢀSetupꢀTimeꢀ SeeꢀDataꢀRetentionꢀWaveformꢀ
ꢀ
ꢀ
0ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
ns
ns
RecoveryꢀTimeꢀ
SeeꢀDataꢀRetentionꢀWaveformꢀ
trCꢀ
O
Note 1:ꢀTypicalꢀvaluesꢀareꢀmeasuredꢀatꢀVddꢀ=ꢀVdr(min),ꢀTaꢀ=ꢀ25 Cꢀandꢀnotꢀ100%ꢀtested.
DATA RETENTION WAVEFORM (CEꢀControlled)
t
SDR
Data Retention Mode
tRDR
VDD
VDR
CE ≥ VDD - 0.2V
CE
GND
10ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
11/08/2011
IS61/64WV2568EDBLL
ORDERING INFORMATIONꢀ
1
Industrial Range: -40°C to +85°C
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
ꢀ
8ꢀ
ꢀ
ꢀ
IS61WV2568EDBLL-8BLIꢀ
IS61WV2568EDBLL-8TLIꢀ
IS61WV2568EDBLL-8KLIꢀ
36ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-freeꢀ
2
TSOPꢀ(TypeꢀII),ꢀLead-freeꢀ
ꢀ
ꢀ
ꢀ
400-milꢀPlasticꢀSOJ,ꢀLead-free
3
Industrial Range: -40°C to +85°C
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
10ꢀ
IS61WV2568EDBLL-10BIꢀ
IS61WV2568EDBLL-10BLIꢀ
IS61WV2568EDBLL-10TIꢀ
IS61WV2568EDBLL-10TLIꢀ
IS61WV2568EDBLL-10KLIꢀ
36ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm)ꢀ
36ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-freeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
4
TSOPꢀ(TypeꢀII)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
TSOPꢀ(TypeꢀII),ꢀLead-freeꢀ
400-milꢀPlasticꢀSOJ,ꢀLead-free
5
Automotive (A1) Range: -40°C to +85°C
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
10ꢀ
IS64WV2568EDBLL-10BA1ꢀ
IS64WV2568EDBLL-10BLA1ꢀ
IS64WV2568EDBLL-10CTA1ꢀ
IS64WV2568EDBLL-10CTLA1ꢀ TSOPꢀ(TypeꢀII),ꢀLead-free,ꢀCopperꢀLeadframeꢀꢀ
IS64WV2568EDBLL-10KLA1ꢀ
36ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm)ꢀ
36ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-freeꢀ
TSOPꢀ(TypeꢀII),ꢀCopperꢀLeadframeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
6
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
400-milꢀPlasticꢀSOJ,ꢀLead-freeꢀ
7
Automotive (A3) Range: -40°C to +125°C
8
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
10ꢀ
IS64WV2568EDBLL-10BA3ꢀ
IS64WV2568EDBLL-10BLA3ꢀ
IS64WV2568EDBLL-10CTA3ꢀ
IS64WV2568EDBLL-10CTLA3ꢀ TSOPꢀ(TypeꢀII),ꢀLead-free,ꢀCopperꢀLeadframeꢀ ꢀ
IS64WV2568EDBLL-10KLA3ꢀ 400-milꢀPlasticꢀSOJ,ꢀLead-free
36ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm)ꢀ
36ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-freeꢀꢀ
TSOPꢀ(TypeꢀII),ꢀCopperꢀLeadframeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.comꢀ
11
Rev. A
11/08/2011
IS61/64WV2568EDBLL
12ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
11/08/2011
IS61/64WV2568EDBLL
1
2
3
4
5
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.comꢀ
13
Rev. A
11/08/2011
IS61/64WV2568EDBLL
14ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
11/08/2011
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