IS61WV3216DALL/DALS [ISSI]
32K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM; 32K ×16高速异步的CMOS静态RAM
| 型号： | IS61WV3216DALL/DALS |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 32K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM |
| 文件： | 总20页 (文件大小：678K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
performanceꢀCMOSꢀtechnology.Thisꢀhighlyꢀreliableꢀprocessꢀ
IS61WV3216DALL/DALS
IS61WV3216DBLL/DBLS
IS64WV3216DBLL/DBLS
32K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM
MAY 2012
DESCRIPTION
FEATURES
TheꢀISSIꢀIS61WV3216DAxx/DBxxꢀandꢀIS64WV3216DBxxꢀ
areꢀ high-speed,ꢀ 524,288-bitꢀ staticꢀ RAMsꢀ organizedꢀ asꢀ
32,768ꢀwordsꢀbyꢀ16ꢀbits.ꢀItꢀisꢀfabricatedꢀusingꢀISSI'sꢀhigh-
HIGHꢀSPEED:ꢀ(IS61/64WV3216DALL/DBLL)
•ꢀ High-speedꢀaccessꢀtime:ꢀ8,ꢀ10,ꢀ12,ꢀ20ꢀns
•ꢀ LowꢀActiveꢀPower:ꢀ135ꢀmWꢀ(typical)
•ꢀ LowꢀStandbyꢀPower:ꢀ12ꢀµWꢀ(typical)
coupledꢀwithꢀinnovativeꢀcircuitꢀdesignꢀtechniques,ꢀyieldsꢀ
high-performanceꢀandꢀlowꢀpowerꢀconsumptionꢀdevices.
CMOSꢀstandby
LOWꢀPOWER:ꢀ(IS61/64WV3216DALS/DBLS)
•ꢀ High-speedꢀaccessꢀtime:ꢀ25,ꢀ35ꢀns
•ꢀ LowꢀActiveꢀPower:ꢀ55ꢀmWꢀ(typical)
WhenꢀCEꢀisꢀHIGHꢀ(deselected),ꢀtheꢀdeviceꢀassumesꢀaꢀ
standbyꢀmodeꢀatꢀwhichꢀtheꢀpowerꢀdissipationꢀcanꢀbeꢀre-
ducedꢀdownꢀwithꢀCMOSꢀinputꢀlevels.
•ꢀ LowꢀStandbyꢀPower:ꢀ12ꢀµWꢀ(typical)
CMOSꢀstandby
EasyꢀmemoryꢀexpansionꢀisꢀprovidedꢀbyꢀusingꢀChipꢀEnableꢀ
andꢀOutputꢀEnableꢀinputs,ꢀCEꢀandꢀOE.ꢀTheꢀactiveꢀLOWꢀ
WriteꢀEnableꢀ(WE)ꢀcontrolsꢀbothꢀwritingꢀandꢀreadingꢀofꢀtheꢀ
memory.ꢀꢀAꢀdataꢀbyteꢀallowsꢀUpperꢀByteꢀ(UB)ꢀandꢀLowerꢀ
Byteꢀ(LB)ꢀaccess.
•ꢀ Singleꢀpowerꢀsupply
ꢀ —ꢀꢀVddꢀ1.65Vꢀtoꢀ2.2Vꢀ(IS61WV3216DAxx)
ꢀ —ꢀꢀVddꢀ2.4Vꢀtoꢀ3.6Vꢀ(IS61/64WV3216DBxx)
•ꢀ Fullyꢀstaticꢀoperation:ꢀnoꢀclockꢀorꢀrefreshꢀꢀ
required
•ꢀ Threeꢀstateꢀoutputs
•ꢀ Dataꢀcontrolꢀforꢀupperꢀandꢀlowerꢀbytes
•ꢀ IndustrialꢀandꢀAutomotiveꢀtemperatureꢀsupport
•ꢀ Lead-freeꢀavailable
TheꢀIS61WV3216DAxx/DBxxꢀandꢀIS64WV3216DBxxꢀareꢀ
packagedꢀinꢀtheꢀJEDECꢀstandardꢀ44-pinꢀTSOPꢀTypeꢀIIꢀandꢀ
48-pinꢀMiniꢀBGAꢀ(6mmꢀxꢀ8mm).
FUNCTIONAL BLOCK DIAGRAM
32K x 16
MEMORY ARRAY
A0-A14
DECODER
VDD
GND
I/O0-I/O7
Lower Byte
I/O
DATA
COLUMN I/O
CIRCUIT
I/O8-I/O15
Upper Byte
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
Copyrightꢀ©ꢀ2012ꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀꢀAllꢀrightsꢀreserved.ꢀꢀISSIꢀreservesꢀtheꢀrightꢀtoꢀmakeꢀchangesꢀtoꢀthisꢀspecificationꢀandꢀitsꢀproductsꢀatꢀanyꢀtimeꢀwithoutꢀ
notice.ꢀꢀꢀISSIꢀassumesꢀnoꢀliabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀtheꢀlat-
estꢀversionꢀofꢀthisꢀdeviceꢀspecificationꢀbeforeꢀrelyingꢀonꢀanyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.ꢀ
IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀreason-
ablyꢀbeꢀexpectedꢀtoꢀcauseꢀfailureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsignificantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀapplicationsꢀ
unlessꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀreceivesꢀwrittenꢀassuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:
a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;
b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand
c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstances
ꢀ
Integrated Silicon Solution, Inc. — www.issi.comꢀ
1
Rev. A
05/14/2012
IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
TRUTH TABLE
I/O PIN
Mode
WE
CE
OE
LBꢀ
UB
I/O0-I/O7
I/O8-I/O15
VDD Current
Isb1, Isb2
Iccꢀ
NotꢀSelectedꢀ
OutputꢀDisabledꢀ
ꢀ
Xꢀ
Hꢀ
Xꢀ
Hꢀ
Lꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Hꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
High-Z
ꢀ
ꢀ
ꢀ
Readꢀ
ꢀ
Hꢀ
Hꢀ
H
Lꢀ
Lꢀ
L
Lꢀ
Lꢀ
L
Lꢀ
Lꢀ
L
Lꢀ
Lꢀ
L
Xꢀ
Xꢀ
X
Lꢀ
Hꢀ
L
Lꢀ
Hꢀ
L
Hꢀ
Lꢀ
L
Hꢀ
Lꢀ
L
doutꢀ
High-Zꢀ
dout
High-Z
dout
dout
Iccꢀ
Iccꢀ
ꢀ
ꢀ
Writeꢀ
ꢀ
dInꢀ
High-Zꢀ
dIn
High-Z
dIn
dIn
PIN CONFIGURATIONS
44-Pin TSOP-II
PIN DESCRIPTIONS
A0-A14ꢀ ꢀ
AddressꢀInputs
I/O0-I/O15ꢀ
DataꢀInputs/Outputs
ChipꢀEnableꢀInput
OutputꢀEnableꢀInput
WriteꢀEnableꢀInput
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
NC
A14
A13
A12
A11
CE
I/O0
I/O1
I/O2
I/O3
1
2
3
4
5
6
7
8
CEꢀꢀ
OEꢀꢀ
WEꢀꢀ
LBꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Lower-byteꢀControlꢀ(I/O0-I/O7)
Upper-byteꢀControlꢀ(I/O8-I/O15)
NoꢀConnection
UBꢀ
NCꢀ
9
Vddꢀ
GNDꢀ
Power
10
11
12
13
14
15
16
17
18
19
20
21
22
Ground
V
DD
V
DD
GND
I/O4
I/O5
I/O6
I/O7
WE
A10
A9
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
A8
A7
NC
NC
2ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
05/14/2012
IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
PIN CONFIGURATIONS
48-Pin mini BGA (6mm x 8mm)
1
1
2
3
4
5
6
2
3
A0
A3
A1
A4
A2
LB
OE
UB
NC
I/O
A
B
C
D
E
F
I/O
8
CE
0
I/O
9
I/O
A5
A6
I/O
1
I/O
2
10
4
GND
NC
NC
A14
A12
A7
I/O
I/O
I/O
3
I/O
4
I/O
5
VDD
11
GND
VDD
NC
NC
A13
A10
12
I/O
I/O
I/O
13
I/O
6
14
5
NC
A8
WE
I/O
7
15
G
H
NC
A9
A11
NC
6
7
8
PIN DESCRIPTIONS
A0-A14ꢀ ꢀ
AddressꢀInputs
I/O0-I/O15ꢀ
DataꢀInputs/Outputs
ChipꢀEnableꢀInput
OutputꢀEnableꢀInput
WriteꢀEnableꢀInput
9
CEꢀꢀ
OEꢀꢀ
WEꢀꢀ
LBꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
10
11
12
Lower-byteꢀControlꢀ(I/O0-I/O7)
Upper-byteꢀControlꢀ(I/O8-I/O15)
NoꢀConnection
UBꢀ
NCꢀ
Vddꢀ
GNDꢀ
Power
Ground
Integrated Silicon Solution, Inc. — www.issi.comꢀ
3
Rev. A
05/14/2012
IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
DC ELECTRICAL CHARACTERISTICS (OverꢀOperatingꢀRange)
VDD = 3.3V + 5%
Symbol Parameter
Test Conditions
Vdd = Min.,ꢀIoH = –4.0ꢀmAꢀ
Min.
2.4ꢀ
—ꢀ
2ꢀ
–0.3ꢀ
–1ꢀ
Max.
—ꢀ
0.4ꢀ
Unit
V
V
V
V
VoH
ꢀ VoL
ꢀ VIH
ꢀ VIL
ꢀ ILI
OutputꢀHIGHꢀVoltageꢀ
OutputꢀLOWꢀVoltageꢀ
InputꢀHIGHꢀVoltageꢀ
InputꢀLOWꢀVoltage(1)ꢀ
InputꢀLeakageꢀ
Vdd = Min.,ꢀIoL = 8.0ꢀmAꢀ
ꢀ
ꢀ
Vdd + 0.3
0.8ꢀ
ꢀ
GNDꢀ≤ꢀVIn ≤ Vdd
1ꢀ
1ꢀ
µA
µA
ꢀ ILo
OutputꢀLeakageꢀ
GNDꢀ≤ꢀVout ≤ Vdd, OutputsꢀDisabledꢀ
–1ꢀ
Note:
1.ꢀꢀVIL (min.)ꢀ= –0.3VꢀDC;ꢀVILꢀ(min.)ꢀ=ꢀ–2.0VꢀACꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
VIH (max.)ꢀ= Vdd +ꢀ0.3V dc;ꢀVIH (max.)ꢀ= Vdd +ꢀ2.0V Acꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
ꢀ
DC ELECTRICAL CHARACTERISTICS (OverꢀOperatingꢀRange)
VDD = 2.4V-3.6Vꢀ
ꢀ
ꢀ
ꢀ
Symbol Parameter
Test Conditions
Min.
1.8ꢀ
—ꢀ
Max.
—ꢀ
Unit
V
VoH
ꢀ VoL
ꢀ VIH
ꢀ VIL
ꢀ ILI
OutputꢀHIGHꢀVoltageꢀ
OutputꢀLOWꢀVoltageꢀ
InputꢀHIGHꢀVoltageꢀ
InputꢀLOWꢀVoltage(1)ꢀ
InputꢀLeakageꢀ
Vdd = Min.,ꢀIoH = –1.0ꢀmAꢀ
Vdd = Min.,ꢀIoL = 1.0ꢀmAꢀ
0.4ꢀ
V
ꢀ
ꢀ
2.0ꢀ
–0.3ꢀ
–1ꢀ
Vdd + 0.3
0.8ꢀ
V
V
ꢀ
GNDꢀ≤ꢀ VIn ≤ Vdd
1ꢀ
µA
µA
ꢀ ILo
OutputꢀLeakageꢀ
GNDꢀ≤ꢀ Vout ≤ Vdd, OutputsꢀDisabledꢀ
–1ꢀ
1ꢀ
Note:
1.ꢀ VIL (min.)ꢀ= –0.3VꢀDC;ꢀVILꢀ(min.)ꢀ=ꢀ–2.0VꢀACꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
VIH (max.)ꢀ= Vdd +ꢀ0.3V dc;ꢀVIH (max.)ꢀ= Vdd +ꢀ2.0V Acꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
ꢀ
DC ELECTRICAL CHARACTERISTICSꢀ(OverꢀOperatingꢀRange)
VDD = 1.65V-2.2V
Symbol Parameter
Test Conditions
VDD
Min.
1.4ꢀ
—ꢀ
Max.
—ꢀ
Unit
V
VoH
ꢀ VoL
ꢀ VIH
OutputꢀHIGHꢀVoltageꢀ
IoH = -0.1ꢀmAꢀ
1.65-2.2Vꢀ
1.65-2.2Vꢀ
1.65-2.2Vꢀ
1.65-2.2Vꢀ
OutputꢀLOWꢀVoltageꢀ
InputꢀHIGHꢀVoltageꢀ
InputꢀLOWꢀVoltageꢀ
InputꢀLeakageꢀ
IoL = 0.1ꢀmAꢀ
0.2ꢀ
V
ꢀ
1.4ꢀ
–0.2ꢀ
–1ꢀ
Vdd + 0.2
0.4ꢀ
V
(1)
ꢀ VIL
ꢀ ILI
ꢀ
V
ꢀ
GNDꢀ≤ꢀ VIn ≤ ꢀVdd
1ꢀ
µA
µA
ꢀ ILo
OutputꢀLeakageꢀ
GNDꢀ≤ꢀ Vout ≤ ꢀVdd, OutputsꢀDisabledꢀ
–1ꢀ
1ꢀ
Note:
1.ꢀ VIL (min.)ꢀ= –0.3VꢀDC;ꢀVILꢀ(min.)ꢀ=ꢀ–2.0VꢀACꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
VIH (max.)ꢀ= Vdd +ꢀ0.3V dc;ꢀVIH (max.)ꢀ= Vdd +ꢀ2.0V Acꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
ꢀ
4ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
05/14/2012
IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
AC TEST CONDITIONS
1
Parameter
Unit
(2.4V-3.6V)
Unit
(3.3V + 5%)
Unit
(1.65V-2.2V)
InputꢀPulseꢀLevelꢀ
0.4VꢀtoꢀVddꢀ-ꢀ0.3Vꢀ
1V/ꢀnsꢀ
0.4VꢀtoꢀVddꢀ-ꢀ0.3Vꢀ
1V/ꢀnsꢀ
0.4VꢀtoꢀVddꢀ-ꢀ0.3V
1V/ꢀns
2
ꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
ꢀ
ꢀ
InputꢀandꢀOutputꢀTimingꢀ
andꢀReferenceꢀLevelꢀ(VRef)ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ2
VDDꢀ/2ꢀ
VDDꢀꢀ+ꢀ0.05ꢀ
0.9V
ꢀ
ꢀ
ꢀ
ꢀ
OutputꢀLoadꢀ
R1ꢀ( Ω )ꢀ
R2ꢀ( Ω )ꢀ
Vtmꢀ(V)ꢀ
SeeꢀFiguresꢀ1ꢀandꢀ2ꢀ
SeeꢀFiguresꢀ1ꢀandꢀ2ꢀ
SeeꢀFiguresꢀ1ꢀandꢀ2
13500
3
1909ꢀ
1105ꢀ
3.0Vꢀ
317ꢀ
351ꢀ
3.3Vꢀ
10800
1.8V
4
AC TEST LOADS
5
R1
VTM
OUTPUT
ZO
= 50Ω
50Ω
6
VDD/2
OUTPUT
30 pF
Including
jig and
scope
R2
5 pF
Including
jig and
7
scope
Figure 1.
Figure 2.
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.comꢀ
5
Rev. A
05/14/2012
IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–0.5ꢀtoꢀVddꢀ+ꢀ0.5ꢀ
–0.3ꢀtoꢀ4.0ꢀ
–65ꢀtoꢀ+150ꢀ
1.0ꢀ
Unit
V
V
°C
W
Vterm
ꢀ Vdd
TerminalꢀVoltageꢀwithꢀRespectꢀtoꢀGNDꢀ
VddꢀRelatesꢀtoꢀGNDꢀ
StorageꢀTemperatureꢀ
PowerꢀDissipationꢀ
ꢀ tstg
ꢀ Pt
Notes:
1.ꢀꢀStressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀ
theꢀdevice.ꢀThisꢀisꢀaꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀ
aboveꢀthoseꢀindicatedꢀinꢀtheꢀoperationalꢀsectionsꢀofꢀthisꢀspecificationꢀisꢀnotꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀ
maximumꢀratingꢀconditionsꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀreliability.ꢀ
CAPACITANCE(1,2)
Symbol
Parameter
Conditions
VIn = 0V
Max.
6ꢀ
Unit
pF
cIn
InputꢀCapacitanceꢀ
Input/OutputꢀCapacitanceꢀ
ꢀ cI/oꢀ
Vout = 0V
8ꢀ
pF
Notes:
1.ꢀꢀTestedꢀinitiallyꢀandꢀafterꢀanyꢀdesignꢀorꢀprocessꢀchangesꢀthatꢀmayꢀaffectꢀtheseꢀparameters.
2.ꢀ Testꢀconditions:ꢀTA = 25°c, fꢀ=ꢀ1ꢀMHz,ꢀVddꢀ=ꢀ3.3V.
6ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
05/14/2012
IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
HIGH SPEED (IS61WV3216DALL/DBLL)
1
OPERATING RANGE (VDD) (IS61WV3216DALL)
Range
Ambient Temperature
VDD
Speed
20ns
20ns
20ns
Commercialꢀ
ꢀ Industrialꢀ
ꢀ Automotiveꢀ
0°Cꢀtoꢀ+70°Cꢀ
–40°Cꢀtoꢀ+85°Cꢀ
–40°Cꢀtoꢀ+125°Cꢀ
1.65V-2.2Vꢀ
1.65V-2.2Vꢀ
1.65V-2.2Vꢀ
2
OPERATING RANGE (VDD) (IS61WV3216DBLL)(1)
3
Range
Ambient Temperature
VDD (8 nS)1
3.3Vꢀ+ꢀ5%ꢀ
3.3Vꢀ+ꢀ5%ꢀ
VDD (10 nS)1
2.4V-3.6V
2.4V-3.6V
Commercialꢀ
ꢀ Industrialꢀ
Note:
0°Cꢀtoꢀ+70°Cꢀ
–40°Cꢀtoꢀ+85°Cꢀ
4
1.ꢀWhenꢀoperatedꢀinꢀtheꢀrangeꢀofꢀ2.4V-3.6V,ꢀtheꢀdeviceꢀmeetsꢀ10ns.ꢀWhenꢀoperatedꢀinꢀtheꢀrangeꢀ
ofꢀ3.3Vꢀ+ꢀ5%,ꢀtheꢀdeviceꢀmeetsꢀ8ns.
5
OPERATING RANGE (VDD) (IS64WV3216DBLL)
Range
Ambient Temperature
VDD (10 nS)
Automotiveꢀ
–40°Cꢀtoꢀ+125°Cꢀ
2.4V-3.6V
6
7
POWER SUPPLY CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
8
-8
-10
Min. Max.
-12
Min. Max.
-20
Min. Max.
Symbol Parameter
Test Conditions
Min. Max.
Unit
ꢀ Icc
ꢀ ꢀ
ꢀ ꢀ
ꢀ ꢀ
ꢀ ꢀ
VddꢀDynamicꢀOperatingꢀ Vdd = Max.,ꢀꢀ
Com.ꢀ
Ind.ꢀ
—ꢀ ꢀ 65ꢀ
—ꢀ ꢀ 70ꢀ
—ꢀ ꢀ —ꢀ
—ꢀ ꢀ 50ꢀ
—ꢀ ꢀ 55ꢀ
—ꢀ ꢀ 65ꢀ
—ꢀ ꢀ 45ꢀ
—ꢀ ꢀ 50ꢀ
—ꢀ ꢀ 55ꢀ
—ꢀ ꢀ 40ꢀ
—ꢀ ꢀ 45ꢀ
—ꢀ ꢀ 50ꢀ
mA
SupplyꢀCurrentꢀ
Iout = 0 mA,ꢀfꢀ=ꢀfmAX
ꢀ
ꢀ
ꢀ
9
ꢀ
ꢀ
ꢀ
CEꢀ=ꢀVILꢀ
VIn ≥ Vdd – 0.3V, orꢀ
VIn ≤ 0.4Vꢀ
Auto.(3)
typ.(2)
ꢀ
ꢀ
ꢀ 45ꢀ ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ45ꢀ
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ45ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ Isb2ꢀ
ꢀ ꢀ
CMOSꢀStandbyꢀ
Currentꢀ(CMOSꢀInputs)ꢀ CEꢀ≥ꢀVdd – 0.2V,
VIn ≥ Vdd – 0.2V, orꢀ
Vdd = Max.,ꢀ
Com.
Ind.
—
—
—ꢀ
ꢀ
40
55
—ꢀ
—
—
40
55
—
—
—
40
55
90
—
—
—
ꢀ 40ꢀ
55
90
µA
10
11
12
Auto.ꢀ
ꢀ
—ꢀ ꢀ 90ꢀ
ꢀ ꢀ
ꢀ
VIn ≤ 0.2V, fꢀ=ꢀ0ꢀ
typ.(2)
ꢀ
4ꢀ ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ꢀꢀꢀꢀꢀꢀꢀꢀꢀ4ꢀ
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ4
Note:
1.ꢀꢀAtꢀfꢀ=ꢀfmAX,ꢀaddressꢀandꢀdataꢀinputsꢀareꢀcyclingꢀatꢀtheꢀmaximumꢀfrequency,ꢀfꢀ=ꢀ0ꢀmeansꢀnoꢀinputꢀlinesꢀchange.
2.ꢀTypicalꢀvaluesꢀareꢀmeasuredꢀatꢀVddꢀ=ꢀ3.0V,ꢀTAꢀ=ꢀ25oCꢀandꢀnotꢀ100%ꢀtested.
3.ꢀForꢀAutomotiveꢀgradeꢀatꢀ15ns,ꢀtyp.ꢀIccꢀ=ꢀ38mA,ꢀnotꢀ100%ꢀtested.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
7
Rev. A
05/14/2012
IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
LOW POWER (IS61WV3216DALS/DBLS)
OPERATING RANGE (VDD) (IS61WV3216DALS)
Range
Ambient Temperature
VDD
Speed
45ns
45ns
55ns
Commercialꢀ
ꢀ Industrialꢀ
ꢀ Automotiveꢀ
0°Cꢀtoꢀ+70°Cꢀ
–40°Cꢀtoꢀ+85°Cꢀ
–40°Cꢀtoꢀ+125°Cꢀ
1.65V-2.2Vꢀ
1.65V-2.2Vꢀ
1.65V-2.2Vꢀ
OPERATING RANGE (VDD) (IS61WV3216DBLS)
Range
Commercialꢀ
ꢀ Industrialꢀ
Ambient Temperature
VDD (35 nS)
2.4V-3.6V
2.4V-3.6V
0°Cꢀtoꢀ+70°Cꢀ
–40°Cꢀtoꢀ+85°Cꢀ
OPERATING RANGE (VDD) (IS64WV3216DBLS)
Range
Ambient Temperature
VDD (35 nS)
Automotiveꢀ
–40°Cꢀtoꢀ+125°Cꢀ
2.4V-3.6V
POWER SUPPLY CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
-25
-35
-45
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Unit
ꢀ Icc
VddꢀDynamicꢀOperatingꢀ
SupplyꢀCurrentꢀ
ꢀ
ꢀ
ꢀ
Vdd = Max.,ꢀꢀ
Iout = 0 mA,ꢀfꢀ=ꢀfmAX
CEꢀ=ꢀVILꢀ
VIn ≥ Vdd – 0.3V, orꢀ
VIn ≤ 0.4V
Com.ꢀ
Ind.ꢀ
—ꢀ
—ꢀ
—ꢀ
20ꢀ
25ꢀ
40ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
20ꢀ
25ꢀ
35ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
18ꢀ
20ꢀ
30ꢀ
ꢀ
mA
ꢀ ꢀ
ꢀ ꢀ
ꢀ ꢀ
ꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Auto.ꢀ
typ.(2)
ꢀ
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ18ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ Isb2ꢀ
ꢀ ꢀ
CMOSꢀStandbyꢀ
Currentꢀ(CMOSꢀInputs)ꢀ
Vdd = Max.,ꢀ
CEꢀ≥ꢀVdd – 0.2V,
VIn ≥ Vdd – 0.2V, orꢀ
VIn ≤ 0.2V, fꢀ=ꢀ0ꢀ
Com.
Ind.
—
—
—ꢀ
40
50
75ꢀ
—
—
—
40ꢀ
50
75
—ꢀ
—ꢀ
—ꢀ
40ꢀ
50
75
µA
Auto.ꢀ
ꢀ ꢀ
ꢀ
typ.(2)
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ4
Note:
1.ꢀꢀAtꢀfꢀ=ꢀfmAX,ꢀaddressꢀandꢀdataꢀinputsꢀareꢀcyclingꢀatꢀtheꢀmaximumꢀfrequency,ꢀfꢀ=ꢀ0ꢀmeansꢀnoꢀinputꢀlinesꢀchange.
2.ꢀTypicalꢀvaluesꢀareꢀmeasuredꢀatꢀVddꢀ=ꢀ3.0V,ꢀTAꢀ=ꢀ25oCꢀandꢀnotꢀ100%ꢀtested.
8ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
05/14/2012
IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
1
-8
-10
-12
Symbol
ꢀ ꢀ trc
ꢀ ꢀ tAA
ꢀ ꢀ toHA
Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ꢀ
ReadꢀCycleꢀTimeꢀ
AddressꢀAccessꢀTimeꢀ
OutputꢀHoldꢀTimeꢀ
CEꢀAccessꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
8ꢀ
—ꢀ
2.0ꢀ
—ꢀ
—ꢀ
—ꢀ
0ꢀ
—ꢀ
8ꢀ
10ꢀ
—ꢀ
2.0ꢀ
—ꢀ
—ꢀ
—ꢀ
0ꢀ
—ꢀ
10ꢀ
—ꢀ
10ꢀ
6.5ꢀ
4ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
12ꢀ
—ꢀ
3ꢀ
—ꢀ
12ꢀ
—ꢀ
12ꢀ
6.5ꢀ
6ꢀ
ꢀ
2
ꢀ
ꢀ
—ꢀ
8ꢀ
ꢀ ꢀ tAce
ꢀ
—ꢀ
—ꢀ
—ꢀ
0ꢀ
ꢀ ꢀ tdoe
OEꢀAccessꢀTimeꢀ
5.5ꢀ
3ꢀ
ꢀ ꢀ tHzoe(2)ꢀ
ꢀ ꢀ tLzoe(2)ꢀ
ꢀ ꢀ tHzce(2ꢀ
ꢀ ꢀ tLzce(2)ꢀ
OEꢀtoꢀHigh-ZꢀOutputꢀ
OEꢀtoꢀLow-ZꢀOutputꢀ
CEꢀtoꢀHigh-ZꢀOutputꢀ
CEꢀtoꢀLow-ZꢀOutputꢀ
LB,ꢀUBꢀAccessꢀTimeꢀ
LB,ꢀUBꢀtoꢀHigh-ZꢀOutputꢀ
LB,ꢀUBꢀtoꢀLow-ZꢀOutputꢀ
PowerꢀUpꢀTimeꢀ
3
—ꢀ
3ꢀ
—ꢀ
4ꢀ
—ꢀ
6ꢀ
0ꢀ
0ꢀ
0ꢀ
3ꢀ
—ꢀ
5.5ꢀ
5.5ꢀ
—ꢀ
—ꢀ
8ꢀ
3ꢀ
—ꢀ
6.5ꢀ
6.5ꢀ
—ꢀ
—ꢀ
10ꢀ
3ꢀ
—ꢀ
6.5ꢀ
6.5ꢀ
—ꢀ
—ꢀ
10ꢀ
4
ꢀ ꢀ tbA
ꢀ
—ꢀ
0ꢀ
—ꢀ
0ꢀ
—ꢀ
0ꢀ
ꢀ ꢀ tHzb(2)ꢀ
ꢀ ꢀ tLzb(2)ꢀ
0ꢀ
0ꢀ
0ꢀ
ꢀ ꢀ tPu
ꢀ ꢀ tPd
ꢀ
ꢀ
0ꢀ
0ꢀ
0ꢀ
5
PowerꢀDownꢀTimeꢀ
—ꢀ
—ꢀ
—ꢀ
Notes:ꢀ
1.ꢀ Testꢀconditionsꢀassumeꢀsignalꢀtransitionꢀtimesꢀofꢀ3ꢀnsꢀorꢀless,ꢀtimingꢀreferenceꢀlevelsꢀofꢀ1.5V,ꢀinputꢀpulseꢀlevelsꢀofꢀ0Vꢀtoꢀ3.0Vꢀ
andꢀoutputꢀloadingꢀspecifiedꢀinꢀFigureꢀ1.
2.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ2.ꢀꢀTransitionꢀisꢀmeasuredꢀ 500ꢀmVꢀfromꢀsteady-stateꢀvoltage.
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.comꢀ
9
Rev. A
05/14/2012
IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
-20 ns
Min. Max.
-25 ns
Min. Max.
-35 ns
Min. Max.
-45 ns
Min. Max.
Symbol Parameter
ꢀ trc ReadꢀCycleꢀTimeꢀ
ꢀ tAA
ꢀ toHA
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
20ꢀ ꢀ —ꢀ
—ꢀ ꢀ 20ꢀ
2.5ꢀ ꢀ —ꢀ
—ꢀ ꢀ 20ꢀ
—ꢀ ꢀ 8ꢀ
0ꢀ ꢀ 8ꢀ
0ꢀ ꢀ —ꢀ
0ꢀ ꢀ 8ꢀ
3ꢀ ꢀ —ꢀ
—ꢀ ꢀ 8ꢀ
0ꢀ ꢀ 8ꢀ
0ꢀ ꢀ —ꢀ
25ꢀ
—ꢀ
6ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
25ꢀ
—ꢀ
25ꢀ
12ꢀ
8ꢀ
35ꢀ ꢀ —ꢀ
—ꢀ ꢀ 35ꢀ
8ꢀ ꢀ —ꢀ
—ꢀ ꢀ 35ꢀ
—ꢀ ꢀ 15ꢀ
0ꢀ ꢀ 10ꢀ
0ꢀ ꢀ —ꢀ
0ꢀ ꢀ 10ꢀ
10ꢀ ꢀ —ꢀ
—ꢀ ꢀ 35ꢀ
0ꢀ ꢀ 10ꢀ
0ꢀ ꢀ —ꢀ
45ꢀ
—ꢀ
10ꢀ
—ꢀ
—ꢀ
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
45ꢀ
—ꢀ
45ꢀ
20ꢀ
15ꢀ
—ꢀ
15ꢀ
—ꢀ
45ꢀ
15ꢀ
—ꢀ
ꢀ
AddressꢀAccessꢀTimeꢀ
OutputꢀHoldꢀTimeꢀ
CEꢀAccessꢀTimeꢀ
ꢀ
ꢀ
ꢀ tAce
ꢀ
—ꢀ
—ꢀ
0ꢀ
ꢀ tdoe
OEꢀAccessꢀTimeꢀ
ꢀ tHzoe(2)ꢀ
ꢀ tLzoe(2)ꢀ
ꢀ tHzce(2ꢀ
ꢀ tLzce(2)ꢀ
OEꢀtoꢀHigh-ZꢀOutputꢀ
OEꢀtoꢀLow-ZꢀOutputꢀ
CEꢀtoꢀHigh-ZꢀOutputꢀ
CEꢀtoꢀLow-ZꢀOutputꢀ
LB,ꢀUBꢀAccessꢀTimeꢀ
0ꢀ
—ꢀ
8ꢀ
0ꢀ
0ꢀ
0ꢀ
10ꢀ
—ꢀ
0ꢀ
—ꢀ
25ꢀ
8ꢀ
10ꢀ
—ꢀ
0ꢀ
ꢀ tbA
ꢀ tHzb
ꢀ tLzb
ꢀ
ꢀ
LB,ꢀUBꢀtoꢀHigh-ZꢀOutputꢀꢀ
LB,ꢀUBꢀtoꢀLow-ZꢀOutputꢀ ꢀ
ꢀ
0ꢀ
—ꢀ
0ꢀ
Notes:ꢀ
1.ꢀ Testꢀconditionsꢀassumeꢀsignalꢀtransitionꢀtimesꢀofꢀ1.5ꢀnsꢀorꢀless,ꢀtimingꢀreferenceꢀlevelsꢀofꢀ1.25V,ꢀinputꢀpulseꢀlevelsꢀofꢀ0.4Vꢀtoꢀ
Vdd-0.3VꢀandꢀoutputꢀloadingꢀspecifiedꢀinꢀFigureꢀ1a.
2.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ1b.ꢀꢀTransitionꢀisꢀmeasuredꢀ 500ꢀmVꢀfromꢀsteady-stateꢀvoltage.ꢀNotꢀ100%ꢀtested.
3.ꢀ Notꢀ100%ꢀtested.
10ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
05/14/2012
IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
AC WAVEFORMS
READ CYCLE NO. 1(1,2)ꢀ(AddressꢀControlled)ꢀ(CEꢀ=ꢀOEꢀ=ꢀVIL, UB and/orꢀLB = VIL)
1
2
t
RC
ADDRESS
t
AA
t
OHA
3
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
4
5
READ CYCLE NO. 2(1,3)
t
RC
6
ADDRESS
OE
t
AA
t
OHA
7
t
HZOE
t
DOE
LZOE
ACE
t
CE
t
tHZCE
8
tLZCE
LB, UB
t
BA
t
HZB
tRC
tLZB
HIGH-Z
DOUT
9
DATA VALID
I
CC
V
DD
Supply
Current
50%
50%
t
PD
tPU
I
SB
10
11
12
UB_CEDR2.eps
Notes:ꢀ
1.ꢀ WEꢀisꢀHIGHꢀforꢀaꢀReadꢀCycle.
2.ꢀ Theꢀdeviceꢀisꢀcontinuouslyꢀselected.ꢀOE,ꢀCE,ꢀUBꢀand/orꢀLBꢀ=ꢀVIL.
3.ꢀ AddressꢀisꢀvalidꢀpriorꢀtoꢀorꢀcoincidentꢀwithꢀCEꢀLOWꢀtransition.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
11
Rev. A
05/14/2012
ꢀ ꢀ tHd
ꢀ
0ꢀ
0ꢀ
0ꢀ
IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (OverꢀOperatingꢀRange)
-8
-10
-12
Symbol
Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
ns
ꢀ ꢀ twc
ꢀ
WriteꢀCycleꢀTimeꢀ
CEꢀtoꢀWriteꢀEndꢀ
ꢀ
ꢀ
ꢀ
8ꢀ
—ꢀ
—ꢀ
—ꢀ
10ꢀ
8ꢀ
—ꢀ
—ꢀ
—ꢀ
12ꢀ
9ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ ꢀ tsce
6.5ꢀ
6.5ꢀ
ns
ꢀ ꢀ tAw
ꢀ
AddressꢀSetupꢀTimeꢀꢀ
toꢀWriteꢀEnd
8ꢀ
9ꢀ
ns
ꢀ ꢀ ꢀ
ꢀ ꢀ tHA
ꢀ ꢀ tsA
ꢀ ꢀ tPwb
ꢀ
AddressꢀHoldꢀfromꢀWriteꢀEndꢀ
AddressꢀSetupꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0ꢀ
0ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
3.5ꢀ
—ꢀ
0ꢀ
0ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
5ꢀ
0ꢀ
0ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
6ꢀ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ꢀ
ꢀ
LB,ꢀUBꢀValidꢀtoꢀEndꢀofꢀWriteꢀ
WEꢀPulseꢀWidthꢀ
6.5ꢀ
6.5ꢀ
8.0ꢀ
5ꢀ
8ꢀ
9ꢀ
ꢀ ꢀ tPwe1ꢀ
ꢀ ꢀ tPwe2ꢀ
8ꢀ
9ꢀ
WEꢀPulseꢀWidthꢀꢀ(OEꢀ=ꢀLOW)ꢀ
DataꢀSetupꢀtoꢀWriteꢀEndꢀ
DataꢀHoldꢀfromꢀWriteꢀEndꢀ
WEꢀLOWꢀtoꢀHigh-ZꢀOutputꢀ
WEꢀHIGHꢀtoꢀLow-ZꢀOutputꢀ
10ꢀ
6ꢀ
11ꢀ
9ꢀ
ꢀ ꢀ tsd
ꢀ
ꢀ ꢀ tHzwe(2)ꢀ
ꢀ ꢀ tLzwe(2)ꢀ
Notes:ꢀ
—ꢀ
2ꢀ
—ꢀ
2ꢀ
—ꢀ
3ꢀ
—ꢀ
—ꢀ
1.ꢀ Testꢀconditionsꢀassumeꢀsignalꢀtransitionꢀtimesꢀofꢀ3ꢀnsꢀorꢀless,ꢀtimingꢀreferenceꢀlevelsꢀofꢀ1.5V,ꢀinputꢀpulseꢀlevelsꢀofꢀ0Vꢀtoꢀ3.0Vꢀ
andꢀoutputꢀloadingꢀspecifiedꢀinꢀFigureꢀ1.
2.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ2.ꢀꢀTransitionꢀisꢀmeasuredꢀ 500ꢀmVꢀfromꢀsteady-stateꢀvoltage.ꢀNotꢀ100%ꢀtested.
3.ꢀ TheꢀinternalꢀwriteꢀtimeꢀisꢀdefinedꢀbyꢀtheꢀoverlapꢀofꢀCEꢀLOWꢀandꢀUBꢀorꢀLB,ꢀandꢀWEꢀLOW.ꢀꢀAllꢀsignalsꢀmustꢀbeꢀinꢀvalidꢀstatesꢀ
toꢀinitiateꢀaꢀWrite,ꢀbutꢀanyꢀoneꢀcanꢀgoꢀinactiveꢀtoꢀterminateꢀtheꢀWrite.ꢀꢀTheꢀDataꢀInputꢀSetupꢀandꢀHoldꢀtimingꢀareꢀreferencedꢀtoꢀ
theꢀrisingꢀorꢀfallingꢀedgeꢀofꢀtheꢀsignalꢀthatꢀterminatesꢀtheꢀwrite.ꢀShadedꢀareaꢀproductꢀinꢀdevelopmentꢀ
12ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
05/14/2012
ꢀ
DataꢀHoldꢀfromꢀWriteꢀEndꢀ
IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (OverꢀOperatingꢀRange)
-20 ns
Min. Max.
-25 ns
Min. Max.
-35 ns
Min. Max.
-45ns
Min. Max.
1
Symbol Parameter
Unit
ns
ꢀ twc
ꢀ
WriteꢀCycleꢀTimeꢀ
ꢀ
ꢀ
ꢀ
20ꢀ
12ꢀ
12ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
25ꢀ
18ꢀ
15ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
35ꢀ ꢀ —ꢀ
25ꢀ ꢀ —ꢀ
25ꢀ ꢀ —ꢀ
45ꢀ
35ꢀ
35ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ tsce
CEꢀtoꢀWriteꢀEndꢀ
ns
2
ꢀ tAw
ꢀ
AddressꢀSetupꢀTimeꢀꢀ
toꢀWriteꢀEnd
ns
ꢀ ꢀ
ꢀ tHA
ꢀ tsA
ꢀ tPwb
ꢀ tPwe1ꢀ
ꢀ tPwe
ꢀ tsd
ꢀ tHd
ꢀ
AddressꢀHoldꢀfromꢀWriteꢀEndꢀ
AddressꢀSetupꢀTimeꢀ
ꢀ
ꢀ
ꢀ
0ꢀ
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
9ꢀ
0ꢀ
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
0ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
30ꢀ ꢀ —ꢀ
30ꢀ ꢀ —ꢀ
30ꢀ ꢀ —ꢀ
15ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
—ꢀ ꢀ 20ꢀ
5ꢀ ꢀ —ꢀ
0ꢀ
0ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
20ꢀ
—ꢀ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ꢀ
3
ꢀ
LB,ꢀUBꢀValidꢀtoꢀEndꢀofꢀWriteꢀ
12ꢀ
18ꢀ
18ꢀ
20ꢀ
12ꢀ
0ꢀ
35ꢀ
35ꢀ
35ꢀ
20ꢀ
0ꢀ
WEꢀPulseꢀWidthꢀ(OEꢀ=ꢀHIGH)ꢀ ꢀ 12ꢀ
WEꢀPulseꢀWidthꢀ(OEꢀ=ꢀLOW)ꢀ ꢀ 17ꢀ
2
4
ꢀ
DataꢀSetupꢀtoꢀWriteꢀEndꢀ
ꢀ
ꢀ
ꢀ
ꢀ
9ꢀ
0ꢀ
ꢀ tHzwe(3)ꢀ WEꢀLOWꢀtoꢀHigh-ZꢀOutputꢀ
ꢀ tLzwe(3)ꢀ WEꢀHIGHꢀtoꢀLow-ZꢀOutputꢀ
Notes:ꢀ
—ꢀ
3ꢀ
—ꢀ ꢀ 12ꢀ
5ꢀ —ꢀ
—ꢀ
5ꢀ
5
—ꢀ
ꢀ
1.ꢀ TestꢀconditionsꢀforꢀIS61WV3216LLꢀassumeꢀsignalꢀtransitionꢀtimesꢀofꢀ1.5nsꢀorꢀless,ꢀtimingꢀreferenceꢀlevelsꢀofꢀ1.25V,ꢀinputꢀpulseꢀ
levelsꢀofꢀ0.4VꢀtoꢀVdd-0.3VꢀandꢀoutputꢀloadingꢀspecifiedꢀinꢀFigureꢀ1a.
2.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ1b.ꢀꢀTransitionꢀisꢀmeasuredꢀ 500ꢀmVꢀfromꢀsteady-stateꢀvoltage.ꢀNotꢀ100%ꢀtested.
3.ꢀ TheꢀinternalꢀwriteꢀtimeꢀisꢀdefinedꢀbyꢀtheꢀoverlapꢀofꢀCEꢀLOWꢀandꢀUBꢀorꢀLB,ꢀandꢀWEꢀLOW.ꢀꢀAllꢀsignalsꢀmustꢀbeꢀinꢀvalidꢀstatesꢀtoꢀ
initiateꢀaꢀWrite,ꢀbutꢀanyꢀoneꢀcanꢀgoꢀinactiveꢀtoꢀterminateꢀtheꢀWrite.ꢀꢀTheꢀDataꢀInputꢀSetupꢀandꢀHoldꢀtimingꢀareꢀreferencedꢀtoꢀtheꢀ
risingꢀorꢀfallingꢀedgeꢀofꢀtheꢀsignalꢀthatꢀterminatesꢀtheꢀwrite.
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.comꢀ
13
Rev. A
05/14/2012
IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
AC WAVEFORMS
WRITE CYCLE NO. 1ꢀ(CEꢀControlled,ꢀOEꢀisꢀHIGHꢀorꢀLOW)ꢀ(1ꢀ)
t
WC
VALID ADDRESS
SCE
ADDRESS
CE
t
SA
t
t
HA
t
AW
t
tPPWWEE21
WE
t
PWB
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR1.eps
Notes:ꢀ
1.ꢀ WRITEꢀisꢀanꢀinternallyꢀgeneratedꢀsignalꢀassertedꢀduringꢀanꢀoverlapꢀofꢀtheꢀLOWꢀstatesꢀonꢀtheꢀCEꢀandꢀWEꢀinputsꢀandꢀatꢀleastꢀ
oneꢀofꢀtheꢀLBꢀandꢀUBꢀinputsꢀbeingꢀinꢀtheꢀLOWꢀstate.
2.ꢀ WRITEꢀ=ꢀ(CE)ꢀ[ꢀ(LB)ꢀ=ꢀ(UB)ꢀ]ꢀ(WE).
WRITE CYCLE NO. 2ꢀ(WE Controlled.ꢀ OE isꢀHIGHꢀDuringꢀWriteꢀCycle)ꢀ(1,2)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
UB, LB
DOUT
t
SA
t
PWB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR2.eps
14ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
05/14/2012
IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
AC WAVEFORMS
WRITE CYCLE NO. 3ꢀ(WE Controlled.ꢀ OE isꢀLOWꢀDuringꢀWriteꢀCycle)ꢀ(1)
1
t
WC
2
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
LOW
3
CE
t
t
AW
t
PWE2
WE
t
SA
t
PWB
4
UB, LB
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
5
t
SD
t
HD
DATAIN VALID
DIN
UB_CEWR3.eps
6
WRITE CYCLE NO. 4ꢀ(LB, UB Controlled,ꢀBack-to-BackꢀWrite)ꢀ(1,3)
7
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
8
OE
CE
t
SA
LOW
9
t
HA
SA
t
HA
t
WE
t
PWB
t
PWB
10
11
12
UB, LB
WORD 1
WORD 2
t
HZWE
t
LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
UB_CEWR4.eps
Notes:ꢀ
1.ꢀ TheꢀꢀinternalꢀWriteꢀtimeꢀisꢀdefinedꢀbyꢀtheꢀoverlapꢀofꢀCEꢀ=ꢀLow, UBꢀand/orꢀLBꢀ=ꢀLow,ꢀandꢀWEꢀ=ꢀLOW.ꢀAllꢀsignalsꢀmustꢀbeꢀinꢀ
validꢀstatesꢀtoꢀinitiateꢀaꢀWrite,ꢀbutꢀanyꢀcanꢀbeꢀdeassertedꢀtoꢀterminateꢀtheꢀWrite.ꢀTheꢀtsA,ꢀtHA, tsd,ꢀandꢀtHdꢀtimingꢀisꢀreferencedꢀ
toꢀtheꢀrisingꢀorꢀfallingꢀedgeꢀofꢀtheꢀsignalꢀthatꢀterminatesꢀtheꢀWrite.
2.ꢀ TestedꢀwithꢀOEꢀHIGHꢀforꢀaꢀminimumꢀofꢀ4ꢀnsꢀbeforeꢀWEꢀ=ꢀLOWꢀtoꢀplaceꢀtheꢀI/OꢀinꢀaꢀHIGH-Zꢀstate.
3.ꢀ WEꢀmayꢀbeꢀheldꢀLOWꢀacrossꢀmanyꢀaddressꢀcyclesꢀandꢀtheꢀLB,ꢀUBꢀpinsꢀcanꢀbeꢀusedꢀtoꢀcontrolꢀtheꢀWriteꢀfunction.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
15
Rev. A
05/14/2012
IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
HIGH SPEED (IS61WV3216DALL/DBLL)
DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V)
Symbol
ꢀ ꢀ Vdrꢀ
Parameter
Test Condition
Options
Min.
2.0ꢀ
—ꢀ
Typ.(1)
—ꢀ
Max.
3.6ꢀ
40ꢀ
Unit
V
VddꢀforꢀDataꢀRetentionꢀ
DataꢀRetentionꢀCurrentꢀ
SeeꢀDataꢀRetentionꢀWaveformꢀ
Vddꢀ=ꢀ2.0V,ꢀCEꢀ≥ꢀVddꢀ–ꢀ0.2Vꢀ
ꢀ
ꢀ ꢀ Idrꢀ
Com.ꢀ
4ꢀ
µA
ꢀ
ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Ind.ꢀ
Auto.ꢀ
—ꢀ
ꢀ
—ꢀ
ꢀ
55ꢀ
90
ꢀ
ꢀ ꢀ tsdr
ꢀ ꢀ trdr
DataꢀRetentionꢀSetupꢀTimeꢀ SeeꢀDataꢀRetentionꢀWaveformꢀ
ꢀ
ꢀ
0ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
ns
ns
RecoveryꢀTimeꢀ
SeeꢀDataꢀRetentionꢀWaveformꢀ
trcꢀ
o
Note 1:ꢀTypicalꢀvaluesꢀareꢀmeasuredꢀatꢀVddꢀ=ꢀ3.0V,ꢀTA = 25 c andꢀnotꢀ100%ꢀtested.
DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V)
Symbol
ꢀ ꢀ Vdrꢀ
Parameter
Test Condition
Options
Min.
1.2ꢀ
—ꢀ
Typ.(1)
—ꢀ
Max.
3.6ꢀ
40ꢀ
Unit
V
VddꢀforꢀDataꢀRetentionꢀ
DataꢀRetentionꢀCurrentꢀ
SeeꢀDataꢀRetentionꢀWaveformꢀ
Vddꢀ=ꢀ1.2V,ꢀCEꢀ≥ꢀVddꢀ–ꢀ0.2Vꢀ
ꢀ
ꢀ ꢀ Idrꢀ
Com.ꢀ
4ꢀ
µA
ꢀ
ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Ind.ꢀ
Auto.ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
55ꢀ
90
ꢀ
ꢀ ꢀ tsdr
ꢀ ꢀ trdr
DataꢀRetentionꢀSetupꢀTimeꢀ SeeꢀDataꢀRetentionꢀWaveformꢀ
ꢀ
ꢀ
0ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
ns
ns
RecoveryꢀTimeꢀ
SeeꢀDataꢀRetentionꢀWaveformꢀ
trcꢀ
o
Note 1:ꢀTypicalꢀvaluesꢀareꢀmeasuredꢀatꢀVddꢀ=ꢀ1.8V,ꢀTA = 25 c andꢀnotꢀ100%ꢀtested.
DATA RETENTION WAVEFORM (CEꢀControlled)
t
SDR
Data Retention Mode
tRDR
VDD
VDR
CE ≥ VDD - 0.2V
CE
GND
16ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
05/14/2012
IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
LOW POWER (IS61WV3216DALS/DBLS)
1
DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V)
Symbol
ꢀ ꢀ Vdrꢀ
ꢀ ꢀ Idrꢀ
Parameter
Test Condition
Options
Min.
2.0ꢀ
—ꢀ
Typ.(1)
—ꢀ
Max.
3.6ꢀ
40ꢀ
Unit
V
VddꢀforꢀDataꢀRetentionꢀ
DataꢀRetentionꢀCurrentꢀ
SeeꢀDataꢀRetentionꢀWaveformꢀ
Vddꢀ=ꢀ2.0V,ꢀCEꢀ≥ꢀVddꢀ–ꢀ0.2Vꢀ
ꢀ
2
Com.ꢀ
4ꢀ
µA
ꢀ
ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Ind.ꢀ
Auto.ꢀ
—ꢀ
ꢀ
—ꢀ
ꢀ
50ꢀ
75
ꢀ
ꢀ ꢀ tsdr
ꢀ ꢀ trdr
DataꢀRetentionꢀSetupꢀTimeꢀ SeeꢀDataꢀRetentionꢀWaveformꢀ
ꢀ
ꢀ
0ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
ns
ns
3
RecoveryꢀTimeꢀ
SeeꢀDataꢀRetentionꢀWaveformꢀ
trcꢀ
o
Note 1:ꢀTypicalꢀvaluesꢀareꢀmeasuredꢀatꢀVddꢀ=ꢀ3.0V,ꢀTA = 25 c andꢀnotꢀ100%ꢀtested.
4
DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V)
Symbol
ꢀ ꢀ Vdrꢀ
ꢀ ꢀ Idrꢀ
Parameter
Test Condition
Options
Min.
1.2ꢀ
—ꢀ
Typ.(1)
—ꢀ
Max.
3.6ꢀ
40ꢀ
Unit
V
5
VddꢀforꢀDataꢀRetentionꢀ
DataꢀRetentionꢀCurrentꢀ
SeeꢀDataꢀRetentionꢀWaveformꢀ
Vddꢀ=ꢀ1.2V,ꢀCEꢀ≥ꢀVddꢀ–ꢀ0.2Vꢀ
ꢀ
ꢀ
ꢀ
Com.ꢀ
4ꢀ
µA
ꢀ
ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ
ꢀ
ꢀ
Ind.ꢀ
Auto.ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
50ꢀ
75
ꢀ
6
ꢀ ꢀ tsdr
ꢀ ꢀ trdr
DataꢀRetentionꢀSetupꢀTimeꢀ SeeꢀDataꢀRetentionꢀWaveformꢀ
ꢀ
ꢀ
0ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
ns
ns
RecoveryꢀTimeꢀ
SeeꢀDataꢀRetentionꢀWaveformꢀ
trcꢀ
o
Note 1:ꢀTypicalꢀvaluesꢀareꢀmeasuredꢀatꢀVddꢀ=ꢀ1.8V,ꢀTA = 25 c andꢀnotꢀ100%ꢀtested.
7
8
DATA RETENTION WAVEFORM (CEꢀControlled)
9
t
SDR
Data Retention Mode
tRDR
V
DD
10
11
12
VDR
CE ≥ VDD - 0.2V
CE
GND
Integrated Silicon Solution, Inc. — www.issi.comꢀ
17
Rev. A
05/14/2012
IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
ORDERING INFORMATION (HIGH SPEED)
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
ꢀ
ꢀ
8ꢀ
ꢀ
ꢀ
IS61WV3216DBLL-8BIꢀ
IS61WV3216DBLL-8BLIꢀ
IS61WV3216DBLL-8TIꢀ
IS61WV3216DBLL-8TLIꢀ
48ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm)ꢀ
48ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-freeꢀ
ꢀ
TSOPꢀ(TypeꢀII)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
TSOPꢀ(TypeꢀII),ꢀLead-freeꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
10ꢀ
IS61WV3216DBLL-10BIꢀ
IS61WV3216DBLL-10BLIꢀ
IS61WV3216DBLL-10TIꢀ
IS61WV3216DBLL-10TLIꢀ
48ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
48ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-freeꢀ
TSOPꢀ(TypeꢀII)ꢀ
ꢀ
ꢀ
ꢀ
TSOPꢀ(TypeꢀII),ꢀLead-freeꢀ
Industrial Range: -40°C to +85°C
Voltage Range: 1.65V to 2.2V
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
20ꢀ
ꢀ
IS61WV3216DALL-20BLIꢀ
IS61WV3216DALL-20TLIꢀ
48ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-freeꢀ
TSOPꢀ(TypeꢀII),ꢀLead-freeꢀꢀ
Automotive Range: -40°C to +125°C
Voltage Range: 2.4V to 3.6V
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
ꢀ
ꢀ
10ꢀ
IS64WV3216DBLL-10BA3ꢀ
IS64WV3216DBLL-10BLA3ꢀ
IS64WV3216DBLL-10CTA3ꢀ
48ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm)ꢀ
48ꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-freeꢀ
TSOPꢀ(TypeꢀII),ꢀCopperꢀLeadframeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
IS64WV3216DBLL-10CTLA3ꢀ TSOPꢀ(TypeꢀII),ꢀLead-free,ꢀCopperꢀLeadframe
ORDERING INFORMATION (LOW POWER - IN EVALUATION)
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
Speed (ns)
Order Part No.
Package
ꢀ
35ꢀ
IS61WV3216DBLS-35TLIꢀ TSOPꢀ(TypeꢀII),ꢀLead-freeꢀ
18ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
05/14/2012
IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
1
2
3
4
5
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.comꢀ
19
Rev. A
05/14/2012
IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
20ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
05/14/2012
相关型号：
IS61WV51216BLL-10MLI-TR
Standard SRAM, 512KX16, 10ns, CMOS, PBGA48, 9 X 11 MM, LEAD FREE, MBGA-48
ISSI
IS61WV51216BLL-10TLI-TR
Standard SRAM, 512KX16, 10ns, CMOS, PDSO44, LEAD FREE, PLASTIC, TSOP2-44
ISSI
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