IS62C1024AL-35QI [ISSI]
128K x 8 LOW POWER CMOS STATIC RAM; 128K ×8低功耗CMOS静态RAM
| 型号： | IS62C1024AL-35QI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 128K x 8 LOW POWER CMOS STATIC RAM |
| 文件： | 总11页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS62C1024AL
IS65C1024AL
ISSI
128K x 8 LOW POWER CMOS
STATIC RAM
JANUARY 2005
FEATURES
DESCRIPTION
TheISSIIS62C1024AL/IS65C1024ALisalowpower,131,072-
word by 8-bit CMOS static RAM. It is fabricated using high-
performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques,
yields higher performance and low power consumption
devices.
• High-speed access time: 35, 45 ns
• Low active power: 100 mW (typical)
• Low standby power: 20 µW (typical) CMOS
standby
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
WhenCE1isHIGHorCE2isLOW(deselected),thedevice
assumes a standby mode at which the power dissipation
can be reduced by using CMOS input levels.
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V (±10%) power supply
Easy memory expansion is provided by using two Chip
Enableinputs,CE1andCE2.TheactiveLOWWriteEnable
(WE) controls both writing and reading of the memory.
• Commercial, Industrial, and Automotive tem-
perature ranges available
• Standard Pin Configuration:
—
32-pin SOP/ 32-pin TSOP (Type 1)
• Lead free available
FUNCTIONAL BLOCK DIAGRAM
128K x 8
MEMORY ARRAY
A0-A16
DECODER
VDD
GND
I/O
DATA
CIRCUIT
COLUMN I/O
I/O0-I/O7
CE1
CONTROL
CIRCUIT
CE2
OE
WE
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany
publishedinformationandbeforeplacingordersforproducts.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
1
01/24/05
®
IS62C1024AL
IS65C1024AL
ISSI
PIN CONFIGURATION
32-Pin SOP
PIN CONFIGURATION
32-Pin TSOP (Type 1)
NC
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
A11
A9
A8
A13
WE
CE2
A15
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
A15
CE2
WE
A13
A8
2
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
3
3
4
4
5
5
A6
6
6
A5
7
A9
7
A4
8
A11
OE
V
DD
8
A3
9
NC
A16
A14
A12
A7
A6
A5
A4
9
A2
10
11
12
13
14
15
16
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
10
11
12
13
14
15
16
A1
A0
I/O0
I/O1
I/O2
GND
A1
A2
A3
PIN DESCRIPTIONS
A0-A16
CE1
Address Inputs
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
Write Enable Input
Input/Output
OPERATING RANGE (IS62C1024AL)
CE2
OE
Range
Commercial 0°C to +70°C
Industrial -40°Cto+85°C
AmbientTemperature
VDD
WE
5V ± 10%
5V ± 10%
I/O0-I/O7
VDD
Power
GND
Ground
OPERATING RANGE (IS65C1024AL)
Range
AmbientTemperature
VDD
Automotive
-40°Cto+125°C
5V ± 10%
TRUTH TABLE
Mode
WE
CE1
CE2
OE
I/OOperation
VDD Current
Not Selected
(Power-down)
X
X
H
X
X
L
X
X
High-Z
High-Z
ISB1, ISB2
ISB1, ISB2
OutputDisabled
Read
H
H
L
L
L
L
H
H
H
H
L
High-Z
DOUT
DIN
ICC
ICC
ICC
Write
X
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/24/05
®
IS62C1024AL
IS65C1024AL
ISSI
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TSTG
PT
Parameter
Value
–0.5 to +7.0
–65 to +125
1.0
Unit
V
Terminal Voltage with Respect to GND
StorageTemperature
PowerDissipation
°C
W
IOUT
DCOutputCurrent(LOW)
20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
InputCapacitance
OutputCapacitance
6
8
COUT
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 5.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
TestConditions
Options
Min.
Max.
Unit
VOH
VOL
VIH
VIL
ILI
OutputHIGHVoltage
VDD = Min., IOH = –1.0 mA
VDD = Min., IOL = 2.1 mA
2.4
—
—
0.4
V
V
OutputLOWVoltage
Input HIGH Voltage
Input LOW Voltage(1)
InputLeakage
2.2
-0.5
VDD + 0.5
0.8
V
V
GND ≤ VIN ≤ VDD
Com.
Ind.
Auto.
-1
-2
-5
1
2
5
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD
CE1 = VIH, or
CE2 = VIL, or OE = VIH or
WE = VIL
Com.
Ind.
Auto.
-1
-2
-5
1
2
5
µA
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
3
01/24/05
®
IS62C1024AL
IS65C1024AL
ISSI
IS62C1024AL/IS65C1024AL
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-35 ns
Min. Max.
-45 ns
Min. Max.
Symbol Parameter
TestConditions
Unit
ICC
Averageoperating
Current
CE1=VIL,CE2=VIH
Com.
Ind.
—
—
25
30
mA
V
IN =VIHorVIL
,
II/O=0mA
Auto.
—
—
35
40
I
CC
1
VDD DynamicOperating
V
DD =Max.,CE1=VIL
OUT =0mA, f=fMAX
IN =VIH orVIL
CE2=VIH
Com.
Ind.
—
—
30
35
mA
SupplyCurrent
I
V
Auto.
typ.(2)
—
20
I
SB
1
TTLStandbyCurrent
(TTLInputs)
V
DD=Max.,
Com.
Ind.
Auto.
—
—
1
1.5
mA
µA
VIN =VIHorVIL,CE1≥VIH
,
orCE2≤VIL,f=0
DD=Max.,
CE1≥ VDD –0.2V,or
—
—
2
ISB
2
CMOSStandby
Current(CMOSInputs)
V
Com.
Ind.
—
—
5
10
CE2≤0.2V,VIN ≥VDD –0.2V,
orVIN ≤VSS +0.2V, f=0
Auto.
15
typ.(2)
—
4
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical Values are measured at VDD = 5V, TA = 25oC and not 100% tested.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-35 ns
-45 ns
Symbol
tRC
Parameter
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
35
—
3
—
35
—
35
35
10
—
10
—
—
10
45
—
3
—
45
—
45
45
20
—
15
—
—
15
tAA
Address Access Time
Output Hold Time
tOHA
tACE1
tACE2
tDOE
CE1 Access Time
CE2 Access Time
OE Access Time
—
—
—
3
—
—
—
5
(2)
tLZOE
OE to Low-Z Output
OE to High-Z Output
CE1 to Low-Z Output
CE2 to Low-Z Output
CE1 or CE2 to High-Z Output
(2)
tHZOE
0
0
tLZCE1(2)
tLZCE2(2)
3
5
3
5
(2)
tHZCE
0
0
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of
0.6 to 2.4V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/24/05
®
IS62C1024AL
IS65C1024AL
ISSI
AC TEST CONDITIONS
Parameter
Unit
0.6V to 2.4V
5 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
andReferenceLevel
1.5V
OutputLoad
See Figures 1a and 1b
AC TEST LOADS
1838 Ω
1838 Ω
5V
5V
OUTPUT
OUTPUT
993 Ω
993 Ω
100 pF
Including
jig and
5 pF
Including
jig and
scope
scope
Figure1a.
Figure1b.
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
5
01/24/05
®
IS62C1024AL
IS65C1024AL
ISSI
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
CE1
t
LZOE
t
ACE1/tACE2
CE2
tLZCE1/
tLZCE2
t
HZCE
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low Power)
-35 ns
-45 ns
Symbol
tWC
Parameter
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
35
25
25
25
0
—
—
—
—
—
—
—
—
—
10
—
45
35
35
35
0
—
—
—
—
—
—
—
—
—
15
—
tSCE1
tSCE2
tAW
CE1 to Write End
CE2 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width
tHA
tSA
0
0
(4)
tPWE
25
20
0
35
25
0
tSD
tHD
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
(2)
tHZWE
—
3
—
5
(2)
tLZWE
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.6 to 2.4V
and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/24/05
®
IS62C1024AL
IS65C1024AL
ISSI
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
t
WC
ADDRESS
CE1
t
HA
t
SCE1
t
SCE2
CE2
t
AW
(4)
t
PWE
WE
DOUT
DIN
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
t
SD
t
HD
DATA-IN VALID
WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2)
t
WC
ADDRESS
t
SA
t
HA
t
SCE1
CE1
t
SCE2
CE2
t
AW
(4)
t
PWE
WE
DOUT
DIN
t
HZWE
tLZWE
HIGH-Z
SD
DATA-IN VALID
DATA UNDEFINED
t
HD
t
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIH.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
7
01/24/05
®
IS62C1024AL
IS65C1024AL
ISSI
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter
DD forDataRetention
TestCondition
Min.
Typ.
Max. Unit
VDR
V
SeeDataRetentionWaveform
2.0
5.5
V
IDR
DataRetentionCurrent
V
DD =2.0V,CE1≥VDD –0.2V
Com.
Ind.
—
—
—
—
5
10
µA
or CE2 ≤ 0.2V
VIN ≥ VDD – 0.2V, or VIN
≤
VSS + 0.2V
Auto.
—
0
—
15
—
—
t
SDR
DataRetentionSetupTime
RecoveryTime
SeeDataRetentionWaveform
SeeDataRetentionWaveform
ns
ns
tRDR
tRC
Note:
1.TypicalValuesaremeasuredatVDD =5V,T
A
=25oCandnot100%tested.
DATA RETENTION WAVEFORM (CE1 Controlled)
t
Data Retention Mode
t
RDR
SDR
VDD
4.5V
2.2V
V
DR
CE1 ≥ VDD - 0.2V
CE1
GND
DATA RETENTION WAVEFORM (CE2 Controlled)
Data Retention Mode
VDD
CE2
4.5V
2.2V
t
t
RDR
SDR
V
DR
CE2 ≤ 0.2V
0.4V
GND
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
01/24/05
®
IS62C1024AL
IS65C1024AL
ISSI
ORDERING INFORMATION: IS62C1024AL
Commercial Range: 0°C to +70°C
Speed(ns)
Order Part No.
Package
35
35
IS62C1024AL-35Q
IS62C1024AL-35T
Plastic SOP
TSOP, Type 1
Industrial Range: –40°C to +85°C
Speed(ns)
Order Part No.
Package
35
35
35
35
IS62C1024AL-35QI
IS62C1024AL-35QLI
IS62C1024AL-35TI
IS62C1024AL-35TLI
Plastic SOP
Plastic SOP, Lead-free
TSOP, Type 1
TSOP, Type 1, Lead-free
ORDERING INFORMATION: IS65C1024AL
Automotive Range: -40°C to +125°C
Speed(ns)
Order Part No.
IS65C1024AL-45QA3 Plastic SOP
IS65C1024AL-45TA3 TSOP, Type 1
Package
45
45
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
9
01/24/05
®
PACKAGING INFORMATION
450-mil Plastic SOP
ISSI
Package Code: Q (32-pin)
N
E1 E
1
D
SEATING PLANE
A
S
L
α
e
B
C
A1
Notes:
MILLIMETERS
INCHES
1. Controlling dimension: inches, unless
otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold
flash protrusions and should be measured
from the bottom of the package.
4. Formed leads shall be planar with respect to
one another within 0.004 inches at the
seating plane.
Symbol
Min.
Max.
Min.
Max.
No. Leads
32
A
A1
B
C
D
E
—
0.10
0.36
0.15
20.14
13.87
11.18
3.00
—
—
0.118
—
0.004
0.014
0.006
0.793
0.546
0.440
0.51
0.30
20.75
14.38
11.43
0.020
0.012
0.817
0.566
0.450
E1
e
1.27 BSC
0.050 BSC
L
α
0.58
0°
0.99
10°
0.023
0°
0.039
10°
S
—
0.86
—
0.034
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
06/13/03
®
PACKAGING INFORMATION
ISSI
Plastic TSOP-Type I
Package Code: T (32-pin)
1
E
H
N
D
SEATING PLANE
A
S
L
α
e
B
C
A1
Notes:
MILLIMETERS
INCHES
1. Controlling dimension: millimeters, unless
otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold
flash protrusions and should be measured
from the bottom of the package.
4. Formed leads shall be planar with respect
to one another within 0.004 inches at the
seating plane.
Symbol
Min.
Max.
Min.
Max.
No. Leads
32
A
A1
B
C
D
E
H
e
—
1.20
0.25
0.23
0.17
8.10
—
0.047
0.010
0.009
0.007
0.319
0.728
0.795
0.05
0.17
0.12
7.90
18.30
19.80
0.002
0.007
0.005
0.311
0.720
0.780
18.50
20.20
0.50 BSC
0.020 BSC
L
α
0.40
0°
0.60
8°
0.016
0°
0.024
8°
S
0.25 REF
0.010 REF
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
06/13/03
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