IS62C1024L-70QI [ISSI]
128K x 8 LOW POWER CMOS STATIC RAM; 128K ×8低功耗CMOS静态RAM
| 型号： | IS62C1024L-70QI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 128K x 8 LOW POWER CMOS STATIC RAM |
| 文件： | 总11页 (文件大小：66K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS62C1024L
ISSI
128K x 8 LOW POWER CMOS STATIC RAM
DECEMBER 2003
FEATURES
DESCRIPTION
The ISSI IS62C1024L is a low power,131,072-word by 8-bit
CMOS static RAM. It is fabricated using ISSI's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields higher
performance and low power consumption devices.
• High-speed access time: 35, 70 ns
• Low active power: 450 mW (typical)
• Low standby power: 150 µW (typical) CMOS
standby
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
When CE1 is HIGH or CE2 is LOW (deselected), the
device assumes a standby mode at which the power
dissipation can be reduced by using CMOS input levels.
• Fully static operation: no clock or refresh
required
Easy memory expansion is provided by using two Chip
Enable inputs, CE1 and CE2. The active LOW Write
Enable (WE) controls both writing and reading of the
memory.
• TTL compatible inputs and outputs
• Single 5V (±10%) power supply
The IS62C1024L is available in 32-pin plastic SOP and
TSOP (type 1) packages.
FUNCTIONAL BLOCK DIAGRAM
128K x 8
MEMORY ARRAY
A0-A16
DECODER
VDD
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE1
CONTROL
CIRCUIT
CE2
OE
WE
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany
publishedinformationandbeforeplacingordersforproducts.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
1
11/26/03
®
IS62C1024L
ISSI
PIN CONFIGURATION
32-Pin SOP
PIN CONFIGURATION
32-Pin TSOP (Type 1)
NC
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
A15
CE2
WE
A13
A8
A11
A9
A8
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
2
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
3
3
4
A13
WE
CE2
A15
VDD
NC
A16
A14
A12
A7
4
5
ISSI
5
A6
6
62C1024L
6
A5
7
A9
7
A4
8
A11
OE
8
A3
9
9
A2
10
11
12
13
14
15
16
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
10
11
12
13
14
15
16
A1
A0
I/O0
I/O1
I/O2
GND
A6
A5
A4
A1
A2
A3
PIN DESCRIPTIONS
OPERATING RANGE
A0-A16
CE1
Address Inputs
Range
Ambient Temperature
VDD
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
Write Enable Input
Input/Output
Commercial
Industrial
0°C to +70°C
5V ± 10%
5V ± 10%
CE2
–40°Cto+85°C
OE
WE
I/O0-I/O7
VDD
Power
GND
Ground
TRUTH TABLE
Mode
WE CE1 CE2 OE
I/OOperation
VDD Current
Not Selected
(Power-down)
X
X
H
X
X
L
X
X
High-Z
High-Z
ISB1, ISB2
ISB1, ISB2
OutputDisabled
Read
H
H
L
L
L
L
H
H
H
H
L
High-Z
DOUT
DIN
ICC
ICC
ICC
Write
X
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03
®
IS62C1024L
ISSI
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–0.5 to +7.0
–65 to +150
1.5
Unit
V
VTERM
TSTG
PT
Terminal Voltage with Respect to GND
StorageTemperature
°C
PowerDissipation
W
IOUT
DCOutputCurrent(LOW)
20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
InputCapacitance
OutputCapacitance
6
8
COUT
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 5.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
VOH
VOL
VIH
VIL
ILI
OutputHIGHVoltage
VDD = Min., IOH = –1.0 mA
VDD = Min., IOL = 2.1 mA
2.4
—
—
0.4
V
V
OutputLOWVoltage
Input HIGH Voltage
Input LOW Voltage(1)
InputLeakage
2.2
–0.3
VDD + 0.5
0.8
V
V
GND ≤ VIN ≤ VDD
GND ≤ VOUT ≤ VDD
Com.
Ind.
–2
–10
2
10
µA
ILO
OutputLeakage
Com.
Ind.
–2
–10
2
10
µA
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
3
11/26/03
®
IS62C1024L
ISSI
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-35ns
Min. Max.
-70ns
Min. Max.
Symbol Parameter
DD DynamicOperating
TestConditions
DD =Max.,CE=VIL
OUT =0mA,f=fMAX
Unit
ICC
V
V
I
Com.
Ind.
—
—
100
110
—
—
70
80
mA
SupplyCurrent
I
SB
1
TTLStandbyCurrent
(TTLInputs)
V
DD=Max.,
Com.
Ind.
—
—
10
15
—
—
10
15
mA
µA
VIN =VIHorVIL,CE1≥VIH
,
orCE2≤VIL,f=0
DD=Max.,
CE1≤VDD –0.2V,
ISB
2
CMOSStandby
Current(CMOSInputs)
V
Com.
Ind.
—
—
500
750
—
—
500
750
CE2≤0.2V,VIN ≥VDD –0.2V,
orVIN ≤0.2V, f=0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-35
-70
Min.
Symbol
Parameter
Min.
35
—
3
Max.
—
35
—
35
35
10
—
10
—
—
10
Max.
—
70
—
70
70
35
—
25
—
—
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
AA
OHA
ACE
ACE
DOE
ReadCycleTime
70
—
3
t
AddressAccessTime
OutputHoldTime
t
t
1
CE1AccessTime
CE2AccessTime
OEAccessTime
—
—
—
0
—
—
—
0
t
2
t
(2)
tLZOE
OEtoLow-ZOutput
OEtoHigh-ZOutput
CE1toLow-ZOutput
CE2toLow-ZOutput
CE1orCE2toHigh-ZOutput
(2)
t
HZOE
LZCE1(2)
LZCE2(2)
0
0
t
3
10
10
0
t
3
(2)
tHZCE
0
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
outputloadingspecifiedinFigure1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03
®
IS62C1024L
ISSI
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
5 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1a and 1b
AC TEST LOADS
480 Ω
480 Ω
5V
5V
OUTPUT
OUTPUT
255 Ω
255 Ω
100 pF
Including
jig and
5 pF
Including
jig and
scope
scope
Figure 1a.
Figure 1b.
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
DOUT
t
AA
t
OHA
t
OHA
DATA VALID
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
5
11/26/03
®
IS62C1024L
ISSI
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
LZOE
CE1
t
ACE1/tACE2
CE2
tLZCE1/
tLZCE2
t
HZCE
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low Power)
-35
Min.
-70
Min.
Symbol
Parameter
Max.
—
—
—
—
—
—
—
—
—
10
—
Max.
—
—
—
—
—
—
—
—
—
25
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
WC
SCE
SCE
AW
HA
SA
WriteCycleTime
35
25
25
25
0
70
60
60
60
0
t
1
CE1toWriteEnd
t
2
CE2toWriteEnd
t
AddressSetupTimetoWriteEnd
AddressHoldfromWriteEnd
AddressSetupTime
WEPulseWidth
t
t
0
0
(4)
t
PWE
SD
HD
HZWE
25
20
0
50
30
0
t
DataSetuptoWriteEnd
DataHoldfromWriteEnd
WELOWtoHigh-ZOutput
WEHIGHtoLow-ZOutput
t
(2)
t
—
3
—
5
(2)
tLZWE
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
outputloadingspecifiedinFigure1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03
®
IS62C1024L
ISSI
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
t
WC
ADDRESS
CE1
t
HA
t
SCE1
t
SCE2
CE2
t
AW
(4)
t
PWE
WE
DOUT
DIN
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
t
SD
t
HD
DATA-IN VALID
WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2)
t
WC
ADDRESS
t
SA
t
HA
t
SCE1
CE1
t
SCE2
CE2
t
AW
(4)
t
PWE
WE
DOUT
DIN
t
HZWE
tLZWE
HIGH-Z
SD
DATA-IN VALID
DATA UNDEFINED
t
HD
t
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIH.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
7
11/26/03
®
IS62C1024L
ISSI
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
DD forDataRetention
TestCondition
Min.
Typ.
Max.
Unit
V
VDR
V
SeeDataRetentionWaveform
2.0
5.5
IDR
DataRetentionCurrent
VDD =3.0V,CE1≥VDD –0.2V
Com.
Ind.
—
—
45
60
250
400
µA
t
SDR
DataRetentionSetupTime
RecoveryTime
SeeDataRetentionWaveform
SeeDataRetentionWaveform
0
—
—
ns
ns
tRDR
t
RC
DATA RETENTION WAVEFORM (CE1 Controlled)
t
Data Retention Mode
t
RDR
SDR
VDD
4.5V
2.2V
V
DR
CE1 ≥ VDD - 0.2V
CE1
GND
DATA RETENTION WAVEFORM (CE2 Controlled)
Data Retention Mode
VDD
CE2
4.5V
2.2V
t
t
RDR
SDR
V
DR
CE2 ≤ 0.2V
0.4V
GND
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
11/26/03
®
IS62C1024L
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed(ns)
Order Part No.
Package
35
35
IS62C1024L-35Q
IS62C1024L-35T
Plastic SOP
TSOP, Type 1
70
70
IS62C1024L-70Q
IS62C1024L-70T
Plastic SOP
TSOP, Type 1
Industrial Range: –40°C to +85°C
Speed(ns)
Order Part No.
Package
35
35
IS62C1024L-35QI
IS62C1024L-35TI
Plastic SOP
TSOP, Type 1
70
70
IS62C1024L-70QI
IS62C1024L-70TI
Plastic SOP
TSOP, Type 1
®
ISSI
IntegratedSiliconSolution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. E
9
11/26/03
®
PACKAGING INFORMATION
450-mil Plastic SOP
ISSI
Package Code: Q (32-pin)
N
E1 E
1
D
SEATING PLANE
A
S
L
α
e
B
C
A1
Notes:
MILLIMETERS
INCHES
1. Controlling dimension: inches, unless
otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold
flash protrusions and should be measured
from the bottom of the package.
4. Formed leads shall be planar with respect to
one another within 0.004 inches at the
seating plane.
Symbol
Min.
Max.
Min.
Max.
No. Leads
32
A
A1
B
C
D
E
—
0.10
0.36
0.15
20.14
13.87
11.18
3.00
—
—
0.118
—
0.004
0.014
0.006
0.793
0.546
0.440
0.51
0.30
20.75
14.38
11.43
0.020
0.012
0.817
0.566
0.450
E1
e
1.27 BSC
0.050 BSC
L
α
0.58
0°
0.99
10°
0.023
0°
0.039
10°
S
—
0.86
—
0.034
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
06/13/03
®
PACKAGING INFORMATION
ISSI
Plastic TSOP-Type I
Package Code: T (32-pin)
1
E
H
N
D
SEATING PLANE
A
S
L
α
e
B
C
A1
Notes:
MILLIMETERS
INCHES
1. Controlling dimension: millimeters, unless
otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold
flash protrusions and should be measured
from the bottom of the package.
4. Formed leads shall be planar with respect
to one another within 0.004 inches at the
seating plane.
Symbol
Min.
Max.
Min.
Max.
No. Leads
32
A
A1
B
C
D
E
H
e
—
1.20
0.25
0.23
0.17
8.10
—
0.047
0.010
0.009
0.007
0.319
0.728
0.795
0.05
0.17
0.12
7.90
18.30
19.80
0.002
0.007
0.005
0.311
0.720
0.780
18.50
20.20
0.50 BSC
0.020 BSC
L
α
0.40
0°
0.60
8°
0.016
0°
0.024
8°
S
0.25 REF
0.010 REF
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
06/13/03
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