IS62C256AL-25TI [ISSI]
32K x 8 LOW POWER CMOS STATIC RAM; 32K ×8低功耗CMOS静态RAM
| 型号： | IS62C256AL-25TI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 32K x 8 LOW POWER CMOS STATIC RAM |
| 文件： | 总12页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS65C256AL
IS62C256AL
ISSI
32K x 8 LOW POWER CMOS STATIC RAM
MARCH 2006
FEATURES
DESCRIPTION
The ISSI IS62C256AL/IS65C256AL is a low power,
32,768 word by 8-bit CMOS static RAM. It is fabricated
using ISSI's high-performance, low power CMOS tech-
nology.
• Access time: 25 ns, 45 ns
• Low active power: 200 mW (typical)
• Low standby power
— 150 µW (typical) CMOS standby
— 15 mW (typical) operating
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 150 µW (typical) at CMOS input levels.
• Fully static operation: no clock or refresh
required
Easy memory expansion is provided by using an active
LOW Chip Select (CE) input and an active LOW Output
Enable (OE) input. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
• TTL compatible inputs and outputs
• Single 5V power supply
• Lead-free available
• Industrial and Automotive temperatures avail-
able
The IS62C256AL/IS65C256AL is pin compatible with
other 32Kx8 SRAMs in plastic SOP or TSOP (Type I)
package.
FUNCTIONAL BLOCK DIAGRAM
32K X 8
MEMORY ARRAY
A0-A14
DECODER
VDD
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE
CONTROL
CIRCUIT
OE
WE
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arisingoutoftheapplicationoruseofanyinformation, productsorservicesdescribedherein. Customersareadvisedtoobtainthelatestversionofthisdevicespecificationbeforerelyingonany
publishedinformationandbeforeplacingordersforproducts.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
1
Rev. A
03/17/06
®
IS65C256AL
IS62C256AL
ISSI
PIN CONFIGURATION
28-Pin TSOP
PIN CONFIGURATION
28-Pin SOP
OE
A11
A9
22
23
24
25
26
27
28
1
2
3
4
5
21
20
19
18
17
16
15
14
13
12
11
10
9
A10
CE
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
WE
A13
A8
2
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
3
A8
A6
4
A13
WE
VDD
A14
A12
A7
A6
A5
A4
A3
A5
5
A9
A4
6
A11
OE
A3
7
A2
8
A10
CE
A1
9
A0
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
6
7
A1
A2
I/O0
I/O1
I/O2
GND
8
PIN DESCRIPTIONS
TRUTH TABLE
A0-A14
CE
Address Inputs
Mode
WE
CE
OE I/O Operation VDD Current
Chip Select Input
Output Enable Input
Write Enable Input
Input/Output
Not Selected
(Power-down)
X
H
X
High-Z
ISB1, ISB2
OE
Output Disabled
Read
H
H
L
L
L
L
H
L
High-Z
DOUT
DIN
ICC1, ICC2
ICC1, ICC2
ICC1, ICC2
WE
I/O0-I/O7
VDD
Write
X
Power
GND
Ground
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
VTERM
TSTG
PT
Terminal Voltage with Respect to GND
Storage Temperature
–0.5 to +7.0
–65 to +150
0.5
V
°C
W
Power Dissipation
IOUT
DC Output Current (LOW)
20
mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
thisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextended
periods may affect reliability.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
®
IS65C256AL
IS62C256AL
ISSI
OPERATING RANGE
Part No.
IS62C256AL
IS62C256AL
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VDD
5V 10%
5V 10%
–40°C to +85°C
IS65C256AL
Automotive
–40°C to +125°C
5V 10%
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter
Test Conditions
Min.
2.4
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
VDD = Min., IOH = –1.0 mA
VDD = Min., IOL = 2.1 mA
—
0.4
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
—
V
2.2
VDD + 0.5
0.8
V
–0.3
V
GND ≤ VIN ≤ VDD
Com.
Ind.
–1
–2
1
2
µA
Auto.
–10
10
ILO
Output Leakage
GND ≤ VOUT ≤ VDD,
Outputs Disabled
Com.
Ind.
–1
–2
1
2
µA
Auto.
–10
10
Note: 1. VIL = –3.0V for pulse width less than 10 ns.
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. A
03/17/06
®
IS65C256AL
IS62C256AL
ISSI
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-25 ns
-45 ns
Min. Max.
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
ICC1
VDD Operating
Supply Current
VDD = Max., CE = VIL
IOUT = 0 mA, f = 0
Com.
Ind.
Auto.
—
—
—
15
20
25
—
—
—
15
20
25
mA
ICC2
VDD Dynamic Operating
Supply Current
VDD = Max., CE = VIL
IOUT = 0 mA, f = fMAX
Com.
Ind.
—
—
—
25
30
35
—
—
—
20
25
30
mA
Auto.
typ. (2)
15
12
ISB1
ISB2
TTL Standby Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
Com.
Ind.
Auto.
—
—
—
100
120
150
—
—
—
100
120
150
µA
µA
CMOS Standby
Current (CMOS Inputs)
VDD = Max.,
Com.
Ind.
—
—
—
15
20
50
—
—
—
15
20
50
CE ≥ VDD – 0.2V,
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
Auto.
(2)
typ.
5
5
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 5.0V, TA = 25oC and not 100% tested.
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
8
Unit
pF
InputCapacitance
OutputCapacitance
COUT
VOUT = 0V
10
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 5.0V.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
®
IS65C256AL
IS62C256AL
ISSI
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-25 ns
-45 ns
Symbol
tRC
Parameter
Min. Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address Access Time
Output Hold Time
CE Access Time
OE Access Time
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
CE toPower-Up
25
—
2
—
25
—
25
13
—
12
—
12
—
20
45
—
2
—
tAA
45
—
tOHA
tACS
—
—
0
—
—
0
45
25
—
tDOE
(2)
tLZOE
(2)
tHZOE
0
0
20
—
(2)
tLZCS
3
3
(2)
tHZCS
0
0
20
—
(3)
tPU
0
0
(3)
tPD
CEtoPower-Down
—
—
30
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Unit
0V to 3.0V
3 ns
Input and Output Timing
and Reference Levels
1.5V
Output Load
See Figures 1 and 2
AC TEST LOADS
480 Ω
480 Ω
5V
5V
OUTPUT
OUTPUT
255 Ω
255 Ω
100 pF
5 pF
Including
jig and
scope
Including
jig and
scope
Figure 1.
Figure 2.
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. A
03/17/06
®
IS65C256AL
IS62C256AL
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
t
LZOE
ACS
CE
t
HZCS
t
LZCS
HIGH-Z
D
OUT
DATA VALID
CS_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
®
IS65C256AL
IS62C256AL
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-25ns
Min. Max.
-45 ns
Min. Max.
Symbol
tWC
Parameter
Unit
ns
Write Cycle Time
25
15
15
0
—
—
—
—
—
—
45
35
25
0
—
—
—
—
—
—
tSCS
tAW
CE to Write End
ns
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width
ns
tHA
ns
tSA
0
0
ns
tPWE1,
15
25
ns
tPWE2(4)
tSD
tHD
Data Setup to Write End
Data Hold from Write End
12
0
—
—
20
0
—
—
ns
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1(CE Controlled, OE is HIGH or LOW) (1 )
t
WC
VALID ADDRESS
SCS
ADDRESS
t
SA
t
t
HA
CE
t
AW
t
tPPWWEE21
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CS_WR1.eps
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. A
03/17/06
®
IS65C256AL
IS62C256AL
AC WAVEFORMS
ISSI
WRITE CYCLE NO. 2(OE is HIGH During Write Cycle) (1,2)
t
WC
ADDRESS
VALID ADDRESS
t
HA
OE
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CS_WR2.eps
WRITE CYCLE NO. 3(OE is LOW During Write Cycle) (1)
t
WC
ADDRESS
VALID ADDRESS
t
HA
LOW
LOW
OE
CE
t
t
AW
t
PWE2
WE
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CS_WR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
2. I/O will assume the High-Z state if OE = VIH.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
®
IS65C256AL
IS62C256AL
ISSI
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter
TestCondition
Min.
Typ.
Max. Unit
VDR
VDD for Data Retention
See Data Retention Waveform
2.0
5.5
V
IDR
Data Retention Current
V
DD = 2.0V, CE ≥ VDD – 0.2V
Com.
Ind.
—
—
—
—
15
20
µA
VIN ≥ VDD – 0.2V, or VIN
≤ VSS + 0.2V
Auto.
—
0
—
50
—
—
t
SDR
RDR
Data Retention Setup Time See Data Retention Waveform
Recovery Time See Data Retention Waveform
ns
ns
t
t
RC
Note:
1. Typical Values are measured at VDD = 5V, T
= 25oC and not 100% tested.
A
DATA RETENTION WAVEFORM (CE Controlled)
t
Data Retention Mode
t
RDR
SDR
VDD
4.5V
2.2V
V
DR
CE ≥ VDD - 0.2V
CE
GND
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. A
03/17/06
®
IS65C256AL
IS62C256AL
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed
(ns)
Order Part No.
Package
45
IS62C256AL-45T
IS62C256AL-45TL
IS62C256AL-45U
IS62C256AL-45UL
TSOP
TSOP, Lead-free
Plastic SOP
Plastic SOP, Lead-free
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed
(ns)
Order Part No.
Package
25
IS62C256AL-25TI
IS62C256AL-25UI
TSOP
Plastic SOP
45
IS62C256AL-45TI
IS62C256AL-45TLI
IS62C256AL-45UI
IS62C256AL-45ULI
TSOP
TSOP, Lead-free
Plastic SOP
Plastic SOP, Lead-free
ORDERING INFORMATION
Automotive Range: –40°C to +125°C
Speed
(ns)
Order Part No.
Package
25
IS65C256AL-25TA3
TSOP
IS65C256AL-25TLA3 TSOP, Lead-free
IS65C256AL-25UA3 Plastic SOP
IS65C256AL-25ULA3 Plastic SOP, Lead-free
45
IS65C256AL-45TA3 TSOP
IS65C256AL-45TLA3 TSOP, Lead-free
IS65C256AL-45UA3 Plastic SOP
IS65C256AL-45ULA3 Plastic SOP, Lead-free
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06
®
PACKAGINGINFORMATION
ISSI
Plastic TSOP - 28-pins
Package Code: T (Type I)
1
E
H
N
D
SEATING PLANE
A
S
L
α
e
B
C
A1
Plastic TSOP (T—Type I)
Millimeters
Inches
Symbol
Min
Max
Min
Max
Ref. Std.
No. Leads
Notes:
28
1. Controlling dimension: millimeters, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold flash protrusions and
A
A1
B
C
D
E
H
e
1.00
0.05
0.16
0.10
7.90
11.70
13.20
0.55 BSC
1.20
0.20
0.27
0.20
8.10
0.037
0.002
0.006
0.004
0.308
0.456
0.515
0.047
0.008
0.011
0.008
0.316
0.465
0.531
should be measured from the bottom of the package
.
4. Formed leads shall be planar with respect to one another within
0.004 inches at the seating plane.
11.90
13.60
0.022 BSC
L
0.30
0.70
0.011
0.027
α
0°
5°
0°
5°
Integrated Silicon Solution, Inc.
PK13197T28 Rev. B 01/31/97
®
PACKAGINGINFORMATION
330-mil Plastic SOP
ISSI
Package Code: U (28-pin)
N
E1 E
1
D
SEATING PLANE
A
h x 45o
S
L
α
e
B
C
A1
Notes:
MILLIMETERS
INCHES
1. Controlling dimension: inches, unless
otherwise specified.
2. BSC = Basic lead spacing between
centers.
3. Dimensions D and E1 do not include
mold flash protrusions and should be
measured from the bottom of the
package.
4. Formed leads shall be planar with
respect to one another within 0.004
inches at the seating plane.
Sym. Min.
Max.
Min. Max.
28
No. Leads 28
A
—
2.84
—
—
0.112
—
A1
B
0.10
0.36
0.25
0.004
0.51
—
0.014 0.020
0.010
C
D
E
—
17.98 18.24
11.51 12.12
0.708 0.718
0.453 0.477
0.326 0.336
0.050 BSC
E1
e
8.28
8.53
1.27 BSC
h
0.30
0.71
0o
0.51
0.012 0.020
0.028 0.045
L
1.14
8o
α
0o
8o
S
0.58
1.19
0.023 0.047
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
02/26/03
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