IS62C51216AL [ISSI]
512K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM; 512K ×16低电压，超低功耗CMOS静态RAM
| 型号： | IS62C51216AL |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 512K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM |
| 文件： | 总15页 (文件大小：438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS62C51216AL
IS65C51216AL
512K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
APRIL 2009
FEATURES
DESCRIPTION
TheꢀISSIꢀIS62C51216ALꢀandꢀIS65C51216ALꢀareꢀꢀhigh-
speed,ꢀ8MꢀbitꢀstaticꢀRAMsꢀorganizedꢀasꢀ512Kꢀwordsꢀbyꢀ16ꢀ
bits. It is fabricated using ISSI'sꢀhigh-performanceꢀCMOSꢀ
technology.ꢀ Thisꢀ highlyꢀ reliableꢀ processꢀ coupledꢀ withꢀ
innovativeꢀcircuitꢀdesignꢀtechniques,ꢀyieldsꢀhigh-performanceꢀ
and low power consumption devices.
•ꢀ High-speedꢀaccessꢀtime:ꢀ45ns,ꢀ55ns
•ꢀ CMOSꢀlowꢀpowerꢀoperation
– 36 mW (typical) operating
ꢀ –ꢀ12ꢀµWꢀ(typical)ꢀCMOSꢀstandby
•ꢀ TTLꢀcompatibleꢀinterfaceꢀlevels
•ꢀ Singleꢀpowerꢀsupplyꢀꢀ
When CS1ꢀ isꢀ HIGHꢀ (deselected)ꢀ orꢀ whenꢀ CS2ꢀ isꢀ LOW
(deselected) or when CS1 is LOW, CS2 is HIGH and both
LB and UBꢀareꢀHIGH,ꢀtheꢀdeviceꢀassumesꢀaꢀstandbyꢀmodeꢀ
at which the power dissipation can be reduced down with
CMOSꢀinputꢀlevels.
ꢀ –ꢀ4.5V--5.5VꢀVd d
•ꢀ Fullyꢀstaticꢀoperation:ꢀnoꢀclockꢀorꢀrefresh
Easy memory expansion is provided by using Chip Enable
andꢀOutputꢀEnableꢀinputs.ꢀTheꢀactiveꢀLOWꢀWriteꢀEnableꢀ(WE)
controls both writing and reading of the memory.A data byte
allows Upper Byte (UB)ꢀandꢀLowerꢀByteꢀ(LB) access.
required
•ꢀ Threeꢀstateꢀoutputs
•ꢀ Dataꢀcontrolꢀforꢀupperꢀandꢀlowerꢀbytes
•ꢀ Automotiveꢀtemperatureꢀ(-40oC to +125oC)
•ꢀ Lead-freeꢀavailable
TheꢀIS62C51216ALꢀandꢀIS65C51216ALꢀareꢀpackagedꢀinꢀ
theꢀJEDECꢀstandardꢀ48-pinꢀminiꢀBGAꢀ(9mmꢀxꢀ11mm)ꢀandꢀ
44-PinꢀTSOPꢀ(TYPEꢀII).
FUNCTIONAL BLOCK DIAGRAM
512K x 16
MEMORY ARRAY
A0-A18
DECODER
V
DD
GND
I/O0-I/O7
Lower Byte
I/O
DATA
COLUMN I/O
CIRCUIT
I/O8-I/O15
Upper Byte
CS2
CS1
OE
CONTROL
CIRCUIT
WE
UB
LB
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
1
Rev. A
03/18/09
IS62C51216AL, IS65C51216AL
PIN CONFIGURATIONS
PIN DESCRIPTIONS
A0-A18ꢀ ꢀ
I/O0-I/O15ꢀ
CS1, CS2
AddressꢀInputs
48-Pin mini BGA (9mmx11mm)
DataꢀInputs/Outputs
Chip Enable Input
OutputꢀEnableꢀInput
Write Enable Input
Lower-byteꢀControlꢀ(I/O0-I/O7)
Upper-byteꢀControlꢀ(I/O8-I/O15)
No Connection
1
2
3
4
5
6
OEꢀꢀ
WE
ꢀ
LBꢀ
ꢀ
ꢀ
UBꢀ
NC
A0
A3
A1
A4
A2
LB
OE
UB
CS2
A
B
C
D
E
F
I/O
8
CS1
I/O
0
Vd d ꢀ
GNDꢀ
ꢀ
ꢀ
Power
I/O
I/O
A5
A6
I/O
1
I/O
2
9
10
Ground
GND
A17
NC
A14
A12
A7
I/O
I/O
I/O
3
I/O
4
I/O
5
VDD`
11
GND
VDD
A16
A15
A13
A10
12
I/O
I/O
I/O
I/O
6
14
13
NC
A8
WE
I/O
7
15
G
H
A18
A9
A11
NC
44-Pin TSOP (Type II)
A4
A3
1
44
A5
A6
2
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A2
A1
A0
CS1
I/O0
I/O1
I/O2
I/O3
3
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
V
DD
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
VDD
I/O11
I/O10
I/O9
I/O8
A18
A8
A9
A10
A11
A17
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/18/09
IS62C51216AL, IS65C51216AL
TRUTH TABLE
I/O PIN
I/O0-I/O7 I/O8-I/O15 Vd d Current
Mode
WE CS1 CS2
OE
LB
UB
NotꢀSelectedꢀ
ꢀ
ꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Xꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Hꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
Is b 1, Is b 2
Is b 1, Is b 2
Is b 1, Is b 2
ꢀ
ꢀ
OutputꢀDisabledꢀ
ꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
Xꢀ
Lꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
Ic c
Ic c
ꢀ
ꢀ
ꢀ
Readꢀ
ꢀ
Hꢀ
Hꢀ
H
Lꢀ
Lꢀ
L
Hꢀ
Hꢀ
H
Lꢀ
Lꢀ
L
Lꢀ
Hꢀ
L
Hꢀ
Lꢀ
L
do u t ꢀ
High-Zꢀ
do u t
High-Z
do u t
do u t
Ic c
ꢀ
ꢀ
Writeꢀ
ꢀ
Lꢀ
Lꢀ
L
Lꢀ
Lꢀ
L
Hꢀ
Hꢀ
H
Xꢀ
Xꢀ
X
Lꢀ
Hꢀ
L
Hꢀ
Lꢀ
L
dInꢀ
High-Zꢀ
dIn
High-Z
dIn
dIn
Ic c
OPERATING RANGE (Vd d )
Range
Ambient Temperature
0°Cꢀtoꢀ+70°Cꢀ
Vdd
Speed
45ns
55ns
55ns
Commercialꢀ
Industrialꢀ
4.5Vꢀ-ꢀ5.5Vꢀ
4.5Vꢀ-ꢀ5.5Vꢀ
4.5Vꢀ-ꢀ5.5Vꢀ
–40°Cꢀtoꢀ+85°Cꢀ
–40°Cꢀtoꢀ+125°Cꢀ
ꢀ Automotiveꢀ
CAPACITANCE(1,2)
Symbol
Parameter
Conditions
VIn = 0V
Max.
5ꢀ
Unit
cIn
Input Capacitance
pF
pF
co u t ꢀ
OutputꢀCapacitanceꢀ
Vo u t = 0V
7ꢀ
Notes:
1.ꢀꢀTestedꢀinitiallyꢀandꢀafterꢀanyꢀdesignꢀorꢀprocessꢀchangesꢀthatꢀmayꢀaffectꢀtheseꢀparameters.
2.ꢀ Testꢀconditions:ꢀTa = 25°c, fꢀ=ꢀ1ꢀMHz,ꢀVd d ꢀ=ꢀ5.0V.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
3
Rev. A
03/18/09
IS62C51216AL, IS65C51216AL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–0.5ꢀtoꢀ+7.0ꢀ
–65ꢀtoꢀ+150ꢀ
1.5ꢀ
Unit
V
°C
Vt e r m
ts t g
Pt
TerminalꢀVoltageꢀwithꢀRespectꢀtoꢀGNDꢀ
StorageꢀTemperatureꢀ
PowerꢀDissipationꢀ
W
Io u t ꢀ
DCꢀOutputꢀCurrentꢀ(LOW)ꢀ
20ꢀ
mAꢀ
Notes:
1.ꢀꢀStressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀ
permanentꢀdamageꢀtoꢀtheꢀdevice.ꢀThisꢀisꢀaꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀ
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS (OverꢀOperatingꢀRange)
Symbol Parameter
Test Conditions
Min.
2.4ꢀ
—ꢀ
Max.
—ꢀ
Unit
V
Vo H
Vo L
VIH
VIL
IL I
OutputꢀHIGHꢀVoltageꢀ
Vd d = Min.,ꢀIo H = –1ꢀmAꢀ
ꢀ
ꢀ
ꢀ
ꢀ
OutputꢀLOWꢀVoltageꢀ
InputꢀHIGHꢀVoltageꢀ
InputꢀLOWꢀVoltage(1)
InputꢀLeakageꢀ
Vd d = Min.,ꢀIo L = 2.1ꢀmAꢀ
0.4ꢀ
V
ꢀ
2.2ꢀ
–0.3ꢀ
Vd d + 0.5
0.8ꢀ
V
ꢀ
V
GNDꢀ≤ VIn ≤ Vd d
Com.
Ind.
Auto.
–1
–2
–5
1
2
5
µA
IL o
ꢀ
OutputꢀLeakage
ꢀ
GNDꢀ≤ Vo u t ≤ Vd d
OutputsꢀDisabledꢀ
Com.
Ind.ꢀ
Auto.
–1
–2ꢀ
–5
1
2
5
µA
ꢀ
Note:
1. VIL (min) = -0.3VꢀDC;ꢀVIL (min) = -2.0VꢀACꢀ(pulseꢀwidthꢀ-2.0ꢀns).ꢀNotꢀ100%ꢀtested.ꢀ
VIH (max) = Vd d + 0.3VꢀDC;ꢀVIH (max) = Vd d + 2.0VꢀACꢀ(pulseꢀwidthꢀ-2.0ꢀns).ꢀNotꢀ100%ꢀtested.ꢀ
4ꢀ
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/18/09
IS62C51216AL, IS65C51216AL
AC TEST CONDITIONS
Parameter
InputꢀPulseꢀLevelꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
Unit
0Vꢀtoꢀ3.0V
5ꢀns
ꢀ
ꢀ
ꢀ
InputꢀandꢀOutputꢀTimingꢀ
andꢀReferenceꢀLevel
1.5V
ꢀ
OutputꢀLoadꢀ
SeeꢀFiguresꢀ1ꢀandꢀ2
AC TEST LOADS
481 Ω
481 Ω
5V
5V
OUTPUT
OUTPUT
255 Ω
255 Ω
30 pF
Including
jig and
5 pF
Including
jig and
scope
scope
Figureꢀ1
Figureꢀ2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
5
Rev. A
03/18/09
IS62C51216AL, IS65C51216AL
POWER SUPPLY CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
-45 ns
Min. Max.
-55 ns
Min. Max.
Symbol Parameter
Test Conditions
Unit
Ic c
V
d d ꢀDynamicꢀOperatingꢀꢀVd d = Max.,ꢀCE = VIL
Com.
Ind.ꢀ
—ꢀ
ꢀ
ꢀ
25
ꢀ
ꢀ
mA
ꢀ
ꢀ
Supply Current
Io u t = 0 mA, f = fm a X
—ꢀ
—ꢀ
25ꢀ
40ꢀ
VIn = VIH or VIL
Auto.ꢀ
ꢀ
typ.(2)
13
12
I
c c
1
Average operating
Current
CE = VIL
In = VIH or VIL
I I/o= 0 mA
,
Com.
Ind.ꢀ
Auto.ꢀ
—ꢀ
ꢀ
ꢀ
10
ꢀ
ꢀ
mA
mA
µA
V
,
—ꢀ
—ꢀ
10
20
Is b
1
TTLꢀStandbyꢀCurrentꢀ
(TTLꢀInputs)ꢀ
ꢀꢀ
V
V
d d = Max.,ꢀ
In = VIH or VIL, CE ≥ VIH
Com.
Ind.ꢀ
Auto.ꢀ
—
ꢀ
ꢀ
1
ꢀ
ꢀ
,
—ꢀ
—ꢀ
1.5
2
ꢀ ꢀ
fꢀ=ꢀ0ꢀ
Is b 2ꢀ
CMOSꢀStandbyꢀ
V
d d = Max.,ꢀ
Com.
Ind.ꢀ
—
ꢀ
ꢀ
40
ꢀ
ꢀ
ꢀ ꢀ
Currentꢀ(CMOSꢀInputs)ꢀ CE ≥ Vd d – 0.2V,ꢀ
In ≥ Vd d – 0.2V,ꢀ
or VIn ≤ Vs s + 0.2V, f = 0
—ꢀ
—ꢀ 180
60
V
Auto.ꢀ
typ.(2)
15
Note:
1. At f = fm a X , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2.ꢀꢀTypicalꢀValuesꢀareꢀmeasuredꢀatꢀVccꢀ=ꢀ5V,ꢀTa = 25oCꢀandꢀnotꢀ100%ꢀtested.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/18/09
IS62C51216AL, IS65C51216AL
READ CYCLE SWITCHING CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
45 ns
55 ns
70 ns
Symbol
tr c ꢀ
Parameter
Min.
Max.
—ꢀ
Min.
Max.
—ꢀ
Min.
Max.
—ꢀ
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ReadꢀCycleꢀTimeꢀ
45ꢀ
—ꢀ
10ꢀ
—ꢀ
—ꢀ
—ꢀ
5ꢀ
55ꢀ
—ꢀ
10ꢀ
—ꢀ
—ꢀ
—ꢀ
5ꢀ
70ꢀ
—ꢀ
10ꢀ
—ꢀ
—ꢀ
—ꢀ
5ꢀ
ta a ꢀ
AddressꢀAccessꢀTimeꢀ
OutputꢀHoldꢀTimeꢀ
45ꢀ
—ꢀ
55ꢀ
—ꢀ
70ꢀ
—ꢀ
3
to H a ꢀ
ta c s 1/ta c s 2
td o e
CS1/CS2ꢀAccessꢀTimeꢀ
OEꢀAccessꢀTimeꢀ
45ꢀ
20ꢀ
15ꢀ
—ꢀ
55ꢀ
25ꢀ
20ꢀ
—ꢀ
70ꢀ
35ꢀ
25ꢀ
—ꢀ
(2)
tH z o e
OEꢀtoꢀHigh-ZꢀOutputꢀ
OEꢀtoꢀLow-ZꢀOutputꢀ
CS1/CS2ꢀtoꢀHigh-ZꢀOutputꢀ
CS1/CS2ꢀtoꢀLow-ZꢀOutputꢀ
LB, UBꢀAccessꢀTimeꢀ
LB, UBꢀtoꢀHigh-ZꢀOutputꢀ
LB, UBꢀtoꢀLow-ZꢀOutputꢀ
(2)
tL z o e
(2)
tH z c s 1/tH z c s 2
0ꢀ
15ꢀ
—ꢀ
0ꢀ
20ꢀ
—ꢀ
0ꢀ
25ꢀ
—ꢀ
(2)
tL z c s 1/tL z c s 2
10ꢀ
—ꢀ
0ꢀ
10ꢀ
—ꢀ
0ꢀ
10ꢀ
—ꢀ
0ꢀ
tb a
45ꢀ
15ꢀ
—ꢀ
55ꢀ
20ꢀ
—ꢀ
70ꢀ
25ꢀ
—ꢀ
tH z b
tL z b
0ꢀ
0ꢀ
0ꢀ
Notes:
1.ꢀ Testꢀconditionsꢀassumeꢀsignalꢀtransitionꢀtimesꢀofꢀ5ꢀnsꢀorꢀless,ꢀtimingꢀreferenceꢀlevelsꢀofꢀ1.5V,ꢀinputꢀpulseꢀlevelsꢀofꢀ0Vꢀtoꢀ3.0Vꢀ
andꢀoutputꢀloadingꢀspecifiedꢀinꢀFigureꢀ1.
2.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ2.ꢀTransitionꢀisꢀmeasuredꢀ±500ꢀmVꢀfromꢀsteady-stateꢀvoltage.ꢀNotꢀ100%ꢀtested.
3.ꢀꢀ10nsꢀforꢀCMOSꢀLoading.ꢀ8nsꢀ@ꢀACꢀLoading.
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OEꢀ=ꢀVIL, cs2 = WEꢀ=ꢀVIH, UB or LB = VIL)
tRC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DQ0-D15
PREVIOUS DATA VALID
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ꢀ
7
Rev. A
03/18/09
IS62C51216AL, IS65C51216AL
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, CS2, OE,ꢀANDꢀUB/LB Controlled)
tRC
ADDRESS
t
AA
tOHA
OE
tHZOE
t
DOE
t
LZOE
CS1
s
t
ACE1/tACE2
CS2
s
tLZCE1/
tLZCE2
tHZCS1/
t
HZCS1
LBs, UB
s
tBA
t
HZB
tLZB
HIGH-Z
DOUT
DATA VALID
Notes:
1. WEꢀisꢀHIGHꢀforꢀaꢀReadꢀCycle.
2.ꢀ Theꢀdeviceꢀisꢀcontinuouslyꢀselected.ꢀOE, CS1, UB, or LB = VIL. cs2=WE=VIH.
3. Address is valid prior to or coincident with CS1ꢀLOWꢀtransition.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/18/09
IS62C51216AL, IS65C51216AL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2)ꢀ(OverꢀOperatingꢀRange)
45ns
55 ns
70 ns
Symbol
Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ꢀns
ns
ns
tw c ꢀ
WriteꢀCycleꢀTimeꢀ
ꢀꢀꢀ45ꢀꢀ
ꢀꢀꢀ35ꢀ
ꢀꢀꢀ35ꢀ
ꢀꢀꢀ0ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
20ꢀ
—ꢀ
ꢀꢀꢀ55ꢀ
ꢀꢀꢀ45ꢀ
ꢀꢀꢀ45ꢀ
ꢀꢀꢀ0ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
20ꢀ
—ꢀ
ꢀꢀꢀ70ꢀ
ꢀꢀꢀ60ꢀ
ꢀꢀꢀ60ꢀ
ꢀꢀꢀꢀꢀ0ꢀ
ꢀꢀꢀꢀꢀ0ꢀ
ꢀꢀꢀ60ꢀ
ꢀꢀꢀꢀ50ꢀ
ꢀꢀꢀ30ꢀ
ꢀꢀꢀꢀꢀ0ꢀ
ꢀꢀꢀꢀꢀ—ꢀ
ꢀꢀꢀꢀꢀ5ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
30ꢀ
—ꢀ
ts c s 1/ts c s 2 CS1/CS2ꢀtoꢀWriteꢀEndꢀ
ta w ꢀ
tH a ꢀ
ts a ꢀ
AddressꢀSetupꢀTimeꢀtoꢀWriteꢀEndꢀꢀ
AddressꢀHoldꢀfromꢀWriteꢀEndꢀ
AddressꢀSetupꢀTimeꢀ
ꢀꢀꢀ0ꢀ
ꢀꢀꢀ0ꢀ
tP w b
tP w e
ts d ꢀ
tH d ꢀ
tH z w e
tL z w e
LB, UBꢀValidꢀtoꢀEndꢀofꢀWriteꢀ
WEꢀPulseꢀWidthꢀ
ꢀꢀꢀ35ꢀ
ꢀꢀꢀ35ꢀ
ꢀꢀꢀ25ꢀ
ꢀꢀꢀ0ꢀ
ꢀꢀꢀ45ꢀ
ꢀꢀꢀ40ꢀ
ꢀꢀꢀ30ꢀ
ꢀꢀꢀ0ꢀ
(4)
DataꢀSetupꢀtoꢀWriteꢀEndꢀ
DataꢀHoldꢀfromꢀWriteꢀEndꢀ
WEꢀLOWꢀtoꢀHigh-ZꢀOutputꢀ
WEꢀHIGHꢀtoꢀLow-ZꢀOutputꢀ
(3)
ꢀꢀꢀ—ꢀ
ꢀꢀꢀꢀ5ꢀ
ꢀꢀꢀ—ꢀ
ꢀꢀꢀ5ꢀ
(3)
Notes:
1.ꢀ Testꢀconditionsꢀassumeꢀsignalꢀtransitionꢀtimesꢀofꢀ5ꢀnsꢀorꢀless,ꢀtimingꢀreferenceꢀlevelsꢀofꢀ1.5V,ꢀinputꢀpulseꢀlevelsꢀofꢀ0Vꢀtoꢀ
3.0VꢀandꢀoutputꢀloadingꢀspecifiedꢀinꢀFigureꢀ1.
2. Theꢀinternalꢀwriteꢀtimeꢀisꢀdefinedꢀbyꢀtheꢀoverlapꢀof CS1 LOW,ꢀCS2ꢀHIGHꢀandꢀUB or LB, and WEꢀLOW.ꢀAllꢀsignalsꢀmustꢀbeꢀinꢀvalidꢀstatesꢀtoꢀinitiateꢀaꢀWrite,ꢀbutꢀ
any one can go inactive to terminateꢀtheꢀWrite.ꢀTheꢀDataꢀInputꢀSetupꢀandꢀHoldꢀtimingꢀareꢀreferencedꢀtoꢀtheꢀrisingꢀorꢀfallingꢀedgeꢀofꢀtheꢀsignalꢀthatꢀterminatesꢀtheꢀ
write.
3.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ2.ꢀTransitionꢀisꢀmeasuredꢀ±500ꢀmVꢀfromꢀsteady-stateꢀvoltage.ꢀNotꢀ100%ꢀtested.
4.ꢀꢀꢀtP w e > tH z w e + ts d when OEꢀisꢀLOW.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OEꢀ=ꢀHIGHꢀorꢀLOW)
t
WC
ADDRESS
CS1
t
HA
tSCS1
tSCS2
CS2
tAW
t
PWE
WE
tPWB
LB, UB
t
SA
tHZWE
t
LZWE
HIGH-Z
SD
DOUT
DIN
DATA UNDEFINED
t
t
HD
DATA-IN VALID
Notes:
1.ꢀ WRITEꢀisꢀanꢀinternallyꢀgeneratedꢀsignalꢀassertedꢀduringꢀanꢀoverlapꢀofꢀtheꢀLOWꢀstatesꢀonꢀtheꢀCS1 , CS2 and WE inputs and at
least one of the LB and UBꢀinputsꢀbeingꢀinꢀtheꢀLOWꢀstate.
2.ꢀ WRITEꢀ=ꢀ(CS1) [ (LB) = (UB) ] (WE).
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
9
Rev. A
03/18/09
IS62C51216AL, IS65C51216AL
WRITE CYCLE NO. 2 (WEꢀControlled:ꢀOEꢀisꢀHIGHꢀDuringꢀWriteꢀCycle)
t
WC
ADDRESS
OE
t
HA
tSCS1
CS1
tSCS2
CS2
tAW
t
PWE
WE
LB, UB
DOUT
DIN
t
SA
tHZWE
t
LZWE
HIGH-Z
SD
DATA UNDEFINED
t
t
HD
DATA-IN VALID
WRITE CYCLE NO. 3 (WEꢀControlled:ꢀOEꢀisꢀLOWꢀDuringꢀWriteꢀCycle)
t
WC
ADDRESS
OE
tHA
tSCS1
tSCS2
CS1
CS2
tAW
tPWE
WE
LB, UB
DOUT
DIN
tSA
DATA UNDEFINED
tHZWE
tLZWE
HIGH-Z
tSD
DATA-IN VALID
tHD
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/18/09
IS62C51216AL, IS65C51216AL
WRITE CYCLE NO. 4 (UB/LB Controlled)
t
WC
t
WC
ADDRESSꢀ1
ADDRESSꢀ2
ADDRESS
OE
t
SA
LOW
HIGH
CS1
CS2
t
HA
SA
t
HA
t
WE
t
PBW
t
PBW
UB, LB
WORDꢀ1
WORDꢀ2
t
HZWE
t
LZWE
HIGH-Z
DOUT
DATAꢀUNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
UB_CSWR4.eps
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
11
Rev. A
03/18/09
IS62C51216AL, IS65C51216AL
DATA RETENTION SWITCHING CHARACTERISTICS (4.5V - 5.5V)
Symbol
ꢀ ꢀ Vd r ꢀ
Id r ꢀ
Parameter
Test Condition
Min.
Typ.(1)
Max.
Unit
Vd d ꢀforꢀDataꢀRetentionꢀ
SeeꢀDataꢀRetentionꢀWaveformꢀ
ꢀ
2.0ꢀ
ꢀ
5.5ꢀ
V
DataꢀRetentionꢀCurrentꢀ
Vd d ꢀ=ꢀ2.0V,ꢀCS1 ≥ꢀVd d –ꢀ0.2Vꢀ
ꢀ
Com.ꢀ
Ind.ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
20ꢀ
40ꢀ
60ꢀ
µAꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
15ꢀ
—ꢀ
—ꢀ
ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ
Auto.ꢀ
180
ts d r
tr d r
DataꢀRetentionꢀSetupꢀTimeꢀ SeeꢀDataꢀRetentionꢀWaveformꢀ
RecoveryꢀTimeꢀ SeeꢀDataꢀRetentionꢀWaveformꢀ
ꢀ
ꢀ
0ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ns
ns
tr c ꢀ
Note:
1.ꢀꢀTypicalꢀValuesꢀareꢀmeasuredꢀatꢀVccꢀ=ꢀ5V,ꢀTa = 25oCꢀandꢀnotꢀ100%ꢀtested.
DATA RETENTION WAVEFORM (CS1 Controlled)
t
SDR
Data Retention Mode
tRDR
VDD
1.65V
1.4V
VDR
CS1 ≥ VDD - 0.2V
CS1
GND
DATA RETENTION WAVEFORM (CS2 Controlled)
Data Retention Mode
V
DD
3.0
t
t
RDR
SDR
CE2
2.2V
V
DR
CS2 ≤ 0.2V
0.4V
GND
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/18/09
IS62C51216AL, IS65C51216AL
IS62C51216AL (4.5V - 5.5V)
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.*
Package
ꢀ
ꢀ
55ꢀ
ꢀ
IS62C51216AL-55TLIꢀ
IS62C51216AL-55MLIꢀ
TSOP-II,ꢀLead-free
miniꢀBGA,ꢀLead-freeꢀ(9mmx11mm)
*Devices will meet 45ns when used in 0oC to +70oC temperature range.
IS65C51216AL (4.5V - 5.5V)
Industrial Range: –40°C to +125°C
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
55ꢀ
ꢀ
IS65C51216AL-55CTLA3ꢀ
IS65C51216AL-55MLA3ꢀ
TSOP-II,ꢀLead-free,ꢀCopperꢀLead-frame
miniꢀBGA,ꢀLead-freeꢀ(9mmx11mm)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
13
Rev. A
03/18/09
IS62C51216AL, IS65C51216AL
14
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
03/18/09
IS62C51216AL, IS65C51216AL
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
15
Rev. A
03/18/09
相关型号：
IS62C5128BL-45QLI
Standard SRAM, 512KX8, 45ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, PLASTIC, SOP-32
ISSI
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