IS62LV12816BLL-55TI [ISSI]
128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM; 128K ×16低电压，超低功耗CMOS静态RAM
| 型号： | IS62LV12816BLL-55TI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM |
| 文件： | 总10页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS62LV12816BLL
128K x 16 LOW VOLTAGE, ULTRA
LOW POWER CMOS STATIC RAM
ISSI
FEBRUARY 2001
FEATURES
DESCRIPTION
The ISSIIS62LV12816BLL is a high-speed, 2,097,152-bit
static RAM organized as 131,072 words by 16 bits. It is
fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovativecircuitdesigntechniques,yieldshigh-performance
and low power consumption devices.
• High-speed access time: 55, 70, 100 ns
• CMOS low power operation
– 120 mW (typical) operating
– 6 µW (typical) CMOS standby
• TTL compatible interface levels
• Single 2.7V-3.45V VCC power supply
When CE is HIGH (deselected) or when CE is low and
both LB and UB are HIGH, the device assumes a standby
modeatwhichthepowerdissipationcanbereduceddown
with CMOS input levels.
• Fully static operation: no clock or refresh
required
• Three state outputs
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
• Data control for upper and lower bytes
• Industrial temperature available
• Available in the 44-pin TSOP (Type II) and
48-pin mini BGA (6mm x 8mm)
TheIS62LV12816BLLispackagedintheJEDECstandard
44-pinTSOP(TypeII)and48-pinminiBGA(6mmx8mm).
FUNCTIONAL BLOCK DIAGRAM
128K x 16
MEMORY ARRAY
A0-A16
DECODER
VCC
GND
I/O0-I/O7
Lower Byte
I/O
DATA
COLUMN I/O
CIRCUIT
I/O8-I/O15
Upper Byte
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. B
03/07/01
®
IS62LV12816BLL
ISSI
PIN CONFIGURATIONS
44-Pin TSOP (Type II)
48-Pin mini BGA
1
2
3
4
5
6
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
CE
A0
A3
A1
A4
A2
LB
OE
UB
N/C
A
B
C
D
E
F
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
I/O
8
CE
I/O
0
9
I/O
9
I/O
10
A5
A6
I/O
1
I/O
2
10
11
12
13
14
15
16
17
18
19
20
21
22
GND
Vcc
NC
NC
A14
A12
A7
I/O
I/O
I/O
3
I/O
4
I/O
5
Vcc
11
GND
A16
A15
A13
A10
12
I/O
14
I/O
13
I/O
6
I/O
15
NC
A8
WE
I/O
7
G
H
NC
A9
A11
NC
PIN DESCRIPTIONS
A0-A16
I/O0-I/O15
CE
Address Inputs
LB
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
UB
NC
OE
Vcc
GND
Power
WE
Ground
TRUTHTABLE
I/O PIN
Mode
WE
CE
OE
LB
UB
I/O0-I/O7
I/O8-I/O15 Vcc Current
Not Selected
X
X
H
L
X
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
ISB1, ISB2
ISB1, ISB2
Output Disabled
Read
H
X
L
L
H
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
ICC
ISB
H
H
H
L
L
L
L
L
L
L
H
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
ICC
Write
L
L
L
L
L
L
X
X
X
L
H
L
H
L
L
DIN
High-Z
DIN
High-Z
DIN
DIN
ICC
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
03/07/01
®
IS62LV12816BLL
ISSI
OPERATING RANGE
Range
Ambient Temperature
VCC
Commercial
Industrial
0°C to +70°C
2.7V - 3.45V
2.7V - 3.45V
1
–40°C to +85°C
2
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TBIAS
VCC
Parameter
Value
–0.5 to Vcc+0.5
–40 to +85
–0.3 to +3.6
–65 to +150
1.0
Unit
V
3
Terminal Voltage with Respect to GND
Temperature Under Bias
Vcc Related to GND
°C
V
TSTG
PT
Storage Temperature
°C
W
4
Power Dissipation
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
5
6
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
7
Symbol Parameter
Test Conditions
Min.
2.0
—
Max.
Unit
V
VOH
VOL
VIH
Output HIGH Voltage
VCC = Min., IOH = –1 mA
VCC = Min., IOL = 2.1 mA
—
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
0.4
V
8
2.2
–0.2
–1
VCC + 0.2
V
(1)
VIL
0.4
1
V
ILI
GND ≤ VIN ≤ VCC
µA
µA
9
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled
–1
1
Notes:
1. VIL (min.) = –2.0V for pulse width less than 10 ns.
10
11
12
CAPACITANCE(1)
Symbol
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
CIN
Input Capacitance
Input/Output Capacitance
6
8
COUT
Note:
VOUT = 0V
pF
1. Tested initially and after any design or process changes that may affect these parameters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. B
03/07/01
®
IS62LV12816BLL
ISSI
AC TEST CONDITIONS
Parameter
Unit
0.4V to 2.2V
5 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
1.3V
Output Load
See Figures 1 and 2
AC TEST LOADS
3070 Ω
3070 Ω
3.0V
3.0V
OUTPUT
OUTPUT
3150 Ω
3150 Ω
30 pF
Including
jig and
5 pF
Including
jig and
scope
scope
Figure 1
Figure 2
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
03/07/01
®
IS62LV12816BLL
ISSI
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-55
-70
-100
Symbol Parameter
Test Conditions
CC = Max.,
OUT = 0 mA, f = fMAX
Min. Max.
Min. Max.
Min. Max.
Unit
mA
1
I
CC
Vcc Dynamic Operating
SupplyCurrent
V
I
Com.
Ind.
—
—
40
45
—
—
30
35
—
—
20
25
I
SB
1
TTLStandbyCurrent
(TTLInputs)
V
CC = Max.,
Com.
Ind.
—
—
0.4
1.0
—
—
0.4
1.0
—
—
0.4
1.0
mA
V
IN = VIH or VIL
2
CE
≥ VIH , f = 0
OR
ULB Control
VCC = Max., VIN = VIH or VIL
CE = VIL, f = 0, UB = VIH, LB = VIH
3
I
SB2
CMOS Standby
Current (CMOS Inputs)
V
CE
V
V
CC = Max.,
Com.
Ind.
—
—
5
5
—
—
5
5
—
—
5
5
µA
≥
≥
≤
V
CC – 0.2V,
CC – 0.2V, or
0.2V, f = 0
IN
V
4
IN
OR
ULB Control
VCC = Max., CE = VIL
VIN ≤ 0.2V, f = 0; UB / LB = VCC – 0.2V
5
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
6
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
7
-55
-70
-100
Symbol
tRC
Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
55
—
10
—
—
—
5
—
55
—
55
30
20
—
20
—
55
25
—
70
—
10
—
—
—
5
—
70
—
70
35
25
—
25
—
70
25
—
100
—
15
—
—
—
5
—
100
—
8
tAA
Address Access Time
Output Hold Time
tOHA
tACE
tDOE
CE Access Time
100
50
9
OE Access Time
(2)
tHZOE
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
30
(2)
tLZOE
—
10
11
12
(2)
tHZCE
0
0
0
30
(2)
tLZCE
10
—
0
10
—
0
10
—
0
—
tBA
100
35
tHZB
tLZB
0
0
0
—
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels of
0.4 to 2.2V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100ꢀ tested.
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. B
03/07/01
®
IS62LV12816BLL
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
tRC
ADDRESS
tAA
tOHA
tOHA
DATA VALID
DOUT
PREVIOUS DATA VALID
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CE, OE, AND UB/LB Controlled)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
LZOE
ACE
t
CE
t
t
HZCE
t
LZCE
LB, UB
t
BA
t
HZB
t
LZB
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
03/07/01
®
IS62LV12816BLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
ISSI
-55
-70
-100
Symbol
tWC
Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
55
50
50
0
—
—
—
—
—
—
—
—
—
30
—
70
65
65
0
—
—
—
—
—
—
—
—
—
30
—
100
80
80
0
—
—
—
—
—
—
—
—
—
40
—
1
tSCE
tAW
CE to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
tHA
2
tSA
0
0
0
tPWB
tPWE
tSD
LB, UB Valid to End of Write
WE Pulse Width
45
45
25
0
60
60
30
0
80
80
40
0
3
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
tHD
(3)
tHZWE
—
5
—
5
—
5
4
(3)
tLZWE
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write.
5
3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100ꢀ tested.
6
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
7
t
WC
VALID ADDRESS
SCS
ADDRESS
8
t
SA
t
t
HA
CE
t
AW
9
t
tPPWWEE21
WE
t
PBW
10
11
12
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
UB_CSWR1.eps
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one
of the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. B
03/07/01
®
IS62LV12816BLL
ISSI
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
t
WC
ADDRESS
VALID ADDRESS
t
HA
OE
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
PBW
UB, LB
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
D
IN
UB_CSWR2.eps
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
tWC
ADDRESS
VALID ADDRESS
tHA
LOW
LOW
OE
CE
tAW
tPWE2
tPBW
WE
tSA
UB, LB
tHZWE
tLZWE
HIGH-Z
DATA UNDEFINED
D
OUT
tSD
tHD
DATAIN VALID
D
IN
UB_CSWR3.eps
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
03/07/01
®
IS62LV12816BLL
ISSI
WRITE CYCLE NO. 4 (UB/LB Controlled)
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
1
OE
CE
2
t
SA
LOW
t
HA
SA
t
HA
3
t
WE
t
PBW
t
PBW
4
UB, LB
WORD 1
WORD 2
t
HZWE
t
LZWE
HIGH-Z
D
OUT
DATA UNDEFINED
5
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
6
UB_CSWR4.eps
DATA RETENTION SWITCHING CHARACTERISTICS
7
Symbol
VDR
Parameter
TestCondition
Min.
Max.
3.45
5
Unit
V
Vcc for Data Retention
DataRetentionCurrent
Data Retention Setup Time
RecoveryTime
SeeDataRetentionWaveform
Vcc = 2.0V, CE • Vcc – 0.2V
SeeDataRetentionWaveform
SeeDataRetentionWaveform
1.5
—
0
8
IDR
µA
ns
tSDR
—
tRDR
tRC
—
ns
9
DATA RETENTION WAVEFORM (CE Controlled)
10
11
12
tSDR
Data Retention Mode
tRDR
VCC
2.3V
2.0V
VDR
CE ≥ VCC Ð 0.2V
CE
GND
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. B
03/07/01
®
IS62LV12816BLL
ISSI
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No.
Package
Speed (ns) Order Part No.
Package
55
IS62LV12816BLL-55TI TSOP (Type II)
55
IS62LV12816BLL-55T TSOP (Type II)
IS62LV12816BLL-55BI Mini BGA (6mm x 8mm)
IS62LV12816BLL-55B Mini BGA (6mm x 8mm)
70
IS62LV12816BLL-70TI TSOP (Type II)
70
IS62LV12816BLL-70T TSOP (Type II)
IS62LV12816BLL-70BI Mini BGA (6mm x 8mm)
IS62LV12816BLL-70B Mini BGA (6mm x 8mm)
100
IS62LV12816BLL-10T TSOP (Type II)
100
IS62LV12816BLL-10TI TSOP (Type II)
IS62LV12816BLL-10B Mini BGA (6mm x 8mm)
IS62LV12816BLL-10BI Mini BGA (6mm x 8mm)
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
03/07/01
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