IS62LV12816L-100B [ISSI]
128K x 16 CMOS STATIC RAM; 128K ×16的CMOS静态RAM
| 型号： | IS62LV12816L-100B |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 128K x 16 CMOS STATIC RAM |
| 文件： | 总9页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ISSI
IS62LV12816L
128K x 16 CMOS STATIC RAM
ADVANCE INFORMATION
AUGUST 1998
1
FEATURES
DESCRIPTION
The ISSI IS62LV12816L is a high-speed, 2,097,152-bit static
RAM organized as 131,072 words by 16 bits. It is fabricated
usingISSI'shigh-performanceCMOStechnology. Thishighly
reliable process coupled with innovative circuit design
techniques, yields high-performance and low power
consumption devices.
• High-speed access time: 70, 100, and 120 ns
• CMOS low power operation
2
– 120 mW (typical) operating
– 6 µW (typical) CMOS standby
• TTL compatible interface levels
• Single 3V ± 10% VCC power supply
3
WhenCEisHIGH(deselected),thedeviceassumesastandby
mode at which the power dissipation can be reduced down
with CMOS input levels.
• Fully static operation: no clock or refresh
required
4
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CEand OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
5
• Available in the 44-pin TSOP (Type II) and
48-pin mini BGA
The IS62LV12816L is packaged in the JEDEC standard
44-pin TSOP (Type II) and 48-pin mini BGA.
6
FUNCTIONAL BLOCK DIAGRAM
7
128K x 16
MEMORY ARRAY
A0-A16
DECODER
8
VCC
GND
9
I/O0-I/O7
Lower Byte
I/O
DATA
COLUMN I/O
10
11
12
CIRCUIT
I/O8-I/O15
Upper Byte
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
The specification contains ADVANCE INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
1
08/20/98
®
ISSI
IS62LV12816L
PIN CONFIGURATIONS
44-Pin TSOP (Type II)
48-Pin mini BGA
A4
A3
A2
A1
A0
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
1
2
3
4
5
6
2
3
A0
A3
A1
A4
A2
LB
I/O
OE
UB
N/C
A
B
C
D
E
F
4
5
CE
I/O
0
8
CE
6
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
7
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
I/O
I/O
I/O
I/O
A5
A6
I/O
I/O
2
9
10
1
8
9
GND
Vcc
NC
NC
A14
A12
A7
I/O
I/O
I/O
Vcc
11
3
4
5
10
11
12
13
14
15
16
17
18
19
20
21
22
GND
A16
A15
A13
A10
12
I/O
14
I/O
I/O
6
13
I/O
15
NC
A8
WE
A11
I/O
7
G
H
NC
A9
NC
PIN DESCRIPTIONS
LB
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
A0-A16
I/O0-I/O15
CE
Address Inputs
UB
NC
Vcc
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Power
OE
GND
Ground
WE
TRUTH TABLE
I/O PIN
Mode
WE
X
CE
H
OE
LB
X
UB
I/O0-I/O7
I/O8-I/O15 Vcc Current
Not Selected
X
X
High-Z
High-Z
ISB1, ISB2
ICC
Output Disabled
H
X
L
L
H
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
Read
Write
H
H
H
L
L
L
L
L
L
L
H
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
ICC
ICC
L
L
L
L
L
L
X
X
X
L
H
L
H
L
L
DIN
High-Z
DIN
High-Z
DIN
DIN
2
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
08/20/98
®
ISSI
IS62LV12816L
OPERATING RANGE
Range
Ambient Temperature
VCC
Commercial
Industrial
0°C to +70°C
3.0V ± 10%
3.0V ± 10%
–40°C to +85°C
1
ABSOLUTE MAXIMUM RATINGS(1)
2
Symbol
VTERM
TBIAS
VCC
Parameter
Value
–0.5 to Vcc+0.5
–40 to +85
–0.3 to +4.0
–65 to +150
1.0
Unit
V
Terminal Voltage with Respect to GND
Temperature Under Bias
Vcc Related to GND
°C
V
3
TSTG
Storage Temperature
°C
W
PT
Power Dissipation
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
4
5
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
2.0
—
Max.
Unit
V
6
VOH
VOL
VIH
Output HIGH Voltage
VCC = Min., IOH = –1 mA
VCC = Min., IOL = 2.1 mA
—
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
0.4
V
2.2
–0.2
–1
VCC + 0.2
V
7
(1)
VIL
ILI
0.4
1
V
GND ≤ VIN ≤ VCC
µA
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled
–1
1
8
Notes:
1. VIL (min.) = –2.0V for pulse width less than 10 ns.
9
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-70
-100
-120
Min. Max.
Symbol Parameter
Test Conditions
CC = Max.,
OUT = 0 mA, f = fMAX
Min. Max.
Min. Max.
Unit
10
11
12
I
CC
Vcc Dynamic Operating
Supply Current
V
I
Com.
Ind.
—
—
40
60
—
—
30
50
—
—
20
40
mA
I
SB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
Com.
Ind.
—
—
0.4
1.0
—
—
0.4
1.0
—
—
0.4
1.0
mA
VIN = VIH or VIL
CE ≥ VIH , f = 0
I
SB2
CMOS Standby
VCC = Max.,
Com.
Ind.
—
—
15
25
—
—
15
25
—
—
15
25
µA
Current (CMOS Inputs) CE ≥ VCC – 0.2V,
V
V
IN ≥ VCC – 0.2V, or
IN ≤ 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
3
08/20/98
®
ISSI
IS62LV12816L
CAPACITANCE(1)
Symbol
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
CIN
Input Capacitance
6
8
COUT
Note:
Input/Output Capacitance
VOUT = 0V
pF
1. Tested initially and after any design or process changes that may affect these parameters.
AC TEST CONDITIONS
Parameter
Unit
0.4V to 2.2V
5 ns
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
1.5V
Output Load
See Figures 1 and 2
AC TEST LOADS
3070 Ω
3070 Ω
2.8V
2.8V
OUTPUT
OUTPUT
3150 Ω
3150 Ω
5 pF
100 pF
Including
jig and
Including
jig and
scope
scope
Figure 2
Figure 1
4
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
08/20/98
®
ISSI
IS62LV12816L
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-70
-100
-120
Symbol
tRC
Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
70
—
10
—
—
—
5
—
70
—
70
35
25
—
25
—
35
25
—
100
—
15
—
—
—
5
—
100
—
120
—
15
—
—
0
—
120
—
1
tAA
Address Access Time
Output Hold Time
CE Access Time
tOHA
tACE
2
100
50
30
—
120
60
40
—
tDOE
OE Access Time
(2)
tHZOE
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
(2)
3
tLZOE
5
(2)
tHZCE
0
0
30
—
0
40
—
(2)
tLZCE
10
—
0
10
—
0
10
—
0
4
tBA
50
35
—
60
50
—
tHZB
tLZB
0
0
0
5
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels
of 0.4 to 2.2V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
6
7
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
8
t
RC
ADDRESS
9
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
10
11
12
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
5
08/20/98
®
ISSI
IS62LV12816L
AC WAVEFORMS
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
OE
tAA
tOHA
tHZOE
tHZCE
tHZB
tDOE
tLZOE
CE
tACE
tLZCE
LB, UB
tBA
tLZB
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-70
-100
-120
Symbol
tWC
Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
70
65
65
0
—
—
—
—
—
—
—
—
—
30
—
100
80
80
0
—
—
—
—
—
—
—
—
—
40
—
120
100
100
0
—
—
—
—
—
—
—
—
—
50
—
tSCE
tAW
CE to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
tHA
tSA
0
0
0
tPWB
tPWE
tSD
LB, UB Valid to End of Write
WE Pulse Width
60
60
30
0
80
80
40
0
100
100
50
0
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
tHD
(3)
tHZWE
—
5
—
5
—
(3)
tLZWE
5
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to
2.2V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to
the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
6
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
08/20/98
®
ISSI
IS62LV12816L
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (WE Controlled)
t
WC
1
ADDRESS
CE
t
HA
t
SCE
2
t
PWB
LB, UB
3
t
AW
t
PWE
4
WE
t
SA
(1)
WRITE
5
t
SD
t
HD
DIN
6
t
HZWE
t
LZWE
HIGH-Z
HIGH-Z
DOUT
UNDEFINED
UNDEFINED
7
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE
inputs and at least one of the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
8
9
10
11
12
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
7
08/20/98
®
ISSI
IS62LV12816L
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
VDR
Parameter
Test Condition
Min.
1.5
—
Max.
3.3
15
Unit
V
Vcc for Data Retention
Data Retention Current
See Data Retention Waveform
Vcc = 2.0V, CE ≥ Vcc – 0.2V
IDR
µA
ns
tSDR
Data Retention Setup Time See Data Retention Waveform
Recovery Time See Data Retention Waveform
0
—
tRDR
tRC
—
ns
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
Data Retention Mode
tRDR
VCC
2.3V
2.0V
VDR
CE
CE ≥ VCC – 0.2V
GND
8
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
08/20/98
®
ISSI
IS62LV12816L
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
1
Speed (ns) Order Part No.
Package
70
70
IS62LV12816L-70T
IS62LV12816L-70B
TSOP (Type II)
Mini BGA
2
100
100
IS62LV12816L-100T TSOP (Type II)
IS62LV12816L-100B Mini BGA
120
120
IS62LV12816L-120T TSOP (Type II)
IS62LV12816L-120B Mini BGA
3
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No.
Package
TSOP (Type II)
4
70
70
IS62LV12816L-70TI
IS62LV12816L-70BI Mini BGA
100
100
IS62LV12816L-100TI TSOP (Type II)
IS62LV12816L-100BI Mini BGA
5
120
120
IS62LV12816L-120TI TSOP (Type II)
IS62LV12816L-120BI Mini BGA
6
7
8
9
10
11
12
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Fax: (408) 588-0806
Toll Free: 1-800-379-4774
email: sales@issi.com
http://www.issi.com
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C
9
08/20/98
相关型号：
©2020 ICPDF网 联系我们和版权申明