IS62U6416LL-20B [ISSI]
64K x 16 LOW VOLTAGE, ULTRA-LOW POWER CMOS STATIC RAM; 64K ×16低电压，超低功耗CMOS静态RAM
| 型号： | IS62U6416LL-20B |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 64K x 16 LOW VOLTAGE, ULTRA-LOW POWER CMOS STATIC RAM |
| 文件： | 总9页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ISSI
IS62U6416LL
64K x 16 LOW VOLTAGE,
ADVANCE INFORMATION
DECEMBER 1998
ULTRA-LOW POWER CMOS STATIC RAM
1
FEATURES
DESCRIPTION
The ISSI IS62U6416LL is an ultra-low power, 1,048,576-bit
static RAM organized as 65,536 words by 16 bits. It is
fabricated using ISSI's high-performance CMOS technology.
This highly reliable process coupled with innovative circuit
design techniques yields access times as fast as 200 ns with
low power consumption.
• Access time: 200 ns
2
• CMOS low power operation
– 40 mW (typical) operating
– 90 µW (typical) standby
• TTL compatible interface levels
• Single 1.8V-2.7V power supply
3
WhenCEisHIGH(deselected),thedeviceassumesastandby
mode at which the power dissipation can be reduced down
with CMOS input levels.
• Fully static operation: no clock or refresh
required
4
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CEand OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
5
• Available in Jedec Std 44-pin SOJ package,
44-pin TSOP (Type II), and 48-pin mini BGA
6
FUNCTIONAL BLOCK DIAGRAM
7
64K x 16
MEMORY ARRAY
A0-A15
DECODER
8
VCC
GND
9
I/O0-I/O7
Lower Byte
I/O
DATA
COLUMN I/O
10
11
12
CIRCUIT
I/O8-I/O15
Upper Byte
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
The specification contains ADVANCE INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION SR034-0C
1
12/09/98
®
ISSI
IS62U6416LL
PIN CONFIGURATIONS
44-Pin SOJ
44-Pin TSOP
A4
A3
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A4
A3
A2
A1
A0
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
2
A6
2
A2
3
A7
3
A1
4
OE
A0
5
UB
4
CE
6
LB
5
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
7
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
CE
6
8
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
7
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
9
8
10
11
12
13
14
15
16
17
18
19
20
21
22
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A8
A9
A10
A11
NC
PIN DESCRIPTIONS
48-Pin mini BGA (Top View)
1
2
3
4
5
6
A0-A15
I/O0-I/O15
CE
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
OE
A0
A3
A1
A4
A2
LB
OE
UB
N/C
A
B
C
D
E
F
WE
I/O
8
I/O
0
CE
LB
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
I/O
9
I/O
10
I/O
1
I/O
2
A5
A6
UB
I/O
11
I/O
3
GND
Vcc
NC
NC
A14
A12
A7
Vcc
NC
I/O
12
I/O
4
GND
NC
A15
A13
A10
Vcc
Power
I/O
14
I/O
13
I/O
5
I/O
6
GND
Ground
I/O
7
I/O
15
NC
A8
WE
G
H
NC
A9
A11
NC
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION SR034-0C
12/09/98
®
ISSI
IS62U6416LL
TRUTH TABLE
I/O Pin
I/O0-I/O7 I/O8-I/O15 Vcc Current
1
Mode
WE
X
CE
H
OE
X
LB
X
UB
X
Not Selected
High-Z
High-Z
ISB1, ISB2
Output Disabled
H
X
L
L
H
X
X
H
X
H
High-Z
High-Z
High-Z
High-Z
ICC
2
Read
Write
H
H
H
L
L
L
L
L
L
L
H
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
ICC
3
L
L
L
L
L
L
X
X
X
L
H
L
H
L
L
DIN
High-Z
DIN
High-Z
DIN
DIN
ICC
4
AC TEST CONDITIONS
5
Parameter
Unit
Input Pulse Level
Input Rise and Fall Times
0.4 to 1.8V(1)
5 ns
0.9V(1)
6
Input and Output Timing and Reference Level
Output Load
See Figures 1 and 2
7
AC TEST LOADS
THEVENIN EQUIVALENT
3070 Ω
3070 Ω
1.8V
1.8V
1554 Ω
8
OUTPUT
0.91V
OUTPUT
OUTPUT
Figure 3.
3150 Ω
3150 Ω
30 pF
100 pF
Including
jig and
scope
Including
jig and
scope
9
Figure 1.
Figure 2.
10
11
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION SR034-0C
3
12/09/98
®
ISSI
IS62U6416LL
ABSOLUTE MAXIMUM RATINGS(1)
Note:
1. Stress greater than those listed under
ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the
device. This is a stress rating only and
functional operation of the device at
these or any other conditions above
those indicated in the operational sec-
tions of this specification is not im-
plied. Exposure to absolute maximum
rating conditions for extended periods
may affect reliability.
Symbol Parameter
Value
Unit
V
VTERM
TSTG
PT
Terminal Voltage with Respect to GND –0.5 to Vcc +0.5
Storage Temperature
Power Dissipation
–65 to +150
°C
W
1.5
20
IOUT
DC Output Current (LOW)
mA
OPERATING RANGE
Range
Ambient Temperature
VCC
Commercial
Industrial
0°C to +70°C
1.8V (Min.) to 2.7V (Max.)
1.8V (Min.) to 2.7V (Max.)
–40°C to +85°C
DC ELECTRICAL CHARACTERISTICS (Over Operating Range Unless Otherwise Specified)
Symbol Parameter
Test Conditions
Min.
1.6
—
Max.
Unit
V
VOH
VOL
VIH
Output HIGH Voltage
VCC = Min., IOH = –0.44 mA
VCC = Min., IOL = 0.33 mA
—
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
0.4
V
1.6
–0.2
–1
VCC + 0.2
V
(1)
VIL
ILI
0.4
1
V
GND ≤ VIN ≤ VCC
µA
µA
ILO
Output Leakage
GND ≤ VOUT ≤ VCC, Outputs Disabled
–1
1
Note:
1. VIL (min.) = –1.5V for pulse width less than 30 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range Unless Otherwise Specified)
-200
Symbol Parameter
Test Conditions
Min. Max.
Unit
ICC
Vcc Dynamic Operating
Supply Current
VCC = Max.,
IOUT = 0 mA, f = fMAX
CE = VIH
Com.
Ind.
—
—
25
40
mA
ISB1
ISB2
TTL Standby Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CE ≥ VIH , f = 0
Com.
Ind.
—
—
0.3
0.3
mA
CMOS Standby
Current (CMOS Inputs)
VCC = Max.,
CE ≥ VCC – 0.2V,
VIN ≤ 0.2V, f = 0
Com.
Ind.
—
—
5
5
µA
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency; f = 0 means no input lines change.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION SR034-0C
12/09/98
®
ISSI
IS62U6416LL
CAPACITANCE(1)
1
Symbol
Parameter
Conditions
VIN = 0V
Max.
8
Unit
pF
CIN
Input Capacitance
Input/Output Capacitance
COUT
Note:
VOUT = 0V
10
pF
2
1. Tested initially and after any design or process changes that may affect these parameters.
3
4
READ CYCLE SWITCHING CHARACTERISTICS(1)
(Over Operating Range)
5
-200
Min. Max.
Symbol Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
Read Cycle Time
200
—
20
—
—
0
—
200
—
6
tAA
Address Access Time
Output Hold Time
tOHA
tACE
tDOE
tHZOE
CE Access Time
200
100
50
7
OE Access Time
(2)
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
(2)
tLZOE
20
0
—
8
(2)
tHZCE
50
(2)
tLZCE
tBA
30
—
0
—
100
50
9
tHZB
tLZB
20
—
Notes:
10
11
12
1. Test conditions assume signal transition times of 5 ns or less, timing
reference levels of 0.9V, input pulse levels of 0.4 to 1.8V and output
loading specified in Figure 1.
2. TestedwiththeloadinFigure2.Transitionismeasured ±500mVfrom
steady-state voltage. Not 100% tested.
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION SR034-0C
5
12/09/98
®
ISSI
IS62U6416LL
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
LZOE
ACE
t
CE
t
t
HZCE
t
LZCE
LB, UB
t
BA
t
HZB
t
LZB
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION SR034-0C
12/09/98
®
ISSI
IS62U6416LL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-200
Symbol
tWC
Parameter
Min.
200
160
160
0
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
Write Cycle Time
tSCE
tAW
CE to Write End
—
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
—
2
tHA
—
tSA
0
—
tPWB
tPWE
tSD
LB, UB Valid to End of Write
WE Pulse Width
160
160
160
0
—
3
—
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
—
tHD
—
4
(3)
tHZWE
—
50
—
(3)
tLZWE
20
Notes:
5
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V,
input pulse levels of 0.4V to 1.8V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All
signals must be in valid states to initiate a Write, but any one can go inactive to terminate the
Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the
signal that terminates the write.
6
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
7
DATA RETENTION CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
1.5
—
Max.
—
Unit
VDR
Vcc for Data Retention
Data Retention Current
CE ≥ VCC – 0.2V
V
8
I
DR
V
CC = VDR
5.0
µA
CE ≥ VCC – 0.2V
t
t
SDR
RDR
Data Retention Set up Time
Recovery Time
See Data Retention Waveform
See Data Retention Waveform
0
—
—
ns
ns
9
t
RC
10
11
12
DATA RETENTION TIMING DIAGRAM
t
SDR
DATA RETENTION MODE
tRDR
VCC
1.8V
VIH
VDR
CE ≥ VCC – 0.2V
CE
GND
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION SR034-0C
7
12/09/98
®
ISSI
IS62U6416LL
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (WE Controlled)
tWC
ADDRESS
CE
tHA
tSCE
tPWB
LB, UB
tAW
tPWE
WE
tSA
(1)
WRITE
tSD
tHD
DIN
tHZWE
tLZWE
HIGH-Z
HIGH-Z
DOUT
UNDEFINED
UNDEFINED
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least
one of the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION SR034-0C
12/09/98
®
ISSI
IS62U6416LL
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
1
2
3
4
5
6
7
8
9
10
Speed (ns) Order Part No.
Package
200
IS62U6416LL-20T
IS62U6416LL-20K
IS62U6416LL-20B
Plastic TSOP (Type II)
400-mil Plastic SOJ
Mini BGA (6mm x 8mm)
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No.
Package
200
IS62U6416LL-20TI
IS62U6416LL-20KI
IS62U6416LL-20BI
Plastic TSOP (Type II)
400-mil Plastic SOJ
Mini BGA (6mm x 8mm)
NOTICE
Integrated Silicon Solution, Inc., reserves the right to make changes to the products contained in this publication in
order to improve design, performance or reliability. Integrated Silicon Solution, Inc. assumes no responsibility for the
use of any circuits described herein, conveys no license under any patent or other right, and makes no representation
thatthecircuitsarefreeofpatentinfringement. Chartsandschedulescontainedhereinreflectrepresentativeoperating
parameters, and may vary depending upon a user's specific application. While the information in this publication has
been carefully checked, Integrated Silicon Solution, Inc. shall not be liable for any damages arising as a result of any
error or omission.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where
the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to
significantlyaffectitssafetyoreffectiveness. ProductsarenotauthorizedforuseinsuchapplicationsunlessIntegrated
Silicon Solution, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been
minimized;(b)theuserassumesallsuchrisks;and(c)potentialliabilityofIntegratedSiliconSolution,Inc.isadequately
protected under the circumstances.
Copyright 1998 Integrated Silicon Solution, Inc.
Reproduction in whole or in part, without the prior written consent of Integrated Silicon Solution, Inc., is prohibited.
®
ISSI
Integrated Silicon Solution, Inc. 11
2231 Lawson Lane
Santa Clara, CA 95054
Fax: (408) 588-0806
12
Toll Free: 1-800-379-4774
email: sales@issi.com
http://www.issi.com
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION SR034-0C
9
12/09/98
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