IS62WV10008BLL-55BI [ISSI]
Standard SRAM, 1MX8, 55ns, CMOS, PBGA48, 7.20 X 8.70 MM, MINI, BGA-48;
| 型号： | IS62WV10008BLL-55BI |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Standard SRAM, 1MX8, 55ns, CMOS, PBGA48, 7.20 X 8.70 MM, MINI, BGA-48 静态存储器 |
| 文件： | 总12页 (文件大小：56K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS62WV10008ALL
IS62WV10008BLL
ISSI
PRELIMINARYINFORMATION
FEBRUARY2002
1M x 8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
DESCRIPTION
TheISSIIS62WV10008ALL/IS62WV10008BLLare high-
speed,8MbitstaticRAMsorganizedas1Mwordsby8bits.
It is fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-
performance and low power consumption devices.
• High-speed access time: 55ns, 70ns
• CMOS low power operation
– 36 mW (typical) operating
– 9 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply
When CS1 is HIGH (deselected) or when CS2 is LOW
(deselected)orwhenCS1isLOW,CS2isHIGH,thedevice
assumes a standby mode at which the power dissipation
can be reduced down with CMOS input levels.
– 1.65V--2.2V VCC (62WV10008ALL)
– 2.5V--3.6V VCC (62WV10008BLL)
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
• Fully static operation: no clock or refresh
required
TheIS62WV10008ALLandIS62WV10008BLLarepackged
in the JEDEC standard 48-pin mini BGA (7.2mm x 8.7mm)
and 44-Pin TSOP (TYPE II).
• Three state outputs
• Industrial temperature available
FUNCTIONAL BLOCK DIAGRAM
1M x 8
MEMORY ARRAY
A0-A19
DECODER
VCC
GND
I/O
DATA
CIRCUIT
COLUMN I/O
I/O0-I/O7
CS2
CS1
OE
CONTROL
CIRCUIT
WE
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00A
1
02/28/02
®
IS62WV10008ALL, IS62WV10008BLL
ISSI
PIN DESCRIPTIONS
A0-A19
CS1
Address Inputs
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
Write Enable Input
Input/Output
CS2
OE
WE
I/O0-I/O7
NC
NoConnection
Power
Vcc
GND
Ground
PIN CONFIGURATION
36-pin mini BGA (B) (7.2mm x 8.7mm)
44-pin TSOP (Type II)
1
2
3
4
5
6
A4
A3
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
2
A6
A
A
A
2
NC
NC
OE
CS
2
0
1
A2
3
A7
A
B
C
D
E
F
A1
4
OE
A0
5
CS2
A8
A
NC
NC
A
CS1
NC
4
6
3
5
CS1
NC
6
7
NC
I/O
0
A
A
NC
I/O
V
4
NC
8
NC
I/O0
I/O1
Vcc
GND
I/O2
I/O3
NC
9
I/O7
I/O6
GND
Vcc
I/O5
I/O4
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
GND
A
17
A
7
I/O
I/O
5
1
CC
V
CC
I/O
6
V
SS
I/O
NC
A
16
2
I/O
3
A
14
NC
NC
NC
A
15
I/O
7
NC
NC
WE
A19
A18
A17
A16
A15
A9
A
A
A
A10
A11
A12
A13
A14
NC
12
13
WE
NC
G
H
A
18
A
8
A
9
A
11
A
19
10
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00A
02/28/02
®
IS62WV10008ALL, IS62WV10008BLL
ISSI
OPERATING RANGE (Vcc)
Range
AmbientTemperature
0°C to +70°C
IS62WV10008ALL
1.65V - 2.2V
IS62WV10008BLL
2.5V - 3.6V
Commercial
Industrial
–40°Cto+85°C
1.65V - 2.2V
2.5V - 3.6V
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TBIAS
VCC
Parameter
Value
Unit
Terminal Voltage with Respect to GND
TemperatureUnderBias
Vcc Related to GND
–0.2 to Vcc+0.3
–40 to +85
–0.2 to +3.8
–65 to +150
1.0
V
°C
V
TSTG
PT
StorageTemperature
°C
W
PowerDissipation
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
TestConditions
Vcc
Min.
Max.
Unit
VOH
VOL
VIH
OutputHIGHVoltage
IOH = -0.1 mA
IOH = -1 mA
1.65-2.2V
2.5-3.6V
1.4
2.2
—
—
V
V
OutputLOWVoltage
Input HIGH Voltage
Input LOW Voltage
IOL = 0.1 mA
IOL = 2.1 mA
1.65-2.2V
2.5-3.6V
—
—
0.2
0.4
V
V
1.65-2.2V
2.5-3.6V
1.4
2.2
VCC + 0.2
VCC + 0.3
V
V
(1)
VIL
1.65-2.2V
2.5-3.6V
–0.2
–0.2
0.4
0.6
V
V
ILI
InputLeakage
GND ≤ VIN ≤ VCC
–1
–1
1
1
µA
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VCC, Outputs Disabled
Notes:
1. VIL (min.) = –1.0V for pulse width less than 10 ns.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00A
3
02/28/02
®
IS62WV10008ALL, IS62WV10008BLL
ISSI
CAPACITANCE(1)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
8
Unit
pF
InputCapacitance
Input/OutputCapacitance
COUT
VOUT = 0V
10
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
AC TEST CONDITIONS
Parameter
62WV10008ALL
(Unit)
62WV10008BLL
(Unit)
Input Pulse Level
0.4V to Vcc-0.2
0.4 to 2.2V
5ns
Input Rise and Fall Times
5 ns
Input and Output Timing
andReferenceLevel
VREF
VREF
OutputLoad
See Figures 1 and 2
See Figures 1 and 2
1.65-2.2V
2.5V - 3.6V
3070
R1(Ω)
R2(Ω)
3070
3150
3150
VREF
VTM
0.9V
1.8V
1.5V
2.8V
AC TEST LOADS
R1
R1
VTM
VTM
OUTPUT
OUTPUT
R2
5 pF
Including
jig and
R2
30 pF
Including
jig and
scope
scope
Figure 2
Figure 1
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00A
02/28/02
®
IS62WV10008ALL, IS62WV10008BLL
ISSI
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
62WV10008ALL
Symbol Parameter
TestConditions
Max. Max.
Max.
70
Unit
mA
mA
mA
45
55
ICC
VccDynamicOperating
SupplyCurrent
V
CC=Max.,
OUT=0mA,f=fMAX
CC=Max.,
OUT=0mA,f=0
CC=Max.,
IN=VIHorVIL
CS1=VIH ,CS2=VIL
f=1MH
Com.
Ind.
25
25
20
20
15
15
I
I
CC
1
OperatingSupply
Current
V
I
Com.
Ind.
3
3
3
3
3
3
I
SB
1
TTLStandbyCurrent
(TTLInputs)
V
V
Com.
Ind.
0.3
0.3
0.3
0.3
0.3
0.3
,
Z
I
SB
2
CMOSStandby
Current(CMOSInputs)
V
CC=Max.,
CS1 CC–0.2V,
CS2 ≤ 0.2V,
Com.
Ind.
15
15
15
15
15
15
µA
≥V
V
IN
≥
≤
V
CC –0.2V,or
VIN
0.2V,f=0
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
62WV10008BLL
Symbol Parameter
TestConditions
Max. Max.
Max.
70
Unit
mA
mA
mA
45
55
ICC
VccDynamicOperating
SupplyCurrent
V
CC=Max.,
OUT=0mA,f=fMAX
CC=Max.,
OUT=0mA,f=0
CC=Max.,
IN=VIHorVIL
CS1=VIH ,CS2=VIL
f=1MH
Com.
Ind.
35
40
30
35
25
30
I
I
CC
1
OperatingSupply
Current
V
I
Com.
Ind.
3
3
3
3
3
3
I
SB
1
TTLStandbyCurrent
(TTLInputs)
V
V
Com.
Ind.
0.3
0.3
0.3
0.3
0.3
0.3
,
Z
I
SB
2
CMOSStandby
Current(CMOSInputs)
V
CC=Max.,
CS1 CC–0.2V,
CS2 ≤ 0.2V,
Com.
Ind.
20
20
20
20
20
20
µA
≥V
V
IN
≥
≤
V
CC –0.2V,or
VIN
0.2V,f=0
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00A
5
02/28/02
®
IS62WV10008ALL, IS62WV10008BLL
ISSI
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
55 ns
70 ns
Symbol
tRC
Parameter
Min.
Max.
—
Min.
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
55
—
10
—
—
—
5
70
—
10
—
—
—
5
tAA
Address Access Time
Output Hold Time
55
—
70
—
tOHA
tACS1/tACS2
tDOE
CS1/CS2 Access Time
OE Access Time
55
25
20
—
70
35
25
—
(2)
tHZOE
OE to High-Z Output
OE to Low-Z Output
CS1/CS2 to High-Z Output
CS1/CS2 to Low-Z Output
(2)
tLZOE
(2)
tHZCS1/tHZCS2
0
20
—
0
25
—
(2)
tLZCS1/tLZCS2
10
10
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4 to 1.4V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, CS2 = WE = VIH)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00A
02/28/02
®
IS62WV10008ALL, IS62WV10008BLL
ISSI
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, CS2, OE Controlled)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
LZOE
CS1
t
ACS1/tACS2
CS2
tLZCS1/
tLZCS2
t
HZCS
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1= VIL. CS2=WE=VIH.
3. Address is valid prior to or coincident with CS1 LOW and CS2 HIGH transition.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00A
7
02/28/02
®
IS62WV10008ALL, IS62WV10008BLL
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
55 ns
70 ns
Symbol
Parameter
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
Write Cycle Time
55
45
45
0
—
—
—
—
—
—
—
—
20
—
70
60
60
0
—
—
—
—
—
—
—
—
20
—
tSCS1/tSCS2 CS1/CS2 to Write End
tAW
tHA
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
tSA
0
0
tPWE
tSD
WE Pulse Width
40
25
0
50
30
0
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
tHD
(3)
tHZWE
—
5
—
5
(3)
tLZWE
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW)
t
WC
ADDRESS
CS1
t
HA
t
SCS1
t
SCS2
CS2
t
AW
t
PWE
WE
DOUT
DIN
t
SA
t
HZWE
t
LZWE
HIGH-Z
SD
DATA UNDEFINED
t
t
HD
DATA-IN VALID
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00A
02/28/02
®
IS62WV10008ALL, IS62WV10008BLL
ISSI
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
t
WC
ADDRESS
OE
t
HA
t
SCS1
CS1
t
SCS2
CS2
t
AW
t
PWE
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
SD
DOUT
DIN
DATA UNDEFINED
t
t
HD
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
OE
t
HA
t
SCS1
CS1
t
SCS2
CS2
t
AW
t
PWE
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
SD
DOUT
DIN
DATA UNDEFINED
t
t
HD
DATA-IN VALID
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00A
9
02/28/02
®
IS62WV10008ALL, IS62WV10008BLL
ISSI
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter
TestCondition
Min.
1.0
—
Max.
Unit
V
VDR
IDR
Vcc for Data Retention
DataRetentionCurrent
SeeDataRetentionWaveform
Vcc = 1.0V, CS1/CS2 ≥ Vcc – 0.2V
3.6
15
—
—
µA
ns
tSDR
tRDR
Data Retention Setup Time SeeDataRetentionWaveform
0
RecoveryTime
SeeDataRetentionWaveform
tRC
ns
DATA RETENTION WAVEFORM (
Controlled)
t
Data Retention Mode
t
RDR
SDR
V
CC
DR
3.0V
2.2V
V
CS1 ³ V
0.2V
CC
-
CS1
GND
DATA RETENTION WAVEFORM (CS2 Controlled)
Data Retention Mode
V
CC
3.0
t
t
RDR
SDR
CS2
2.2V
V
DR
CS2 ≤ 0.2V
0.4V
GND
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00A
02/28/02
®
IS62WV10008ALL, IS62WV10008BLL
ISSI
ORDERING INFORMATION
IS62WV10008ALL (1.65V - 2.2V)
Commercial Range: 0°C to +70°C
Speed(ns)
Order Part No.
Package
70
70
IS62WV10008ALL-70T
IS62WV10008ALL-70B
TSOP
mini BGA (7.2mm x 8.7mm)
Industrial Range: –40°C to +85°C
Speed(ns)
Order Part No.
Package
70
70
70
IS62WV10008ALL-70TI
IS62WV10008ALL-70BI
IS62WV10008ALL-70XI
TSOP
mini BGA (7.2mm x 8.7mm)
DIE
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00A
11
02/28/02
®
IS62WV10008ALL, IS62WV10008BLL
ISSI
ORDERING INFORMATION
IS62WV10008BLL (2.5V - 3.6V)
Commercial Range: 0°C to +70°C
Speed(ns)
Order Part No.
Package
55
55
70
70
IS62WV10008BLL-55T
IS62WV10008BLL-55B
IS62WV10008BLL-70T
IS62WV10008BLL-70B
TSOP
mini BGA (7.2mm x 8.7mm)
TSOP
mini BGA (7.2mm x 8.7mm)
Industrial Range: –40°C to +85°C
Speed(ns)
Order Part No.
Package
55
55
70
70
70
IS62WV10008BLL-55TI
IS62WV10008BLL-55BI
IS62WV10008BLL-70TI
IS62WV10008BLL-70BI
IS62WV10008BLL-70XI
TSOP
mini BGA (7.2mm x 8.7mm)
TSOP
mini BGA (7.2mm x 8.7mm)
DIE
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00A
02/28/02
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