IS62WV1288DALL-55BLI-TR [ISSI]
Standard SRAM, 128KX8, 55ns, CMOS, PBGA36,;
| 型号： | IS62WV1288DALL-55BLI-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Standard SRAM, 128KX8, 55ns, CMOS, PBGA36, 静态存储器 |
| 文件： | 总16页 (文件大小：432K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
performanceꢀCMOSꢀtechnology.Thisꢀhighlyꢀreliableꢀprocessꢀ
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLLꢀ
ꢀ
128Kꢀxꢀ8ꢀLOWꢀVOLTAGE,ꢀ
DECEMBERꢀ2010
ULTRAꢀLOWꢀPOWERꢀCMOSꢀSTATICꢀRAM
FEATURES
DESCRIPTION
TheꢀISSIꢀIS62/65WV1288DALLꢀandꢀIS62/65WV1288DBLLꢀ
areꢀ ꢀ high-speed,ꢀ 1Mꢀ bitꢀ staticꢀ RAMsꢀ organizedꢀ asꢀ
128Kꢀwordsꢀbyꢀ8ꢀbits.ꢀItꢀisꢀfabricatedꢀusingꢀISSI'sꢀhigh-
•ꢀ High-speedꢀaccessꢀtime:ꢀꢀ35ns,ꢀ45ns,ꢀ55ns
•ꢀ CMOSꢀlowꢀpowerꢀoperation:
ꢀ 12ꢀmWꢀ(typical)ꢀoperating
coupledꢀwithꢀinnovativeꢀcircuitꢀdesignꢀtechniques,ꢀyieldsꢀ
high-performanceꢀandꢀlowꢀpowerꢀconsumptionꢀdevices.
ꢀ ꢀ4ꢀµWꢀ(typical)ꢀCMOSꢀstandby
•ꢀ TTLꢀcompatibleꢀinterfaceꢀlevels
•ꢀ Singleꢀpowerꢀsupply:ꢀꢀ
WhenꢀCS1ꢀisꢀHIGHꢀ(deselected)ꢀorꢀwhenꢀCS2ꢀisꢀLOWꢀ
(deselected),ꢀ theꢀ deviceꢀ assumesꢀ aꢀ standbyꢀ modeꢀ atꢀ
whichꢀtheꢀpowerꢀdissipationꢀcanꢀbeꢀreducedꢀdownꢀwithꢀ
CMOSꢀinputꢀlevels.
ꢀ ꢀ1.65V--2.2VꢀVdd (62WV1288dALL)
ꢀ ꢀ2.3V--3.6VꢀVdd (62WV1288dBLL)
EasyꢀmemoryꢀexpansionꢀisꢀprovidedꢀbyꢀusingꢀChipꢀEnableꢀ
andꢀOutputꢀEnableꢀinputs.ꢀTheꢀactiveꢀLOWꢀWriteꢀEnableꢀ
(WE)ꢀcontrolsꢀbothꢀwritingꢀandꢀreadingꢀofꢀtheꢀmemory.
•ꢀ Fullyꢀstaticꢀoperation:ꢀnoꢀclockꢀorꢀrefreshꢀ
required
TheꢀIS62/65WV1288DALLꢀandꢀIS62/65WV1288DBLLꢀareꢀ
packagedꢀinꢀtheꢀJEDECꢀstandardꢀ32-pinꢀTSOPꢀ(TYPEI),ꢀ
sTSOPꢀ(TYPEI),ꢀSOP,ꢀandꢀ36-pinꢀminiꢀBGA.
•ꢀ Threeꢀstateꢀoutputs
•ꢀ Industrialꢀandꢀautomotiveꢀtemperatureꢀsupport
•ꢀ Lead-freeꢀavailableꢀ
FUNCTIONALꢀBLOCKꢀDIAGRAM
128K x 8
MEMORY ARRAY
A0-A16
DECODER
VDD
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CS2
CS1
OE
CONTROL
CIRCUIT
WE
Copyrightꢀ©ꢀ2010ꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀꢀAllꢀrightsꢀreserved.ꢀꢀISSIꢀreservesꢀtheꢀrightꢀtoꢀmakeꢀchangesꢀtoꢀthisꢀspecificationꢀandꢀitsꢀproductsꢀatꢀanyꢀtimeꢀwithoutꢀ
notice.ꢀꢀꢀISSIꢀassumesꢀnoꢀliabilityꢀarisingꢀoutꢀofꢀtheꢀapplicationꢀorꢀuseꢀofꢀanyꢀinformation,ꢀproductsꢀorꢀservicesꢀdescribedꢀherein.ꢀCustomersꢀareꢀadvisedꢀtoꢀobtainꢀtheꢀlat-
estꢀversionꢀofꢀthisꢀdeviceꢀspecificationꢀbeforeꢀrelyingꢀonꢀanyꢀpublishedꢀinformationꢀandꢀbeforeꢀplacingꢀordersꢀforꢀproducts.
IntegratedꢀSiliconꢀSolution,ꢀInc.ꢀdoesꢀnotꢀrecommendꢀtheꢀuseꢀofꢀanyꢀofꢀitsꢀproductsꢀinꢀlifeꢀsupportꢀapplicationsꢀwhereꢀtheꢀfailureꢀorꢀmalfunctionꢀofꢀtheꢀproductꢀcanꢀreason-
ablyꢀbeꢀexpectedꢀtoꢀcauseꢀfailureꢀofꢀtheꢀlifeꢀsupportꢀsystemꢀorꢀtoꢀsignificantlyꢀaffectꢀitsꢀsafetyꢀorꢀeffectiveness.ꢀProductsꢀareꢀnotꢀauthorizedꢀforꢀuseꢀinꢀsuchꢀapplicationsꢀ
unlessꢀIntegratedꢀSiliconꢀSolution,ꢀInc.ꢀreceivesꢀwrittenꢀassuranceꢀtoꢀitsꢀsatisfaction,ꢀthat:
a.)ꢀtheꢀriskꢀofꢀinjuryꢀorꢀdamageꢀhasꢀbeenꢀminimized;
b.)ꢀtheꢀuserꢀassumeꢀallꢀsuchꢀrisks;ꢀand
c.)ꢀpotentialꢀliabilityꢀofꢀIntegratedꢀSiliconꢀSolution,ꢀIncꢀisꢀadequatelyꢀprotectedꢀunderꢀtheꢀcircumstancesꢀꢀ
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
1
Rev.ꢀ B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLLꢀ
PIN CONFIGURATION
32-pinꢀTSOPꢀ(TYPEꢀI)ꢀ(T),ꢀꢀ
32-pinꢀsTSOPꢀ(TYPEꢀI)ꢀ(H)ꢀ
36-pinꢀminiꢀBGAꢀ(B)ꢀꢀ(6mmꢀxꢀ8mm)ꢀ
1
2
3
4
5
6
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A11
A9
A8
A13
WE
CS2
A15
1
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
2
3
4
A
B
C
D
E
F
A0
A1
A2
CS2
WE
NC
A3
A4
A5
A6
A7
A8
5
I/O4
I/O5
GND
I/O0
I/O1
6
7
VDD
8
V
DD
NC
A16
A14
A12
A7
A6
A5
A4
9
V
DD
GND
I/O2
I/O3
A14
10
11
12
13
14
15
16
I/O6
I/O7
A9
NC
CS1
A11
NC
A16
A12
OE
A15
A13
G
H
A10
A1
A2
A3
PINꢀDESCRIPTIONS
32-pinꢀSOPꢀ(Q)
A0-A16ꢀ ꢀ
AddressꢀInputs
CS1ꢀꢀ
CS2ꢀꢀ
OEꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ChipꢀEnableꢀ1ꢀInputꢀ
ChipꢀEnableꢀ2ꢀInputꢀ
OutputꢀEnableꢀInput
WriteꢀEnableꢀInput
Input/Output
NC
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
2
A15
CS2
WE
A13
A8
WEꢀꢀ
3
4
I/O0-I/O7ꢀ
5
NCꢀ
ꢀ
ꢀ
ꢀ
NoꢀConnection
Power
A6
6
Vddꢀ
GNDꢀ
A5
7
A9
Ground
A4
8
A11
OE
A3
9
A2
10
11
12
13
14
15
16
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
A1
A0
I/O0
I/O1
I/O2
GND
2ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLLꢀ
TRUTHꢀTABLE
ꢀ
Modeꢀ
WEꢀ
CS1ꢀ CS2ꢀ OEꢀ
I/OꢀOperationꢀ
VDDꢀCurrentꢀ
ꢀ
NotꢀSelectedꢀ
(Power-down)ꢀ
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Lꢀ
Xꢀ
Xꢀ
ꢀ High-Zꢀꢀꢀ
ꢀ High-Z
isB1, isB2
isB1, isB2ꢀ
ꢀ
ꢀ
ꢀ
OutputꢀDisabledꢀ
Readꢀ
Writeꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
ꢀ High-Zꢀ
dOutꢀ
dinꢀ
iCCꢀ
iCCꢀ
iCCꢀ
ABSOLUTEꢀMAXIMUMꢀRATINGS(1)
ꢀ
Symbolꢀ Parameterꢀ
Valueꢀ
–0.5ꢀtoꢀVddꢀ+ꢀ0.5ꢀ
–0.3ꢀtoꢀ4.0ꢀ
–65ꢀtoꢀ+150ꢀ
1.0ꢀ
Unit
V
V
°C
W
ꢀ Vterm
ꢀ Vdd
ꢀ tstg
ꢀ Pt
TerminalꢀVoltageꢀwithꢀRespectꢀtoꢀGNDꢀ
VddꢀRelatesꢀtoꢀGNDꢀ
StorageꢀTemperatureꢀ
PowerꢀDissipationꢀ
Notes:
1.ꢀꢀStressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀ
theꢀdevice.ꢀThisꢀisꢀaꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀ
aboveꢀthoseꢀindicatedꢀinꢀtheꢀoperationalꢀsectionsꢀofꢀthisꢀspecificationꢀisꢀnotꢀimplied.ꢀExposureꢀtoꢀabsoluteꢀ
maximumꢀratingꢀconditionsꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀreliability.ꢀ
CAPACITANCE(1,2)
ꢀ
Symbolꢀ
Parameterꢀ
Conditionsꢀ
Vin = 0V
Max.ꢀ
6ꢀ
Unit
pF
ꢀ Cin
InputꢀCapacitanceꢀ
Input/OutputꢀCapacitanceꢀ
ꢀ Ci/Oꢀ
VOut = 0V
8ꢀ
pF
Notes:
1.ꢀꢀTestedꢀinitiallyꢀandꢀafterꢀanyꢀdesignꢀorꢀprocessꢀchangesꢀthatꢀmayꢀaffectꢀtheseꢀparameters.
2.ꢀ Testꢀconditions:ꢀTA = 25°C, fꢀ=ꢀ1ꢀMHz,ꢀVddꢀ=ꢀ3.3V.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
3
Rev.ꢀ B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLLꢀ
ACꢀTESTꢀCONDITIONS
ꢀ
ꢀ
Parameterꢀ
ꢀ
Unitꢀ
(2.3V-3.6V)ꢀ
Unitꢀ
(3.3Vꢀ+ꢀ5%)ꢀ
Unitꢀ
(1.65V-2.2V)
ꢀ
ꢀ
ꢀ
InputꢀPulseꢀLevelꢀ
0.4VꢀtoꢀVddꢀ-ꢀ0.3Vꢀ
1V/ꢀnsꢀ
0.4VꢀtoꢀVddꢀ-ꢀ0.3Vꢀ
1V/ꢀnsꢀ
0.4VꢀtoꢀVddꢀ-ꢀ0.3V
1V/ꢀns
ꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
ꢀ
ꢀ
InputꢀandꢀOutputꢀTimingꢀ
andꢀReferenceꢀLevelꢀ(VRef)ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ2
VDDꢀ/2ꢀ
VDDꢀꢀ+ꢀ0.05ꢀ
0.9V
ꢀ
ꢀ
ꢀ
ꢀ
OutputꢀLoadꢀ
R1ꢀ( Ω )ꢀ
R2ꢀ( Ω )ꢀ
Vtmꢀ(V)ꢀ
SeeꢀFiguresꢀ1ꢀandꢀ2ꢀ
SeeꢀFiguresꢀ1ꢀandꢀ2ꢀ
SeeꢀFiguresꢀ1ꢀandꢀ2
13500
317ꢀ
351ꢀ
3.3Vꢀ
317ꢀ
351ꢀ
3.3Vꢀ
10800
1.8V
ACꢀTESTꢀLOADS
R1
R1
VTM
OUTPUT
VTM
OUTPUT
R2
5 pF
Including
jig and
R2
30 pF
Including
jig and
scope
scope
Figureꢀ1.
Figureꢀ2.
4ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLLꢀ
DCꢀELECTRICALꢀCHARACTERISTICSꢀ(OverꢀOperatingꢀRange)
VDDꢀ=ꢀ3.3Vꢀ+ꢀ5%
ꢀ
Symbolꢀ Parameterꢀ
TestꢀConditionsꢀ
Vdd = Min.,ꢀiOh = –1ꢀmAꢀ
Min.ꢀ
2.4ꢀ
—ꢀ
2ꢀ
–0.3ꢀ
–1ꢀ
Max.ꢀ
—ꢀ
0.4ꢀ
Unit
V
V
V
V
ꢀ VOh
ꢀ VOL
ꢀ Vih
ꢀ ViL
ꢀ iLi
OutputꢀHIGHꢀVoltageꢀ
OutputꢀLOWꢀVoltageꢀ
InputꢀHIGHꢀVoltageꢀ
InputꢀLOWꢀVoltage(1)ꢀ
InputꢀLeakageꢀ
Vdd = Min.,ꢀiOL = 2.1ꢀmAꢀ
ꢀ
ꢀ
Vdd + 0.3
0.8ꢀ
ꢀ
GNDꢀ≤ꢀVin ≤ Vdd
1ꢀ
1ꢀ
µA
µA
ꢀ iLO
OutputꢀLeakageꢀ
GNDꢀ≤ꢀVOut ≤ Vdd, OutputsꢀDisabledꢀ
–1ꢀ
Note:
1.ꢀꢀViL (min.)ꢀ= –0.3VꢀDC;ꢀViLꢀ(min.)ꢀ=ꢀ–2.0VꢀACꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
Vih (max.)ꢀ= Vdd +ꢀ0.3V dC;ꢀVih (max.)ꢀ= Vdd +ꢀ2.0V ACꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
ꢀ
DCꢀELECTRICALꢀCHARACTERISTICSꢀ(OverꢀOperatingꢀRange)
VDDꢀ=ꢀ2.3V-3.6Vꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Symbolꢀ Parameterꢀ
TestꢀConditionsꢀ
Min.ꢀ
1.8ꢀ
—ꢀ
Max.ꢀ
—ꢀ
Unit
V
ꢀ VOh
ꢀ VOL
ꢀ Vih
ꢀ ViL
ꢀ iLi
ꢀ iLO
OutputꢀHIGHꢀVoltageꢀ
OutputꢀLOWꢀVoltageꢀ
InputꢀHIGHꢀVoltageꢀ
InputꢀLOWꢀVoltage(1)ꢀ
InputꢀLeakageꢀ
Vdd = Min.,ꢀiOh = –1.0ꢀmAꢀ
Vdd = Min.,ꢀiOL = 2.1ꢀmAꢀ
0.4ꢀ
V
ꢀ
ꢀ
2.0ꢀ
–0.3ꢀ
–1ꢀ
Vdd + 0.3
0.8ꢀ
V
V
ꢀ
GNDꢀ≤ꢀ Vin ≤ Vdd
1ꢀ
µA
µA
OutputꢀLeakageꢀ
GNDꢀ≤ꢀ VOut ≤ Vdd, OutputsꢀDisabledꢀ
–1ꢀ
1ꢀ
Note:
1.ꢀ ViL (min.)ꢀ= –0.3VꢀDC;ꢀViLꢀ(min.)ꢀ=ꢀ–2.0VꢀACꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
Vih (max.)ꢀ= Vdd +ꢀ0.3V dC;ꢀVih (max.)ꢀ= Vdd +ꢀ2.0V ACꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
ꢀ
DCꢀELECTRICALꢀCHARACTERISTICSꢀ(OverꢀOperatingꢀRange)
VDD =ꢀ1.65V-2.2V
ꢀ
Symbolꢀ Parameterꢀ
TestꢀConditionsꢀ
VDDꢀ
Min.ꢀ
1.4ꢀ
—ꢀ
Max.ꢀ
—ꢀ
Unit
V
ꢀ VOh
ꢀ VOL
ꢀ Vih
OutputꢀHIGHꢀVoltageꢀ
OutputꢀLOWꢀVoltageꢀ
InputꢀHIGHꢀVoltageꢀ
InputꢀLOWꢀVoltageꢀ
InputꢀLeakageꢀ
iOh = -0.1ꢀmAꢀ
1.65-2.2Vꢀ
1.65-2.2Vꢀ
1.65-2.2Vꢀ
1.65-2.2Vꢀ
iOL = 0.1ꢀmAꢀ
0.2ꢀ
V
ꢀ
1.4ꢀ
–0.2ꢀ
–1ꢀ
Vdd + 0.2
0.4ꢀ
V
(1)
ꢀ ViL
ꢀ iLi
ꢀ
V
ꢀ
GNDꢀ≤ꢀ Vin ≤ ꢀVdd
1ꢀ
µA
µA
ꢀ iLO
OutputꢀLeakageꢀ
GNDꢀ≤ꢀ VOut ≤ ꢀVdd, OutputsꢀDisabledꢀ
–1ꢀ
1ꢀ
Note:
1.ꢀ ViL (min.)ꢀ= –0.3VꢀDC;ꢀViLꢀ(min.)ꢀ=ꢀ–2.0VꢀACꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
Vih (max.)ꢀ= Vdd +ꢀ0.3V dC;ꢀVih (max.)ꢀ= Vdd +ꢀ2.0V ACꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
ꢀ
Integrated Silicon Solution, Inc. — www.issi.comꢀ
5
Rev.ꢀ B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLLꢀ
OPERATINGꢀRANGEꢀ(VDD)
ꢀ Rangeꢀ
AmbientꢀTemperature
0°Cꢀtoꢀ+70°Cꢀ
VDD
Speed
45ns
55ns
55ns
ꢀ Commercialꢀ
ꢀ Industrialꢀ
ꢀ Automotiveꢀ
1.65V-2.2Vꢀ
1.65V-2.2Vꢀ
1.65V-2.2Vꢀ
–40°Cꢀtoꢀ+85°Cꢀ
–40°Cꢀtoꢀ+125°Cꢀ
OPERATINGꢀRANGEꢀ(VDD)
ꢀ Rangeꢀ
AmbientꢀTemperature
0°Cꢀtoꢀ+70°Cꢀ
VDD (45 nS)
2.3V-3.6Vꢀ
2.3V-3.6Vꢀ
VDD (35 nS)
3.3V+5%
3.3V+5%
ꢀ Commercialꢀ
ꢀ Industrialꢀ
–40°Cꢀtoꢀ+85°Cꢀ
OPERATINGꢀRANGEꢀ(VDD)
ꢀ Rangeꢀ
AmbientꢀTemperature
VDD (45 nS)
ꢀ Automotiveꢀ
–40°Cꢀtoꢀ+125°Cꢀ
2.3V-3.6V
POWERꢀSUPPLYꢀCHARACTERISTICS(1)ꢀ(OverꢀOperatingꢀRange)
ꢀ
ꢀ
-35ꢀ
-45ꢀ
-55ꢀ
ꢀ Symbolꢀ Parameterꢀ
TestꢀConditionsꢀ
ꢀ
Min.ꢀ Max.ꢀ
Min.ꢀ Max.ꢀ
Min.ꢀ Max.ꢀ
Unit
ꢀ iCC
ꢀ ꢀ
ꢀ ꢀ
ꢀ ꢀ
ꢀ ꢀ
VddꢀDynamicꢀOperatingꢀ
SupplyꢀCurrentꢀ
ꢀ
ꢀ
ꢀ
Vdd = Max.,ꢀꢀ
iOut = 0 mA,ꢀfꢀ=ꢀfmAx
CS1ꢀ=ꢀViLꢀ
Vin ≥ Vdd – 0.3V, orꢀ
Vin ≤ 0.4V
Com.ꢀ
Ind.ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ4ꢀ
ꢀ
8ꢀ
12ꢀ
15ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
6ꢀ
8ꢀ
12ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
5ꢀ
7ꢀ
12ꢀ
ꢀ
mA
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Auto.ꢀ
typ.(2)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
iCC1
Operatingꢀ
SupplyꢀCurrentꢀ
ꢀ
ꢀ
ꢀ
Vdd = Max.,ꢀꢀ
iOut = 0 mA,ꢀfꢀ=ꢀ0
CS1ꢀ=ꢀViLꢀ
Vin ≥ Vdd – 0.3V, orꢀ
Vin ≤ 0.4V
Com.ꢀ
Ind.ꢀ
Auto.ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
2.5ꢀ
2.5ꢀ
3ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
2.5ꢀ
2.5ꢀ
3ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
2.5ꢀ
2.5ꢀ
3ꢀ
mA
ꢀ ꢀ
ꢀ ꢀ
ꢀ ꢀ
ꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ isB2ꢀ
ꢀ ꢀ
CMOSꢀStandbyꢀ
Currentꢀ(CMOSꢀInputs)ꢀ
Vdd = Max.,ꢀ
Com.
Ind.
—
—
—ꢀ
2
4
18ꢀ
—
—
—
2ꢀ
4
18
—ꢀ
—ꢀ
—ꢀ
2ꢀ
4
18
µA
CS1ꢀ≥ꢀVdd – 0.2V,
Vin ≥ Vdd – 0.2V, orꢀ
Vin ≤ 0.2V, fꢀ=ꢀ0ꢀ
Auto.ꢀ
ꢀ ꢀ
ꢀ
typ.(2)
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ0.6
Note:
1.ꢀꢀAtꢀfꢀ=ꢀfmAx,ꢀaddressꢀandꢀdataꢀinputsꢀareꢀcyclingꢀatꢀtheꢀmaximumꢀfrequency,ꢀfꢀ=ꢀ0ꢀmeansꢀnoꢀinputꢀlinesꢀchange.
2.ꢀTypicalꢀvaluesꢀareꢀmeasuredꢀatꢀVddꢀ=ꢀ3.0V,ꢀTAꢀ=ꢀ25oCꢀandꢀnotꢀ100%ꢀtested.
6ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLLꢀ
READꢀCYCLEꢀSWITCHINGꢀCHARACTERISTICS(1)ꢀ(OverꢀOperatingꢀRange)
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀ
ꢀ 35ꢀns
ꢀ
ꢀ
ꢀ 45ꢀnsꢀꢀ ꢀ
ꢀ 55ꢀnsꢀ ꢀ
ꢀ Symbolꢀ
Parameterꢀ
Min.ꢀ ꢀ Max.ꢀ
35ꢀ ꢀ —ꢀ
—ꢀ ꢀ 35ꢀ
10ꢀ ꢀ —ꢀ
—ꢀ ꢀ 35ꢀ
—ꢀ ꢀ 10ꢀ
—ꢀ ꢀ 10ꢀ
3ꢀ ꢀ —ꢀ
0ꢀ ꢀ 10ꢀꢀ
5ꢀ ꢀ —ꢀ
Min.ꢀ ꢀ Max.ꢀ
Min.ꢀ ꢀ Max.ꢀ ꢀ Unit
ꢀ ꢀ trCꢀ
ReadꢀCycleꢀTimeꢀ
45ꢀ ꢀ —ꢀ
—ꢀ ꢀ 45ꢀ
10ꢀ ꢀ —ꢀ
—ꢀ ꢀ 45ꢀ
—ꢀ ꢀ 20ꢀ
—ꢀ ꢀ 15ꢀ
55ꢀ ꢀ —ꢀ
—ꢀ ꢀ 55ꢀ
10ꢀ ꢀ —ꢀ
—ꢀ ꢀ 55ꢀ
—ꢀ ꢀ 25ꢀ
—ꢀ ꢀ 20ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ꢀ ꢀ tAAꢀ
AddressꢀAccessꢀTimeꢀ
OutputꢀHoldꢀTimeꢀ
ꢀ ꢀ tOhAꢀ
ꢀ ꢀ tACs1/tACs2ꢀ
ꢀ ꢀ tdOeꢀ
CS1/CS2ꢀAccessꢀTimeꢀ
OEꢀAccessꢀTimeꢀ
(2)
ꢀ ꢀ thzOe ꢀ
OEꢀtoꢀHigh-ZꢀOutputꢀ
OEꢀtoꢀLow-ZꢀOutputꢀ
(2)
ꢀ ꢀ tLzOe ꢀ
5ꢀ
ꢀ
—ꢀ
5ꢀ
0ꢀ
ꢀ
ꢀ
—ꢀ
20ꢀ
(2)
ꢀ ꢀ thzCs1/thzCs2 ꢀ CS1/CS2ꢀtoꢀHigh-ZꢀOutputꢀ
0ꢀ ꢀ 15ꢀ
10ꢀ ꢀ —ꢀ
(2)
ꢀ ꢀ tLzCs1/tLzCs2 ꢀ CS1/CS2ꢀtoꢀLow-ZꢀOutputꢀ
10ꢀ ꢀ —ꢀ
Notes:ꢀ
1.ꢀ Testꢀconditionsꢀassumeꢀsignalꢀtransitionꢀtimesꢀofꢀ5ꢀnsꢀorꢀless,ꢀtimingꢀreferenceꢀlevelsꢀofꢀ0.9V/1.5V,ꢀinputꢀpulseꢀlevelsꢀofꢀ0.4ꢀtoꢀ
Vdd-0.2V/Vdd-0.3VꢀandꢀoutputꢀloadingꢀspecifiedꢀinꢀFigureꢀ1.
2.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ2.ꢀTransitionꢀisꢀmeasuredꢀ 500ꢀmVꢀfromꢀsteady-stateꢀvoltage.ꢀNotꢀ100%ꢀtested.
Integrated Silicon Solution, Inc. — www.issi.comꢀ
7
Rev.ꢀ B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLLꢀ
ACꢀWAVEFORMS
READꢀCYCLEꢀNO.ꢀ1(1,2)ꢀ(AddressꢀControlled)ꢀ(CS1ꢀ=ꢀOEꢀ=ꢀViL, Cs2ꢀ=ꢀWEꢀ=ꢀVih)
tRC
ADDRESS
t
AA
t
OHA
tOHA
DATA VALID
DOUT
PREVIOUS DATA VALID
ACꢀWAVEFORMS
READꢀCYCLEꢀNO.ꢀ2(1,3)ꢀ (CS1,ꢀCS2,ꢀꢀOEꢀControlled)
t
RC
ADDRESS
OE
t
AA
tOHA
t
HZOE
tDOE
t
LZOE
CS1
t
ACS1/tACS2
CS2
t
LZCS1/
LZCS2
t
tHZCS
HIGH-Z
DOUT
DATA VALID
Notes:ꢀ
1.ꢀ WEꢀisꢀHIGHꢀforꢀaꢀReadꢀCycle.
2.ꢀ Theꢀdeviceꢀisꢀcontinuouslyꢀselected.ꢀOE,ꢀCS1=ꢀViL. Cs2=WE=Vih.
3.ꢀ AddressꢀisꢀvalidꢀpriorꢀtoꢀorꢀcoincidentꢀwithꢀCS1ꢀLOWꢀandꢀCs2 highꢀtransition.
8ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ B
12/01/2010
ꢀ ꢀ thdꢀ
ꢀ ꢀ thzWe ꢀ
ꢀ ꢀ tLzWe ꢀ
0ꢀ ꢀ —ꢀ ꢀꢀꢀꢀꢀ
—ꢀ ꢀ 20ꢀ ꢀꢀꢀꢀꢀ
5ꢀ ꢀ —ꢀ ꢀꢀꢀꢀꢀ
ns
ns
ns
AddressꢀHoldꢀfromꢀWriteꢀEndꢀ
AddressꢀSetupꢀTimeꢀ
0ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
25ꢀ ꢀ —ꢀꢀ
20ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
—ꢀ ꢀ 10ꢀ
3ꢀ ꢀ —ꢀꢀ
0ꢀ ꢀ —ꢀ ꢀꢀꢀꢀꢀ
0ꢀ ꢀ —ꢀ ꢀꢀꢀꢀꢀ
ns
ns
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLLꢀ
WRITEꢀCYCLEꢀSWITCHINGꢀCHARACTERISTICS(1,2)ꢀ(OverꢀOperatingꢀRange)
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀ
ꢀ 35nsꢀ ꢀ
ꢀ 45nsꢀ ꢀ
ꢀ 55ꢀnsꢀ
ꢀ Symbolꢀ
Parameterꢀ
Min.ꢀ ꢀ Max.ꢀꢀꢀ
Min.ꢀꢀMax.ꢀ
ꢀꢀMin.ꢀꢀMax.ꢀ ꢀꢀꢀ Unit
55ꢀ ꢀ —ꢀ ꢀꢀꢀꢀ ns
45ꢀ ꢀ —ꢀ ꢀꢀꢀꢀ ns
45ꢀ ꢀ —ꢀ ꢀꢀꢀꢀ ns
ꢀ ꢀ tWCꢀ
ꢀ ꢀ tsCs1/tsCs2
ꢀ ꢀ tAWꢀ
ꢀ ꢀ thAꢀ
ꢀ ꢀ tsAꢀ
WriteꢀCycleꢀTimeꢀ
35ꢀꢀ ꢀ —ꢀ
25ꢀ ꢀ —ꢀ
45ꢀꢀ ꢀ —ꢀ
35ꢀ ꢀ —ꢀ
35ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
35ꢀ ꢀ —ꢀ
20ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
—ꢀ ꢀ 20ꢀ
5ꢀ ꢀ —ꢀ
CS1/CS2ꢀtoꢀWriteꢀEndꢀ
AddressꢀSetupꢀTimeꢀtoꢀWriteꢀEndꢀꢀ 25ꢀ ꢀ —ꢀ
ꢀ ꢀ tPWeꢀ
ꢀ ꢀ tsdꢀ
WEꢀPulseꢀWidthꢀ
40ꢀ ꢀ —ꢀ ꢀꢀꢀꢀꢀns
25ꢀ ꢀ —ꢀ ꢀꢀꢀꢀ ns
DataꢀSetupꢀtoꢀWriteꢀEndꢀ
DataꢀHoldꢀfromꢀWriteꢀEndꢀ
WEꢀLOWꢀtoꢀHigh-ZꢀOutputꢀ
WEꢀHIGHꢀtoꢀLow-ZꢀOutputꢀ
(3)
(3)
Notes:ꢀ
1.ꢀ Testꢀconditionsꢀassumeꢀsignalꢀtransitionꢀtimesꢀofꢀ5ꢀnsꢀorꢀless,ꢀtimingꢀreferenceꢀlevelsꢀofꢀ0.9V/1.5V,ꢀinputꢀpulseꢀlevelsꢀofꢀ0.4Vꢀtoꢀ
Vdd-0.2V/Vdd-0.3VꢀandꢀoutputꢀloadingꢀspecifiedꢀinꢀFigureꢀ1.
2.ꢀ TheꢀinternalꢀwriteꢀtimeꢀisꢀdefinedꢀbyꢀtheꢀoverlapꢀofꢀCS1ꢀLOW,ꢀCS2ꢀHIGHꢀandꢀUBꢀorꢀLB,ꢀandꢀWEꢀLOW.ꢀAllꢀsignalsꢀmustꢀbeꢀinꢀ
validꢀstatesꢀtoꢀinitiateꢀaꢀWrite,ꢀbutꢀanyꢀoneꢀcanꢀgoꢀinactiveꢀtoꢀterminateꢀtheꢀWrite.ꢀTheꢀDataꢀInputꢀSetupꢀandꢀHoldꢀtimingꢀareꢀ
referencedꢀtoꢀtheꢀrisingꢀorꢀfallingꢀedgeꢀofꢀtheꢀsignalꢀthatꢀterminatesꢀtheꢀwrite.
3.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ2.ꢀTransitionꢀisꢀmeasuredꢀ 500ꢀmVꢀfromꢀsteady-stateꢀvoltage.ꢀNotꢀ100%ꢀtested.
ACꢀWAVEFORMS
WRITEꢀCYCLEꢀNO.ꢀ1ꢀ(CS1/CS2ꢀControlled,ꢀOEꢀ=ꢀHIGHꢀorꢀLOW)
t
WC
ADDRESS
CS1
t
HA
tSCS1
tSCS2
CS2
tAW
t
PWE
WE
DOUT
DIN
t
SA
tHZWE
t
LZWE
HIGH-Z
SD
DATA UNDEFINED
t
t
HD
DATA-IN VALID
Integrated Silicon Solution, Inc. — www.issi.comꢀ
9
Rev.ꢀ B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLLꢀ
ACꢀWAVEFORMS
WRITEꢀCYCLEꢀNO.ꢀ2ꢀ(WEꢀControlled:ꢀOEꢀisꢀHIGHꢀDuringꢀWriteꢀCycle)
t
WC
ADDRESS
OE
t
HA
tSCS1
CS1
tSCS2
CS2
tAW
t
PWE
WE
t
SA
tHZWE
t
LZWE
HIGH-Z
SD
DOUT
DIN
DATA UNDEFINED
t
t
HD
DATA-IN VALID
WRITEꢀCYCLEꢀNO.ꢀ3ꢀ(WEꢀControlled:ꢀOEꢀisꢀLOWꢀDuringꢀWriteꢀCycle)
t
WC
ADDRESS
OE
t
HA
tSCS1
CS1
tSCS2
CS2
tAW
t
PWE
WE
t
SA
tHZWE
t
LZWE
HIGH-Z
SD
DOUT
DIN
DATA UNDEFINED
t
t
HD
DATA-IN VALID
10ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLLꢀ
DATAꢀRETENTIONꢀSWITCHINGꢀCHARACTERISTICS
ꢀ ꢀSymbolꢀ Parameterꢀ
ddꢀforꢀDataꢀRetentionꢀ
TestꢀConditionꢀ
ꢀ
Min.ꢀ typ.(1)ꢀ Max.ꢀ Unit
ꢀ ꢀ Vdr
ꢀ
V
SeeꢀDataꢀRetentionꢀWaveformꢀ
ꢀ
1.2ꢀ
ꢀ
3.6ꢀ
V
ꢀ ꢀ idr
ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ
ꢀ
DataꢀRetentionꢀCurrentꢀ
ꢀ
ꢀ
V
ꢀ
ꢀ
ddꢀ=ꢀ1.2V,ꢀCS1ꢀ≥ꢀVddꢀ–ꢀ0.2Vꢀ
Com.ꢀ
Ind.ꢀ
Auto.ꢀ
—ꢀ
ꢀ
ꢀ
0.5ꢀ
ꢀ
ꢀ
2ꢀ
4ꢀ
18
µAꢀ
ꢀꢀ
ꢀ ꢀ tsdr
DataꢀRetentionꢀSetupꢀTimeꢀ SeeꢀDataꢀRetentionꢀWaveformꢀ
ꢀ
ꢀ
0ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ns
ns
ꢀ ꢀ trdr
RecoveryꢀTimeꢀ SeeꢀDataꢀRetentionꢀWaveformꢀ
t
rC
ꢀ
Note:ꢀ1.ꢀTypicalꢀvaluesꢀareꢀmeasuredꢀatꢀVddꢀ=ꢀ3.0V,ꢀTAꢀ=ꢀ25oCꢀandꢀnotꢀ100%ꢀtested.
DATAꢀRETENTIONꢀWAVEFORMꢀ(CS1ꢀControlled)
t
Data Retention Mode
t
RDR
SDR
VDD
V
DR
CS1 ≥ V
0.2V
DD
-
CS1
GND
DATAꢀRETENTIONꢀWAVEFORMꢀ(CS2ꢀControlled)
Data Retention Mode
V
DD
t
t
RDR
SDR
CS2
V
DR
CS2 ≤ 0.2V
GND
Integrated Silicon Solution, Inc. — www.issi.comꢀ
11
Rev.ꢀ B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLLꢀ
ORDERINGꢀINFORMATION
IS62WV1288DALLꢀ(1.65Vꢀ-ꢀ2.2V)
IndustrialꢀRange:ꢀ–40°Cꢀtoꢀ+85°C
ꢀ
Speedꢀ(ns)ꢀ
OrderꢀPartꢀNo.ꢀ
Package
ꢀ
55ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
IS62WV1288DALL-55TIꢀ
IS62WV1288DALL-55TLIꢀ
IS62WV1288DALL-55HIꢀ
IS62WV1288DALL-55HLIꢀ
TSOP-Iꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
TSOP-I,ꢀLead-freeꢀ
sTSOP-Iꢀ
sTSOP-I,ꢀLead-free
miniꢀBGAꢀ(6mmꢀxꢀ8mm)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
IS62WV1288DALL-55BIꢀ
IS62WV1288DALL-55BLIꢀ
ꢀ
ꢀ
miniꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-free
ORDERINGꢀINFORMATION
IS62WV1288DBLLꢀ(2.3Vꢀ-ꢀ3.6V)
IndustrialꢀRange:ꢀ–40°Cꢀtoꢀ+85°C1
ꢀ
Speedꢀ(ns)ꢀ
OrderꢀPartꢀNo.ꢀ
Package
ꢀ
45ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
IS62WV1288DBLL-45TIꢀ
IS62WV1288DBLL-45TLIꢀ
IS62WV1288DBLL-45HIꢀ
IS62WV1288DBLL-45HLIꢀ
IS62WV1288DBLL-45QIꢀ
IS62WV1288DBLL-45QLIꢀ
TSOP-Iꢀ
TSOP-I,ꢀLead-freeꢀ
sTSOP-Iꢀ
sTSOP-I,ꢀLead-freeꢀ
SOPꢀ ꢀ
SOP,ꢀLead-free
miniꢀBGAꢀ(6mmꢀxꢀ8mm)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
IS62WV1288DBLL-45BIꢀ
IS62WV1288DBLL-45BLIꢀ
ꢀ
ꢀ
miniꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-free
AutomotiveꢀRange:ꢀ–40°Cꢀtoꢀ+125°C
ꢀ
Speedꢀ(ns)ꢀ
OrderꢀPartꢀNo.ꢀ
Package
ꢀ
45ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
IS65WV1288DBLL-45TLA3ꢀ TSOP-I,ꢀLead-freeꢀ
IS65WV1288DBLL-45HLA3ꢀ sTSOP-I,ꢀLead-freeꢀ
IS65WV1288DBLL-45QLA3ꢀ SOP,ꢀLead-freeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Notes:ꢀ
1.ꢀSpeedꢀ=ꢀ35nsꢀforꢀtemperatureꢀrangeꢀofꢀ0oCꢀtoꢀ+70oCꢀorꢀforꢀVddꢀ=ꢀ3.3Vꢀ±ꢀ5%.
12ꢀ
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Rev.ꢀ B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLLꢀ
Integrated Silicon Solution, Inc. — www.issi.comꢀ
13
Rev.ꢀ B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLLꢀ
14ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLLꢀ
Integrated Silicon Solution, Inc. — www.issi.comꢀ
15
Rev.ꢀ B
12/01/2010
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLLꢀ
16ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ B
12/01/2010
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