IS62WV1288DBLL-45TLI-TR [ISSI]
IC SRAM 1M PARALLEL 32TSOP;
| 型号： | IS62WV1288DBLL-45TLI-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | IC SRAM 1M PARALLEL 32TSOP 静态存储器 |
| 文件： | 总16页 (文件大小：442K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
128K x 8 LOW VOLTAGE,
NOVEMBER 2016
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
DESCRIPTION
TheꢀISSIꢀIS62/65WV1288DALLꢀandꢀIS62/65WV1288DBLLꢀ
areꢀ ꢀ high-speed,ꢀ 1Mꢀ bitꢀ staticꢀ RAMsꢀ organizedꢀ asꢀ
128Kꢀwordsꢀbyꢀ8ꢀbits.ꢀItꢀisꢀfabricatedꢀusingꢀISSI's high-
performanceꢀCMOSꢀtechnology.ꢀThisꢀhighlyꢀreliableꢀprocessꢀ
coupled with innovative circuit design techniques, yields
high-performance and low power consumption devices.
•ꢀ High-speedꢀaccessꢀtime:ꢀꢀ35ns,ꢀ45ns,ꢀ55ns
•ꢀ CMOSꢀlowꢀpowerꢀoperation:
12 mW (typical) operating
ꢀ ꢀ4ꢀµWꢀ(typical)ꢀCMOSꢀstandby
•ꢀ TTLꢀcompatibleꢀinterfaceꢀlevels
•ꢀ Singleꢀpowerꢀsupply:ꢀꢀ
When CS1ꢀisꢀHIGHꢀ(deselected)ꢀorꢀwhenꢀCS2ꢀisꢀLOW
(deselected), the device assumes a standby mode at
which the power dissipation can be reduced down with
CMOSꢀinputꢀlevels.
ꢀ ꢀ1.65V--2.2VꢀVdd (62WV1288dALL)
ꢀ ꢀ2.3V--3.6VꢀVdd (62WV1288dBLL)
Easy memory expansion is provided by using Chip Enable
andꢀOutputꢀEnableꢀinputs.ꢀTheꢀactiveꢀLOWꢀWriteꢀEnableꢀ
(WE) controls both writing and reading of the memory.
•ꢀ Fullyꢀstaticꢀoperation:ꢀnoꢀclockꢀorꢀrefresh
required
TheꢀIS62/65WV1288DALLꢀandꢀIS62/65WV1288DBLLꢀareꢀ
packagedꢀinꢀtheꢀJEDECꢀstandardꢀ32-pinꢀTSOPꢀ(TYPEI),ꢀ
sTSOPꢀ(TYPEI),ꢀSOP,ꢀandꢀ36-pinꢀminiꢀBGA.
•ꢀ Threeꢀstateꢀoutputs
•ꢀ Industrialꢀandꢀautomotiveꢀtemperatureꢀsupport
•ꢀ Lead-freeꢀavailableꢀ
FUNCTIONAL BLOCK DIAGRAM
128K x 8
MEMORY ARRAY
A0-A16
DECODER
VDD
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CS2
CS1
OE
CONTROL
CIRCUIT
WE
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. C1
11/1/2016
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IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
PIN CONFIGURATION
32-pin TSOP (TYPE I) (T),
32-pin sTSOP (TYPE I) (H)
36-pin mini BGA (B) (6mm x 8mm)
1
2
3
4
5
6
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A11
A9
A8
A13
WE
CS2
A15
1
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
2
3
4
A
B
C
D
E
F
A0
A1
A2
CS2
WE
NC
A3
A4
A5
A6
A7
A8
5
I/O4
I/O5
GND
I/O0
I/O1
6
7
VDD
8
V
DD
NC
A16
A14
A12
A7
A6
A5
A4
9
V
DD
GND
I/O2
I/O3
A14
10
11
12
13
14
15
16
I/O6
I/O7
A9
NC
CS1
A11
NC
A16
A12
OE
A15
A13
G
H
A10
A1
A2
A3
PIN DESCRIPTIONS
32-pin SOP (Q)
A0-A16
CS1
Address Inputs
Chip Enable 1 Input
Chip Enable 2 Input
OutputꢀEnableꢀInput
Write Enable Input
Input/Output
CS2
NC
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
OEꢀꢀ
WE
ꢀ
2
A15
CS2
WE
A13
A8
3
4
I/O0-I/O7ꢀ
NC
5
No Connection
Power
A6
6
Vdd
A5
7
A9
GNDꢀ
ꢀ
Ground
A4
8
A11
OE
A3
9
A2
10
11
12
13
14
15
16
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
A1
A0
I/O0
I/O1
I/O2
GND
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C1
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IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
TRUTH TABLE
Mode
WE
CS1
CS2
OE
I/O Operation
VDD Current
NotꢀSelectedꢀ
(Power-down)ꢀ
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Lꢀ
Xꢀ
Xꢀ
ꢀ High-Zꢀꢀꢀ
ꢀ High-Z
isB1, isB2
isB1, isB2
ꢀ
ꢀ
ꢀ
OutputꢀDisabledꢀ
Readꢀ
Writeꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Xꢀ
ꢀ High-Zꢀ
dOut
iCC
iCC
iCC
din
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–0.5ꢀtoꢀVddꢀ+ꢀ0.5ꢀ
–0.3ꢀtoꢀ4.0ꢀ
–65ꢀtoꢀ+150ꢀ
1.0ꢀ
Unit
V
V
°C
W
Vterm
Vdd
TerminalꢀVoltageꢀwithꢀRespectꢀtoꢀGNDꢀ
VddꢀRelatesꢀtoꢀGNDꢀ
tstg
Pt
StorageꢀTemperatureꢀ
PowerꢀDissipationꢀ
Notes:
1.ꢀꢀStressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀ
theꢀdevice.ꢀThisꢀisꢀaꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀ
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
Parameter
Conditions
Vin = 0V
Max.
6ꢀ
Unit
pF
Cin
Input Capacitance
Input/OutputꢀCapacitanceꢀ
Ci/Oꢀ
VOut = 0V
8ꢀ
pF
Notes:
1.ꢀꢀTestedꢀinitiallyꢀandꢀafterꢀanyꢀdesignꢀorꢀprocessꢀchangesꢀthatꢀmayꢀaffectꢀtheseꢀparameters.
2.ꢀ Testꢀconditions:ꢀTA = 25°C, fꢀ=ꢀ1ꢀMHz,ꢀVddꢀ=ꢀ3.3V.
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Rev. C1
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IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
AC TEST CONDITIONS
Parameter
Unit
Unit
(3.3V + 5%)
Unit
(1.65V-2.2V)
(2.3V-3.6V)
0.4VꢀtoꢀVddꢀ-ꢀ0.3Vꢀ
1V/ꢀnsꢀ
InputꢀPulseꢀLevelꢀ
0.4VꢀtoꢀVddꢀ-ꢀ0.3Vꢀ
0.4VꢀtoꢀVddꢀ-ꢀ0.3V
1V/ꢀns
ꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
1V/ꢀnsꢀ
ꢀ
ꢀ
InputꢀandꢀOutputꢀTimingꢀ
andꢀReferenceꢀLevelꢀ(VRef
VDDꢀ/2ꢀ
VDDꢀꢀ+ꢀ0.05ꢀ
2
0.9V
)
ꢀ
OutputꢀLoadꢀ
R1ꢀ( Ω )ꢀ
R2ꢀ( Ω )ꢀ
Vtmꢀ(V)ꢀ
SeeꢀFiguresꢀ1ꢀandꢀ2ꢀ
SeeꢀFiguresꢀ1ꢀandꢀ2ꢀ
SeeꢀFiguresꢀ1ꢀandꢀ2
13500
317ꢀ
351ꢀ
3.3Vꢀ
317ꢀ
351ꢀ
3.3Vꢀ
ꢀ
ꢀ
10800
1.8V
AC TEST LOADS
R1
R1
VTM
OUTPUT
VTM
OUTPUT
R2
5 pF
Including
jig and
R2
30 pF
Including
jig and
scope
scope
Figure 1.
Figure 2.
4ꢀ
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IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
DC ELECTRICAL CHARACTERISTICS (OverꢀOperatingꢀRange)
VDD = 3.3V + 5%
Symbol Parameter
Test Conditions
Vdd = Min.,ꢀiOh = –1ꢀmAꢀ
Min.
2.4ꢀ
—ꢀ
2ꢀ
–0.3ꢀ
–1ꢀ
Max.
—ꢀ
0.4ꢀ
Unit
V
V
V
V
VOh
VOL
Vih
ViL
OutputꢀHIGHꢀVoltageꢀ
OutputꢀLOWꢀVoltageꢀ
InputꢀHIGHꢀVoltageꢀ
InputꢀLOWꢀVoltage(1)
InputꢀLeakageꢀ
Vdd = Min.,ꢀiOL = 2.1ꢀmAꢀ
ꢀ
ꢀ
Vdd + 0.3
0.8ꢀ
iLi
GNDꢀ≤ Vin ≤ Vdd
GNDꢀ≤ VOut ≤ Vdd, OutputsꢀDisabledꢀ
1ꢀ
1ꢀ
µA
µA
iLO
OutputꢀLeakage
–1ꢀ
Note:
1. ViL (min.) = –0.3VꢀDC;ꢀViLꢀ(min.)ꢀ=ꢀ–2.0VꢀACꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
Vih (max.) = Vdd + 0.3V dC; Vih (max.) = Vdd + 2.0V ACꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
DC ELECTRICAL CHARACTERISTICS (OverꢀOperatingꢀRange)
VDD = 2.3V-3.6V
Symbol Parameter
Test Conditions
Min.
1.8ꢀ
—ꢀ
Max.
—ꢀ
Unit
V
VOh
VOL
Vih
ViL
iLi
OutputꢀHIGHꢀVoltageꢀ
Vdd = Min.,ꢀiOh = –1.0ꢀmAꢀ
OutputꢀLOWꢀVoltageꢀ
InputꢀHIGHꢀVoltageꢀ
InputꢀLOWꢀVoltage(1)
InputꢀLeakageꢀ
Vdd = Min.,ꢀiOL = 2.1ꢀmAꢀ
0.4ꢀ
V
ꢀ
2.0ꢀ
–0.3ꢀ
–1ꢀ
Vdd + 0.3
0.8ꢀ
V
ꢀ
V
GNDꢀ≤ Vin ≤ Vdd
1ꢀ
µA
µA
iLO
OutputꢀLeakage
GNDꢀ≤ VOut ≤ Vdd, OutputsꢀDisabledꢀ
–1ꢀ
1ꢀ
Note:
1. ViL (min.) = –0.3VꢀDC;ꢀViLꢀ(min.)ꢀ=ꢀ–2.0VꢀACꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
Vih (max.) = Vdd + 0.3V dC; Vih (max.) = Vdd + 2.0V ACꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
DC ELECTRICAL CHARACTERISTICS (OverꢀOperatingꢀRange)
VDD = 1.65V-2.2V
Symbol Parameter
Test Conditions
VDD
Min.
1.4ꢀ
—ꢀ
Max.
—ꢀ
Unit
V
VOh
VOL
Vih
OutputꢀHIGHꢀVoltageꢀ
iOh = -0.1ꢀmAꢀ
1.65-2.2Vꢀ
1.65-2.2Vꢀ
1.65-2.2Vꢀ
1.65-2.2Vꢀ
OutputꢀLOWꢀVoltageꢀ
InputꢀHIGHꢀVoltageꢀ
InputꢀLOWꢀVoltage
InputꢀLeakageꢀ
iOL = 0.1ꢀmAꢀ
0.2ꢀ
V
ꢀ
1.4ꢀ
–0.2ꢀ
–1ꢀ
Vdd + 0.2
0.4ꢀ
V
(1)
ViL
iLi
ꢀ
V
GNDꢀ≤ Vin ≤ ꢀVdd
1ꢀ
µA
µA
iLO
OutputꢀLeakage
GNDꢀ≤ VOut ≤ ꢀVdd, OutputsꢀDisabledꢀ
–1ꢀ
1ꢀ
Note:
1. ViL (min.) = –0.3VꢀDC;ꢀViLꢀ(min.)ꢀ=ꢀ–2.0VꢀACꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
Vih (max.) = Vdd + 0.3V dC; Vih (max.) = Vdd + 2.0V ACꢀ(pulseꢀwidthꢀ<ꢀ10ꢀns).ꢀNotꢀ100%ꢀtested.
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IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
OPERATING RANGE (VDD)
Range
Ambient Temperature
0°Cꢀtoꢀ+70°Cꢀ
VDD
Speed
45ns
55ns
55ns
Commercialꢀ
ꢀ Industrialꢀ
ꢀ Automotiveꢀ
1.65V-2.2Vꢀ
1.65V-2.2Vꢀ
1.65V-2.2Vꢀ
–40°Cꢀtoꢀ+85°Cꢀ
–40°Cꢀtoꢀ+125°Cꢀ
OPERATING RANGE (VDD)
Range
Ambient Temperature
0°Cꢀtoꢀ+70°Cꢀ
VDD (45 nS)
2.3V-3.6Vꢀ
2.3V-3.6Vꢀ
VDD (35 nS)
3.3V+5%
3.3V+5%
Commercialꢀ
ꢀ Industrialꢀ
–40°Cꢀtoꢀ+85°Cꢀ
OPERATING RANGE (VDD)
Range
Ambient Temperature
VDD (45 nS)
Automotiveꢀ
–40°Cꢀtoꢀ+125°Cꢀ
2.3V-3.6V
POWER SUPPLY CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
-35
-45
-55
Symbol Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Unit
iCC
VddꢀDynamicꢀOperatingꢀ
Supply Current
Vdd = Max.,ꢀꢀ
iOut = 0 mA, f = fmAx
CS1 = ViLꢀ
Vin ≥ Vdd – 0.3V, or
Vin ≤ 0.4V
Com.ꢀ
Ind.ꢀ
—ꢀ
—ꢀ
—ꢀ
8ꢀ
12ꢀ
15ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
6ꢀ
8ꢀ
12ꢀ
ꢀ
—ꢀ
—ꢀ
—ꢀ
ꢀ
5ꢀ
7ꢀ
12ꢀ
ꢀ
mA
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Auto.ꢀ
typ.(2)
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ4ꢀ
iCC1
isB2ꢀ
Operatingꢀ
Supply Current
Vdd = Max.,ꢀꢀ
iOut = 0 mA, f = 0
CS1 = ViLꢀ
Vin ≥ Vdd – 0.3V, or
Vin ≤ 0.4V
Com.ꢀ
Ind.ꢀ
Auto.ꢀ
—ꢀ
—ꢀ
—ꢀ
2.5ꢀ
2.5ꢀ
3ꢀ
—ꢀ
—ꢀ
—ꢀ
2.5ꢀ
2.5ꢀ
3ꢀ
—ꢀ
—ꢀ
—ꢀ
2.5ꢀ
2.5ꢀ
3ꢀ
mA
ꢀ
ꢀ
ꢀ
ꢀ
CMOSꢀStandbyꢀ
Currentꢀ(CMOSꢀInputs)ꢀ
Vdd = Max.,ꢀ
Com.
Ind.
—
—
—ꢀ
0.6
2
4
18ꢀ
—
—
—
2ꢀ
4
18
—ꢀ
—ꢀ
—ꢀ
2ꢀ
4
18
µA
ꢀ ꢀ
CS1 ≥ Vdd – 0.2V,
Vin ≥ Vdd – 0.2V, orꢀ
Vin ≤ 0.2V, f = 0
Auto.ꢀ
typ.(2)
Note:
1. At f = fmAx, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2.ꢀTypicalꢀvaluesꢀareꢀmeasuredꢀatꢀVddꢀ=ꢀ3.0V,ꢀTAꢀ=ꢀ25oCꢀandꢀnotꢀ100%ꢀtested.
6
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IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
READ CYCLE SWITCHING CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
35 ns
45 ns
55 ns
Symbol
trCꢀ
Parameter
Min. Max.
Min. Max.
Min. Max.
55ꢀ ꢀ —ꢀ
—ꢀ ꢀ 55ꢀ
10ꢀ ꢀ —ꢀ
—ꢀ ꢀ 55ꢀ
—ꢀ ꢀ 25ꢀ
—ꢀ ꢀ 20ꢀ
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ReadꢀCycleꢀTimeꢀ
35ꢀ ꢀ —ꢀ
—ꢀ ꢀ 35ꢀ
10ꢀ ꢀ —ꢀ
—ꢀ ꢀ 35ꢀ
—ꢀ ꢀ 10ꢀ
—ꢀ ꢀ 10ꢀ
3ꢀ ꢀ —ꢀ
0ꢀ ꢀ 10ꢀꢀ
5ꢀ ꢀ —ꢀ
45ꢀ ꢀ —ꢀ
—ꢀ ꢀ 45ꢀ
10ꢀ ꢀ —ꢀ
—ꢀ ꢀ 45ꢀ
—ꢀ ꢀ 20ꢀ
—ꢀ ꢀ 15ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
tAAꢀ
AddressꢀAccessꢀTimeꢀ
OutputꢀHoldꢀTimeꢀ
tOhAꢀ
tACs1/tACs2
CS1/CS2ꢀAccessꢀTimeꢀ
OEꢀAccessꢀTimeꢀ
tdOe
(2)
thzOe
OEꢀtoꢀHigh-ZꢀOutputꢀ
OEꢀtoꢀLow-ZꢀOutputꢀ
CS1/CS2ꢀtoꢀHigh-ZꢀOutputꢀ
CS1/CS2ꢀtoꢀLow-ZꢀOutputꢀ
(2)
tLzOe
5ꢀ
ꢀ
—ꢀ
5ꢀ
0ꢀ
ꢀ
ꢀ
—ꢀ
20ꢀ
(2)
thzCs1/thzCs2
0ꢀ ꢀ 15ꢀ
10ꢀ ꢀ —ꢀ
(2)
tLzCs1/tLzCs2
10ꢀ ꢀ —ꢀ
Notes:
1.ꢀ Testꢀconditionsꢀassumeꢀsignalꢀtransitionꢀtimesꢀofꢀ5ꢀnsꢀorꢀless,ꢀtimingꢀreferenceꢀlevelsꢀofꢀ0.9V/1.5V,ꢀinputꢀpulseꢀlevelsꢀofꢀ0.4ꢀtoꢀ
Vdd-0.2V/Vdd-0.3VꢀandꢀoutputꢀloadingꢀspecifiedꢀinꢀFigureꢀ1.
2.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ2.ꢀTransitionꢀisꢀmeasuredꢀ±500ꢀmVꢀfromꢀsteady-stateꢀvoltage.ꢀNotꢀ100%ꢀtested.
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IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OEꢀ=ꢀViL, Cs2 = WEꢀ=ꢀVih)
tRC
ADDRESS
t
AA
t
OHA
tOHA
DATA VALID
DOUT
PREVIOUS DATA VALID
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, CS2, OE Controlled)
t
RC
ADDRESS
OE
t
AA
tOHA
t
HZOE
tDOE
t
LZOE
CS1
t
ACS1/tACS2
CS2
t
LZCS1/
LZCS2
t
tHZCS
HIGH-Z
DOUT
DATA VALID
Notes:
1. WEꢀisꢀHIGHꢀforꢀaꢀReadꢀCycle.
2.ꢀ Theꢀdeviceꢀisꢀcontinuouslyꢀselected.ꢀOE, CS1= ViL. Cs2=WE=Vih.
3.ꢀ AddressꢀisꢀvalidꢀpriorꢀtoꢀorꢀcoincidentꢀwithꢀCS1ꢀLOWꢀandꢀCs2 high transition.
8ꢀ
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11/1/2016
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IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2)ꢀ(OverꢀOperatingꢀRange)
35ns
45ns
55 ns
Symbol
tWCꢀ
tsCs1/tsCs2
tAWꢀ
thAꢀ
tsAꢀ
Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
WriteꢀCycleꢀTimeꢀ
CS1/CS2ꢀtoꢀWriteꢀEndꢀ
35ꢀꢀ ꢀ —ꢀ
25ꢀ ꢀ —ꢀ
45ꢀꢀ ꢀ —ꢀ
35ꢀ ꢀ —ꢀ
35ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
35ꢀ ꢀ —ꢀ
20ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
—ꢀ ꢀ 20ꢀ
5ꢀ ꢀ —ꢀ
55ꢀ ꢀ —ꢀ ꢀꢀꢀꢀ ns
45ꢀ ꢀ —ꢀ ꢀꢀꢀꢀ ns
45ꢀ ꢀ —ꢀ ꢀꢀꢀꢀ ns
0ꢀ ꢀ —ꢀ ꢀꢀꢀꢀꢀꢀns
0ꢀ ꢀ —ꢀ ꢀꢀꢀꢀꢀꢀns
40ꢀ ꢀ —ꢀ ꢀꢀꢀꢀꢀns
25ꢀ ꢀ —ꢀ ꢀꢀꢀꢀ ns
0ꢀ ꢀ —ꢀ ꢀꢀꢀꢀꢀꢀns
—ꢀ ꢀ 20ꢀ ꢀꢀꢀꢀꢀꢀns
5ꢀ ꢀ —ꢀ ꢀꢀꢀꢀꢀꢀns
AddressꢀSetupꢀTimeꢀtoꢀWriteꢀEndꢀꢀ 25ꢀ ꢀ —ꢀ
AddressꢀHoldꢀfromꢀWriteꢀEndꢀ
AddressꢀSetupꢀTimeꢀ
0ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
25ꢀ ꢀ —ꢀꢀ
20ꢀ ꢀ —ꢀ
0ꢀ ꢀ —ꢀ
—ꢀ ꢀ 10ꢀ
3ꢀ ꢀ —ꢀꢀ
tPWe
tsdꢀ
WEꢀPulseꢀWidthꢀ
DataꢀSetupꢀtoꢀWriteꢀEndꢀ
DataꢀHoldꢀfromꢀWriteꢀEndꢀ
WEꢀLOWꢀtoꢀHigh-ZꢀOutputꢀ
WEꢀHIGHꢀtoꢀLow-ZꢀOutputꢀ
thdꢀ
thzWe
tLzWe
(3)
(3)
Notes:
1.ꢀ Testꢀconditionsꢀassumeꢀsignalꢀtransitionꢀtimesꢀofꢀ5ꢀnsꢀorꢀless,ꢀtimingꢀreferenceꢀlevelsꢀofꢀ0.9V/1.5V,ꢀinputꢀpulseꢀlevelsꢀofꢀ0.4Vꢀtoꢀ
Vdd-0.2V/Vdd-0.3VꢀandꢀoutputꢀloadingꢀspecifiedꢀinꢀFigureꢀ1.
2.ꢀ TheꢀinternalꢀwriteꢀtimeꢀisꢀdefinedꢀbyꢀtheꢀoverlapꢀofꢀCS1ꢀLOW,ꢀCS2ꢀHIGHꢀandꢀUB or LB, and WEꢀLOW.ꢀAllꢀsignalsꢀmustꢀbeꢀinꢀ
validꢀstatesꢀtoꢀinitiateꢀaꢀWrite,ꢀbutꢀanyꢀoneꢀcanꢀgoꢀinactiveꢀtoꢀterminateꢀtheꢀWrite.ꢀTheꢀDataꢀInputꢀSetupꢀandꢀHoldꢀtimingꢀareꢀ
referenced to the rising or falling edge of the signal that terminates the write.
3.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ2.ꢀTransitionꢀisꢀmeasuredꢀ±500ꢀmVꢀfromꢀsteady-stateꢀvoltage.ꢀNotꢀ100%ꢀtested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OEꢀ=ꢀHIGHꢀorꢀLOW)
t
WC
ADDRESS
CS1
t
HA
tSCS1
tSCS2
CS2
tAW
t
PWE
WE
DOUT
DIN
t
SA
tHZWE
t
LZWE
HIGH-Z
SD
DATA UNDEFINED
t
t
HD
DATA-IN VALID
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Rev. C1
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IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
AC WAVEFORMS
WRITE CYCLE NO. 2 (WE Controlled: OEꢀisꢀHIGHꢀDuringꢀWriteꢀCycle)
t
WC
ADDRESS
OE
t
HA
tSCS1
CS1
tSCS2
CS2
tAW
t
PWE
WE
t
SA
tHZWE
t
LZWE
HIGH-Z
SD
DOUT
DIN
DATA UNDEFINED
t
t
HD
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OEꢀisꢀLOWꢀDuringꢀWriteꢀCycle)
t
WC
ADDRESS
OE
t
HA
tSCS1
CS1
tSCS2
CS2
tAW
t
PWE
WE
t
SA
tHZWE
t
LZWE
HIGH-Z
SD
DOUT
DIN
DATA UNDEFINED
t
t
HD
DATA-IN VALID
10
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IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter
ddꢀforꢀDataꢀRetentionꢀ
Test Condition
Min. typ.(1) Max. Unit
ꢀ ꢀ Vdr
ꢀ
V
SeeꢀDataꢀRetentionꢀWaveformꢀ
ꢀ
1.2ꢀ
ꢀ
3.6ꢀ
V
i
ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ
drꢀ
DataꢀRetentionꢀCurrentꢀ
ꢀ
ꢀ
V
ꢀ
ꢀ
ddꢀ=ꢀ1.2V,ꢀCS1 ≥ꢀVddꢀ–ꢀ0.2Vꢀ
Com.ꢀ
Ind.ꢀ
Auto.ꢀ
—ꢀ
ꢀ
ꢀ
0.5ꢀ
ꢀ
ꢀ
2ꢀ
4ꢀ
18
µAꢀ
ꢀꢀ
t
sdr
DataꢀRetentionꢀSetupꢀTimeꢀ SeeꢀDataꢀRetentionꢀWaveformꢀ
RecoveryꢀTimeꢀ SeeꢀDataꢀRetentionꢀWaveformꢀ
ꢀ
ꢀ
0ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ns
ns
trdr
t
rC
ꢀ
Note: 1.ꢀTypicalꢀvaluesꢀareꢀmeasuredꢀatꢀVddꢀ=ꢀ3.0V,ꢀTAꢀ=ꢀ25oCꢀandꢀnotꢀ100%ꢀtested.
DATA RETENTION WAVEFORM (CS1 Controlled)
t
Data Retention Mode
t
RDR
SDR
VDD
V
DR
CS1 ≥ V
0.2V
DD
-
CS1
GND
DATA RETENTION WAVEFORM (CS2 Controlled)
Data Retention Mode
V
DD
t
t
RDR
SDR
CS2
V
DR
CS2 ≤ 0.2V
GND
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IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
ORDERING INFORMATION
IS62WV1288DALL (1.65V - 2.2V)
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
55ꢀ
ꢀ
ꢀ
ꢀ
IS62WV1288DALL-55TLIꢀ
IS62WV1288DALL-55HLIꢀ
TSOP-I,ꢀLead-freeꢀ(8mmx20mm)ꢀ
sTSOP-I,ꢀLead-freeꢀ(8mmx13.4mm)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
IS62WV1288DALL-55BIꢀ
IS62WV1288DALL-55BLIꢀ
miniꢀBGAꢀ(6mmꢀxꢀ8mm)ꢀ
ꢀ
miniꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-free
ORDERING INFORMATION
IS62WV1288DBLL (2.3V - 3.6V)
Industrial Range: –40°C to +85°C1
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
45ꢀ
ꢀ
IS62WV1288DBLL-45TLIꢀ
TSOP-I,ꢀLead-freeꢀ(8mmx20mm)ꢀ
sTSOP-I,ꢀLead-freeꢀ(8mmx13.4mm)ꢀ
SOP,ꢀLead-free
ꢀ
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀIS62WV1288DBLL-45HLIꢀ
ꢀ
ꢀ
IS62WV1288DBLL-45QLIꢀ
ꢀ
ꢀ
ꢀ
ꢀ
IS62WV1288DBLL-45BIꢀ
IS62WV1288DBLL-45BLIꢀ
miniꢀBGAꢀ(6mmꢀxꢀ8mm)ꢀ
ꢀ
ꢀ
miniꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-free
Automotive Range: –40°C to +125°C
Speed (ns)
Order Part No.
Package
ꢀ
45ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
IS65WV1288DBLL-45TLA3ꢀ TSOP-I,ꢀLead-freeꢀ(8mmx20mm)ꢀ
IS65WV1288DBLL-45HLA3ꢀ sTSOP-I,ꢀLead-freeꢀ(8mmx13.4mm)ꢀ
ꢀ
ꢀ
IS65WV1288DBLL-45QLA3ꢀ SOP,ꢀLead-freeꢀ
ꢀ
Notes:
1.ꢀSpeedꢀ=ꢀ35nsꢀforꢀtemperatureꢀrangeꢀofꢀ0oCꢀtoꢀ+70oCꢀorꢀforꢀVddꢀ=ꢀ3.3Vꢀ±ꢀ5%.
12
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11/1/2016
®
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IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
Integrated Silicon Solution, Inc. — www.issi.comꢀ
13
Rev. C1
11/1/2016
®
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IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C1
11/1/2016
®
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World Class Quality
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
Integrated Silicon Solution, Inc. — www.issi.comꢀ
15
Rev. C1
11/1/2016
®
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World Class Quality
IS62WV1288DALL/DBLL
IS65WV1288DALL/DBLL
16
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C1
11/1/2016
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