IS62WV6416ALL-55B [ISSI]
64K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM; 64K ×16低电压，超低功耗CMOS静态RAM
| 型号： | IS62WV6416ALL-55B |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 64K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM |
| 文件： | 总17页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS62WV6416ALL
IS62WV6416BLL
ISSI
64K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
JUNE2005
FEATURES
DESCRIPTION
The ISSI IS62WV6416ALL/ IS62WV6416BLL are high-
speed, 1M bit static RAMs organized as 64K words by 16
bits. It is fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-
performance and low power consumption devices.
• High-speed access time: 45ns, 55ns
• CMOS low power operation:
30 mW (typical) operating
15 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply
When CS1 is HIGH (deselected) or when CS2 is LOW
(deselected) or when CS1 is LOW, CS2 is HIGH and both
LBandUBareHIGH, thedeviceassumesastandbymode
at which the power dissipation can be reduced down with
CMOS input levels.
1.7V--2.2V VDD (62WV6416ALL)
2.5V--3.6V VDD (62WV6416BLL)
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• 2CS Option Available
TheIS62WV6416ALLandIS62WV6416BLLarepackaged
intheJEDECstandard48-pinminiBGA(6mmx8mm)and
44-Pin TSOP (TYPE II).
• Lead-free available
FUNCTIONAL BLOCK DIAGRAM
64K x 16
MEMORY ARRAY
A0-A15
DECODER
V
DD
GND
I/O0-I/O7
Lower Byte
I/O
DATA
CIRCUIT
COLUMN I/O
I/O8-I/O15
Upper Byte
CS2
CS1
OE
WE
UB
CONTROL
CIRCUIT
LB
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
1
06/03/05
®
IS62WV6416ALL, IS62WV6416BLL
ISSI
PIN CONFIGURATIONS
48-Pin mini BGA (6mm x 8mm)
2 CS Option (Package Code B2)
48-Pin mini BGA (6mm x 8mm)
(Package Code B)
1
2
3
4
5
6
1
2
3
4
5
6
A0
A3
A1
A4
A2
A0
A3
A1
A4
A2
LB
I/O
OE
UB
NC
I/O
LB
OE
UB
CS2
A
B
C
D
E
F
A
B
C
D
E
F
CSI
I/O
8
CS1
I/O
0
8
0
I/O
I/O
A5
A6
I/O
I/O
I/O
I/O
A5
A6
I/O
I/O
2
9
10
1
2
9
10
1
GND
NC
NC
A14
A12
A7
GND
NC
NC
A14
A12
A7
I/O
I/O
I/O
I/O
I/O
V
DD
I/O
I/O
I/O
I/O
I/O
VDD
11
3
4
5
11
3
4
5
GND
GND
V
DD
NC
A15
A13
A10
V
DD
NC
A15
A13
A10
12
12
I/O
I/O
I/O
I/O
I/O
I/O
6
I/O
I/O
6
14
14
13
13
NC
A8
WE
NC
A8
WE
I/O
7
I/O
7
15
15
G
H
G
H
NC
NC
A9
A11
NC
A9
A11
NC
44-Pin mini TSOP (Type II)
(Package Code T)
PIN DESCRIPTIONS
A0-A15
I/O0-I/O15
CS1, CS2
OE
Address Inputs
DataInputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
A4
A3
A2
A1
A0
CS1
I/O0
I/O1
I/O2
I/O3
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
WE
LB
Lower-byteControl(I/O0-I/O7)
Upper-byteControl(I/O8-I/O15)
NoConnection
9
UB
10
11
12
13
14
15
16
17
18
19
20
21
22
V
DD
NC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
VDD
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
VDD
Power
GND
Ground
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/03/05
®
IS62WV6416ALL, IS62WV6416BLL
ISSI
TRUTH TABLE
I/O PIN
Mode
WE CS1 CS2
OE
LB
UB
I/O0-I/O7
I/O8-I/O15
VDD Current
Not Selected
X
X
X
H
X
X
X
L
X
X
X
X
X
X
H
X
X
H
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
ISB1, ISB2
ISB1, ISB2
ISB1, ISB2
OutputDisabled
Read
H
H
L
L
H
H
H
H
L
X
X
L
High-Z
High-Z
High-Z
High-Z
ICC
ICC
H
H
H
L
L
L
H
H
H
L
L
L
L
H
L
H
L
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
ICC
Write
L
L
L
L
L
L
H
H
H
X
X
X
L
H
L
H
L
L
DIN
High-Z
DIN
High-Z
DIN
DIN
ICC
OPERATING RANGE (VDD)
Range
AmbientTemperature
0°C to +70°C
IS62WV6416ALL
1.7V - 2.2V
IS62WV6416BLL
2.5V - 3.6V
Commercial
Industrial
–40°Cto+85°C
1.7V - 2.2V
2.5V - 3.6V
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
VDD
Parameter
Value
–0.2 to VDD+0.3
–0.2 to +3.8
–65 to +150
1.0
Unit
Terminal Voltage with Respect to GND
VDD Related to GND
V
V
TSTG
PT
StorageTemperature
°C
W
PowerDissipation
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
3
06/03/05
®
IS62WV6416ALL, IS62WV6416BLL
ISSI
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
TestConditions
VDD
Min.
Max.
Unit
VOH
VOL
VIH
OutputHIGHVoltage
IOH = -0.1 mA
IOH = -1 mA
1.7-2.2V
2.5-3.6V
1.4
2.2
—
—
V
V
OutputLOWVoltage
Input HIGH Voltage
Input LOW Voltage
IOL = 0.1 mA
IOL = 2.1 mA
1.7-2.2V
2.5-3.6V
—
—
0.2
0.4
V
V
1.7-2.2V
2.5-3.6V
1.4
2.2
VDD + 0.2
VDD + 0.3
V
V
(1)
VIL
1.7-2.2V
2.5-3.6V
–0.2
–0.2
0.4
0.6
V
V
ILI
InputLeakage
GND ≤ VIN ≤ VDD
–1
–1
1
1
µA
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
Notes:
1. VIL (min.) = –1.0V for pulse width less than 10 ns.
CAPACITANCE(1)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
8
Unit
pF
InputCapacitance
Input/OutputCapacitance
COUT
VOUT = 0V
10
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/03/05
®
IS62WV6416ALL, IS62WV6416BLL
ISSI
AC TEST CONDITIONS
Parameter
62WV6416ALL
62WV6416BLL
(Unit)
(Unit)
0.4V to VDD-0.2V
5 ns
Input Pulse Level
0.4V to VDD-0.3V
Input Rise and Fall Times
5ns
Input and Output Timing
andReferenceLevel
VREF
VREF
OutputLoad
See Figures 1 and 2
See Figures 1 and 2
AC TEST LOADS
R1
R1
VTM
VTM
OUTPUT
OUTPUT
R2
R2
30 pF
Including
jig and
5 pF
Including
jig and
scope
scope
Figure 1
Figure 2
1.7-2.2V
2.5V - 3.6V
3070
R1(Ω)
R2(Ω)
VREF
3070
3150
0.9V
1.8V
3150
1.5V
VTM
2.8V
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
5
06/03/05
®
IS62WV6416ALL, IS62WV6416BLL
ISSI
IS62WV6416ALL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol
Parameter
TestConditions
Max.
55
Unit
ICC
V
DD DynamicOperating
V
DD=Max.,
Com.
Ind.
10
10
6
mA
SupplyCurrent
IOUT =0mA,f=fMAX
typ.(1)
I
CC
1
OperatingSupply
Current
V
DD=Max.,
Com.
Ind.
5
5
mA
mA
I
OUT =0mA,f=0
ISB
1
TTLStandbyCurrent
(TTLInputs)
VDD=Max.,
Com.
Ind.
1.2
1.2
VIN =VIH orVIL
CS1=VIH,CS2=VIL
,
f=1MH
Z
OR
ULBControl
VDD =Max.,VIN =VIH orVIL
CS1=VIL,f=0,UB=VIH,LB=VIH
I
SB
2
CMOSStandby
Current(CMOSInputs)
V
DD=Max.,
CS1 DD–0.2V,
CS2 ≤ 0.2V,
Com.
Ind.
10
10
4
µA
≥V
typ.(1)
V
IN
≥
≤
V
DD –0.2V,or
VIN
0.2V,f=0
OR
ULBControl
VDD = Max., CS1 = VIL, CS2=VIH
IN ≤0.2V,f=0;UB/LB=VDD –0.2V
V
Note:
1. Typical values are measured at VDD=1.8V, TA=25oC. Not 100% tested.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/03/05
®
IS62WV6416ALL, IS62WV6416BLL
ISSI
IS62WV6416BLL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol
Parameter
TestConditions
Max.
45
Max.
55
Unit
ICC
V
DD DynamicOperating
V
DD =Max.,
Com.
Ind.
17
17
12
15
15
10
mA
SupplyCurrent
IOUT =0mA,f=fMAX
typ.(2)
I
CC
1
OperatingSupply
Current
V
I
DD =Max.,
OUT =0mA,f=0
DD =Max.,
IN =VIH orVIL
CS1=VIH ,CS2=VIL
f=1MH
Com.
Ind.
5
5
5
5
mA
mA
ISB
1
TTLStandbyCurrent
(TTLInputs)
V
V
Com.
Ind.
1.2
1.2
1.2
1.2
,
Z
OR
ULBControl
VDD =Max.,VIN =VIH orVIL
CS1=VIL,f=0,UB=VIH,LB=VIH
I
SB
2
CMOSStandby
Current(CMOSInputs)
V
DD =Max.,
CS1 DD–0.2V,
CS2 ≤ 0.2V,
Com.
Ind.
15
15
5
15
15
5
µA
≥V
typ.(2)
V
IN
≥
≤
V
DD –0.2V,or
VIN
0.2V,f=0
OR
ULBControl
VDD = Max., CS1 = VIL, CS2=VIH
IN ≤0.2V,f=0;UB/LB=VDD –0.2V
V
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD=3.0V, TA=25oC. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
7
06/03/05
®
IS62WV6416ALL, IS62WV6416BLL
ISSI
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
45 ns
55 ns
Symbol
tRC
Parameter
Min. Max.
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
45
—
10
—
—
—
5
—
45
—
45
20
15
—
15
—
45
15
—
55
—
10
—
—
—
5
—
55
—
55
25
20
—
20
—
55
20
—
tAA
Address Access Time
Output Hold Time
tOHA
tACS1/tACS2
tDOE
CS1/CS2 Access Time
OE Access Time
(2)
tHZOE
OE to High-Z Output
OE to Low-Z Output
CS1/CS2 to High-Z Output
CS1/CS2 to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
(2)
tLZOE
(2)
tHZCS1/tHZCS2
0
0
(2)
tLZCS1/tLZCS2
10
—
0
10
—
0
tBA
tHZB
tLZB
0
0
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to
VDD-0.2V/VDD-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/03/05
®
IS62WV6416ALL, IS62WV6416BLL
ISSI
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, CS2 = WE = VIH, UB or LB = VIL)
t
RC
ADDRESS
DOUT
t
AA
t
OHA
t
OHA
DATA VALID
PREVIOUS DATA VALID
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, CS2, OE, AND UB/LB Controlled)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
LZOE
CS1
t
ACE1/tACE2
CS2
tLZCE1/
tLZCE2
t
t
HZCS1/
HZCS2
LB UB
,
t
BA
t
HZB
t
LZB
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1, UB, or LB = VIL. CS2=WE=VIH.
3. Address is valid prior to or coincident with CS1 LOW transition.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
9
06/03/05
®
IS62WV6416ALL, IS62WV6416BLL
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
45ns
55 ns
Symbol
tWC
Parameter
Min.
Max.
—
Min.
55
45
45
0
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
45
35
35
0
—
—
—
—
—
—
—
—
—
20
—
tSCS1/tSCS2
tAW
CS1/CS2 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
—
—
tHA
—
tSA
0
—
0
tPWB
tPWE
tSD
LB, UB Valid to End of Write
WE Pulse Width
35
35
20
0
—
45
40
25
0
—
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
—
tHD
—
(3)
tHZWE
—
5
20
—
—
5
(3)
tLZWE
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to
VDD-0.2V/VDD-0.3V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW)
t
WC
ADDRESS
CS1
t
HA
t
SCS1
t
SCS2
CS2
t
AW
t
PWE
WE
t
PWB
LB, UB
t
SA
t
HZWE
t
LZWE
HIGH-Z
SD
DOUT
DIN
DATA UNDEFINED
t
t
HD
DATA-IN VALID
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at
least one of the LB and UB inputs being in the LOW state.
2. WRITE = (CS1) [ (LB) = (UB) ] (WE).
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/03/05
®
IS62WV6416ALL, IS62WV6416BLL
ISSI
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
t
WC
ADDRESS
OE
t
HA
t
SCS1
CS1
t
SCS2
CS2
t
AW
t
PWE
WE
LB, UB
DOUT
DIN
t
SA
t
HZWE
t
LZWE
HIGH-Z
SD
DATA UNDEFINED
t
t
HD
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
OE
t
HA
t
SCS1
CS1
t
SCS2
CS2
t
AW
t
PWE
WE
LB, UB
DOUT
DIN
t
SA
tHZWE
t
LZWE
HIGH-Z
SD
DATA UNDEFINED
t
t
HD
DATA-IN VALID
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
11
06/03/05
®
IS62WV6416ALL, IS62WV6416BLL
ISSI
WRITE CYCLE NO. 4 (UB/LB Controlled)
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
OE
t
SA
LOW
HIGH
CS1
CS2
t
HA
SA
t
HA
t
WE
t
PBW
t
PBW
UB, LB
WORD 1
WORD 2
t
HZWE
t
LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/03/05
®
IS62WV6416ALL, IS62WV6416BLL
ISSI
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
VDR
Parameter
Test Condition
Min.
1.2
—
Max.
3.6
5
Unit
V
VDD for Data Retention
Data Retention Current
See Data Retention Waveform
VDD = 1.2V, CS1 ≥ VDD – 0.2V
IDR
µA
ns
tSDR
Data Retention Setup Time See Data Retention Waveform
Recovery Time See Data Retention Waveform
0
—
tRDR
tRC
—
ns
DATA RETENTION WAVEFORM (CS1 Controlled)
t
SDR
Data Retention Mode
tRDR
V
DD
DR
V
CS1 ≥ VDD - 0.2V
CS1
GND
DATA RETENTION WAVEFORM (CS2 Controlled)
Data Retention Mode
VDD
t
t
RDR
SDR
CE2
V
DR
CS2 ≤ 0.2V
0.4V
GND
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
13
06/03/05
®
IS62WV6416ALL, IS62WV6416BLL
ISSI
ORDERING INFORMATION
IS62WV6416ALL (1.7V - 2.2V)
Commercial Range: 0°C to +70°C
Speed(ns)
Order Part No.
Package
55
IS62WV6416ALL-55T
IS62WV6416ALL-55B
TSOP-II
mini BGA (6mm x 8mm)
Industrial Range: –40°C to +85°C
Speed(ns)
Order Part No.
Package
55
IS62WV6416ALL-55TI
IS62WV6416ALL-55TLI
TSOP-II
TSOP-II,Lead-free
IS62WV6416ALL-55BI
IS62WV6416ALL-55BLI
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
IS62WV6416ALL-55B2I
mini BGA (6mm x 8mm), 2 CS Option
14
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
06/03/05
®
IS62WV6416ALL, IS62WV6416BLL
ISSI
ORDERING INFORMATION
IS62WV6416BLL (2.5V - 3.6V)
Commercial Range: 0°C to +70°C
Speed(ns)
Order Part No.
Package
45
IS62WV6416BLL-45T
IS62WV6416BLL-45B
TSOP-II
mini BGA (6mm x 8mm)
Industrial Range: –40°C to +85°C
Speed(ns)
Order Part No.
Package
45
IS62WV6416BLL-45TI
IS62WV6416BLL-45BI
TSOP-II
mini BGA (6mm x 8mm)
55
IS62WV6416BLL-55TI
IS62WV6416BLL-55TLI
TSOP-II
TSOP-II,Lead-free
IS62WV6416BLL-55BI
IS62WV6416BLL-55BLI
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
IS62WV6416BLL-55B2I
mini BGA (6mm x 8mm), 2 CS Option
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
15
06/03/05
®
PACKAGING INFORMATION
Mini Ball Grid Array
ISSI
Package Code: B (48-pin)
Top View
Bottom View
φ b (48x)
1
2
3
4
5 6
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
e
D
D1
G
H
G
H
e
E
E1
Notes:
1. Controllingdimensionsareinmillimeters.
A2
A
A1
SEATING PLANE
mBGA - 6mm x 8mm
mBGA - 8mm x 10mm
MILLIMETERS
INCHES
MILLIMETER
INCHES
Sym. Min. Typ. Max.
Min. Typ. Max.
Sym. Min. Typ. Max.
Min. Typ. Max.
N0.
N0.
Leads
48
Leads
48
A
—
—
—
—
—
1.20
0.30
—
—
—
—
—
—
0.047
0.012
—
A
—
—
—
—
—
1.20
0.30
—
—
—
—
—
—
0.047
0.012
—
A1
A2
D
0.24
0.60
7.90
0.009
0.024
0.311
A1
A2
D
0.24
0.60
9.90
0.009
0.024
0.390
8.10
0.319
10.10
0.398
D1
E
5.25 BSC
—
0.207 BSC
D1
E
5.25 BSC
—
0.207 BSC
5.90
6.10
0.232
—
0.240
7.90
8.10
0.311
—
0.319
E1
e
3.75 BSC
0.75 BSC
0.148 BSC
E1
e
3.75 BSC
0.75 BSC
0.148 BSC
0.030 BSC
0.030 BSC
b
0.30 0.35 0.40
0.012 0.014 0.016
b
0.30 0.35 0.40
0.012 0.014 0.016
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
01/15/03
®
PACKAGING INFORMATION
ISSI
Plastic TSOP
Package Code: T (Type II)
N
N/2+1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
E
E1
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
1
N/2
D
SEATING PLANE
A
ZD
.
L
α
e
b
C
A1
Plastic TSOP (T - Type II)
Millimeters Inches
Millimeters
Inches
Millimeters
Inches
Symbol Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Ref. Std.
No. Leads (N)
32
44
50
A
A1
b
C
D
E1
E
e
—
1.20
—
0.047
—
1.20
0.15
0.45
0.21
—
0.047
—
1.20
—
0.047
0.05 0.15
0.30 0.52
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
1.27 BSC
0.002 0.006
0.012 0.020
0.005 0.008
0.820 0.830
0.391 0.400
0.451 0.466
0.050 BSC
0.05
0.30
0.12
18.31 18.52
10.03 10.29
11.56 11.96
0.80 BSC
0.002 0.006
0.012 0.018
0.005 0.008
0.721 0.729
0.395 0.405
0.455 0.471
0.032 BSC
0.05 0.15
0.30 0.45
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
0.80 BSC
0.002 0.006
0.012 0.018
0.005 0.008
0.820 0.830
0.395 0.405
0.455 0.471
0.031 BSC
L
ZD
α
0.40 0.60
0.95 REF
0.016 0.024
0.037 REF
0.41
0.81 REF
0°
0.60
0.016 0.024
0.032 REF
0.40 0.60
0.88 REF
0.016 0.024
0.035 REF
0°
5°
0°
5°
5°
0°
5°
0°
5°
0°
5°
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
06/18/03
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