IS63LV1024-8KL [ISSI]
128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT; 128K ×8高速CMOS静态RAM 3.3V革命引脚
| 型号： | IS63LV1024-8KL |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT |
| 文件： | 总18页 (文件大小：615K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS63LV1024
IS63LV1024L
128K x 8 HIGH-SPEED CMOS STATIC RAM
3.3V REVOLUTIONARY PINOUT
JANUARY2007
DESCRIPTION
FEATURES
TheISSIIS63LV1024/IS63LV1024Lisaveryhigh-speed,
low power, 131,072-word by 8-bit CMOS static RAM in
revolutionarypinout.TheIS63LV1024/IS63LV1024Lisfab-
ricatedusingISSI'shigh-performanceCMOStechnology.
This highly reliable process coupled with innovative circuit
design techniques, yields higher performance and low
powerconsumptiondevices.
• High-speed access times:
8, 10, 12 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE
options
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.
• CE power-down
• Fully static operation: no clock or refresh
required
TheIS63LV1024/IS63LV1024Loperatesfromasingle3.3V
power supply and all inputs are TTL-compatible.
• TTL compatible inputs and outputs
• Single 3.3V power supply
• Packages available:
– 32-pin 300-mil SOJ
– 32-pin 400-mil SOJ
– 32-pin TSOP (Type II)
– 32-pin STSOP (Type I)
– 36-pin BGA (8mmx10mm)
• Lead-free Available
FUNCTIONAL BLOCK DIAGRAM
128K X 8
MEMORY ARRAY
A0-A16
DECODER
VDD
GND
I/O
DATA
CIRCUIT
COLUMN I/O
I/O0-I/O7
CE
OE
WE
CONTROL
CIRCUIT
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
1
Rev. I
1/26/07
IS63LV1024
IS63LV1024L
PIN CONFIGURATION
32-Pin SOJ
PIN CONFIGURATION
32-Pin TSOP (Type II) (T)
32-Pin STSOP (Type I) (H)
A0
A1
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
2
A0
A1
A2
A3
CE
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A4
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VDD
I/O5
I/O4
A12
A11
A10
A9
A2
3
A3
4
CE
5
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A4
6
I/O7
I/O6
GND
VDD
I/O5
I/O4
A12
A11
A10
A9
7
8
9
9
10
11
12
13
14
15
16
10
11
12
13
14
15
16
A5
A6
A7
A5
A8
A6
A7
A8
PIN DESCRIPTIONS
PIN CONFIGURATION
36-mini BGA (B) (8 mm x 10 mm)
A0-A16
CE
Address Inputs
Chip Enable Input
1
2
3
4
5
6
OE
Output Enable Input
Write Enable Input
DataInputs/Outputs
Power
WE
I/O0-I/O7
VDD
NC
WE
NC
A3
A4
A5
A6
A7
A0
I/O4
I/O5
GND
VDD
I/O6
I/O7
A9
A1
A2
A8
I/O
A
B
C
D
E
F
GND
Ground
0
I/O
1
VDD
GND
NC
CE
NC
A16
A12
I/O
2
OE
A15
A13
I/O
3
G
H
A10
A11
A14
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. I
1/26/07
IS63LV1024
IS63LV1024L
TRUTH TABLE
Mode
WE
CE
OE
I/OOperation
VDD Current
Not Selected
(Power-down)
X
H
X
High-Z
ISB1, ISB2
OutputDisabled
Read
H
H
L
L
L
L
H
L
High-Z
DOUT
DIN
ICC1,ICC2
ICC1,ICC2
ICC1,ICC2
Write
X
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TSTG
Parameter
Value
–0.5 to VDD + 0.5
–65 to +150
1.0
Unit
V
°C
W
Terminal Voltage with Respect to GND
StorageTemperature
PowerDissipation
PT
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
OPERATING RANGE
Range
Commercial
Industrial
AmbientTemperature
0°C to +70°C
VDD
3.3V 0.3V
3.3V 0.15V
–40°Cto+85°C
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
TestConditions
Min.
2.4
Max.
—
Unit
V
VOH
VOL
VIH
VIL
ILI
OutputHIGHVoltage
VDD = Min., IOH = –4.0 mA
VDD = Min., IOL = 8.0 mA
OutputLOWVoltage
Input HIGH Voltage
Input LOW Voltage(1)
InputLeakage
—
0.4
V
2.2
VDD + 0.3
0.8
V
–0.3
V
GND ≤ VIN ≤ VDD
Com.
Ind.
–1
–5
1
5
µA
ILO
OutputLeakage
GND ≤ VOUT ≤ VDD, Outputs Disabled
Com.
Ind.
–1
–5
1
5
µA
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
3
Rev. I
1/26/07
IS63LV1024
IS63LV1024L
IS63LV1024 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns
Min. Max.
-10 ns
Min. Max.
-12 ns
Min. Max.
Symbol Parameter
Test Conditions
Unit
ICC1
VDD Operating
Supply Current
VDD = Max., CE = VIL
IOUT = 0 mA, f = Max.
Com.
Ind.
—
—
—
160
170
105
—
—
—
150
160
95
—
—
—
—
130
140
75
mA
typ.(2)
Ind. (@15 ns)
90
ISB
TTL Standby
Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = Max
Com.
Ind.
—
—
55
55
—
—
45
45
—
—
40
40
mA
mA
mA
ISB1
ISB2
TTL Standby
Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
Com.
Ind.
—
—
25
30
—
—
25
30
—
—
25
30
CMOS Standby
Current
VDD = Max.,
CE ≥ VDD – 0.2V,
Com.
Ind.
—
—
—
5
10
0.5
—
—
—
5
10
0.5
—
—
—
5
10
0.5
typ.(2)
(CMOS Inputs)
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 3.3V, TA = 25oC. Not 100% tested.
IS63LV1024L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns
Min. Max.
-10 ns
Min. Max.
-12 ns
Min. Max.
Symbol Parameter
Test Conditions
Unit
ICC1
ISB
VDD Operating
Supply Current
VDD = Max., CE = VIL
IOUT = 0 mA, f = Max.
Com.
Ind.
—
—
—
100
110
75
—
—
—
95
105
70
—
—
—
90
100
65
mA
typ.(2)
TTL Standby
Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = Max
Com.
Ind.
—
—
35
40
—
—
30
35
—
—
25
30
mA
mA
mA
ISB1
ISB2
TTL Standby
Current
(TTL Inputs)
VDD = Max.,
VIN = VIH or VIL
CE ≥ VIH, f = 0
Com.
Ind.
—
—
15
20
—
—
15
20
—
—
15
20
CMOS Standby
Current
VDD = Max.,
CE ≥ VDD – 0.2V,
Com.
Ind.
—
—
—
1
1.5
0.05
—
—
—
1
1.5
0.05
—
—
—
1
1.5
0.05
typ.(2)
(CMOS Inputs)
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 3.3V, TA = 25oC. Not 100% tested.
CAPACITANCE(1,2)
Symbol
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
pF
CIN
InputCapacitance
Input/OutputCapacitance
6
8
CI/O
VOUT = 0V
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. I
1/26/07
IS63LV1024
IS63LV1024L
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 ns
Min.
-10 ns
Min.
-12 ns
Min.
Symbol
tRC
Parameter
Max.
—
8
Max.
—
10
—
10
5
Max.
—
12
—
12
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
8
—
2
10
—
2
12
—
2
tAA
Address Access Time
Output Hold Time
CE Access Time
tOHA
—
8
tACE
—
—
0
—
—
0
—
—
0
tDOE
OE Access Time
4
(2)
tLZOE
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
CE to Power Up Time
CE to Power Down Time
—
4
—
5
—
6
(2)
tHZOE
0
0
0
(2)
tLZCE
3
—
4
3
—
5
3
—
6
(2)
tHZCE
0
0
0
tPU
tPD
0
—
8
0
—
10
0
—
12
—
—
—
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
loading specified in Figure 1.
2. Tested with the loading specified in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Unit
0V to 3.0V
3 ns
Input and Output Timing
andReferenceLevels
1.5V
OutputLoad
See Figures 1 and 2
AC TEST LOADS
317 Ω
3.3V
ZOUT = 50 Ω
OUTPUT
OUTPUT
50 Ω
351 Ω
5 pF
Including
jig and
scope
VT = 1.5V
Figure 1
Figure 2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
5
Rev. I
1/26/07
IS63LV1024
IS63LV1024L
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
t
LZOE
ACE
CE
t
HZCE
t
LZCE
HIGH-Z
DOUT
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. I
1/26/07
IS63LV1024
IS63LV1024L
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 ns
-10 ns
-12 ns
Symbol
tWC
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
ns
Write Cycle Time
CE to Write End
8
7
8
—
10
7
—
12
8
—
tSCE
—
—
—
ns
tAW
Address Setup Time to
Write End
—
8
—
8
—
ns
tHA
tSA
(1)
tPWE
1
(2)
tPWE
2
Address Hold from
Write End
0
—
0
—
0
—
ns
Address Setup Time
0
7
—
—
—
—
—
4
0
7
—
—
—
—
—
5
0
8
—
—
—
—
—
6
ns
ns
ns
ns
ns
ns
ns
WE Pulse Width (OE High)
WE Pulse Width (OE Low)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
8
10
5
12
6
tSD
tHD
5
0
0
0
(2)
tHZWE
—
3
—
3
—
3
(2)
tLZWE
—
—
—
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2 (CE Controlled, OE = HIGH or LOW)
t
WC
VALID ADDRESS
SCE
ADDRESS
t
SA
t
t
HA
CE
t
AW
t
PWE1
PWE2
t
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR1.eps
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
7
Rev. I
1/26/07
IS63LV1024
IS63LV1024L
AC WAVEFORMS
WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR2.eps
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
LOW
CE
t
t
AW
t
PWE2
WE
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
D
OUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > VIH.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. I
1/26/07
IS63LV1024
IS63LV1024L
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
VDR
Parameter
Test Condition
Options
Min.
Typ.(1)
Max.
Unit
V
VDD for Data Retention
Data Retention Current
See Data Retention Waveform
VDD = 2.0V, CE ≥ VDD – 0.2V
2.0
—
3.6
IDR
IS63LV1024
—
—
0.5
10
mA
IS63LV1024L
0.05
1.5
tSDR
tRDR
Data Retention Setup Time
Recovery Time
See Data Retention Waveform
0
—
—
—
—
ns
ns
See Data Retention Waveform
tRC
O
Note 1: Typical values are measured at VDD = 3.0V, T
A
= 25 C and not 100% tested.
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
Data Retention Mode
tRDR
VDD
VDR
CE ≥ VDD - 0.2V
CE
GND
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
9
Rev. I
1/26/07
IS63LV1024
IS63LV1024L
IS63LV1024 ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No.
Package
8
IS63LV1024-8K
IS63LV1024-8KL
400-mil Plastic SOJ
400-mil Plastic SOJ, Lead-free
10
IS63LV1024-10T
IS63LV1024-10J
IS63LV1024-10K
TSOP (Type II)
300-mil Plastic SOJ
400-mil Plastic SOJ
12
IS63LV1024-12T
IS63LV1024-12J
IS63LV1024-12KL
TSOP (Type II)
300-mil Plastic SOJ
400-mil Plastic SOJ, Lead-free
Industrial Range: –40°C to +85°C
Speed(ns)
OrderPartNo.
IS63LV1024-8KI
IS63LV1024-10KI
IS63LV1024-12TI
Package
8
400-milPlasticSOJ
400-milPlasticSOJ
TSOP(TypeII)
10
12
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. I
1/26/07
IS63LV1024
IS63LV1024L
IS63LV1024L ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed(ns)
Order Part No.
Package
8
IS63LV1024L-8T
IS63LV1024L-8B
TSOP (Type II)
mBGA(8mmx10mm)
10
12
IS63LV1024L-10T
IS63LV1024L-10TL
IS63LV1024L-10HL
TSOP (Type II)
TSOP (Type II), Lead-free
sTSOP (Type I) (8mm x13.4mm), Lead-free
IS63LV1024L-12T
TSOP (Type II)
IS63LV1024L-12H
IS63LV1024L-12J
IS63LV1024L-12JL
IS63LV1024L-12B
sTSOP (Type I) (8mm x13.4mm)
300-mil Plastic SOJ
300-mil Plastic SOJ, Lead-free
mBGA(8mmx10mm)
Industrial Range: –40°C to +85°C
Speed(ns)
Order Part No.
Package
8
IS63LV1024L-8TI
IS63LV1024L-8JI
IS63LV1024L-8KI
IS63LV1024L-8BI
TSOP (Type II)
300-mil Plastic SOJ
400-mil Plastic SOJ
mBGA(8mmx10mm)
10
12
IS63LV1024L-10HI
IS63LV1024L-10JLI
IS63LV1024L-10KLI
IS63LV1024L-10TLI
sTSOP (Type I) (8mm x13.4mm)
300-mil Plastic SOJ, Lead-free
400-mil Plastic SOJ, Lead-free
TSOP (Type II), Lead-free
IS63LV1024L-12BI
IS63LV1024L-12BLI
IS63LV1024L-12TI
mBGA(8mmx10mm)
mBGA(8mmx10mm),Lead-free
TSOP (Type II)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
11
Rev. I
1/26/07
PACKAGING INFORMATION
400-mil Plastic SOJ
Package Code: K
Notes:
1. Controlling dimension:
millimeters.
N
N/2+1
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions
and should be measured from
the bottom of the package.
4. Reference document: JEDEC
MS-027.
E1
E
1
N/2
SEATING PLANE
D
A
b
C
A2
e
B
A1
E2
Millimeters
Inches
Min Max
Millimeters
Inches
Min Max
Millimeters
Inches
Symbol Min
Max
Min
Max
Min
Max
Min
Max
No. Leads (N)
28
32
36
A
A1
A2
B
b
C
D
E
E1
E2
e
3.25 3.75
0.128 0.148
3.25
0.64
2.08
0.38
0.66
0.18
20.82 21.08
11.05 11.30
10.03 10.29
9.40 BSC
3.75
—
—
0.51
0.81
0.33
0.128 0.148
3.25 3.75
0.128 0.148
0.64
2.08
—
—
0.025
0.082
—
—
0.025
0.082
—
—
0.64
2.08
—
—
0.025
0.082
—
—
0.38 0.51
0.66 0.81
0.18 0.33
18.29 18.54
11.05 11.30
10.03 10.29
9.40 BSC
0.015 0.020
0.026 0.032
0.007 0.013
0.720 0.730
0.435 0.445
0.395 0.405
0.370 BSC
0.015 0.020
0.026 0.032
0.007 0.013
0.820 0.830
0.435 0.445
0.395 0.405
0.370 BSC
0.38 0.51
0.66 0.81
0.18 0.33
23.37 23.62
11.05 11.30
10.03 10.29
9.40 BSC
0.015 0.020
0.026 0.032
0.007 0.013
0.920 0.930
0.435 0.445
0.395 0.405
0.370 BSC
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
10/29/03
PACKAGING INFORMATION
Millimeters
Symbol Min Max
No. Leads (N)
Inches
Min Max
Millimeters
Inches
Min Max
Millimeters
Min Max
Inches
Min Max
Min
Max
40
42
44
A
A1
A2
B
b
C
D
E
E1
E2
e
3.25 3.75
0.128 0.148
3.25
0.64
2.08
0.38
0.66
0.18
27.18 27.43
11.05 11.30
10.03 10.29
9.40 BSC
3.75
—
—
0.51
0.81
0.33
0.128 0.148
3.25 3.75
0.128 0.148
0.64
2.08
—
—
0.025
0.082
—
—
0.025
0.082
—
—
0.64
2.08
—
—
0.025
0.082
—
—
0.38 0.51
0.66 0.81
0.18 0.33
25.91 26.16
11.05 11.30
10.03 10.29
9.40 BSC
0.015 0.020
0.026 0.032
0.007 0.013
1.020 1.030
0.435 0.445
0.395 0.405
0.370 BSC
0.015 0.020
0.026 0.032
0.007 0.013
1.070 1.080
0.435 0.445
0.395 0.405
0.370 BSC
0.38 0.51
0.66 0.81
0.18 0.33
28.45 28.70
11.05 11.30
10.03 10.29
9.40 BSC
0.015 0.020
0.026 0.032
0.007 0.013
1.120 1.130
0.435 0.445
0.395 0.405
0.370 BSC
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
10/29/03
PACKAGING INFORMATION
300-mil Plastic SOJ
Package Code: J
N
E1
E
1
SEATING PLANE
D
A
A2
B
C
e
b
A1
E2
Notes:
1. Controlling dimension: inches, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash
protrusionsandshouldbemeasuredfromthebottomof
MILLIMETERS
INCHES
Min. Typ. Max.
Sym. Min. Typ. Max.
N0.
Leads
thepackage
.
4. Formed leads shall be planar with respect to one
24/26
another within 0.004 inches at the seating plane.
A
—
—
—
—
—
—
—
—
—
—
—
3.56
—
—
—
—
—
—
—
—
—
—
—
—
0.140
—
A1
A2
b
0.64
2.41
0.41
0.66
0.20
17.02
8.26
7.49
6.27
0.025
0.095
0.016
0.026
0.008
0.670
0.325
0.295
0.247
2.67
0.51
0.81
0.25
17.27
8.76
7.75
7.29
0.105
0.020
0.032
0.010
0.680
0.345
0.305
0.287
B
C
D
E
E1
E2
e
1.27 BSC
0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
02/25/03
PACKAGING INFORMATION
300-mil Plastic SOJ
Package Code: J
MILLIMETERS
INCHES
MILLIMETERS
INCHES
Sym. Min. Typ. Max.
Min. Typ. Max.
Sym. Min. Typ. Max.
Min. Typ. Max.
N0.
N0.
Leads
28
Leads
32
A
—
—
—
—
—
—
—
—
—
—
—
3.56
—
—
—
—
—
—
—
—
—
—
—
—
0.140
—
A
—
—
—
—
—
—
—
—
—
—
—
3.56
—
—
—
—
—
—
—
—
—
—
—
—
0.140
—
A1
A2
b
0.64
2.41
0.41
0.66
0.20
18.29
8.26
7.49
6.27
0.025
0.095
0.016
0.026
0.008
0.720
0.325
0.295
0.247
A1
A2
b
0.64
2.41
0.41
0.66
0.20
20.83
8.26
7.49
6.27
0.025
0.095
0.016
0.026
0.008
0.820
0.325
0.295
0.247
2.67
0.51
0.81
0.25
18.54
8.76
7.75
7.29
0.105
0.020
0.032
0.010
0.730
0.345
0.305
0.287
2.67
0.51
0.81
0.25
21.08
8.76
7.75
7.29
0.105
0.020
0.032
0.010
0.830
0.345
0.305
0.287
B
B
C
C
D
D
E
E
E1
E2
e
E1
E2
e
1.27 BSC
0.050 BSC
1.27 BSC
0.050 BSC
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.D
02/25/03
PACKAGING INFORMATION
Plastic STSOP - 32 pins
Package Code: H (Type I)
A2
A
A1
1
N
E
b
e
D1
D
S
SEATING PLANE
L
α
C
Plastic STSOP (H - Type I)
Millimeters
Inches
Notes:
Symbol Min Max
Min
Max
1. Controlling dimension: millimeters, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D1 and E do not include mold flash protru-
sions and should be measured from the bottom of the package
4. Formed leads shall be planar with respect to one another
within 0.004 inches at the seating plane.
Ref. Std.
N
32
A
A1
A2
b
C
D
D1
E
e
—
0.05
1.25
—
—
0.049
—
0.041
0.009
.
0.002
0.037
0.007
0.95 1.05
0.17 0.23
0.14 0.16
13.20 13.60
11.70 11.90
7.90 8.10
0.50 BSC
0.0055 0.0063
0.520
0.461
0.311
0.535
0.469
0.319
0.020 BSC
L
S
0.30 0.70
0.28 Typ.
0.012
0.011 Typ.
0.028
α
0°
5°
0°
5°
Integrated Silicon Solution, Inc.
PK13197H32 Rev.B 04/21/03
PACKAGING INFORMATION
Mini Ball Grid Array
Package Code: B (36-pin)
Top View
Bottom View
φ b (36x)
1
2
3
4
5 6
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
e
D
D1
G
H
G
H
e
E
E1
Notes:
1. Controllingdimensionsareinmillimeters.
A2
A
A1
SEATING PLANE
mBGA - 6mm x 8mm
mBGA - 8mm x 10mm
MILLIMETERS
INCHES
Min. Typ. Max.
36
MILLIMETER
INCHES
Min. Typ. Max.
36
Sym. Min. Typ. Max.
Sym. Min. Typ. Max.
N0.
Leads
N0.
Leads
36
36
A
—
—
—
—
1.20
0.30
—
—
—
—
—
0.047
0.012
—
A
—
—
—
—
1.20
0.30
—
—
—
—
—
0.047
0.012
—
A1
A2
D
0.24
0.60
0.009
0.024
A1
A2
D
0.24
0.60
0.009
0.024
7.90 8.00 8.10
5.25BSC
0.311 0.315 0.319
0.207BSC
9.90 10.00 10.10
5.25BSC
0.390 0.394 0.398
.207BSC
D1
E
D1
E
5.90 6.00 6.10
3.75BSC
0.232 0.236 0.240
0.148BSC
7.90 8.00 8.10
3.75BSC
0.311 0.315 0.319
0.148BSC
E1
e
E1
e
0.75BSC
0.030BSC
0.75BSC
0.030BSC
b
0.30 0.35 0.40
0.012 0.014 0.016
b
0.30 0.35 0.40
0.012 0.014 0.016
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. E
01/15/03
PACKAGING INFORMATION
PlasticTSOP
Package Code: T (Type II)
N
N/2+1
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
E
E1
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
1
N/2
D
SEATING PLANE
A
ZD
.
L
α
e
b
C
A1
Plastic TSOP (T - Type II)
Millimeters Inches
Millimeters
Inches
Millimeters
Inches
Symbol Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Ref. Std.
No. Leads (N)
32
44
50
A
A1
b
C
D
E1
E
e
—
1.20
—
0.047
—
1.20
0.15
0.45
0.21
—
0.047
—
1.20
—
0.047
0.05 0.15
0.30 0.52
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
1.27 BSC
0.002 0.006
0.012 0.020
0.005 0.008
0.820 0.830
0.391 0.400
0.451 0.466
0.050 BSC
0.05
0.30
0.12
18.31 18.52
10.03 10.29
11.56 11.96
0.80 BSC
0.002 0.006
0.012 0.018
0.005 0.008
0.721 0.729
0.395 0.405
0.455 0.471
0.032 BSC
0.05 0.15
0.30 0.45
0.12 0.21
20.82 21.08
10.03 10.29
11.56 11.96
0.80 BSC
0.002 0.006
0.012 0.018
0.005 0.008
0.820 0.830
0.395 0.405
0.455 0.471
0.031 BSC
L
ZD
α
0.40 0.60
0.95 REF
0.016 0.024
0.037 REF
0.41
0.81 REF
0°
0.60
0.016 0.024
0.032 REF
0.40 0.60
0.88 REF
0.016 0.024
0.035 REF
0°
5°
0°
5°
5°
0°
5°
0°
5°
0°
5°
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. F
06/18/03
相关型号：
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