IS65WV102416FALL-55CTLA3 [ISSI]
Standard SRAM, 1MX16, 55ns, CMOS, PDSO48, TSOP1-48;
| 型号： | IS65WV102416FALL-55CTLA3 |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Standard SRAM, 1MX16, 55ns, CMOS, PDSO48, TSOP1-48 静态存储器 光电二极管 |
| 文件： | 总17页 (文件大小：671K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS62WV102416FALL/BLL
IS65WV102416FALL/BLL
JANUARY 2017
1Mx16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
KEY FEATURES
DESCRIPTION
High-speed access time: 45ns, 55ns
CMOS low power operation
The ISSI IS62/65WV102416FALL/FBLL are high-speed,
low power, 16M bit static RAMs organized as 1024K words
by 16 bits. It is fabricated using ISSI's high-performance
CMOS technology.
– Operating Current: 36mA (max.)
– CMOS standby Current: 5.8uA (typ.)
TTL compatible interface levels
Single power supply
This highly reliable process coupled with innovative circuit
design techniques, yields high-performance and low power
consumption devices. When CS1# is HIGH (deselected) or
when CS2 is LOW (deselected) or when CS1# is LOW,
CS2 is HIGH and both LB# and UB# are HIGH, the device
assumes a standby mode at which the power dissipation
can be reduced down with CMOS input levels.
–1.65V-2.2V VDD (IS62/65WV102416FALL)
– 2.2V-3.6V VDD (IS62/65WV102416FBLL)
Three state outputs
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE#) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB#) and Lower Byte (LB#)
access.
Commercial, Industrial and Automotive
temperature support
Lead-free available
The IS62/65WV102416FALL/FBLL are packaged in the
JEDEC standard 48-pin mini BGA (6mm x 8mm) and 48-Pin
TSOP (TYPE I).
FUNCTIONAL BLOCK DIAGRAM
1M x 16
MEMORY
ARRAY
DECODER
A0 – A19(20)
VDD
GND
I/O0 – I/O7
Lower Byte
I/O
DATA
COLUMN I/O
I/O8 – I/O15
CIRCUIT
Upper Byte
BYTE#
CS2
CS1#
OE#
CONTROL
CIRCUIT
WE#
UB#
LB#
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
1
Rev. A
01/05/2017
IS62WV102416FALL/BLL
IS65WV102416FALL/BLL
PIN CONFIGURATIONS
48-Pin mini BGA (6mm x 8mm)
48-Pin TSOP (TYPE I)
1
2
3
4
5
6
A16
1
A15
48
47
A
B
BYTE#
VSS
2
3
A14
A13
LB#
OE#
A0
A1
A2
CS2
46
45
I/O15/A20
I/O7
4
5
A12
A11
A10
44
I/O8
I/O9
UB#
A3
A5
A4
A6
CS1#
I/O1
I/O0
I/O2
I/O14
6
7
43
42
I/O6
A9
A8
I/O13
I/O10
C
D
8
9
41
I/O5
I/O12
I/O4
A19
NC
40
39
10
11
VSS
VDD
I/O11
I/O12
A17
NC
A7
I/O3
I/O4
VDD
VSS
WE#
CS2
38
37
36
VDD
12
I/O11
I/O3
NC
UB#
LB#
13
14
15
16
E
A16
35
34
I/O10
I/O2
I/O9
I/O1
I/O8
A18
A17
A7
33
32
31
F
I/O14
I/O15
A18
I/O13
A19
A8
A14
A12
A9
A15
A13
A10
I/O5
WE#
A11
I/O6
I/O7
NC
17
18
30
A6
19
20
21
G
I/O0
OE#
VSS
A5
A4
29
28
27
A3
A2
A1
22
23
24
CS1#
A0
H
26
25
PIN DESCRIPTIONS
A0-A19
Address Inputs
I/O0-I/O14
Data Inputs/Outputs
I/O15/A20(1) I/O15, when used in a x16 mode, A20
when used in a x8 mode.
CS1#, CS2
OE#
Chip Enable Inputs
Output Enable Input
Write Enable Input
WE#
LB#
Lower-byte Control
(I/O0-I/O7)
UB#
Upper-byte Control
(I/O8-I/O15)
BYTE#(1)
Must be tied to VDD to use as X16 or VSS
to use as X8 . UB#,LB#, I/O 8~I/O14
are not used and I/O 15 become A20
in x8 mode.
NC
VDD
No Connection
Power
VSS
Notes:
Ground
1. No BYTE# pin for 48 pin mini BGA Package.
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2
Rev. A
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IS62WV102416FALL/BLL
IS65WV102416FALL/BLL
FUNCTION DESCRIPTION
SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM
has three different modes supported. Each function is described below with Truth Table.
STANDBY MODE
Device enters standby mode when deselected (CS1# HIGH or CS2 LOW or both UB# and LB# are HIGH). The input
and output pins (I/O0-15) are placed in a high impedance state. The current consumption in this mode will be ISB1 or
ISB2. CMOS input in this mode will maximize saving power.
WRITE MODE
Write operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input LOW. The input
and output pins (I/O0-15) are in data input mode. Output buffers are closed during this time even if OE# is LOW. UB#
and LB# enables a byte write feature. By enabling LB# LOW, data from I/O pins (I/O0 through I/O7) are written into the
location specified on the address pins. And with UB# being LOW, data from I/O pins (I/O8 through I/O15) are written
into the location.
READ MODE
Read operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input HIGH. When
OE# is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. UB#
and LB# enables a byte read feature. By enabling LB# LOW, data from memory appears on I/O0-7. And with UB#
being LOW, data from memory appears on I/O8-15.
In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as
READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used.
TRUTH TABLE
Mode
CS1#
CS2
WE#
OE#
LB#
UB#
I/O0-I/O7
I/O8-I/O15
VDD Current
H
X
X
L
L
L
L
L
L
L
L
X
L
X
X
X
H
H
H
H
H
L
X
X
X
H
H
L
L
L
X
X
X
X
X
H
L
X
L
H
L
L
X
X
H
X
L
H
L
L
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
Not Selected
ISB2
X
H
H
H
H
H
H
H
H
Output Disabled
Read
ICC,ICC1
ICC,ICC1
H
L
L
Write
L
L
H
L
High-Z
DIN
ICC,ICC1
DIN
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3
Rev. A
01/05/2017
IS62WV102416FALL/BLL
IS65WV102416FALL/BLL
ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vterm
VDD
Parameter
Value
Unit
V
Terminal Voltage with Respect to GND
VDD Related to GND
Storage Temperature
Power Dissipation
–0.5 to VDD + 0.5V
–0.3 to 4.0
–65 to +150
1.0
V
tStg
C
W
PT
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE(1)
Range
Ambient Temperature
PART
NUMBER
SPEED (MAX)
VDD(MIN) VDD(TYP)
VDD(MAX)
Commercial
Industrial
55 ns
55 ns
55 ns
45ns
45ns
55ns
1.65V
1.65V
1.65V
2.2V
1.8V
1.8V
1.8V
3.0V
3.0V
3.0V
2.2V
2.2V
2.2V
3.6V
3.6V
3.6V
0C to +70C
-40C to +85C
-40C to +125C
0C to +70C
~ALL
~BLL
Automotive
Commercial
Industrial
2.2V
-40C to +85C
-40C to +125C
Automotive
2.2V
Note:
1.
Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization.
PIN CAPACITANCE (1)
Parameter
Symbol Test Condition
Max
Units
pF
Input capacitance
CIN
6
8
TA = 25°C, f = 1 MHz, VDD = VDD(typ)
DQ capacitance (IO0–IO15)
CI/O
pF
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
THERMAL CHARACTERISTICS (1)
Parameter
Symbol
RθJA
Rating
TBD
Units
°C/W
°C/W
°C/W
Thermal resistance from junction to ambient (airflow = 1m/s)
Thermal resistance from junction to pins
Thermal resistance from junction to case
RθJB
TBD
RθJC
TBD
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
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Rev. A
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IS62WV102416FALL/BLL
IS65WV102416FALL/BLL
AC TEST CONDITIONS (OVER THE OPERATING RANGE)
Parameter
Unit
Unit
(1.65V~2.2V)
(2.2V~3.6V)
Input Pulse Level
0V to VDD
0V to VDD
Input Rise and Fall Time
1V/ns
0.9V
1V/ns
½ VDD
1005
820
Output Timing Reference Level
R1
13500
10800
1.8V
R2
VTM
VDD
Output Load Conditions
Refer to Figure 1 and 2
OUTPUT LOAD CONDITIONS FIGURES
FIGURE 1
FIGURE 2
R1
R1
VTM
VTM
OUTPUT
OUTPUT
30pF,
Including
jig
5pF,
Including
jig
R2
R2
and scope
and scope
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Rev. A
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IS62WV102416FALL/BLL
IS65WV102416FALL/BLL
DC ELECTRICAL CHARACTERISTICS
IS62(5)WV102416FALL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE)
VDD = 1.65V ~ 2.2V
Symbol
VOH
Parameter
Test Conditions
IOH = -0.1 mA
IOL = 0.1 mA
Min.
1.4
—
Max.
Unit
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
—
VOL
0.2
V
(1)
VIH
1.4
–0.2
–1
VDD + 0.2
V
(1)
VIL
0.4
1
V
ILI
GND < VIN < VDD
µA
µA
ILO
Output Leakage
GND < VIN < VDD, Output Disabled
–1
1
Notes:
1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested.
IS62(5)WV102416FBLL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE)
VDD = 2.2V ~ 3.6V
Symbol
Parameter
Test Conditions
Min.
2.0
2.4
—
Max.
Unit
V
VOH
Output HIGH Voltage
2.2 ≤ VDD < 2.7, IOH = -0.1 mA
2.7 ≤ VDD ≤ 3.6, IOH = -1.0 mA
2.2 ≤ VDD < 2.7, IOL = 0.1 mA
2.7 ≤ VDD ≤ 3.6, IOL = 2.1 mA
2.2 ≤ VDD < 2.7
—
—
V
VOL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
0.4
V
—
0.4
V
(1)
VIH
1.8
2.0
–0.3
–0.3
–1
VDD + 0.3
V
2.7 ≤ VDD ≤ 3.6
VDD + 0.3
V
(1)
VIL
2.2 ≤ VDD < 2.7
0.6
0.8
1
V
2.7 ≤ VDD ≤ 3.6
V
ILI
Input Leakage
GND < VIN < VDD
µA
µA
ILO
Output Leakage
GND < VIN < VDD, Output Disabled
–1
1
Notes:
1. VILL(min) = -2.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested.
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Rev. A
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IS62WV102416FALL/BLL
IS65WV102416FALL/BLL
IS62(5)WV102416FALL DC ELECTRICAL CHARACTERISTICS-II FOR POWER
(OVER THE OPERATING RANGE)
Typ(1)
Max
Symbol
Parameter
Test Conditions
Grade
Unit
-
-
-
-
-
-
Com.
Ind.
Auto. A3
Com.
Ind.
Auto. A3
36
36
36
6
6
6
VDD Dynamic
Operating Supply
Current
VDD = VDD(max), IOUT = 0mA,
f = fmax,
ICC
mA
VDD Static
Operating Supply
Current
VDD = VDD(max), IOUT = 0mA,
f = 0
ICC1
mA
µA
25°C
5.8
6.8
9.5
10.5
24
15
17
23
25
60
VDD = VDD(max), f = 0,
CS1# ≥ VDD - 0.2V or
CS2 < 0.2V or
(LB# and UB#) ≥ VDD - 0.2V,
VIN ≤ 0.2V or VIN ≥ VDD - 0.2V
Com.
40°C
70°C
85°C
125°C
CMOS Standby
Current (CMOS
Inputs)
ISB2
Note:
Ind.
Auto. A3
1. Typical values are included for reference purpose only and are not guaranteed or tested. Typical values are measured at VDD=VDD (Typ.).
IS62(5)WV102416FBLL DC ELECTRICAL CHARACTERISTICS-II FOR POWER
(OVER THE OPERATING RANGE)
Typ(1)
Max
Symbol
Parameter
Test Conditions
Grade
Unit
-
-
-
-
-
-
Com.
Ind.
Auto. A3
Com.
36
36
36
6
VDD Dynamic
Operating Supply
Current
VDD = VDD(max), IOUT = 0mA,
f = fmax,
ICC
mA
VDD Static
Operating Supply
Current
VDD = VDD(max), IOUT = 0mA,
f = 0
ICC1
Ind.
Auto. A3
6
6
mA
µA
25°C
5.8
6.8
9.5
10.5
24
15
17
23
25
60
VDD = VDD(max), f = 0,
CS1# ≥ VDD - 0.2V or
CS2 < 0.2V or
(LB# and UB#) ≥ VDD - 0.2V,
VIN ≤ 0.2V or VIN ≥ VDD - 0.2V
Com.
40°C
70°C
85°C
125°C
CMOS Standby
Current (CMOS
Inputs)
ISB2
Note:
Ind.
Auto. A3
1. Typical values are included for reference purpose only and are not guaranteed or tested. Typical values are measured at VDD=VDD (Typ.).
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Rev. A
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IS62WV102416FALL/BLL
IS65WV102416FALL/BLL
AC CHARACTERISTICS(6) (OVER OPERATING RANGE)
READ CYCLE AC CHARACTERISTICS
45ns
55ns
Min
Parameter
Symbol
unit notes
Min
Max
-
Max
-
Read Cycle Time
tRC
45
-
55
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,5
1
Address Access Time
Output Hold Time
tAA
45
-
55
-
tOHA
tACS1/ACS2
tBA
10
-
10
-
1
CS1#, CS2 Access Time
UB#, LB# Access Time
OE# Access Time
45
45
20
15
-
55
55
25
20
-
1
-
-
1
tDOE
tHZOE
tLZOE
tHZCS
tLZCS
tHZB
-
-
1
OE# to High-Z Output
OE# to Low-Z Output
CS1#, CS2 to High-Z Output
CS1#, CS2 to Low-Z Output
UB#, LB# to High-Z Output
UB#, LB# to Low-Z Output
-
-
2
5
-
5
-
2
15
-
20
-
2
10
-
10
-
2
15
-
20
-
2
tLZB
10
10
2
WRITE CYCLE AC CHARACTERISTICS
45ns
55ns
Parameter
Symbol
unit notes
Min
45
35
35
35
0
Max
Min
55
40
40
40
0
Min
Write Cycle Time
tWC
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,3,5
1,3
CS1#, CS2 to Write End
tSCS1/SCS2
Address Setup Time to Write End tAW
-
-
1,3
UB#,LB# to Write End
tPWB
-
-
1,3
Address Hold from Write End
Address Setup Time
tHA
-
-
1,3
tSA
0
-
0
-
1,3
WE# Pulse Width
tPWE
tSD
35
20
0
-
40
25
0
-
1,3,4
1,3
Data Setup to Write End
Data Hold from Write End
WE# LOW to High-Z Output
WE# HIGH to Low-Z Output
-
-
tHD
-
-
1,3
tHZWE
tLZWE
-
15
-
-
20
-
2,3
5
5
2,3
Notes:
1. Tested with the load in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. tHZOE, tHZCS, tHZB, and tHZWE transitions are
measured when the output enters a high impedance state. Not 100% tested.
3. The internal write time is defined by the overlap of CS1# = LOW, CS2=HIGH, UB# or LB# = LOW, and WE# = LOW. All four conditions must be
in valid states to initiate a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write.
4. tPWE > tHZWE + tSD when OE# is LOW.
5. Address inputs must meet VIH and VIL SPEC during this period. Any glitch or unknown inputs are not permitted. Unknown input with standby
mode is acceptable.
6. Data retention characteristics are defined later in DATA RETENTION CHARACTERISTICS.
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IS62WV102416FALL/BLL
IS65WV102416FALL/BLL
Timing Diagram
READ CYCLE NO. 1(1) (ADDRESS CONTROLLED, CS1# = OE# = UB# = LB# = LOW, CS2 = WE# = HIGH)
tRC
ADDRESS
tAA
tOHA
tOHA
I/O0-15
PREVIOUS DATA VALID
Low-Z
DATA VALID
Low-Z
Notes:
1. The device is continuously selected.
READ CYCLE NO.2(1) (OE# CONTROLLED, WE# = HIGH)
tRC
ADDRESS
tAA
tOHA
tDOE
OE#
tHZOE
tLZOE
tACS1/tACS2
CS1#
tHZCS1/
tHZCS2
CS2
tLZCS1/
tLZCS2
UB#,LB#
tHZB
tBA
tLZB
HIGH-Z
DOUT
LOW-Z
DATA VALID
Notes:
1. Address is valid prior to or coincident with CS1# LOW or CS2 HIGH transition.
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IS62WV102416FALL/BLL
IS65WV102416FALL/BLL
WRITE CYCLE NO.1(1,2) (CS1# , CS2 CONTROLLED, OE# = HIGH OR LOW)
tWC
ADDRESS
tSCS1
tSCS2
tSA
tHA
CS1#
CS2
tAW
tPWE
WE#
tPWB
UB#, LB#
tHZWE
tLZWE
tHD
HIGH-Z
tSD
DATA UNDEFINED(1)
DOUT
DIN
DATA UNDEFINED (2)
DATA IN VALID
Notes:
1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if OE# goes high before Write
Cycle. tHZOE is the time DOUT goes to High-Z after OE# goes high.
2. During this period the I/Os are in output state. Do not apply input signals.
WRITE CYCLE NO. 2(1,2) (WE# CONTROLLED: OE# IS HIGH DURING WRITE CYCLE)
tWC
ADDRESS
tSCS1
tSCS2
tHA
CS1#
CS2
tAW
tPWE
WE#
tSA
tPWB
UB#, LB#
OE#
DOUT
DIN
tHZOE
HIGH-Z
tHD
DATA UNDEFINED(1)
tSD
DATA UNDEFINED (2)
DATA IN VALID
Notes:
1. tHZOE is the time DOUT goes to High-Z after OE# goes high.
2. During this period the I/Os are in output state. Do not apply input signals.
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IS62WV102416FALL/BLL
IS65WV102416FALL/BLL
WRITE CYCLE NO. 3(1) (WE# CONTROLLED: OE# IS LOW DURING WRITE CYCLE)
tWC
ADDRESS
tSCS1
tSCS2
tHA
CS1#
CS2
tAW
tPWE
WE#
tSA
tPWB
UB#, LB#
tHZWE
tLZWE
tHD
HIGH-Z
tSD
DATA UNDEFINED(1)
DOUT
DIN
DATA UNDEFINED (2)
DATA IN VALID
Notes:
1. If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the
previous READ operation will drive IO BUS.
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Rev. A
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IS62WV102416FALL/BLL
IS65WV102416FALL/BLL
WRITE CYCLE NO. 4(1,2,3) (UB# & LB# Controlled, OE# = LOW)
tWC
tWC
ADDRESS
ADDRESS 1
ADDRESS 2
CS1#=LOW
CS2=HIGH
OE#=LOW
tSA
tHA
tSA
tHA
WE#
tPWB
tPWB
UB#, LB#
WORD 1
WORD 2
tHZWE
tLZWE
HIGH-Z
DOUT
DIN
DATA UNDEFINED
tHD
tSD
DATA IN
VALID
DATA IN
VALID
Notes:
1. If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the
previous READ operation will drive IO BUS.
2. Due to the restriction of note1, OE# is recommended to be HIGH during write period.
3. WE# stays LOW in this example. If WE# toggles, tPWE and tHZWE must be considered.
Integrated Silicon Solution, Inc.- www.issi.com
12
Rev. A
01/05/2017
IS62WV102416FALL/BLL
IS65WV102416FALL/BLL
DATA RETENTION CHARACTERISTICS
Symbol Parameter
Min. Typ.(1)
Max.
Unit
Test Condition
VDD(max)
VDR
VDD for Data Retention See Data Retention Waveform
1.5
-
V
25°C
85°C
125°C
-
-
-
5.8
10.5
24
15
25
60
CS1# ≥ VDD – 0.2V or CS2 ≤ 0.2V or
(LB# and UB#) ≥ VDD - 0.2V,
VIN ≤ 0.2V or VIN ≥ VDD - 0.2V
Data Retention
Current
IDR
uA
Data Retention Setup
Time
(2)
tSDR
See Data Retention Waveform
See Data Retention Waveform
0
-
-
-
-
ns
ns
Recovery Time
tRC
tRDR
Notes:
1. Typical values are measured at VDD=1.8V or 3V, and not 100% tested.
2. VDD power down slope must be longer than 100 us/volt when enter into Data Retention Mode.
DATA RETENTION WAVEFORM (CS1# CONTROLLED)
Data Retention Mode
tSDR
tRDR
VDD
VDR
CS1# > VDD – 0.2V
CS1#
GND
DATA RETENTION WAVEFORM (CS2 CONTROLLED)
Data Retention Mode
tSDR
tRDR
VDD
CS2
VDR
CS2 < 0.2V
VSS
Integrated Silicon Solution, Inc.- www.issi.com
13
Rev. A
01/05/2017
IS62WV102416FALL/BLL
IS65WV102416FALL/BLL
DATA RETENTION WAVEFORM (UB# AND LB# CONTROLLED)
Data Retention Mode
tSDR
tRDR
VDD
VDR
UB# and LB# > VDD – 0.2V
UB#/LB#
GND
Integrated Silicon Solution, Inc.- www.issi.com
14
Rev. A
01/05/2017
IS62WV102416FALL/BLL
IS65WV102416FALL/BLL
ORDERING INFORMATION
IS62/65WV102416FALL (1.65V - 2.2V)
Industrial Range: -40°C to +85°C
Speed (ns)
Order Part No.
Package
55
55
55
IS62WV102416FALL-55TLI
IS62WV102416FALL-55BI
IS62WV102416FALL-55BLI
TSOP (Type I), Lead-free
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
Automotive (A3) Range: –40°C to +125°C
Speed (ns)
Order Part No.
Package
55
55
55
IS65WV102416FALL-55CTLA3
IS65WV102416FALL-55BA3
IS65WV102416FALL-55BLA3
TSOP (Type I), Lead-free
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
IS62/65WV102416FBLL (2.2V - 3.6V)
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
45
45
45
55
55
55
IS62WV102416FBLL-45TLI
IS62WV102416FBLL-45BI
IS62WV102416FBLL-45BLI
IS62WV102416FBLL-55TLI
IS62WV102416FBLL-55BI
IS62WV102416FBLL-55BLI
TSOP (Type I), Lead-free
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
TSOP (Type I), Lead-free
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
Automotive Range (A3): –40°C to +125°C
Speed (ns)
Order Part No.
Package
55
55
55
IS65WV102416FBLL-55CTLA3
IS65WV102416FBLL-55BA3
IS65WV102416FBLL-55BLA3
TSOP (Type I), Copper Lead-frame, Lead-free
mini BGA (6mm x 8mm)
mini BGA (6mm x 8mm), Lead-free
Integrated Silicon Solution, Inc.- www.issi.com
15
Rev. A
01/05/2017
IS62WV102416FALL/BLL
IS65WV102416FALL/BLL
PACKAGE INFORMATION
Integrated Silicon Solution, Inc.- www.issi.com
16
Rev. A
01/05/2017
IS62WV102416FALL/BLL
IS65WV102416FALL/BLL
Integrated Silicon Solution, Inc.- www.issi.com
17
Rev. A
01/05/2017
相关型号：
IS65WV10248EBLL-45CTLA3
Standard SRAM, 1MX8, 45ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, TSOP2-44
ISSI
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