IS66WV51216DBLL-55TLI-TR [ISSI]
Application Specific SRAM, 512KX16, 55ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, TSOP2-44;
| 型号： | IS66WV51216DBLL-55TLI-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Application Specific SRAM, 512KX16, 55ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, TSOP2-44 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总17页 (文件大小：463K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS66WV51216DALL
IS66/67WV51216DBLL
JULYꢀ2011
8MbꢀLOWꢀVOLTAGE,ꢀ
ULTRAꢀLOWꢀPOWERꢀPSEUDOꢀCMOSꢀSTATICꢀRAMꢀ
ꢀꢀꢀꢀꢀꢀ
FEATURES
DESCRIPTION
• High-speed access time:
TheISSIIS66WV51216DALLandIS66/67WV51216DBLL
are high-speed, 8M bit static RAMs organized as 512K
words by 16 bits. It is fabricated using ISSI's high-
performanceCMOStechnology.Thishighlyreliableprocess
coupled with innovative circuit design techniques, yields
high-performance and low power consumption devices.
– 70ns (IS66WV51216DALL, IS66/67WV51216DBLL)
– 55ns (IS66/67WV51216DBLL)
• CMOS low power operation
• Single power supply
– Vdd = 1.7V-1.95V (IS66WV51216dALL)
– Vdd = 2.5V-3.6V (IS66/67WV51216dBLL)
• Three state outputs
When CS1 is HIGH (deselected) or when CS2 is LOW
(deselected) or when CS1 is LOW, CS2 is HIGH and both
LBandUBareHIGH, thedeviceassumesastandbymode
at which the power dissipation can be reduced down with
CMOS input levels.
• Data control for upper and lower bytes
• Industrial temperature available
• Lead-free available
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS66WV51216DALL and IS66/67WV51216DBLL are
packaged in the JEDEC standard 48-ball mini BGA (6mm
x 8mm) and 44-Pin TSOP (TYPE II). The device is aslo
available for die sales.
FUNCTIONALꢀBLOCKꢀDIAGRAM
512K x 16
MEMORY ARRAY
A0-A18
DECODER
V
DD
GND
I/O0-I/O7
Lower Byte
I/O
DATA
COLUMN I/O
CIRCUIT
I/O8-I/O15
Upper Byte
CS2
CS1
OE
CONTROL
CIRCUIT
WE
UB
LB
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev.ꢀ A
06/28/2011
IS66WV51216DALL
IS66/67WV51216DBLL
PINꢀCONFIGURATIONS:
48-BallꢀminiꢀBGAꢀ(6mmꢀxꢀ8mm)
44-PinꢀTSOPꢀ(TypeꢀII)
1
2
3
4
5
6
A4
A3
A2
A1
A0
CS1
I/O0
I/O1
I/O2
I/O3
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
2
3
4
5
A0
A3
A1
A4
A2
LB
OE
UB
CS2
A
B
C
D
E
F
6
7
I/O
8
CS1
I/O
0
8
9
I/O
I/O
A5
A6
I/O
1
I/O
2
9
10
10
11
12
13
14
15
16
17
18
19
20
21
22
V
DD
GND
A17
NC
A14
A12
A7
I/O
I/O
I/O
3
I/O
4
I/O
5
VDD`
11
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
VDD
GND
VDD
A16
A15
A13
A10
I/O11
I/O10
I/O9
I/O8
A18
A8
12
I/O
I/O
I/O
I/O
6
14
13
NC
A8
WE
I/O
7
15
G
H
A18
A9
A11
NC
A9
A10
A11
A17
PINꢀDESCRIPTIONS
A0-A18
I/O0-I/O15
CS1, CS2
OE
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
WE
LB
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
UB
NC
Vdd
Power
GND
Ground
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ A
06/28/2011
IS66WV51216DALL
IS66/67WV51216DBLL
TRUTHꢀTABLE
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
I/OꢀPIN
I/O0-I/O7ꢀ I/O8-I/O15ꢀ VddꢀCurrentꢀ
Modeꢀ
WEꢀ CS1ꢀ CS2ꢀ OEꢀ
LB
UBꢀ
ꢀ Not Selected
X
X
X
H
X
X
X
L
X
X
X
X
X
X
H
X
X
H
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
ISB1, ISB2
ISB1, ISB2
ISB1, ISB2
Output Disabled
Read
H
H
L
L
H
H
H
H
L
X
X
L
High-Z
High-Z
High-Z
High-Z
Icc
Icc
H
H
H
L
L
L
H
H
H
L
L
L
L
H
L
H
L
L
dout
High-Z
dout
High-Z
dout
dout
Icc
Write
L
L
L
L
L
L
H
H
H
X
X
X
L
H
L
H
L
L
dIn
High-Z
dIn
High-Z
dIn
dIn
Icc
Note:
CS2 input signal pin is only available for 48-ball mini BGA package parts. CS2 input is internally enabled for 44-pin TSOP-II pack-
age parts.
OPERATINGꢀRANGEꢀ(Vdd)
ꢀ ꢀ
ꢀ
IS66WV51216DALLꢀ
(70ns)ꢀ
IS66WV51216DBLLꢀ
(55ns,ꢀ70ns)ꢀ
IS67WV51216DBLLꢀ
(55ns,ꢀ70ns)
ꢀ Rangeꢀ
AmbientꢀTemperatureꢀ
ꢀ Industrial
–40°C to +85°C
1.7V - 1.95V
2.5V - 3.6V
–
ꢀ Automotive, A1 –40°C to +85°C
–
–
–
–
2.5V - 3.6V
2.5V - 3.6V
Automotive, A2 –40°C to +105°C
POWER-UPꢀINITIALIzATION
IS66WV512616DALL/DBLL and IS67WV512616DBLL include an on-chip voltage sensor used to launch the power-up initialization
process. When VDD reaches a stable level at or above the VDD (min) , the device will require 50μs to complete its self-initialization
process.Duringtheinitializationperiod,CSshouldremainHIGH.Wheninitializationiscomplete,thedeviceisreadyfornormaloperation.
≥ 50us
VDD (min)
VDD
Device Initialization
Device for Normal Operation
0V
Integrated Silicon Solution, Inc. — www.issi.com
3
Rev.ꢀ A
06/28/2011
IS66WV51216DALL
IS66/67WV51216DBLL
ABSOLUTEꢀMAXIMUMꢀRATINGS(1)
ꢀ
Symbolꢀ
Parameterꢀ
Valueꢀ
–0.2 to Vdd+0.3
–40 to +85
–0.2 to +3.8
–65 to +150
1.0
Unit
V
ꢀ Vterm
tBIAS
Terminal Voltage with Respect to GND
Temperature Under Bias
Vdd Related to GND
Storage Temperature
Power Dissipation
°C
V
Vdd
tStg
°C
W
Pt
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
DCꢀELECTRICALꢀCHARACTERISTICS (Over Operating Range)
Vddꢀ=ꢀ2.5V-3.6V
ꢀ
Symbolꢀ Parameterꢀ
TestꢀConditionsꢀ
IoH = -1 mA
Vddꢀ
Min.ꢀ
2.2
—
Max.ꢀ
Unit
V
ꢀ VoH
VoL
VIH
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage(1)
Input LOW Voltage(1)
Input Leakage
2.5-3.6V
2.5-3.6V
2.5-3.6V
2.5-3.6V
—
IoL = 2.1 mA
0.4
V
2.2
–0.2
–1
Vdd + 0.3
V
VIL
0.6
1
V
ILI
GND ≤ VIn ≤ Vdd
μA
μA
ILo
Output Leakage
GND ≤ Vout ≤ Vdd, Outputs Disabled
–1
1
Notes:
1. VILL (min.) = –2.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max.) = Vdd + 2.0V AC (pulse width < 10ns). Not 100% tested.
DCꢀELECTRICALꢀCHARACTERISTICS (Over Operating Range)
Vddꢀ=ꢀ1.7V-1.95V
ꢀ
Symbolꢀ Parameterꢀ
TestꢀConditionsꢀ
IoH = -0.1 mA
IoL = 0.1 mA
Vddꢀ
Min.ꢀ
1.4
—
Max.ꢀ
Unit
V
ꢀ VoH
VoL
VIH
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage(1)
Input LOW Voltage(1)
Input Leakage
1.7-1.95V
1.7-1.95V
1.7-1.95V
1.7-1.95V
—
0.2
V
1.4
–0.2
–1
Vdd + 0.2
V
VIL
0.4
1
V
ILI
GND ≤ VIn ≤ Vdd
μA
μA
ILo
Output Leakage
GND ≤ Vout ≤ Vdd, Outputs Disabled
–1
1
Notes:
1. VILL (min.) = –1.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max.) = Vdd + 1.0V AC (pulse width < 10ns). Not 100% tested.
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ A
06/28/2011
IS66WV51216DALL
IS66/67WV51216DBLL
CAPACITANCE(1)
ꢀ
Symbolꢀ
Parameterꢀ
Conditionsꢀ
VIn = 0V
Max.ꢀ
8
Unit
pF
ꢀ cIn
Input Capacitance
Input/Output Capacitance
cout
Vout = 0V
10
pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
ACꢀTESTꢀCONDITIONS
ꢀ
ꢀ
Parameterꢀ
ꢀ
1.7V-1.95Vꢀ
(Unit)ꢀ
2.5V-3.6Vꢀ ꢀ
(Unit)
ꢀ
ꢀ
ꢀ
ꢀ Input Pulse Level
0.4V to Vdd-0.2
5 ns
0.4V to Vdd-0.3V
Input Rise and Fall Times
5ns
Input and Output Timing
and Reference Level
Vref
Vref
Output Load
See Figures 1 and 2
See Figures 1 and 2
ꢀ
ꢀ
1.7Vꢀ-ꢀ1.95Vꢀꢀ
3070
2.5Vꢀ-ꢀ3.6V
1029
ꢀ r1(Ω)
R2(Ω)ꢀ
3150
1728
ꢀ
Vref
Vtm
0.9V
1.4V
1.8V
2.8V
ACꢀTESTꢀLOADS
R1
R1
VTM
VTM
OUTPUT
OUTPUT
R2
30 pF
R2
5 pF
Including
jig and
Including
jig and
scope
scope
Figureꢀ2
Figureꢀ1
Integrated Silicon Solution, Inc. — www.issi.com
5
Rev.ꢀ A
06/28/2011
IS66WV51216DALL
IS66/67WV51216DBLL
1.7V-1.95VꢀPOWERꢀSUPPLYꢀCHARACTERISTICSꢀ(Over Operating Range)
Symbolꢀ Parameterꢀ
TestꢀConditionsꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Max.ꢀ
70ns
Unit
ꢀ ꢀ
ꢀ
I
cc
V
dd Dynamic Operating
V
dd = Max.,
Com.
Ind.
Auto.
20
25
30
mA
Supply Current
I
out = 0 mA, f = fmAX
All Inputs 0.4V
or Vdd – 0.2V
I
I
cc
1
Operating Supply
Current
V
dd = Max., CS1 = 0.2V
Com.
Ind.
4
4
mA
mA
WE = Vdd – 0.2V
CS2 = Vdd – 0.2V, f = 1mHz Auto.
V
V
10
SB1
TTL Standby Current
(TTL Inputs)
dd = Max.,
In = VIH or VIL
Com.
Ind.
0.6
0.6
1
CS1 = VIH , CS2 = VIL
,
Auto
.
f = 1 MH
z
ꢀ ꢀ
OR
ULB Control
V
dd = Max., VIn = VIH or VIL
CS1 = VIL, f = 0, UB = VIH, LB = VIH
I
SB2
CMOS Standby
Current (CMOS Inputs) CS1
V
dd = Max.,
Com.
Ind.
Auto.
100
120
150
μA
≥ V
dd – 0.2V,
CS2 ≤ 0.2V,
V
V
In
In
≥
≤
V
dd – 0.2V, or
0.2V, f = 0
ꢀ ꢀ
OR
ULB Control
Vdd = Max., CS1 = VIL, cS2=VIH
0.2V, f = 0;
VIn
≥
V
dd – 0.2V, or VIn
≤
UB / LB = Vdd – 0.2V
Note:.
1. At f = fmAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ A
06/28/2011
IS66WV51216DALL
IS66/67WV51216DBLL
2.5V-3.6VꢀPOWERꢀSUPPLYꢀCHARACTERISTICSꢀ(Over Operating Range)
Symbolꢀ Parameterꢀ
TestꢀConditionsꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Max.ꢀ
55nsꢀ
ꢀ
Unit
ꢀ ꢀ
ꢀ
I
cc
V
dd Dynamic Operating
V
dd = Max.,
Com.
Ind.
25
28
35
15
mA
Supply Current
Iout = 0 mA, f = fmAX
All Inputs 0.4V
or Vdd – 0.3V
Auto.
typ.(2)
I
I
cc
1
Operating Supply
Current
V
dd = Max., CS1 = 0.2V Com.
5
5
10
0.6
0.6
1
mA
mA
WE = Vdd – 0.2V
CS2 = Vdd – 0.2V, f = 1mHz
Ind.
A
uto
.
SB1
TTL Standby Current
(TTL Inputs)
Vdd = Max.,
Com.
Ind.
VIn = VIH or VIL
CS1 = VIH , CS2 = VIL
,
Auto
.
f = 1 MH
z
ꢀ ꢀ
OR
ULB Control
Vdd = Max., VIn = VIH or VIL
CS1 = VIL, f = 0, UB = VIH, LB = VIH
I
SB2
CMOS Standby
Current (CMOS Inputs) CS1
V
dd = Max.,
Com.
Ind.
100
130
150
75
μA
≥ Vdd – 0.2V,
CS2 ≤ 0.2V,
Auto.
V
V
In
In
≥
≤
V
dd – 0.2V, or
typ.(2)
0.2V, f = 0
ꢀ ꢀ
OR
ULB Control
Vdd = Max., CS1 = VIL, cS2=VIH
0.2V, f = 0;
VIn
≥
V
dd – 0.2V, or VIn
≤
UB / LB = Vdd – 0.2V
Note:
1. At f = fmAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, TA = 25oC and not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com
7
Rev.ꢀ A
06/28/2011
IS66WV51216DALL
IS66/67WV51216DBLL
READꢀCYCLEꢀSWITCHINGꢀCHARACTERISTICS(1)ꢀ(Over Operating Range)
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ55ꢀnsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ70ꢀnsꢀ
ꢀ Symbolꢀ
Parameterꢀ
ꢀ
ꢀ
Min.ꢀ
55
—
10
—
—
—
5
Max.ꢀ
Min.ꢀ
70
—
10
—
—
—
5
Max.ꢀ
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
trc
Read Cycle Time
—
tAA
Address Access Time
Output Hold Time
55
—
70
—
toHA
tAcS1/tAcS2
CS1/CS2 Access Time
OE Access Time
55
25
20
—
70
35
25
—
tdoe
(2)
tHzoe
OE to High-Z Output
OE to Low-Z Output
CS1/CS2 to High-Z Output
CS1/CS2 to Low-Z Output
LB, UB Access Time
LB, UB to High-Z Output
LB, UB to Low-Z Output
(2)
tLzoe
tHzcS1/tHzcS2
(2)
(2)
0
20
—
0
25
—
tLzcS1/tLzcS2
10
—
0
10
—
0
tBA
55
20
—
70
25
—
tHzB
tLzB
0
0
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to
Vdd-0.2V/0.4V to Vdd-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 100 mV from steady-state voltage. Not 100% tested.
ACꢀWAVEFORMS
READꢀCYCLEꢀNO.ꢀ1(1,2)ꢀ(Address Controlled) (CS1 = OE = VIL, cS2 = WE = VIH, UB or LB = VIL)
tRC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DQ0-D15
PREVIOUS DATA VALID
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ A
06/28/2011
IS66WV51216DALL
IS66/67WV51216DBLL
ACꢀWAVEFORMS
READꢀCYCLEꢀNO.ꢀ2(1,3) (CS1, CS2, OE, AND UB/LB Controlled)
tRC
ADDRESS
OE
tAA
t
OHA
tHZOE
t
DOE
tLZOE
CS1
tACE1/tACE2
CS2
t
LZCE1/
t
LZCE2
t
t
HZCS1/
HZCS1
LB UB
,
tBA
tHZB
t
LZB
HIGH-Z
DOUT
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1, UB, or LB = VIL. cS2=WE=VIH.
3. Address is valid prior to or coincident with CS1 LOW transition.
Integrated Silicon Solution, Inc. — www.issi.com
9
Rev.ꢀ A
06/28/2011
IS66WV51216DALL
IS66/67WV51216DBLL
WRITEꢀCYCLEꢀSWITCHINGꢀCHARACTERISTICS(1,2) (Over Operating Range)
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ55ꢀnsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ70ꢀns
ꢀ Symbolꢀ
Parameterꢀ
ꢀꢀꢀ
Min.ꢀ
55
45
45
0
Max.ꢀ
ꢀꢀMin.ꢀ Max.ꢀ
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWc
Write Cycle Time
—
70
60
60
0
—
—
—
—
—
—
tScS1/tScS2 CS1/CS2 to Write End
—
tAW
tHA
Address Setup Time to Write End
—
Address Hold from Write End
Address Setup Time
—
tSA
0
—
0
tPWB
tPWe
tSd
LB, UB Valid to End of Write
WE Pulse Width
45
—
60
(4)
45 15,000(5)
60 15,000(5)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
25
0
—
—
20
—
30
0
—
—
30
—
tHd
(3)
tHzWe
—
5
—
5
(3)
tLzWe
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to
Vdd-0.2V/0.4V to Vdd-0.3V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
3. Tested with the load in Figure 2. Transition is measured 100 mV from steady-state voltage. Not 100% tested.
4. tPWe > tHzWe + tSd when OE is LOW.
5. Refer to Avoidable Timing and Recommendations for clear definition.
ACꢀWAVEFORMS
WRITEꢀCYCLEꢀNO.ꢀ1(1,2)ꢀ(CS1 Controlled, OE = HIGH or LOW)
t
WC
ADDRESS
CS1
t
HA
tSCS1
tSCS2
CS2
tAW
t
PWE
WE
t
PWB
LB, UB
t
SA
tHZWE
t
LZWE
HIGH-Z
SD
DOUT
DIN
DATA UNDEFINED
t
t
HD
DATA-IN VALID
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at
least one of the LB and UB inputs being in the LOW state.
2. WRITE = (CS1) [ (LB) = (UB) ] (WE).
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ A
06/28/2011
IS66WV51216DALL
IS66/67WV51216DBLL
WRITEꢀCYCLEꢀNO.ꢀ2ꢀ(WE Controlled: OE is HIGH During Write Cycle)
t
WC
ADDRESS
OE
t
HA
tSCS1
CS1
tSCS2
CS2
tAW
t
PWE
WE
LB, UB
DOUT
DIN
t
SA
tHZWE
t
LZWE
HIGH-Z
SD
DATA UNDEFINED
t
t
HD
DATA-IN VALID
WRITEꢀCYCLEꢀNO.ꢀ3ꢀ(WE Controlled: OE is LOW During Write Cycle)
t
WC
ADDRESS
OE
tHA
tSCS1
tSCS2
CS1
CS2
tAW
tPWE
WE
LB, UB
DOUT
DIN
tSA
DATA UNDEFINED
tHZWE
tLZWE
HIGH-Z
tSD
DATA-IN VALID
tHD
Integrated Silicon Solution, Inc. — www.issi.com
11
Rev.ꢀ A
06/28/2011
IS66WV51216DALL
IS66/67WV51216DBLL
WRITEꢀCYCLEꢀNO.ꢀ4ꢀ(UB/LB Controlled)
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
OE
t
SA
LOW
HIGH
CS1
CS2
t
HA
SA
t
HA
t
WE
t
PWB
t
PWB
UB, LB
WORD 1
WORD 2
t
HZWE
t
LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
UB_CSWR4.eps
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ A
06/28/2011
IS66WV51216DALL
IS66/67WV51216DBLL
AVOIDABLEꢀTIMINGꢀANDꢀRECOMMENDATIONS
Figure 2a
Figure 2b
Figure 2c
Figure 3a
Integrated Silicon Solution, Inc. — www.issi.com
13
Rev.ꢀ A
06/28/2011
IS66WV51216DALL
IS66/67WV51216DBLL
AVOIDABLEꢀTIMINGꢀANDꢀRECOMMENDATIONS
Figure 3b
≥ 15us
WE
CS or
UB & LB
Address
Figure 4
Notes:
1. PSRAM uses DRAM cell which needs a REFRESH action periodically to retain the information. This REFRESH action is per-
formed internally as part of a READ cycle or when the device is not selected. A hidden REFRESH action has to be executed
by the device at least once every 15ms.
2. Figure 2a shows a timing example in which consecutive READ cycles occurs in intervals less than the tRC spec while the
device is selected for a period of 15ms. This timing should be avoided because output data from these READ cycles are not
guaranteed to be valid due to violation of the tRC spec. This timing also prohibits the device from performing a hidden RE-
FRESH action properly. Examples on how to avoid the timing in Figure 2a are shown in Figure 2b and 2c.
3. Figure 3a shows a timing example in which a single WRITE operation is maintained for a period greater than 15ms. Since a
REFRESH action cannot be performed during a WRITE operation, information stored in the device will not be retained if this
timing occurs. A WRITE operation is initiated when active LOW signals WE, CS, UB and LB are enabled (logic LOW) but any
one of these signals can be disabled (logic HIGH) to complete the WRITE operation. Figure 3b is a timing example of using
signal CS being disabled to complete the WRITE operation.
4. Since a REFRESH action cannot be performed during a WRITE operation, consecutive WRITE cycles occurring for a total
period greater than 15ms are not permitted. However, executing consecutive WRITE cycles greater than 15ms is acceptable if
either WE, CS, or both UB and LB, are disabled (logic HIGH) for a period of at least 5ns or higher and can be done once or
multiple times. An example using CS signal is shown in Figure 4
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ A
06/28/2011
Speedꢀ(ns)ꢀ
OrderꢀPartꢀNo.ꢀ
Package
Speedꢀ(ns)ꢀ
OrderꢀPartꢀNo.ꢀ
Package
Speedꢀ(ns)ꢀ
OrderꢀPartꢀNo.ꢀ
Package
IS66WV51216DALL
IS66/67WV51216DBLL
IS66WV51216DALL
IndustrialꢀRange:ꢀ-40°Cꢀtoꢀ+85°Cꢀ
VoltageꢀRange:ꢀ1.7Vꢀtoꢀ1.95Vꢀ
70
IS66WV51216DALL-70TLI
IS66WV51216DALL-70BLI
TSOP-II, Lead-free
mini BGA (6mm x 8mm), Lead-free
IS66WV51216DBLL
IndustrialꢀRange:ꢀ-40°Cꢀtoꢀ+85°Cꢀ
VoltageꢀRange:ꢀ2.5Vꢀtoꢀ3.6Vꢀ
55
IS66WV51216DBLL-55TLI
IS66WV51216DBLL-55BLI
TSOP-II, Lead-free
mini BGA (6mm x 8mm), Lead-free
70
IS66WV51216DBLL-70TLI
IS66WV51216DBLL-70BLI
TSOP-II, Lead-free
mini BGA (6mm x 8mm), Lead-free
IS67WV51216DBLL
Automotiveꢀ(A1)ꢀRange:ꢀ-40°Cꢀtoꢀ+85°Cꢀ
VoltageꢀRange:ꢀ2.5Vꢀtoꢀ3.6Vꢀ
55
IS67WV51216DBLL-55TLA1
IS67WV51216DBLL-55BLA1
TSOP-II, Lead-free
mini BGA (6mm x 8mm), Lead-free
70
IS67WV51216DBLL-70TLA1
IS67WV51216DBLL-70BLA1
TSOP-II, Lead-free
mini BGA (6mm x 8mm), Lead-free
Integrated Silicon Solution, Inc. — www.issi.com
15
Rev.ꢀ A
06/28/2011
IS66WV51216DALL
IS66/67WV51216DBLL
16
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ A
06/28/2011
IS66WV51216DALL
IS66/67WV51216DBLL
Integrated Silicon Solution, Inc. — www.issi.com
17
Rev.ꢀ A
06/28/2011
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