IS66WV51216EALL [ISSI]
Three state outputs;
| 型号： | IS66WV51216EALL |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | Three state outputs |
| 文件： | 总17页 (文件大小：620K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
performanceꢀCMOSꢀtechnology.Thisꢀhighlyꢀreliableꢀprocessꢀ
IS66WV51216EALL
IS66/67WV51216EBLL
ADVANCED INFORMATION
NOVEMBER 2013
8Mb LOW VOLTAGE,
ULTRA LOW POWER PSEUDO CMOS STATIC RAM
FEATURES
DESCRIPTION
•ꢀ High-speedꢀaccessꢀtime:ꢀꢀ
TheꢀISSIIS66WV51216EALLandIS66/67WV51216EBLL
areꢀhigh-speed,ꢀ8MꢀbitꢀstaticꢀRAMsꢀorganizedꢀasꢀ512Kꢀ
words by 16 bits. It is fabricated using ISSI'sꢀ high-
– 70ns (IS66WV51216EALL, IS66/67WV51216EBLL)
– 55ns (IS66/67WV51216EBLL)
•ꢀ CMOSꢀlowꢀpowerꢀoperation
•ꢀ Singleꢀpowerꢀsupplyꢀꢀ
coupled with innovative circuit design techniques, yields
high-performanceꢀandꢀlowꢀpowerꢀconsumptionꢀdevices.
– Vddꢀ=ꢀ1.7V-1.95Vꢀ(IS66WV51216EALL)
– Vddꢀ=ꢀ2.5V-3.6V (IS66/67WV51216EBLL)
•ꢀ Threeꢀstateꢀoutputs
When CS1ꢀisꢀHIGHꢀ(deselected)ꢀorꢀwhenꢀCS2ꢀisꢀLOꢁ
(deselected)thedeviceassumesastandbymodeatwhich
theꢀpowerꢀdissipationꢀcanꢀbeꢀreducedꢀdownꢀwithꢀCMOSꢀ
input levels.
•ꢀ Dataꢀcontrolꢀforꢀupperꢀandꢀlowerꢀbytes
•ꢀ Industrialꢀtemperatureꢀavailableꢀ
•ꢀ Lead-freeꢀavailableꢀ
Easy memory expansion is provided by using Chip Enable
andꢀOutputꢀEnableꢀinputs.ꢀTheꢀactiveꢀLOꢁꢀꢁriteꢀEnableꢀ
(WE) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
TheꢀIS66ꢁV51216EALLꢀandꢀIS66/67ꢁV51216EBLLꢀareꢀ
packagedꢀinꢀtheꢀJEDECꢀstandardꢀ48-ballꢀminiꢀBGAꢀ(6mmꢀ
xꢀ8mm)ꢀandꢀ44-PinꢀTSOPꢀ(TYPEꢀII).ꢀTheꢀdeviceꢀisꢀasloꢀ
available for die sales.
FUNCTIONAL BLOCK DIAGRAM
512K x 16
MEMORY ARRAY
A0-A18
DECODER
V
DD
GND
I/O0-I/O7
Lower Byte
I/O
DATA
COLUMN I/O
CIRCUIT
I/O8-I/O15
Upper Byte
CS2
CS1
OE
CONTROL
CIRCUIT
WE
UB
LB
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. 00A
11/22/2013
IS66WV51216EALL
IS66/67WV51216EBLL
PIN CONFIGURATIONS:
48-Ball mini BGA (6mm x 8mm)
44-Pin TSOP (Type II)
1
2
3
4
5
6
A4
A3
A2
A1
A0
CS1
I/O0
I/O1
I/O2
I/O3
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
2
3
4
5
A0
A3
A1
A4
A2
LB
OE
UB
CS2
A
B
C
D
E
F
6
7
I/O
8
CS1
I/O
0
8
9
I/O
I/O
A5
A6
I/O
1
I/O
2
9
10
10
11
12
13
14
15
16
17
18
19
20
21
22
V
DD
GND
A17
NC
A14
A12
A7
I/O
I/O
I/O
3
I/O
4
I/O
5
VDD`
11
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
VDD
GND
VDD
A16
A15
A13
A10
I/O11
I/O10
I/O9
I/O8
A18
A8
12
I/O
I/O
I/O
I/O
6
14
13
NC
A8
WE
I/O
7
15
G
H
A18
A9
A11
NC
A9
A10
A11
A17
PIN DESCRIPTIONS
A0-A18ꢀ ꢀ
I/O0-I/O15ꢀ
CS1, CS2
AddressꢀInputs
DataꢀInputs/Outputs
Chip Enable Input
OutputꢀEnableꢀInput
Write Enable Input
OEꢀꢀ
WE
LBꢀ
ꢀ
ꢀ
ꢀ
Lower-byteꢀControlꢀ(I/O0-I/O7)
Upper-byteꢀControlꢀ(I/O8-I/O15)
No Connection
UBꢀ
NC
Vdd
GNDꢀ
Power
ꢀ
Ground
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
11/22/2013
IS66WV51216EALL
IS66/67WV51216EBLL
TRUTH TABLE
I/O PIN
I/O0-I/O7 I/O8-I/O15 Vdd Current
Mode
WE CS1 CS2
OE
LB
UB
NotꢀSelectedꢀ
ꢀ
Xꢀ
Xꢀ
Hꢀ
Xꢀ
Xꢀ
Lꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
Xꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
ISB1, ISB2
ISB1, ISB2
ꢀ
ꢀ
OutputꢀDisabledꢀ
ꢀ
Hꢀ
Hꢀ
Xꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Hꢀ
Xꢀ
Lꢀ
Xꢀ
Hꢀ
Xꢀ
Lꢀ
Hꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
High-Zꢀ
Icc
Icc
Icc
ꢀ
ꢀ
Readꢀ
ꢀ
Hꢀ
Hꢀ
H
Lꢀ
Lꢀ
L
Hꢀ
Hꢀ
H
Lꢀ
Lꢀ
L
Lꢀ
Hꢀ
L
Hꢀ
Lꢀ
L
doutꢀ
High-Zꢀ
dout
High-Z
dout
dout
Icc
ꢀ
ꢀ
ꢁriteꢀ
ꢀ
Lꢀ
Lꢀ
L
Lꢀ
Lꢀ
L
Hꢀ
Hꢀ
H
Xꢀ
Xꢀ
X
Lꢀ
Hꢀ
L
Hꢀ
Lꢀ
L
dInꢀ
High-Zꢀ
dIn
High-Z
dIn
dIn
Icc
Note:
CS2ꢀinputꢀsignalꢀpinꢀisꢀonlyꢀavailableꢀforꢀ48-ballꢀminiꢀBGAꢀpackageꢀparts.ꢀCS2ꢀinputꢀisꢀinternallyꢀenabledꢀforꢀ44-pinꢀTSOP-IIꢀpack-
age parts.
OPERATING RANGE (Vdd)
IS66WV51216EALL
(70ns)
IS66WV51216EBLL
(55ns, 70ns)
IS67WV51216EBLL
(55ns, 70ns)
Range
Ambient Temperature
Industrialꢀ
–40°Cꢀtoꢀ+85°Cꢀ
1.7Vꢀ-ꢀ1.95Vꢀ
ꢀ2.5Vꢀ-ꢀ3.6Vꢀ
–
Automotive,ꢀA1ꢀ –40°Cꢀtoꢀ+85°Cꢀ
ꢀ Automotive,ꢀA2ꢀ –40°Cꢀtoꢀ+105°Cꢀ
–ꢀ
–ꢀ
–ꢀ
–ꢀ
2.5Vꢀ-ꢀ3.6V
2.5Vꢀ-ꢀ3.6V
POWER-UP INITIALIzATION
IS66ꢁV51216EALL/EBLLꢀandꢀIS67ꢁV51216EBLLꢀincludeꢀanꢀon-chipꢀvoltageꢀsensorꢀusedꢀtoꢀlaunchꢀtheꢀpower-upꢀinitializationꢀprocess.ꢀ
ꢁhenꢀVDDꢀreachesꢀaꢀstableꢀlevelꢀatꢀorꢀaboveꢀtheꢀVDDꢀ(min)ꢀ,ꢀtheꢀdeviceꢀwillꢀrequireꢀ50μsꢀtoꢀcompleteꢀꢀitsꢀself-initializationꢀprocess.ꢀ
Duringꢀtheꢀinitializationꢀperiod,ꢀCSꢀshouldꢀremainꢀHIGH.ꢀꢁhenꢀinitializationꢀisꢀcomplete,ꢀtheꢀdeviceꢀisꢀreadyꢀforꢀnormalꢀoperation.
≥ 50us
VDD (min)
VDD
Device Initialization
Device for Normal Operation
0V
Integrated Silicon Solution, Inc. — www.issi.com
3
Rev. 00A
11/22/2013
IS66WV51216EALL
IS66/67WV51216EBLL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VtErm
tBIAS
Vdd
Parameter
Value
–0.2ꢀtoꢀVdd+0.3ꢀ
–40ꢀtoꢀ+85ꢀ
–0.2ꢀtoꢀ+3.8ꢀ
–65ꢀtoꢀ+150ꢀ
1.0ꢀ
Unit
V
TerminalꢀVoltageꢀwithꢀRespectꢀtoꢀGNDꢀ
TemperatureꢀUnderꢀBiasꢀ
Vdd RelatedꢀtoꢀGNDꢀ
StorageꢀTemperatureꢀ
PowerꢀDissipationꢀ
°C
V
tStg
°C
ꢁ
Pt
Note:
1.ꢀꢀStressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀ
device.ꢀThisꢀisꢀaꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀaboveꢀ
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS (OverꢀOperatingꢀRange)
Vdd = 2.5V-3.6V
Symbol Parameter
Test Conditions
Vdd
Min.
2.2ꢀ
—ꢀ
Max.
—ꢀ
Unit
V
VoH
VoL
VIH
VIL
ILI
OutputꢀHIGHꢀVoltageꢀ
IoH = -1ꢀmAꢀ
2.5-3.6Vꢀ
2.5-3.6Vꢀ
2.5-3.6Vꢀ
2.5-3.6Vꢀ
OutputꢀLOꢁꢀVoltageꢀ
InputꢀHIGHꢀVoltage(1)ꢀ
InputꢀLOꢁꢀVoltage(1)
InputꢀLeakageꢀ
IoL = 2.1ꢀmAꢀ
0.4ꢀ
V
ꢀ
2.2ꢀ
–0.2ꢀ
–1ꢀ
Vdd + 0.3
0.6ꢀ
V
ꢀ
V
GNDꢀ≤ VIn ≤ Vdd
1ꢀ
μA
μA
ILo
OutputꢀLeakage
GNDꢀ≤ Vout ≤ Vdd, OutputsꢀDisabledꢀ
–1ꢀ
1ꢀ
Notes:
1. VILL (min.) = –2.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max.) = Vddꢀ+ꢀ2.0VꢀACꢀ(pulseꢀwidthꢀ<ꢀ10ns).ꢀNotꢀ100%ꢀtested.
DC ELECTRICAL CHARACTERISTICS (OverꢀOperatingꢀRange)
Vdd = 1.7V-1.95V
Symbol Parameter
Test Conditions
Vdd
Min.
1.4ꢀ
—ꢀ
Max.
—ꢀ
Unit
V
VoH
VoL
VIH
VIL
ILI
OutputꢀHIGHꢀVoltageꢀ
IoH = -0.1ꢀmAꢀ
1.7-1.95Vꢀ
1.7-1.95Vꢀ
1.7-1.95Vꢀ
1.7-1.95Vꢀ
OutputꢀLOꢁꢀVoltageꢀ
InputꢀHIGHꢀVoltage(1)ꢀ
InputꢀLOꢁꢀVoltage(1)
InputꢀLeakageꢀ
IoL = 0.1ꢀmAꢀ
0.2ꢀ
V
ꢀ
1.4ꢀ
–0.2ꢀ
–1ꢀ
Vdd + 0.2
0.4ꢀ
V
ꢀ
V
GNDꢀ≤ VIn ≤ Vdd
1ꢀ
μA
μA
ILo
OutputꢀLeakage
GNDꢀ≤ Vout ≤ Vdd, OutputsꢀDisabledꢀ
–1ꢀ
1ꢀ
Notes:
1. VILL (min.) = –1.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max.) = Vddꢀ+ꢀ1.0VꢀACꢀ(pulseꢀwidthꢀ<ꢀ10ns).ꢀNotꢀ100%ꢀtested.
4ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
11/22/2013
IS66WV51216EALL
IS66/67WV51216EBLL
CAPACITANCE(1)
Symbol
cIn
Parameter
Conditions
VIn = 0V
Max.
8ꢀ
Unit
pF
Input Capacitance
Input/OutputꢀCapacitanceꢀ
coutꢀ
Vout = 0V
10ꢀ
pF
Note:
1.ꢀꢀTestedꢀinitiallyꢀandꢀafterꢀanyꢀdesignꢀorꢀprocessꢀchangesꢀthatꢀmayꢀaffectꢀtheseꢀparameters.
AC TEST CONDITIONS
Parameter
1.7V-1.95V
(Unit)
2.5V-3.6V
(Unit)
0.4VꢀtoꢀVdd-0.3V
5ns
InputꢀPulseꢀLevelꢀ
0.4VꢀtoꢀVdd-0.2ꢀ
5ꢀnsꢀ
ꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
ꢀ
ꢀ
InputꢀandꢀOutputꢀTimingꢀ
andꢀReferenceꢀLevel
VrEf
VrEf
ꢀ
OutputꢀLoadꢀ
SeeꢀFiguresꢀ1ꢀandꢀ2ꢀ
SeeꢀFiguresꢀ1ꢀandꢀ2
1.7V - 1.95V
2.5V - 3.6V
1029
r1(Ω)
R2(Ω)ꢀ
VrEf
3070ꢀ
3150ꢀ
0.9V
ꢀ
1728
ꢀ
1.4V
Vtmꢀ
1.8Vꢀ
2.8V
AC TEST LOADS
R1
R1
VTM
VTM
OUTPUT
OUTPUT
R2
30 pF
R2
5 pF
Including
jig and
Including
jig and
scope
scope
Figure 2
Figure 1
Integrated Silicon Solution, Inc. — www.issi.com
5
Rev. 00A
11/22/2013
IS66WV51216EALL
IS66/67WV51216EBLL
1.7V-1.95V POWER SUPPLY CHARACTERISTICS (OverꢀOperatingꢀRange)
Symbol Parameter
Test Conditions
Max.
70ns
Unit
I
cc
cc
V
ddꢀDynamicꢀOperatingꢀ
V
dd = Max.,ꢀ
Com.ꢀ
Ind.
Auto.ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
20ꢀ
25
30ꢀ
mA
ꢀ
Supply Current
ꢀ
Iout = 0 mA, f = fmAX
AllꢀInputsꢀꢀ0.4Vꢀꢀꢀ
or Vdd – 0.2V
ꢀ ꢀ
ꢀ
ꢀꢀ
I
1
OperatingꢀSupplyꢀ
Current
Vdd = Max., CS1 = 0.2Vꢀ
Com.ꢀ
Ind.ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
4ꢀ
4
mA
WE = Vdd – 0.2V
CS2 = Vdd – 0.2V, f = 1mHz Auto.
10
I
ꢀ ꢀ
SB1
TTLꢀStandbyꢀCurrentꢀ
(TTLꢀInputs)ꢀ
V
V
dd = Max.,
In = VIH or VIL
Com.
Ind.
0.6
0.6
1
mA
CS1 = VIH , CS2 = VIL
,
Auto
.
fꢀ=ꢀ1ꢀMH
z
I
ꢀ ꢀ
SB2ꢀ
CMOSꢀStandbyꢀ
Currentꢀ(CMOSꢀInputs)ꢀ CS1
V
dd = Max.,ꢀ
dd – 0.2V,
Com.
Ind.
Auto.
100
120
150
μA
≥ V
CS2 ≤ 0.2V,
V
V
In
In
≥
≤
V
dd – 0.2V, or
0.2V, f = 0
Note:.
1. At f = fmAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
11/22/2013
IS66WV51216EALL
IS66/67WV51216EBLL
2.5V-3.6V POWER SUPPLY CHARACTERISTICS (OverꢀOperatingꢀRange)
Symbol Parameter
Test Conditions
Max.
55ns
Unit
I
I
cc
cc
V
dd DynamicꢀOperatingꢀ
V
dd = Max.,ꢀ
Com.ꢀ
Ind.ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
25ꢀ
28ꢀ
35
ꢀ
ꢀ
mA
ꢀ
Supply Current
I
out = 0 mA, f = fmAX
ꢀꢀ
All Inputs 0.4V
or Vdd – 0.3V
Auto.
typ.(2)
15
1
OperatingꢀSupplyꢀ
Current
Vdd = Max., CS1 = 0.2V Com.
5
5
10
0.6
0.6
1
mA
mA
WE = Vdd – 0.2V
CS2 = Vdd – 0.2V, f = 1mHz
Ind.
A
uto
.
I
ꢀ ꢀ
SB1
TTLꢀStandbyꢀCurrentꢀ
(TTLꢀInputs)ꢀ
Vdd = Max.,
Com.
Ind.
VIn = VIH or VIL
CS1 = VIH , CS2 = VIL
,
Auto
.
fꢀ=ꢀ1ꢀMH
z
I
ꢀ ꢀ
SB2ꢀ
CMOSꢀStandbyꢀ
Currentꢀ(CMOSꢀInputs)ꢀ CS1
V
dd = Max.,ꢀ
Com.
Ind.
100
130
150
75
μA
≥ Vdd – 0.2V,
CS2 ≤ 0.2V,
Auto.
V
V
In
In
≥
≤
V
dd – 0.2V, or
typ.(2)
0.2V, f = 0
Note:
1. At f = fmAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2.ꢀꢀTypicalꢀvaluesꢀareꢀmeasuredꢀatꢀVddꢀ=ꢀ3.0V,ꢀTA = 25oC and not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com
7
Rev. 00A
11/22/2013
IS66WV51216EALL
IS66/67WV51216EBLL
READ CYCLE SWITCHING CHARACTERISTICS(1) (OverꢀOperatingꢀRange)
55 ns
70 ns
Symbol
trcꢀ
Parameter
Min.
55ꢀ
—ꢀ
10ꢀ
—ꢀ
—ꢀ
—ꢀ
5ꢀ
Max.
15,000ꢀ
55ꢀ
Min.
Max.
15,000ꢀ
70ꢀ
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ReadꢀCycleꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
70ꢀ
—ꢀ
10ꢀ
—ꢀ
—ꢀ
—ꢀ
5ꢀ
tAAꢀ
AddressꢀAccessꢀTimeꢀ
OutputꢀHoldꢀTimeꢀ
toHAꢀ
—ꢀ
—ꢀ
tAcS1/tAcS2
tdoE
CS1/CS2ꢀAccessꢀTimeꢀ
OEꢀAccessꢀTimeꢀ
55ꢀ
70ꢀ
25ꢀ
35ꢀ
(2)
tHzoE
OEꢀtoꢀHigh-ZꢀOutputꢀ
OEꢀtoꢀLow-ZꢀOutputꢀ
CS1/CS2ꢀtoꢀHigh-ZꢀOutputꢀ
CS1/CS2ꢀtoꢀLow-ZꢀOutputꢀ
LB, UBꢀAccessꢀTimeꢀ
LB, UBꢀtoꢀHigh-ZꢀOutputꢀ
LB, UBꢀtoꢀLow-ZꢀOutputꢀ
20ꢀ
25ꢀ
(2)
tLzoE
—ꢀ
—ꢀ
(2)
tHzcS1/tHzcS2
0ꢀ
20ꢀ
0ꢀ
25ꢀ
(2)
tLzcS1/tLzcS2
10ꢀ
—ꢀ
0ꢀ
—ꢀ
10ꢀ
—ꢀ
0ꢀ
—ꢀ
tBA
55ꢀ
70ꢀ
tHzB
20ꢀ
25ꢀ
tLzB
0ꢀ
—ꢀ
0ꢀ
—ꢀ
Notes:
1.ꢀ Testꢀconditionsꢀassumeꢀsignalꢀtransitionꢀtimesꢀofꢀ5ꢀnsꢀorꢀless,ꢀtimingꢀreferenceꢀlevelsꢀofꢀ0.9V/1.5V,ꢀinputꢀpulseꢀlevelsꢀofꢀ0.4ꢀtoꢀ
Vdd-0.2V/0.4VꢀtoꢀVdd-0.3VꢀandꢀoutputꢀloadingꢀspecifiedꢀinꢀFigureꢀ1.
2.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ2.ꢀTransitionꢀisꢀmeasuredꢀ±100ꢀmVꢀfromꢀsteady-stateꢀvoltage.ꢀNotꢀ100%ꢀtested.
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, cS2 = WE = VIH, UB or LB = VIL)
tRC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DQ0-D15
PREVIOUS DATA VALID
8ꢀ
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IS66WV51216EALL
IS66/67WV51216EBLL
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, CS2, OE,ꢀANDꢀUB/LB Controlled)
tRC
ADDRESS
OE
tAA
t
OHA
tHZOE
t
DOE
tLZOE
CS1
tACE1/tACE2
CS2
t
LZCE1/
t
LZCE2
t
t
HZCS1/
HZCS1
LB UB
,
tBA
tHZB
t
LZB
HIGH-Z
DOUT
DATA VALID
Notes:
1. WEꢀisꢀHIGHꢀforꢀaꢀReadꢀCycle.
2.ꢀ Theꢀdeviceꢀisꢀcontinuouslyꢀselected.ꢀOE, CS1, UB, or LB = VIL. cS2=WE=VIH.
3. Address is valid prior to or coincident with CS1ꢀLOꢁꢀtransition.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
9
Rev. 00A
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ꢀꢀꢀꢀꢀ0ꢀ
ꢀꢀꢀꢀꢀ—ꢀ
ꢀꢀꢀꢀꢀ5ꢀ
IS66WV51216EALL
IS66/67WV51216EBLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2)ꢀ(OverꢀOperatingꢀRange)
55 ns
70 ns
Symbol
Parameter
Min.
Max.
15,000ꢀ
—ꢀ
Min. Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWcꢀ
ꢁriteꢀCycleꢀTimeꢀ
ꢀꢀꢀꢀꢀ
ꢀꢀꢀꢀ
55ꢀ
45ꢀ
45ꢀ
0ꢀ
ꢀꢀꢀ70ꢀ 15,000ꢀ
tScS1/tScS2 CS1/CS2ꢀtoꢀꢁriteꢀEndꢀ
ꢀꢀꢀ60ꢀ
ꢀꢀꢀ60ꢀ
ꢀꢀꢀꢀꢀ0ꢀ
ꢀꢀꢀꢀꢀ0ꢀ
ꢀꢀꢀ60ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
tAWꢀ
tHAꢀ
tSAꢀ
AddressꢀSetupꢀTimeꢀtoꢀꢁriteꢀEndꢀꢀ ꢀꢀꢀꢀ
—ꢀ
AddressꢀHoldꢀfromꢀꢁriteꢀEndꢀ
AddressꢀSetupꢀTimeꢀ
ꢀꢀꢀꢀ
ꢀꢀꢀꢀ
ꢀꢀꢀꢀ
ꢀꢀꢀꢀ
ꢀꢀꢀꢀ
ꢀꢀꢀꢀ
ꢀꢀꢀꢀ
ꢀꢀꢀꢀꢀ
—ꢀ
0ꢀ
—ꢀ
tPWB
tPWE
tSdꢀ
tHdꢀ
LB, UBꢀValidꢀtoꢀEndꢀofꢀꢁriteꢀ
WEꢀPulseꢀꢁidthꢀ
45ꢀ
—ꢀ
(4)
45ꢀ 15,000(5)
60 15,000(5)
DataꢀSetupꢀtoꢀꢁriteꢀEndꢀ
DataꢀHoldꢀfromꢀꢁriteꢀEndꢀ
WEꢀLOꢁꢀtoꢀHigh-ZꢀOutputꢀ
WEꢀHIGHꢀtoꢀLow-ZꢀOutputꢀ
25ꢀ
0ꢀ
—ꢀ
—ꢀ
20ꢀ
—ꢀ
ꢀꢀꢀ30ꢀ
—ꢀ
—ꢀ
30ꢀ
—ꢀ
(3)
tHzWE
—ꢀ
5ꢀ
(3)
tLzWE
Notes:
1.ꢀ Testꢀconditionsꢀassumeꢀsignalꢀtransitionꢀtimesꢀofꢀ5ꢀnsꢀorꢀless,ꢀtimingꢀreferenceꢀlevelsꢀofꢀ0.9V/1.5V,ꢀinputꢀpulseꢀlevelsꢀofꢀꢀ0.4ꢀtoꢀ
Vdd-0.2V/0.4VꢀtoꢀVdd-0.3VꢀandꢀoutputꢀloadingꢀspecifiedꢀinꢀFigureꢀ1.
2. Theꢀinternalꢀwriteꢀtimeꢀisꢀdefinedꢀbyꢀtheꢀoverlapꢀof CS1 LOꢁ,ꢀCS2ꢀHIGHꢀandꢀUB or LB, and WEꢀLOꢁ.ꢀAllꢀsignalsꢀmustꢀbeꢀinꢀvalidꢀstatesꢀtoꢀinitiateꢀaꢀꢁrite,ꢀbutꢀ
any one can go inactive to terminateꢀtheꢀꢁrite.ꢀTheꢀDataꢀInputꢀSetupꢀandꢀHoldꢀtimingꢀareꢀreferencedꢀtoꢀtheꢀrisingꢀorꢀfallingꢀedgeꢀofꢀtheꢀsignalꢀthatꢀterminatesꢀtheꢀ
write.
3.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ2.ꢀTransitionꢀisꢀmeasuredꢀ±100ꢀmVꢀfromꢀsteady-stateꢀvoltage.ꢀNotꢀ100%ꢀtested.
4.ꢀꢀꢀtPWE > tHzWE + tSd when OEꢀisꢀLOꢁ.
5.ꢀꢀReferꢀtoꢀAvoidableꢀTimingꢀandꢀRecommendationsꢀforꢀclearꢀdefinition.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OEꢀ=ꢀHIGHꢀorꢀLOꢁ)
t
WC
ADDRESS
CS1
t
HA
tSCS1
tSCS2
CS2
tAW
t
PWE
WE
t
PWB
LB, UB
t
SA
tHZWE
t
LZWE
HIGH-Z
SD
DOUT
DIN
DATA UNDEFINED
t
t
HD
DATA-IN VALID
Notes:
1.ꢀ ꢁRITEꢀisꢀanꢀinternallyꢀgeneratedꢀsignalꢀassertedꢀduringꢀanꢀoverlapꢀofꢀtheꢀLOꢁꢀstatesꢀonꢀtheꢀCS1 , CS2 and WE inputs and at
least one of the LB and UBꢀinputsꢀbeingꢀinꢀtheꢀLOꢁꢀstate.
2.ꢀ ꢁRITEꢀ=ꢀ(CS1) [ (LB) = (UB) ] (WE).
10
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IS66WV51216EALL
IS66/67WV51216EBLL
WRITE CYCLE NO. 2 (WE Controlled: OEꢀisꢀHIGHꢀDuringꢀꢁriteꢀCycle)
t
WC
ADDRESS
OE
t
HA
tSCS1
CS1
tSCS2
CS2
tAW
t
PWE
WE
LB, UB
DOUT
DIN
t
SA
tHZWE
t
LZWE
HIGH-Z
SD
DATA UNDEFINED
t
t
HD
DATA-IN VALID
WRITE CYCLE NO. 3 (WE Controlled: OEꢀisꢀLOꢁꢀDuringꢀꢁriteꢀCycle)
t
WC
ADDRESS
OE
tHA
tSCS1
tSCS2
CS1
CS2
tAW
tPWE
WE
LB, UB
DOUT
DIN
tSA
DATA UNDEFINED
tHZWE
tLZWE
HIGH-Z
tSD
DATA-IN VALID
tHD
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IS66WV51216EALL
IS66/67WV51216EBLL
WRITE CYCLE NO. 4 (UB/LB Controlled)
t
WC
t
WC
ADDRESS 1
ADDRESS 2
ADDRESS
OE
t
SA
LOW
HIGH
CS1
CS2
t
HA
SA
t
HA
t
WE
t
PWB
t
PWB
UB, LB
WORD 1
WORD 2
t
HZWE
t
LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t
HD
t
HD
t
SD
t
SD
DATAIN
VALID
DATAIN
VALID
DIN
UB_CSWR4.eps
12
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Rev. 00A
11/22/2013
IS66WV51216EALL
IS66/67WV51216EBLL
AVOIDABLE TIMING AND RECOMMENDATIONS
Figure 3a
Figure 3b
Figure 3c
Figure 4a
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Rev. 00A
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IS66WV51216EALL
IS66/67WV51216EBLL
AVOIDABLE TIMING AND RECOMMENDATIONS
Figure 4b
≥ 15us
WE
CS or
UB & LB
Address
Figure 5
Notes:
1.ꢀ PSRAMꢀusesꢀDRAMꢀcellꢀwhichꢀneedsꢀaꢀREFRESHꢀactionꢀperiodicallyꢀtoꢀretainꢀtheꢀinformation.ꢀThisꢀREFRESHꢀactionꢀisꢀper-
formedꢀinternallyꢀasꢀpartꢀofꢀaꢀREADꢀcycleꢀorꢀwhenꢀtheꢀdeviceꢀisꢀnotꢀselected.ꢀAꢀhiddenꢀREFRESHꢀactionꢀhasꢀtoꢀbeꢀexecutedꢀ
by the device at least once every 15ms.
2.ꢀ Figureꢀ3aꢀshowsꢀaꢀtimingꢀexampleꢀinꢀwhichꢀconsecutiveꢀREADꢀcyclesꢀoccursꢀinꢀintervalsꢀlessꢀthanꢀtheꢀtRCꢀspecꢀwhileꢀtheꢀ
device is selected for a period of 15ms.ꢀThisꢀtimingꢀshouldꢀbeꢀavoidedꢀbecauseꢀoutputꢀdataꢀfromꢀtheseꢀREADꢀcyclesꢀareꢀnotꢀ
guaranteedꢀtoꢀbeꢀvalidꢀdueꢀtoꢀviolationꢀofꢀtheꢀtRCꢀspec.ꢀThisꢀtimingꢀalsoꢀprohibitsꢀtheꢀdeviceꢀfromꢀperformingꢀaꢀhiddenꢀRE-
FRESHꢀactionꢀproperly.ꢀExamplesꢀonꢀhowꢀtoꢀavoidꢀtheꢀtimingꢀinꢀFigureꢀ3aꢀareꢀshownꢀinꢀFigureꢀ3bꢀandꢀ3c.ꢀ
3.ꢀ Figureꢀ4aꢀshowsꢀaꢀtimingꢀexampleꢀinꢀwhichꢀaꢀsingleꢀꢁRITEꢀoperationꢀisꢀmaintainedꢀforꢀaꢀperiodꢀgreaterꢀthanꢀ15ms. Since a
REFRESHꢀactionꢀcannotꢀbeꢀperformedꢀduringꢀaꢀꢁRITEꢀoperation,ꢀinformationꢀstoredꢀinꢀtheꢀdeviceꢀwillꢀnotꢀbeꢀretainedꢀifꢀthisꢀ
timingꢀoccurs.ꢀAꢀꢁRITEꢀoperationꢀisꢀinitiatedꢀwhenꢀactiveꢀLOꢁꢀsignalsꢀWE, CS, UB and LBꢀareꢀenabledꢀ(logicꢀLOꢁ)ꢀbutꢀanyꢀ
oneꢀofꢀtheseꢀsignalsꢀcanꢀbeꢀdisabledꢀ(logicꢀHIGH)ꢀtoꢀcompleteꢀtheꢀꢁRITEꢀoperation.ꢀFigureꢀ4bꢀisꢀaꢀtimingꢀexampleꢀofꢀusingꢀ
signal CSꢀbeingꢀdisabledꢀtoꢀcompleteꢀtheꢀꢁRITEꢀoperation.
4.ꢀ SinceꢀaꢀREFRESHꢀactionꢀcannotꢀbeꢀperformedꢀduringꢀaꢀꢁRITEꢀoperation,ꢀconsecutiveꢀꢁRITEꢀcyclesꢀoccurringꢀforꢀaꢀtotalꢀ
period greater than 15msꢀareꢀnotꢀpermitted.ꢀHowever,ꢀexecutingꢀconsecutiveꢀꢁRITEꢀcyclesꢀgreaterꢀthanꢀ15ms is acceptable if
either WE, CS, or both UB and LB,ꢀareꢀdisabledꢀ(logicꢀHIGH)ꢀforꢀaꢀperiodꢀofꢀatꢀleastꢀ5nsꢀorꢀhigherꢀandꢀcanꢀbeꢀdoneꢀonceꢀorꢀ
multiple times. An example using CSꢀsignalꢀisꢀshownꢀinꢀFigureꢀ5.
14
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Rev. 00A
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IS66WV51216EALL
IS66/67WV51216EBLL
IS66WV51216EALL
Industrial Range: -40°C to +85°C
Voltage Range: 1.7V to 1.95V
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
70ꢀ
ꢀ
IS66ꢁV51216EALL-70TLIꢀ
IS66ꢁV51216EALL-70BLIꢀ
TSOP-II,ꢀLead-freeꢀ
miniꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-freeꢀ
IS66WV51216EBLL
Industrial Range: -40°C to +85°C
Voltage Range: 2.5V to 3.6V
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
55ꢀ
ꢀ
IS66ꢁV51216EBLL-55TLIꢀ
IS66ꢁV51216EBLL-55BLIꢀ
TSOP-II,ꢀLead-freeꢀ
miniꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-free
ꢀ
ꢀ
70ꢀ
ꢀ
IS66ꢁV51216EBLL-70TLIꢀ
IS66ꢁV51216EBLL-70BLIꢀ
TSOP-II,ꢀLead-freeꢀ
miniꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-freeꢀ
IS67WV51216EBLL
Automotive (A1) Range: -40°C to +85°C
Voltage Range: 2.5V to 3.6V
Speed (ns)
Order Part No.
Package
ꢀ
ꢀ
55ꢀ
ꢀ
IS67ꢁV51216EBLL-55TLA1ꢀ TSOP-II,ꢀLead-freeꢀ
IS67ꢁV51216EBLL-55BLA1ꢀ miniꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-free
ꢀ
ꢀ
70ꢀ
ꢀ
IS67ꢁV51216EBLL-70TLA1ꢀ TSOP-II,ꢀLead-freeꢀ
IS67ꢁV51216EBLL-70BLA1ꢀ miniꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀLead-freeꢀ
PleaseꢀcontactꢀISSIꢀatꢀSRAM@issi.comꢀifꢀyouꢀneedꢀ-40°Cꢀtoꢀ+105°Cꢀproduct.
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IS66/67WV51216EBLL
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