IS66WV51216EBLL-55TLI-TR [ISSI]
IC PSRAM 8MBIT 55NS 44TSOP;
| 型号： | IS66WV51216EBLL-55TLI-TR |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | IC PSRAM 8MBIT 55NS 44TSOP 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总16页 (文件大小：606K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS66WV51216EALL
IS66/67WV51216EBLL
OCTOBER 2015
8Mb LOW VOLTAGE,
ULTRA LOW POWER PSEUDO CMOS STATIC RAM
DESCRIPTION
Features
The ISSI IS66WV51216EALL and IS66/67WV51216EBLL are
high-speed,8M bit static RAMs organized as 512K words by
16 bits. It is fabricated using ISSI’s high performance CMOS
technology.
High-Speed access time :
- 70ns ( IS66WV51216EALL )
- 60ns (IS66/67WV51216EBLL )
CMOS Lower Power Operation
This highly reliable process coupled with innovative circuit
design techniques, yields high-performance and low power
consumption devices.
Single Power Supply
- VDD =1.7V~1.95V( IS66WV51216EALL )
- VDD =2.5V~3.6V (IS66/67WV51216EBLL )
Three State Outputs
Data Control for Upper and Lower bytes
Lead-free Available
When CS1# is HIGH (deselected) or when CS2 is LOW
(deselected), the device assumes a standby mode at which
the power dissipation can be reduced down with CMOS input
levels.
Easy memory expansion is provided by using Chip Enable and
Output Enable inputs. The active LOW Write Enable (WE#)
controls both writing and reading of the memory. A data byte
allows Upper Byte (UB#) and Lower Byte (LB#) access.
The IS66WV51216 EALL and IS66/67WV51216EBLL are
packaged in the JEDEC standard 48-ball mini BGA
(6mm x 8mm) and 44-Pin TSOP(TYPE-II). The device is also
available for die sales.
FUNCTIONAL BLOCK DIAGRAM
Address
A0~A18
Decode Logic
512K X 16
DRAM
VDD
Memory Array
GND
I/O0-I/O7
COLUMN
I/O
Lower Byte
I/O DATA
CIRCUIT
I/O8-I/O15
Upper Byte
CS2
CS1#
OE#
WE#
Control
Logic
UB#
LB#
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assu
mes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specificatio
n before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected
to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution,
Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
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Rev. B | 10/14/2015
IS66WV51216EALL
IS66/67WV51216EBLL
PIN CONFIGURATIONS
48-Ball miniBGA (6mm x 8mm) Ball Assignment
44-pin TSOP (Type II)
1
2
3
4
5
6
LB#
I/Q8
I/Q9
GND
VDD
I/Q14
I/Q15
A18
OE#
UB#
I/Q10
IQ11
IQ12
I/Q13
NC
A0
A3
A1
A4
A2
CS2
I/Q0
IQ2
A5
A6
44
43
42
41
A4
A3
1
2
A
B
C
D
E
F
A7
OE#
UB#
A2
A1
3
4
5
6
7
8
CS1#
I/Q1
I/Q3
I/Q4
I/Q5
WE#
A11
40
39
38
37
36
35
34
33
32
31
30
29
A0
LB#
CS1#
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
A5
A6
I/O15
I/O14
I/O13
I/O12
GND
9
A17
NC
A7
VDD
GND
I/Q6
I/Q7
NC
10
11
12
13
14
15
VDD
A16
A15
A13
A10
I/O11
I/O10
I/O9
A14
A12
A9
I/O8
16
17
18
I/O7
WE#
A16
A15
A14
A13
A12
28
27
26
25
24
23
A18
A8
A9
A10
A11
G
H
19
20
21
22
A8
A17
PIN DESCRIPTIONS
Symbol
Type
Input
Description
A0~A18
Address Inputs
I/Q0~I/Q15
Input /
Output
Data Inputs/Outputs
CS1#, CS2
OE#
Input
Input
Input
Input
Input
Chip Enable
Output Enable
Write Enable
WE#
UB#
Upper Byte select
Lower Byte select
LB#
VDD
Power Supply Power
Power Supply Ground
GND
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Rev. B | 10/14/2015
IS66WV51216EALL
IS66/67WV51216EBLL
POWER UP INITIALIZATION
IS66WV51216EALL and IS66/67WV51216EBLL include an on-chip voltage sensor used to launch the power-up
initialization process. When VDD reaches a stable level at or above the VDD (min) the device will require 50μs
to complete its self-initialization process. During the initialization period, CS1# should remain HIGH. When initialize-
ation is complete, the device is ready for normal operation.
50 us
VDD( min)
VDD
Device Initialization
Device for Normal Operation
0V
TRUTH TABLE
I/O0 –
I/O7
I/O8 –
I/O15
VDD Current
WE#
CS1#
CS2
OE#
LB#
UB#
Mode
SB1 SB2
I
I
,I
Not
Selected
X
X
H
X
X
L
X
X
X
X
H
X
High-Z
High-Z
High-Z
High-Z
SB1 SB2
,I
Output
Disabled
H
H
L
L
H
H
H
H
L
X
X
L
High-Z
High-Z
High-Z
High-Z
CC
CC
I
I
CC
OUT
I
I
I
High-Z
D
H
H
H
L
L
L
H
H
H
L
L
L
L
H
L
H
L
L
OUT
High-Z
CC
CC
D
OUT
Read
Write
OUT
D
D
CC
I
CC
I
CC
I
L
L
L
L
L
L
H
H
H
X
X
X
L
H
L
H
L
L
Din
High-Z
Din
High-Z
Din
Din
Notes:
CS2 input signal pin is only available for 48-ball mini BGA package part. CS2 input is internally enabled for
44-pin TSOP II package part.
OPERATING RANGE (VDD)
Range Ambient Temperature
IS66WV51216EALL
(70ns)
IS66WV51216EBLL
(55ns, 70ns)
IS66WV51216EBLL
(55ns, 70ns)
Industrial
1.7V – 1.95V
2.5V – 3.6V
–
–40°C to +85°C
–40°C to +85°C
–40°C to +105°C
Automotive , A1
Automotive , A2
–
–
–
–
2.5V – 3.6V
2.5V – 3.6V
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Rev. B | 10/14/2015
IS66WV51216EALL
IS66/67WV51216EBLL
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
-0.2 to VDD + 0.3
-40 to +85
-0.2 to +3.8
-65 to +150
1.0
Unit
V
VTERM
TBIAS
VDD
Terminal Voltage with Respect to GND
Temperature Under BIAS
VDD Related to GND
°C
V
TSTG
PT
Storage Temperature
°C
W
Power Dissipation
Notes:
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only,
and functional operation of the device at these or any other conditions above those indicated in this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 2.5V-3.6V (IS66/67WV51216EBLL)
Symbol Parameter
Test
VDD
Min.
Max.
Unit
Conditions
2.2
—
—
0.4
VOH
VOL
VIH
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage(1)
IoH = -1 mA
IoL = 2.1 mA
2.5-3.6V
2.5-3.6V
2.5-3.6V
V
V
V
2.2
VDD + 0.3
–0.2
–1
0.6
1
VIL
ILI
Input LOW Voltage(1)
Input Leakage
2.5-3.6V
V
μA
μA
GND ≤ VIN ≤ VDD
–1
1
ILo
GND ≤ VOUT ≤ VDD,
Output Leakage
Outputs Disabled
Notes:
1. VILL (min.) = –2.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max.) = VDD + 2.0V AC (pulse width < 10ns). Not 100% test
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 1.7V-1.95V(IS66WV51216EALL)
Symbol Parameter
Test
VDD
Min.
Max
.
Unit
Conditions
VOH
VOL
VIH
VIL
Output HIGH Voltage
IOH = -0.1 mA
IOL = 0.1 mA
1.7-1.95V
1.7-1.95V
1.7-1.95V
1.7-1.95V
1.4
—
1.4
–0.2
—
0.2
VDD + 0.2
0.4
V
V
V
V
Output LOw Voltage
Input HIGH Voltage(1)
Input LOw Voltage(1)
ILI
Input Leakage
GND ≤ VIN ≤ VDD
–1
–1
1
1
μA
μA
ILo
Output Leakage
GND ≤ VOUT ≤ VDD,
Outputs Disabled
Notes:
1. VILL (min.) = –1.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max.) = VDD + 1.0V AC (pulse width < 10ns). Not 100% test
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Rev. B | 10/14/2015
IS66WV51216EALL
IS66/67WV51216EBLL
CAPACITANCE
Symbol
CIN
Description
Conditions
VIN = 0V
MIN
MAX
8
Unit
pF
Input Capacitance
-
-
Vout = 0V
CIO
Input/Output Capacitance (DQ)
10
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
ACTEST CONDITIONS
1.7V – 1.95V
2.5V – 3.6V
Parameter
( Unit )
( Unit )
0.4V to VDD – 0.2V
0.4V to VDD – 0.3V
Input Pulse Level
Input Rise and Fall
Time
5ns
5ns
Input and Output
Timing and
Reference Level
VREF
VREF
See Figures 1 and 2
See Figures 1 and 2
Output Load
Symbol
R1(Ω)
R2(Ω)
VREF
1.7V – 1.95V
2.5V – 3.6V
3070
3150
0.9V
1.8V
1029
1728
1.4V
2.8V
VTM
ACTEST LOADS
R1
R1
VTM
VTM
OUTPUT
OUTPUT
R2
R2
5 pF
Including
Jig and
scope
30 pF
Including
Jig and
scope
Figure2
Figure1
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Rev. B | 10/14/2015
IS66WV51216EALL
IS66/67WV51216EBLL
1.7V-1.95V POWER SUPPLY CHARACTERISTICS (Over Operating Range)
MAX.
70ns
Symbol
Parameter
Conditions
Device
TYP.
Unit
VDD=Max.,IOUT=0mA,
f=fMAX , All inputs = 0.4V
or VDD – 0.2V
Com.
Ind.
Auto
-
-
-
20
25
30
VDD Dynamic
Operating
ICC
mA
mA
mA
Supply Current
Operating
Supply Current
VDD=Max.,CS1#=0.2V,
WE#= VDD – 0.2V,
f=1MHz
Com.
Ind.
Auto
-
-
-
8
8
10
ICC1
ISB1
VDD=Max.,VIN=VIH or VIL,
CS1# = VIH, CS2=VIL ,
f=1MHz
Com.
Ind.
Auto
-
-
-
0.6
0.6
1
TTL Standby Current
( TTL Inputs )
VDD=Max.,
Com.
Ind.
Auto
-
-
-
100
120
150
CS1# > VDD – 0.2V,
CS2 < 0.2V, VIN > VDD – 0.2V
or VIN < 0.2V, f=0
CMOS Standby Current
( CMOS Inputs )
ISB2
uA
Notes:
1. Atf=fMAX, address and data inputs are cycling at the maximum frequency , f = 0 means no input lines change.
2.5V-3.6V POWER SUPPLY CHARACTERISTICS (Over Operating Range)
MAX
55ns
Symbol
Parameter
Conditions
Device
TYP
Unit
Com.
Ind.
Auto
25
28
35
15
VDD=Max.,IOUT=0mA,
f=fMAX , All inputs = 0.4V
or VDD – 0.3V
-
-
-
VDD Dynamic
Operating
ICC
mA
Supply Current
Typ.(2)
Operating
Supply Current
VDD=Max.,CS1#=0.2V,
WE#= VDD – 0.2V,
f=1MHz
Com.
Ind.
Auto
-
-
-
8
8
10
ICC1
ISB1
mA
mA
VDD=Max.,VIN=VIH or VIL,
CS1# = VIH, CS2=VIL ,
f=1MHz
Com.
Ind.
Auto
-
-
-
0.6
0.6
1
TTL Standby Current
( TTL Inputs )
VDD=Max.,
Com.
Ind.
100
130
150
75
-
-
-
CS1# > VDD – 0.2V,
CS2 < 0.2V, VIN > VDD – 0.2V
or VIN < 0.2V ,f=0
CMOS Standby Current
( CMOS Inputs )
ISB2
uA
Auto
Typ.(2)
Notes:
1. At f=fMAX, address and data inputs are cycling at the maximum frequency , f = 0 means no input lines change.
2. Typical values are measured at VDD = 3.0V, Ta = 25 ºC , and not 100% tested.
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Rev. B | 10/14/2015
IS66WV51216EALL
IS66/67WV51216EBLL
READ CYCLE SWITCHING CHARACTERISTICS(1)(Over Operating Range)
-55
-70
Symbol
Parameter
Unit
Notes
1
Min
60
-
Max
-
Min
70
-
Max
-
tRC
tAA
Read cycle time
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
Address Acess Time
60
-
70
-
tOHA
Output Hold Time
10
-
10
-
tACS1/ACS2
tDOE
CS1#/CS2 Acess Time
OE# Access Time
60
25
20
-
70
35
25
-
-
-
1
2
2
tHZOE
OE# to High-Z output
OE# to Low-Z output
-
-
tLZOE
5
5
tCSM
Maximum CS1#/CS2 pulse width
CS1#/CS2 to High-Z output
CS1#/CS2 to Low-Z output
UB#/LB# Acess Time
-
15
20
-
-
15
25
-
tHZCS1/HZCS2
tLZCS1/HZCS2
tBA
0
0
2
2
1
2
2
10
-
10
-
60
20
-
70
25
-
tHZB
UB#/LB# to High-Z output
UB#/LB# to Low-Z output
CS1# HIGH (CS2 LOW) time
0
0
tLZB
0
0
tCPH
5
-
5
-
Notes:
1. Test conditions and output loading are specified in the AC Test Conditions and AC Test Loads (Figure 1) on page 5.
2. Tested with the load in Figure 2. Transition is measured ±100 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
READ CYCLE NO. 1(1) (Address Controlled, OE#= VIL, WE#=VIH, UB# or LB# = VIL)
tRC
Address
tCSM
CS1#
CS2
tAA
tOHA
tOHA
DATA VALID
DQ 0-15
PREVIOUS DATA VALID
Notes:
1. WE# is HIGH for a Read Cycle.
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Rev. B | 10/14/2015
IS66WV51216EALL
IS66/67WV51216EBLL
READ CYCLE NO. 2(1) (CS1#, CS2, OE# and UB#/LB# Controlled)
tRC
ADDRESS
tAA
tOHA
tDOE
OE#
tHZOE
tCSM
CS1#
tLZOE
tACE1/tACE2
CS2
tLZCS1/
tLZCS2
tHZCS1/
tHZCS2
tCSM
UB#,LB#
tBA
tHZB
tLZB
HIGH-Z
DOUT
DATA VALID
Notes:
1. Address is valid prior to or coincident with CS1# LOW (CS2 HIGH) transition, and is valid after or coincident with CS1# HI
GH (CS2 LOW) transition.
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IS66WV51216EALL
IS66/67WV51216EBLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-55
-70
Symbol
Parameter
Write Cycle Time
Unit
Notes
Min
55
45
-
Max
Min
70
60
-
Max
tWC
tSCS1/SCS2
tCSM
-
-
-
-
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS1#/CS2 to Write End
Maximum CS1#/CS2 pulse width
Address Setup to Write Time
Address Hold to End of Write
Address Setup Time
15
-
15
-
tAW
45
0
60
0
tHA
-
-
tSA
0
-
0
-
tPWB
tPWE
tSD
UB#/LB# Valid to End of Write
WE# Pulse Width
45
45
25
-
-
60
60
30
-
-
-
-
Data Setup Time
-
-
tHZWE
tLZWE
tCPH
WE# LOW to High-Z output
WE# HIGH to Low-Z output
CS1# HIGH (CS2 LOW) time
20
-
30
-
3
3
5
5
5
-
5
-
Notes:
1. Test conditions and output loading are specified in the AC Test Conditions and AC Test Loads (Figure 1) on page 5.
2. The internal write time is defined by the overlap of CS1#, UB#, LB# and WE# LOW, CS2 HIGH . All signals must be
in valid states to initiate a Write, but anyone can go inactive to terminate Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signals that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±100 mV from steady-state voltage. Not 100% tested.
4. tPWE > tHzWE + tSD when OE# is LOW.
5. Chip Select Active Time (both CS1# LOW and CS2 HIGH) must not be longer than tCMS of 15 us.
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Rev. B | 10/14/2015
IS66WV51216EALL
IS66/67WV51216EBLL
AC WAVEFORMS
WRITE CYCLE NO. 1(1) (CS1# Controlled, OE#= HIGH or LOW)
tWC
ADDRESS
tHA
CS1#
CS2
tCSM
tAW
tPWE
WE#
tPWB
UB#,LB#
tSA
tLZWE
tHZWE
HIGH-Z
tSD
DOUT
DIN
DATA UNDEFINED
tHD
DATA- IN VALID
Notes:
1. Write address is valid prior to or coincident with CS1# LOW (CS2 HIGH) transition, and is valid after or coincident with C
S1# HIGH (CS2 LOW) transition.
WRITE CYCLE NO. 2 (WE# Controlled, OE#= HIGH during Write Cycle)
tWC
ADDRESS
OE#
tSCS1
tSCS2
tPWE
tHA
CS1#
CS2
tAW
WE#
UB#,LB#
tHZWE
tLZWE
tSA
DATA UNDEFINED
HIGH-Z
tSD
DOUT
DIN
tHD
DATA -IN VALID
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Rev. B | 10/14/2015
IS66WV51216EALL
IS66/67WV51216EBLL
WRITE CYCLE NO. 3 (WE# Controlled, OE#= LOW during Write Cycle)
tWC
ADDRESS
LOW
OE#
tHA
tSCS1
CS1#
CS2
tSCS2
tAW
tPWE
WE#
tPWB
UB#,LB#
tSA
tLZWE
tHZWE
HIGH-Z
tSD
DOUT
DIN
DATA UNDEFINED
tHD
DATA-IN VALID
WRITE CYCLE NO. 4 (UB# / LB# Controlled, CS2 is HIGH during Write Cycle)
tWC
tWC
ADDRESS
CS1#
ADDRESS 1
ADDRESS 2
tCSM
tSA
tHA
tSA
tHA
WE#
tPWB
tPWB
UB#,LB#
WORD 1
WORD 2
tLZWE
tHZWE
HIGH-Z
tSD
DOUT
DIN
DATA UNDEFINED
tHD
DATA IN
VALID
DATA IN
VALID
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Rev. B | 10/14/2015
IS66WV51216EALL
IS66/67WV51216EBLL
AVOIDABLE TIMING and RECOMMENDATIONS
Figure 3a : tCSM Violation
15us
CS1#
WE#
Address
Figure 3b : Recommendation
15us
15 us
CS1#
5ns
WE#
Address
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Rev. B | 10/14/2015
IS66WV51216EALL
IS66/67WV51216EBLL
AVOIDABLE TIMING and RECOMMENDATIONS
Figure 4a : tCSM Violation
15us
CS1#,WE#
UB# &LB#
Address
Figure 4b : Recommendation
15us
15us
WE# ,
UB# , LB#
CS1#
Address
Notes:
1. PSRAM uses DRAM cell which needs a REFRESH action periodically to retain the information. This REFRESH
action is performed only when the device is not selected (Chip Select Pins are Disabled). A hidden REFRESH action
has to be executed by the device at least once every 15 μs of tCSM.
2. Figure 3a shows a timing example in which consecutive READ cycles for more than 15 us . This timing should be
avoided for proper REFRESH operation.
REFRESH operation can begin only during Chip Select pins are Disabled (CS1# is High and CS2 is Low ) for more than 5ns.
Example on how to avoid tCSM violation in Figure 3a is shown in Figure 3b.
3. Figure 4a shows a timing example in which a single WRITE operation is maintained for a period greater than 15 μs.
Since a proper REFRESH action cannot be performed during device is selected by Chip Select pins, information
stored in the device will not be retained if this timing occurs.
Figure 4b is a timing example of using CS1# signal toggling for proper the WRITE operation
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Rev. B | 10/14/2015
IS66WV51216EALL
IS66/67WV51216EBLL
IS66WV51216EALL
Industrial Temperature Range: (-40oC to +85oC)
Voltage Range : 1.7V to 1.95V
Config.
Speed (ns)
Order Part No.
Package
512K x16
70
IS66WV51216EALL-70TLI
IS66WV51216EALL-70BLI
TSOP-II, Lead-free
mini BGA(6mm x 8mm), Lead-free
IS66WV51216EBLL
Industrial Temperature Range: (-40oC to +85oC)
Voltage Range : 2.5V to 3.6V
Config.
Speed (ns)
Order Part No.
Package
512K x16
55
IS66WV51216EBLL-55TLI
IS66WV51216EBLL-55BLI
TSOP-II, Lead-free
mini BGA(6mm x 8mm), Lead-free
70
IS66WV51216EBLL-70TLI
IS66WV51216EBLL-70BLI
TSOP-II, Lead-free
mini BGA(6mm x 8mm), Lead-free
IS67WV51216EBLL
Automotive (A1) Temperature Range: (-40oC to +85oC)
Voltage Range : 2.5V to 3.6V
Config.
Speed (ns)
Order Part No.
Package
512K x16
55
IS67WV51216EBLL-55TLA1
IS67WV51216EBLL-55BLA1
TSOP-II, Lead-free
mini BGA(6mm x 8mm), Lead-free
70
IS67WV51216EBLL-70TLA1
IS67WV51216EBLL-70BLA1
TSOP-II, Lead-free
mini BGA(6mm x 8mm), Lead-free
Notes :
1. Please contact ISSI SRAM marketing at sram@issi.com if you need -40 oC to +105 oC product.
14
www.issi.com - SRAM@issi.com
Rev. B | 10/14/2015
IS66WV51216EALL
IS66/67WV51216EBLL
15
www.issi.com - SRAM@issi.com
Rev. B | 10/14/2015
IS66WV51216EALL
IS66/67WV51216EBLL
16
www.issi.com - SRAM@issi.com
Rev. B | 10/14/2015
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