IS75V16F128GS32 [ISSI]
3.0 Volt Multi-Chip Package (MCP) 128 Mbit Simultaneous Operation Flash Memory and 32 Mbit Pseudo Static RAM; 3.0伏多芯片封装（ MCP ） 128兆位同时操作闪存和32兆位伪静态RAM
| 型号： | IS75V16F128GS32 |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | 3.0 Volt Multi-Chip Package (MCP) 128 Mbit Simultaneous Operation Flash Memory and 32 Mbit Pseudo Static RAM |
| 文件： | 总52页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS75V16F128GS32
ISSI
3.0 Volt Multi-Chip Package (MCP)
— 128 Mbit Simultaneous Operation Flash
Memory and 32 Mbit Pseudo Static RAM
PRELIMINARY INFORMATION
MARCH 2003
MCP FEATURES
• Erase Algorithms:
• Power supply voltage 2.7V to 3.3V
Automatically preprograms/erases the flash memory
entirely, or by sector
• High performance:
Flash: 70ns maximum access time
• Program Algorithms:
PSRAM: 65ns maximum access time
Automatically writes and verifies data at specified
address
• Package: 107-ball BGA
• Operating Temperature: -30C to +85C
• Hidden ROM Region:
256 byte with a Factory-serialized secure electronic
serial number (ESN), which is accessible through a
command sequence
FLASH FEATURES
• Power Dissipation:
Read Current at 1 Mhz: 4 mA maximum
Read Current at 5 Mhz:18 mA maximum
Sleep Mode: 5 µA maximum
• Data Polling and Toggle Bit:
Detects the completion of the program or erase cycle
• Ready-Busy Outputs (RY/BY)
Detection of program or erase cycle completion for
each flash chip
• User Configurable Banks
Flash 1 (64 Mbit)
Bank A1: 8Mbit (8KB x 8 and 64KB x 15)
Bank B1: 24Mbit (64KB x 48)
Bank C1: 24Mbit (64KB x 48)
• Over 100,000 write/erase cycles
• Low supply voltage (Vccf ≤ 2.5V) inhibits writes
Bank D1: 8Mbit (8KB x 8 and 64KB x 15)
• WP/ACC input pin:
If VIL, allows partial protection of boot sectors
If VIH, allows removal of boot sector protection
If Vacc, program time is improved
Flash 2 (64 Mbit)
Bank A2: 8Mbit (8KB x 8 and 64KB x 15)
Bank B2: 24Mbit (64KB x 48)
Bank C2: 24Mbit (64KB x 48)
Bank D2: 8Mbit (8KB x 8 and 64KB x 15)
User chooses two virtual banks from a
combination of four physical banks
PSRAM FEATURES (32 Mb density)
• Power Dissipation:
Operating: 25 mA maximum
Standby: 110 µA maximum
• Simultaneous R/W Operations (dual virtual bank):
Zero latency between read and write operations; Data
can be programmed or erased in one bank while data
is simultaneously being read from the other bank
• Chip Selects: CE1r, CE2r
• Power down feature using CE2r
Sleep Mode: 10 µA maximum
Nap: 65 µA maximum
8 mbit Partial: 80 µA maximum
• Low-Power Mode:
A period of no activity causes flash to enter a
low-power state
• Data retention supply voltage: 2.1 V to 3.3V
• Erase Suspend/Resume:
Suspends of erase activity to allow a read in the
same bank
• Byte data control: LB (DQ0–DQ7), UB
(DQ8–DQ15)
• Sector Erase Architecture:
16 sectors of 4K words each and 126 sectors of 32K words
each in Word mode. Any combination of sectors, or
the entire flash can be simultaneously erased
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products. FlexBankTM is a trademark
of Fujitsu Limited, Japan. Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
1
03/24/03
®
IS75V16F128GS32
ISSI
GENERAL DESCRIPTION
This 107-ball MCP is a space-saving combination of 3 memories: two 64Mbit Flash and one 32Mbit Pseudo SRAM.
Each 64Mbit Flash (Flash1 and Flash 2) contains 4,194,304 words and the 32Mbit PSRAM contains 2,097,152
words. Each word is 16 bits wide. Data lines DQ0-DQ15 handle the access for all three memories. Write Enable,
Output Enable, and A0-A20 are shared among the three memories. Single Byte data on the PSRAM can be
accessed one at a time on DQ0-DQ7 or DQ8-DQ15 by using LB or UB, respectively.
The package uses a 3.0V power supply for all operations. No other source is required for program and erase operations.
The flash can be programmed in system using this 3.0V supply, or can be programmed in a standard EPROM
programmer.
The flash chips are compatible with the JEDEC Flash command set standard. The flash access time is 70ns and the
PSRAM access time is 65ns.
Each Flash memory implements an architecture composed of two virtual banks that allows simultaneous operation on
each bank. Optimized performance can be achieved by first initializing a program or erase function in one bank, then
immediately starting a read from the other bank. Both operations would then be operating simultaneously on the same
chip, with zero latency.
MCP BLOCK DIAGRAM
V
CCf GND
1
A0-A21
RESET
CEf
1
RY/BY
1
1
64-MBIT
Flash Memory
(Flash 1)
V
CCf GND
2
A0-A21
A0-A21
RY/BY
2
WP/ACC
32-MBIT
Flash Memory
RESET
2
CEf
2
(Flash 2)
DQ0-DQ15
VCCr GND
A0-A20
LB
UB
WE
OE
32-MBIT
PSRAM
CE1r
CE2r
PE
2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
PIN CONFIGURATION (128 Mb Flash and 32 Mb PSRAM)
PACKAGE CODE: B 107 BALL FBGA (Top View) (9.00 mm x 10.00 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9 10
A
NC
NC
NC
NC
NC
B
C
D
E
F
NC GND RY/BY2
CEf2
WP/ACC
RESET1
RY/BY1
DU
NC
NC
NC
NC
NC
NC
NC
WE
A8 A11
NC
NC
NC
A7
A6
LB
A15
A3
A2
CE2r A19 A12
A20 A9 A13
UB
A21 NC
A5 A18
A4 A17
GND DQ1
OE DQ9
DQ0 DQ10
DQ8 DQ2
NC
A16
NC
NC
NC
A1
DU
DU
NC
NC
A10 A14
G
H
J
A0
DU
DQ6 PE
Vccf1
GND
CEf1
DQ3
NC
NC
DQ4 DQ13 DQ15
Vccr DQ12 DQ7
NC DQ5 DQ14
NC CE1r
Vccf1
DQ11
Shared
K
L
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Flash Only
PSRAM Only
NC
GND Vccf2
NC
RESET2
NC
M
NC
PIN DESCRIPTIONS
A0-A20
A21
Address Inputs, Common
Address Input, Both Flash
Data Inputs/Outputs, Common
Reset, Flash1
LB
UB
Lower-byte Control, PSRAM
Upper-byte Control, PSRAM
Write Protect/Acceleration Pin, Both Flash
Ready/Busy Output , Flash1
Ready/Busy Output , Flash2
No Connection
DQ0-DQ15
RESET1
RESET2
CE1r, CE2r
CEf1
WP/ACC
RY/BY1
RY/BY2
NC
Reset, Flash2
Chip Enable, PSRAM
Chip Enable, Flash1
Chip Enable, Flash2
Output Enable, Common
Write Enable, Common
Partial Enable, PSRAM
DU
Do Not Use
CEf2
Vccf1
Vccf2
Vccr
Power, Flash1
OE
Power, Flash2
WE
Power, PSRAM
PE
GND
Ground, Common
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
3
03/24/03
®
IS75V16F128GS32
ISSI
DEVICE BUS OPERATION
OPERATION(1,2) CEf1 CEf2 CE1r CE2r OE WE LBs UBs PE A21-A0 DQ -DQ DQ -DQ8 RESET1 RESET2 WP/ACC(12)
7
0
15
Full Standby
H
H
H
H
X
X
X
X
H
X
High-Z High-Z
H
H
X
Output Disable(3)
H
L
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
H
H
H
X(10)
X
X
High-Z High-Z
High-Z High-Z
High-Z High-Z
H
H
H
H
H
H
X
X
X
Read from FLASH 1(4)L
Read from FLASH 2(4)H
H
H
H
L
H
X
X
H
Valid
DOUT
DOUT
H
H
X
L
H
L
H
H
H
L
H
H
H
H
L
H
H
L
H
L
X
X
X
X
X
X
H
H
H
H
Valid
Valid
Valid
Valid
DOUT
DIN
DOUT
DIN
H
H
H
H
H
H
H
H
X
X
X
X
Write to FLASH 1
Write to FLASH 2
Read from PSRAM(5)
Write to PSRAM
L
H
H
L
DIN
DIN
H
H
L(9) L(9)
DOUT
DOUT
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
L
L
L
L
H
L
L
L
H
H
H
H
Valid
Valid
Valid
DIN
High-Z
DIN
DIN
DIN
High-Z
H
H
H
H
H
H
X
X
X
FLASH 1Temporary
Sector Group
Unprotection(6)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VID
X
X
X
X
FLASH 2 Temporary
Sector Group
VID
Unprotection(6)
FLASH 1
Hardware Reset
X
X
X
X
X
X
H
H
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
High-Z High-Z
High-Z High-Z
L
X
X
X
L
X
X
L
FLASH 2
Hardware Reset
Boot Block Sector
Write Protection
X
X
X
PSRAM Power(7)
Down Program
H
H
H
H
H
L
H
H
X
L
X
H
X
H
X
H
L
Valid
Valid
High-Z High-Z
High-Z High-Z
H
H
H
H
X
X
PSRAM No Read
H
PSRAM
Power Down(8)
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
Legend : L = VIL, H = VIH, X = VIL or VIH. See “DC CHARACTERISTICS” for voltage levels.
Notes:
1. Other operations except for indicated this column are prohibited.
2. Do not apply CEf = VIL, CE1r = VIL and CE2r = VIH all at once.
3. PSRAM Output Disable condition should not be kept longer than 1ms.
4. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
5. PSRAM LB,UB control at Read operation is not supported.
6. It is also used for the extended sector group protections.
7. The PSRAM Power Down Program can be performed one time after compliance of Power-UP timings and it should not be re-
programmed after regular Read or Write.
8. PSRAM Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. IPDr current and data retention
depends on the selection of Power Down Program.
9. Either or both LB and UB must be Low for PSRAM Read Operation.
10. Can be either VIL or VIH but must be valid before Read or Write.
11. See “ PSRAM Power Down Program Key Table “ located in the next page.
12. Protect “ outer most “ 2x8K bytes ( 4 words ) on both ends of the boot block sectors.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
(1,5)
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Tstg
Parameter
Min.
–55
–30
Max.
+125
+85
Unit
°C
Storage Temperature
TA
Ambient Temperature with Power Applied
Voltage with Respect to Ground All Pins(2)
VCCf Supply(2)
°C
VIN,VOUT
–0.3
–0.3
–0.3
-0.5
VCC + 0.3(6)
V
V
V
V
V
VCCf VCCf
3.5
1,
2
VCCr
VIN
VCCr Supply(2)
3.5
RESET1, RESET2(3)
WP/ACC(4)
+13.0
+10.5
VACC
–0.5
Notes:
1. Voltage is defined on the basis of GND = 0 V.
2. Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, input or I/O pins may undershoot
GND to -1.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3V , VCCf + 0.3V
1
2
or VCCr + 0.3 V. During voltage transitions, input or I/O pins may overshoot to VCCf + 2.0V , VCCf + 2.0 V or VCCr + 1.0 V
1
2
for periods of up to 20 ns.
3. Minimum DC input voltage on RESET1 or RESET2 pin is -0.5 V. During voltage transitions, RESET1 or RESET2 pin may
undershoot GND to -2.0 V for periods of up to 20 ns.
The voltage difference between input and supply voltage (VIN-VCCf or VCCf ) does not exceed 9.0 V.
1
2
The maximum DC input voltage on the RESET pin is +13.0 V that may overshoot to +14.0 V for periods of up to 20 ns.
4. Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may undershoot
GND to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may
overshoot to +12.0 V for periods of up to 20 ns, when VCCf or VCCf is applied.
1
2
5. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
6. This Vcc refers to the minimum of VCCf VCCf
1,
Vccr .
2, or
RECOMMENDED OPERATING CONDITIONS
Rating
Symbol
Parameter
Min.
–30
2.7
Max.
+85
3.3
Unit
°C
V
TA
Ambient Temperature
VCCf Supply Voltages
VCCr Supply Voltages
VCCf VCCf
1,
2
VCCr
2.7
3.3
V
Note:
Voltage is defined on the basis of GND = 0 V.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
5
03/24/03
®
IS75V16F128GS32
ISSI
DC CHARACTERISTICS
Symbol Parameter
Test Conditions
Min.
-1.0
-1.0
—
Typ.
—
Max.
+1.0
+1.0
35
Unit
ILI
Input Leakage
VIN=GND to VCCf, VCCr
VOUT=GND to VCCf, VCCr
µA
µA
µA
ILO
ILIT
Output Leakage
—
RESET Inputs
VCCf=VCCf max.,
—
Leakage Current
RESET = 12.5V
ICC1f
FLASH Vcc (1)
Active Current (Read)
CEf=VIL, OE=VIH
tCycle = 5Mhz
tCycle = 1Mhz
—
—
18
mA
—
—
—
—
4
mA
mA
ICC2f
ICC3f
FLASH Vcc Active(2)
Current(Program/Erase) OE=VIH
FLASH Vcc Active(5)
Current
(Read-While-Program)
FLASH Vcc Active(5)
Current
(Read-While-Erase)
CEf=VIL,
35
CEf=VIL,
OE=VIH
—
—
—
—
—
—
—
—
53
53
40
20
mA
mA
mA
mA
ICC4f
ICC5f
CEf=VIL,
OE=VIH
FLASH Vcc Active
Current
(Erase-Suspend-Program)
CEf=VIL,
OE=VIH
IACC
WP/ACC Acceleration
VCCf = Vcc max,
Program Current
WP/ACC = VACC max
ICC1r
PSRAM Vcc Active
Current
VCCr = Vccr max,
CE1r=VIL, CE2r=VIH,
VIN=VIH or VIL,
trc / twc = min
trc / twc = 1 µs
—
—
—
—
25
3
mA
mA
IOUT=0 mA
ISB1f
FLASH Vcc
Standby Current(7)
VCCf = Vccf max, CEf= VCCf + 0.3V,
RESET = VCCf + 0.3V,
—
1
5
µA
WP/ACC = VCCf + 0.3V
ISB2f
ISB3f
FLASH Vcc (7)
Standby Current
(RESET)
FLASH Vcc(3,7)
Current
VCCf = Vccf max, RESET= GND + 0.3V,
WP/ACC = VCCf + 0.3V
—
—
1
5
5
µA
µA
VCCf = Vccf max, CEf = GND + 0.3V,
RESET = VCCf + 0.3V,
1
(Automatic Sleep Mode)
WP/ACC = VCCf + 0.3V,
VIN = VCCf + 0.3V OR GND + 0.3V
ISB1r
PSRAM Vcc Standby(8)
Current
VCCr = Vccr max, CE1r ≥ VCCr -0.2V,
CE2r ≥ VCCr -0.2V,
VIN ≤ 0.2 V or VIN ≥ VCCr -0.2V
—
—
—
—
110
10
µA
IPDSr
PSRAM VCC Power
Down Current
(Sleep Mode)
PSRAM VCC Power (8)
VCCr = VCCr max.,
CE1r ≥ VCCr - 0.2 V
CE2r ≤ 0.2 V, VIN Cycle time = tRC min
—
—
µA
IPDNr
VCCr = VCCr max.,
65
µA
Down Current
CE1r ≥ VCCr - 0.2 V
(Nap Mode)
CE2r ≤ 0.2 V, VIN Cycle time = tRC min
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
DC CHARACTERISTICS (Continued)
Symbol Parameter
Test Conditions
Min.
Typ.
Max.
Unit
I
PD8r
PSRAM VCC Power
Down Current
(8M Partial)(8)
VCCr = VCCr max.,
CE1r ≥ VCCr - 0.2 V
CE2r ≤ 0.2 V, VIN Cycle time = tRC min
—
—
80
µA
VIL
VIH
VIH
VID
Input Low Level
-0.3
—
0.5
V
V
V
V
Input High Level (FLASH 1 or FLASH 2 )
Input High Level (PSRAM)
VCCf X 0.75 —
VCCr X 0.75 —
VCCf + 0.3
VCCr + 0.3
12.5
Voltage for Sector Protection
11.5
—
and Temp. Unprotection(RESET)(4)
VACC
Voltage for WP/ACC
8.5
9.0
9.5
V
Sector Protection/Unprotection
(4)
and Program Acceleration
VOL
VOH
VOL
VOH
VLKO
Output Low Level
(PSRAM)
VCCr = VCCr min., VCCS=VCCS min.
IOL = 1.0 mA
—
2.2
—
—
0.4
—
V
V
V
V
V
Output High Level
(PSRAM)
VCCr = VCCr min., VCCS=VCCS min.
IOH = -0.5 mA
Output Low Level
(Flash)
VCCf = VCCf min., VCCS=VCCS min.
IOL = 4.0 mA
—
—
0.45
—
Output High Level
(Flash)
VCCf = VCCf min., VCCS=VCCS min.
IOH = -0.1 mA
VCCf - 0.4
2.3
—
FLASH Low Vccf
Lock-Out Voltage
2.4
2.5
Notes:
1. ICC current listed includes both the DC operating current and the frequency dependent component.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
3. Automatic sleep mode enables the low power mode when address remains stable for 150 ns.
4. Applicable for only VCCf applying.
5. Embedded Algorithm (program or erase) is in progress. (@5 MHz)
6. ISB2 r depends on VIN cycle time. Please refer to “APPENDIX A”.
7. Standby current listed is for each FLASH chip.
<
8. Standby and Power down currents are reduced with Vccr 3.0 V .
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
7
03/24/03
®
IS75V16F128GS32
ISSI
AC CHARACTERISTICS - CE TIMING
Parameter
Symbol
Condition
Min Max
Unit
CEf Recover Time
CEf Hold Time
t
CCR
CHOLD
CHWX
—
—
—
0
3
—
—
—
ns
t
ns
CE1r High to WE Invalid time for
t
10
ns
Standby Entry
TIMING DIAGRAM FOR ALTERNATING PSRAM TO FLASH 1 OR FLASH 2
CEf
tCCR
tCCR
CE1r
WE
tCHOLD
tCHWX
tCCR
tCCR
CE2r
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
FLEXIBLE SECTOR-ERASE ARCHITECTURE ON FLASH 1 or FLASH 2
Sector
Address
SA0
Sector
Bank
K-Word
4
Address
000000h
001000h
002000h
003000h
004000h
005000h
006000h
007000h
008000h
010000h
018000h
020000h
028000h
030000h
038000h
040000h
048000h
050000h
058000h
060000h
068000h
070000h
078000h
080000h
088000h
090000h
098000h
0A0000h
0A8000h
0B0000h
0B8000h
0C0000h
0C8000h
0D0000h
0D8000h
0E0000h
Bank
Address K-Word
Address
0E8000h
0F0000h
0F8000h
100000h
108000h
110000h
118000h
120000h
128000h
130000h
138000h
140000h
148000h
150000h
158000h
160000h
168000h
170000h
178000h
180000h
188000h
190000h
198000h
1A0000h
1A8000h
1B0000h
1B8000h
1C0000h
1C8000h
1D0000h
1D8000h
1E0000h
1E8000h
1F0000h
1F8000h
200000h
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank C
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
SA1
4
SA2
4
SA3
4
SA4
4
SA5
4
SA6
4
SA7
4
SA8
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
9
03/24/03
®
IS75V16F128GS32
ISSI
FLEXIBLE SECTOR-ERASE ARCHITECTURE ON FLASH 1 or FLASH 2 (Continued)
Sector
Address
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
Sector
Bank
K-Word
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Address
208000h
210000h
218000h
220000h
228000h
230000h
238000h
240000h
248000h
250000h
258000h
260000h
268000h
270000h
278000h
280000h
290000h
298000h
2A0000h
2A8000h
2B0000h
2B8000h
2C0000h
2C8000h
2D0000h
2D8000h
2E0000h
2E8000h
2F0000h
2F8000h
300000h
308000h
310000h
318000h
Bank
Address K-Word
Address
320000h
328000h
330000h
338000h
340000h
348000h
350000h
358000h
360000h
368000h
370000h
378000h
380000h
388000h
390000h
398000h
3A8000h
3B0000h
3B8000h
3C0000h
3C8000h
3D0000h
3D8000h
3E0000h
3E8000h
3F0000h
3F8000h
3F9000h
3FA000h
3FB000h
3FC000h
3FD000h
3FE000h
3FF000h
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
4
4
4
4
4
4
4
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
USER CONFIGURABLE BANK ARCHITECTURE TABLE - FLASH 1 or FLASH 2
Virtual Bank 1
Virtual Bank 2
Bank Split
Choice 1
Volume
Combination
Volume
Combination
8 Mbit
Bank A
56 Mbit
Bank B, C, D
Bank A, C, D
Bank A, B, D
Bank A, B, C
Choice
Choice
Choice
2
3
4
24 Mbit
24 Mbit
8 Mbit
Bank B
Bank C
Bank D
40 Mbit
40 Mbit
56 Mbit
EXAMPLE OF VIRTUAL BANKS COMBINATION TABLE - FLASH 1 or FLASH 2
Virtual Bank 1 Virtual Bank 2
Bank Split Volume
Combination
Sector Size
Volume
Combination
Sector Size
8x4 Kword
Choice 1 8 Mbit
Bank A
8x4 Kword
56 Mbit Bank B, C, D
15x32 Kword
16x4 Kword
30x32 Kword
48x32 Kword
111x32 Kword
Choice
Choice
2
3
4
16 Mbit
24 Mbit
32 Mbit
Bank A,D
Bank B
48 Mbit Bank B,C
40 Mbit Bank A, C, D
32 Mbit Bank C,D
96x32 Kword
16x4 Kword
78x32 Kword
8x4 Kword
Choice
Notes:
Bank A,B
8x4 Kword
63x32 Kword
63x32 Kword
1) When multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being
erased belongs. For example, if erasing is taking place at both Bank A and Bank B, neither Bank A nor Bank B is read out. They
would output the sequence flag once they were selected. Meanwhile the system would get to read from either Bank C or Bank D.
10
2) Each word is made-up of 2 bytes: one upper byte and one lower byte. A KWord is 2 words.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
11
03/24/03
®
IS75V16F128GS32
ISSI
SIMULTANEOUS OPERATION TABLE - FLASH 1 or FLASH 2
Case
1
Virtual Bank 1 Status
Virtual Bank 2 Status
Read Mode
Read Mode
2
3
4
5
6
7
Read Mode
Autoselect Mode
Program Mode
Erase Mode (1)
Read Mode
Read Mode
Read Mode
Autoselect Mode
Program Mode
Erase Mode (1)
Read Mode
Read Mode
Note:
1) By writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it
enables reading from or programming the remaining sectors.
2) Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank consists of 4 banks,
Bank A, Bank B, Bank C, and Bank D. Bank Address (BA) means to specify each of the Banks.
12
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
SECTOR ADDRESS TABLE - FLASH 1 or FLASH 2
Bank Address Sector Address
Address Range
Bank
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Word Mode
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
000000h to 000FFFh
001000h to 001FFFh
002000h to 002FFFh
003000h to 003FFFh
004000h to 004FFFh
005000h to 005FFFh
006000h to 006FFFh
007000h to 007FFFh
008000h to 00FFFFh
010000h to 017FFFh
018000h to 01FFFFh
020000h to 027FFFh
028000h to 02FFFFh
030000h to 037FFFh
038000h to 03FFFFh
040000h to 047FFFh
048000h to 04FFFFh
050000h to 057FFFh
058000h to 05FFFFh
060000h to 067FFFh
068000h to 06FFFFh
070000h to 077FFFh
078000h to 07FFFFh
080000h to 087FFFh
088000h to 08FFFFh
090000h to 097FFFh
098000h to 09FFFFh
0A0000h to 0A7FFFh
0A8000h to 0AFFFFh
0B0000h to 0B7FFFh
0B8000h to 0BFFFFh
0C0000h to 0C7FFFh
0C8000h to 0CFFFFh
SA8
SA9
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
13
03/24/03
®
IS75V16F128GS32
ISSI
SECTOR ADDRESS TABLE - FLASH 1 or FLASH 2 (Continued)
Bank Address Sector Address
Address Range
Bank
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Word Mode
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
Bank B
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0D0000h to 0D7FFFh
0D8000h to 0DFFFFh
0E0000h to 0E7FFFh
0E8000h to 0EFFFFh
0F0000h to 0F7FFFh
0F8000h to 0FFFFFh
100000h to 107FFFh
108000h to 10FFFFh
110000h to 117FFFh
118000h to 11FFFFh
120000h to 127FFFh
128000h to 12FFFFh
130000h to 137FFFh
138000h to 13FFFFh
140000h to 147FFFh
148000h to 14FFFFh
150000h to 157FFFh
158000h to 15FFFFh
160000h to 167FFFh
168000h to 16FFFFh
170000h to 177FFFh
178000h to 17FFFFh
180000h to 187FFFh
188000h to 18FFFFh
190000h to 197FFFh
198000h to 19FFFFh
1A0000h to 1A7FFFh
1A8000h to 1AFFFFh
1B0000h to 1B7FFFh
1B8000h to 1BFFFFh
1C0000h to 1C7FFFh
1C8000h to 1CFFFFh
1D0000h to 1D7FFFh
14
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
SECTOR ADDRESS TABLE - FLASH 1 or FLASH 2 (Continued)
Bank Address Sector Address
Address Range
Bank
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Word Mode
Bank B
Bank B
Bank B
Bank B
Bank B
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
SA86
SA87
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1D8000h to 1DFFFFh
1E0000h to 1E7FFFh
1E8000h to 1EFFFFh
1F0000h to 1F7FFFh
1F8000h to 1FFFFFh
200000h to 207FFFh
208000h to 20FFFFh
210000h to 217FFFh
218000h to 21FFFFh
220000h to 227FFFh
228000h to 22FFFFh
230000h to 237FFFh
238000h to 23FFFFh
240000h to 247FFFh
248000h to 24FFFFh
250000h to 257FFFh
258000h to 25FFFFh
260000h to 267FFFh
268000h to 26FFFFh
270000h to 277FFFh
278000h to 27FFFFh
280000h to 287FFFh
288000h to 28FFFFh
290000h to 297FFFh
298000h to 29FFFFh
2A0000h to 2A7FFFh
2A8000h to 2AFFFFh
2B0000h to 2B7FFFh
2B8000h to 2BFFFFh
2C0000h to 2C7FFFh
2C8000h to 2CFFFFh
2D0000h to 2D7FFFh
2D8000h to 2DFFFFh
2E0000h to 2E7FFFh
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
15
03/24/03
®
IS75V16F128GS32
ISSI
SECTOR ADDRESS TABLE - FLASH 1 or FLASH 2 (Continued)
Bank Address Sector Address
Address Range
Bank
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Word Mode
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank C
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
Bank D
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
SA128
SA129
SA130
SA131
SA132
SA133
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
2E8000h to 2EFFFFh
2F0000h to 2F7FFFh
2F8000h to 2FFFFFh
300000h to 307FFFh
308000h to 30FFFFh
310000h to 317FFFh
318000h to 31FFFFh
320000h to 327FFFh
328000h to 32FFFFh
330000h to 337FFFh
338000h to 33FFFFh
340000h to 347FFFh
348000h to 34FFFFh
350000h to 357FFFh
358000h to 35FFFFh
360000h to 367FFFh
368000h to 36FFFFh
370000h to 377FFFh
378000h to 37FFFFh
380000h to 387FFFh
388000h to 38FFFFh
390000h to 397FFFh
398000h to 39FFFFh
3A0000h to 3A7FFFh
3A8000h to 3AFFFFh
3B0000h to 3B7FFFh
3B8000h to 3BFFFFh
3C0000h to 3C7FFFh
3C8000h to 3CFFFFh
3D0000h to 3D7FFFh
3D8000h to 3DFFFFh
3E0000h to 3E7FFFh
3E8000h to 3EFFFFh
3F0000h to 3F7FFFh
3F8000h to 3F8FFFh
3F9000h to 3F9FFFh
3FA000h to 3FAFFFh
3FB000h to 3FBFFFh
3FC000h to 3FCFFFh
3FD000h to 3FDFFFh
3FE000h to 3FEFFFh
3FF000h to 3FFFFFh
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
16
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
SECTOR ADDRESS GROUP TABLE - FLASH 1 or FLASH 2
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Sectors
SGA0
SGA1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
0
1
SGA8
0
0
0
0
0
1
0
X
X
X
SA8 to SA10
1
1
SGA9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA11 to SA14
SA15 to SA18
SA19 to SA22
SA23 to SA26
SA27 to SA30
SA31 to SA34
SA35 to SA38
SA39 to SA42
SA43 to SA46
SA47 to SA50
SA51 to SA54
SA55 to SA58
SA59 to SA62
SA63 to SA66
SA67 to SA70
SA71 to SA74
SA75 to SA78
SA79 to SA82
SA83 to SA86
SA87 to SA90
SA91 to SA94
SA95 to SA98
SA99 to SA102
SA103 to SA106
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
SGA16
SGA17
SGA18
SGA19
SGA20
SGA21
SGA22
SGA23
SGA24
SGA25
SGA26
SGA27
SGA28
SGA29
SGA30
SGA31
SGA32
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
17
03/24/03
®
IS75V16F128GS32
ISSI
SECTOR ADDRESS GROUP TABLE - FLASH 1 or FLASH 2 (Continued)
Sector
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Sectors
SGA33
SGA34
SGA35
SGA36
SGA37
SGA38
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
X
X
X
X
X
X
0
0
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
0
1
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA107 to SA110
SA111 to SA114
SA115 to SA118
SA119 to SA122
SA123 to SA126
SA127 to SA130
SGA39
1
1
1
1
1
X
X
X
SA131 to SA133
SGA40
SGA41
SGA42
SGA43
SGA44
SGA45
SGA46
SGA47
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
FLASH MEMORY AUTOSELECT CODES TABLE - FLASH 1 or FLASH 2
Type
A21 to A12
A6
A3
A2
A1
A0
Code (HEX)
Manufacturer's Code
BA
L
L
L
L
L
04h
Device Code
BA
L
L
L
L
H
227Eh
Extended Device
Code(2)
BA
BA
L
L
L
H
H
L
H
H
L
H
H
H
L
H
L
2202h
2201h
01h(1)
Sector Group
Protection
Sector Group
Address
Legend: L = VIL, H = VIH. See “ DC CHARACTERISTICS” for voltage levels.
Notes:
1. Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.
2. A read cycle at address (BA) 01h outputs device code. When 227Eh was output, this indicates that there will require two
additional codes, called Extended Device Codes. Therefore the system may continue reading out these Extended Device Codes
at the address of (BA) 0Eh, as well as at (BA) 0Fh.
.
18
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
FLASH MEMORY COMMAND DEFINITIONS - FLASH 1 or FLASH 2
First Bus
Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fourth Bus
Read/Write
Fifth Bus
Cycle
Sixth Bus
Cycle
Bus
Command
Sequence
Write
Cycle
Req'd
Data Addr. Data
Data
—
Addr. Data
Addr. Data
Addr. Data
Addr.
—
Addr.
Read / Reset (1)
—
—
—
—
—
—
—
—
—
—
—
—
—
F0h
AAh
AAh
1
3
3
4
1
1
XXXh
555h
555h
(1)
555h F0h
(BA)
—
—
—
—
—
—
—
—
—
—
Read / Reset
55h
55h
—
—
2AAh
2AAh
RA
—
RD
—
90h
Autoselect
555h
—
—
—
A0h
PA
—
—
PD
—
AAh 2AAh 55h
B0h
555h
BA
555h
Program
Program Suspend
—
—
—
—
—
BA
Program Resume
Chip Erase
—
—
—
—
30h
55h
—
2AAh
AAh
6
6
555h
555h
AAh 2AAh
555h
555h
80h
—
55h
—
10h
—
555h
—
555h
SA
—
—
80h
55h
2AAh
555h
Sector Erase
Erase Suspend
2AAh
AAh
B0h
30h
60h
30h
AAh
55h
—
—
—
1
1
4
—
—
—
—
—
—
—
—
—
—
—
—
BA
BA
—
—
—
—
—
—
—
—
Erase Resume
—
Extended Sector
Group Protection
60h
SGA
SGA
40h
XXXh
SGA
SD
(3)
Set to Fast
Mode (2)
20h
—
—
—
—
—
—
2AAh
PA
555h
XXXh
BA
AAh
A0h
90h
98h
55h
PD
555h
3
2
Fast Program (2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Reset from Fast
Mode (2)
(6)
F0H
2
1
3
4
4
XXXh
—
(BA)
55h
Query (4)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Hi-ROM
Entry
88h
555h
2AAh
AAh
AAh
AAh
55h
55h
55h
555h
555h
Hi-ROM
Program (5)
(HRA)
PA
—
—
—
—
—
—
—
—
2AAh
2AAh
A0h
90h
555h
555h
PD
Hi-ROM
Exit (5)
(HRBA)
555h
XXXh
00h
Notes:
1. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
2. This command is valid during Fast Mode.
3. This command is valid while RESET = VID
4. The valid address is A6 to A0.
5. This command is valid during Hi-ROM mode.
6. The data “00h” is also acceptable.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
19
03/24/03
®
IS75V16F128GS32
ISSI
FLASH MEMORY COMMAND DEFINITIONS - FLASH 1 or FLASH 2 (Continued)
Notes:
• SPA = Sector group address to be protected.
Set sector group address and (A6, A3, A2, A1,
A0) = (0, 0, 0, 1, 0).
• Address bits A21 to A11 = X = “H” or “L” for all
address commands except or Program Address
(PA), Sector Address (SA), and Bank Address
(BA), and Sector Group Address (SPA).
SD = Sector group protection verify data.
Output 01h at protected sector group
addresses and output 00h at unprotected
sector group addresses.
• Bus operations are defined in "DEVICE BUS
OPERATIONS”.
• HRA = Address of the Hi-ROM area :
000000h to 00007Fh
• RA = Address of the memory location to be read
PA = Address of the memory location to be
programmed. Addresses are latched on the falling
edge of the write pulse.
HRBA = Bank Address of the Hi-ROM area
(A21 = A20 = A19 = VIL)
• The system should generate the following address
patterns : 555h or 2AAh to addresses A10 to A0
• SA = Address of the sector to be erased. The
combination of A21, A20, A19, A18, A17, A16,
A15, A14, A13, and A12 will uniquely select any
sector. BA = Bank Address (A21, A20, A19)
• Both Read/Reset commands are functionally
equivalent, resetting the device to the read mode.
• RD = Data read from location RA during read
operation.
• Command combinations not described in FLASH
Memory Command Definitions are illegal.
PD = Data to be programmed at location PA. Data
is latched on the rising edge of the write pulse.
20
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
FLASH READ ONLY OPERATIONS CHARACTERISTICS - FLASH 1 or FLASH 2
JEDEC
Symbol
Standard
Symbol
Parameter
Condition
Min Max
Unit
ns
Read Cycle Time
t
AVAV
AVQV
ELQV
t
RC
70
—
—
—
—
—
0
—
70
70
30
25
25
—
Address to Output Delay
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High-Z
Output Enable to Output High-Z
t
tACC
CEf = VIL, OE = VIL
OE = VIL
ns
t
t
CE
OE
ns
tGLQV
t
ns
t
EHQZ
t
t
DF
DF
ns
t
GHQZ
ns
Output Hold Time From Addresses,
tAXQX
tOH
ns
CEf or OE, Whichever Occurs First
RESET Pin Low to Read Mode
—
t
READY
—
20
µs
Test Conditions:
Output Load : 1 TTL gate and 30 pF
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V or VCCf
Timing measurement reference level
Input : VCCf/2
Output : VCCf/2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
21
03/24/03
®
IS75V16F128GS32
ISSI
FLASH READ CYCLE - FLASH 1 or FLASH 2
tRC
Address Stable
Address
tACC
CEf1
tDF
t
OE
OE
tOEH
WE
tCE
tOH
High-Z
High-Z
DQ
Output valid
22
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
FLASH HARDWARE RESET / READ OPERATION TIMING DIAGRAM - FLASH 1 or FLASH 2
tRC
Address Stable
Address
t
ACC
CEf1
tRH
tRP
tRH
tCE
RESET
tOH
High-Z
DQ
Output valid
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
23
03/24/03
®
IS75V16F128GS32
ISSI
FLASH WRITE/ERASE/PROGRAM OPERATIONS - FLASH 1 or FLASH 2
JEDEC
Symbol
Standard
Symbol
Parameter
Min
70
0
Typ
—
—
—
Max
—
Unit
ns
Write Cycle Time
Address Setup Time
t
AVAV
t
WC
AS
ASO
t
AVWL
t
—
ns
Address Setup Time to OE Low
During Toggle Bit Polling
—
t
12
—
ns
Address Hold Time
t
WLAX
t
AH
45
0
—
—
—
—
ns
ns
Address Hold Time from CE or
OE High During Toggle Bit Polling
—
t
AHT
f
Data Setup Time
t
t
DVWH
WHDX
—
t
DS
30
0
—
—
—
—
—
—
—
—
ns
ns
ns
ns
Data Hold Time
tDH
Output Enable Hold Time Read
t
t
OEH
OEH
0
Output Enable Hold Time
Toggle and Data Polling
—
10
CE High During Toggle Bit Polling
—
—
t
CEPH
OEPH
20
20
0
—
—
—
—
—
—
—
—
—
—
—
—
6
—
—
—
—
—
—
—
—
—
—
—
—
100
2.0
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
s
f
OE High During Toggle Bit Polling
t
Read Recover Time Before Write (OE to CE )
t
GHWL
t
GHWL
GHEL
WS
CS
WH
f
Read Recover Time Before Write (OE to WE)
t
GHEL
WLEL
ELWL
t
0
WE Setup Time (CE to WE)
t
t
0
f
CE Setup Time (WE to CE )
t
t
0
f
f
WE Hold Time (CE to WE)
t
t
EHWH
WHEH
t
t
t
0
f
CE Hold Time (WE to CE )
t
CH
0
f
f
Write Pulse Width
CEf Pulse Width
Write Pulse Width High
t
WHWL
WP
35
35
25
25
—
—
50
500
500
4
t
ELEH
t
CP
t
WHWL
WP
CE Pulse Width High
t
EHEL
t
CPH
f
Word Programming Operation (1)
Sector Erase Operation (1)
t
WHWH
WHWH
—
1
t
WHWH
1
2
t
2
t
WHWH
0.5
—
—
—
—
—
VCC Setup Time
t
VCS
VIDR
VACCR
VLHT
WPP
µs
ns
ns
µs
µs
(2)
Rise Time to VID
—
t
(3)
Rise Time to VACC
—
t
Voltage Transition Time (2)
Write Pulse Width (2)
—
t
—
t
100
24
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
FLASH WRITE/ERASE/PROGRAM OPERATIONS - FLASH 1 or FLASH 2 (Continued)
JEDEC
Symbol
Standard
Symbol
Parameter
OE Setup Time to WE Active (2)
Min
4
Typ
—
—
—
—
—
—
—
—
—
Max
—
—
—
—
—
90
Unit
µs
µs
ns
ns
ns
ns
ns
µs
µs
—
—
—
—
—
—
—
—
—
t
OESP
CE Setup Time to WE Active (2)
tCSP
4
f
Recover Time from RY/BY
t
RB
RP
0
RESET Pulse Width
t
500
200
—
—
50
—
RESET High Level Period Before Read
Program/Erase Valid to RY/BY Delay
Delay Time from Embedded Output Enable
Erase Time-Out Time
t
RH
BUSY
EOE
TOW
SPD
t
t
70
t
—
20
Erase Suspend Transition Time
t
Notes:
1. Does not include preprogramming time.
2. For Sector Group Protection operation.
3. For Accelerated Program operation.
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PRELIMINARY INFORMATION Rev. 00D
25
03/24/03
®
IS75V16F128GS32
ISSI
FLASH WRITE CYCLE - FLASH 1 or FLASH 2
(WE CONTROL)
3rd Bus Cycle
Data Polling
tRC
555h
PA
PA
ADDRESS
tWC
tAS
tAH
CEf
OE
t
CS
t
CH
t
CE
t
WPH
t
WP
DS
tWHWH1
t
OE
t
GHWL
WE
t
tOH
t
DH
tDF
A0h
PD
DQ7
Dout
Dout
DQ
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
26
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
FLASH WRITE CYCLE - FLASH 1 or FLASH 2
(CEf CONTROL)
3rd Bus Cycle
Data Polling
555h
PA
PA
ADDRESS
tWC
tAS
tAH
CEf1
tWS
tWH
OE
t
CPH
t
CP
DS
tGHEL
tWHWH1
WE
t
t
DH
A0h
PD
DQ7
Dout
DQ
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
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PRELIMINARY INFORMATION Rev. 00D
27
03/24/03
®
IS75V16F128GS32
ISSI
FLASH AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS - FLASH 1 or FLASH 2
*
555h
2AAh
555h
555h
2AAh
SA
ADDRESS
tWC
tAS
tAH
CEf1
OE
tCH
tCS
tWP
tWPH
tGHWL
WE
tDS
tDH
30h for Sector Erase
10h/
30h
AAh
AAh
80h
55h
55h
DQ
tVCS
Vccf
Notes:
1. SA is the sector address for Sector Erase. Address = 555h for Chip Erase.
28
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
FLASH AC WAVEFORMS FOR DATA POLLING
DURING EMBEDDED ALGORITHM OPERATIONS - FLASH 1 or FLASH 2
CEf1
tCH
tOE
tDF
OE
WE
DQ
tOEH
t
CEf1
(1)
High - Z
High - Z
DQ7 =
Valid Data
Data In
Data In
DQ7
t
WHWH1 or 2
DQ0 to DQ6
Valid Data
DQ0 to DQ6 = Output Flag
DQ0/DQ6
tBUSY
tEOE
RY/BY
Notes:
1. DQ7 = Valid Data (the device has completed the Embedded operation.)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
29
03/24/03
®
IS75V16F128GS32
ISSI
FLASH AC WAVEFORMS
FOR TOGGLE BIT DURING EMBEDDED ALGORITHM OPERATIONS - FLASH 1 or FLASH 2
ADDRESS
tAHT
tASO
tAHT
tAS
CEf1
tCEPH
WE
OE
tOEH
tOEPH
tOEH
tOE
tDH
tCEf
(1)
Toggle
Data
Toggle
Data
Toggle
Data
Stop
Toggle
Output
Valid
Data
DQ6/DQ2
tBUSY
RY/BY
Notes:
1. DQ6 stops toggling (the device has completed the Embedded operation).
30
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
FLASH BACK-to-BACK READ/WRITE TIMING DIAGRAM - FLASH 1 or FLASH 2
Read
Command
Read
Command
Read
Read
t
RC
t
RC
tWC
t
RC
tRC
t
WC
BA2
(555h)
BA2
(PA)
BA2
(PA)
BA1
BA1
BA1
ADDRESS
t
ACC
tAS
t
AS
tAH
t
CE
t
AHT
CEf1
t
CEPH
t
OE
OE
t
DF
t
GHWL
t
OEH
t
WP
WE
t
DS
tDF
t
DH
Valid
Output
Valid
Input
Valid
Output
Valid
Input
Valid
Output
DQ
Status
(A0h)
(PD)
Note:
1. This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1: Address of Virtual Bank 1.
BA2: Address of Virtual Bank 2.
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PRELIMINARY INFORMATION Rev. 00D
31
03/24/03
®
IS75V16F128GS32
ISSI
FLASH RY/BY TIMING DIAGRAM
DURING WRITE/ERASE OPERATIONS - FLASH 1 or FLASH 2
CEf
The rising edge of the last write pulse
WE
Entire programming
or erase operations
RY/BY
tBUSY
FLASH RESET, RY/BY TIMING DIAGRAM - FLASH 1 or FLASH 2
WE
RESET
tRP
tRB
RY/BY
tREADY
32
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
FLASH TEMPORARY SECTOR GROUP UNPROTECTION - FLASH 1 or FLASH 2
tVIDR
VCCf
tVLHT
tVCS
VID
3V
RESET
CEf1
WE
t
VLHT
Program or Erase Command Sequence
Unprotection Period
tVLHT
RY/BY
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PRELIMINARY INFORMATION Rev. 00D
33
03/24/03
®
IS75V16F128GS32
ISSI
FLASH ACCELERATED PROGRAM - FLASH 1 or FLASH 2
tVACCR
VCCf
tVCS
tVLHT
VACC
VIH
WP/ACC
CEf1
WE
tVLHT
tVLHT
Program Command Sequence
Acceleration Period
RY/BY
34
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
FLASH EXTENDED SECTOR GROUP PROTECTION- FLASH 1 or FLASH 2
tVCS
Vccf
tVLHT
tWC
tWC
RESET
tVIDR
SPAX
Address
SPAX
SPAY
A6, A3
A2, A0
A1
CEf1
OE
tWP
TIME-OUT
WE
60h
Data
60h
40h
01h
60h
tOE
Notes:
1. SPAX : Sector Group Address to be protected, SPAY : Next Group Sector Address to be protected,
TIME-OUT: Time-Out window = 250 µs (Min)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
35
03/24/03
®
IS75V16F128GS32
ISSI
FLASH ERASE AND PROGRAMMING PERFORMANCE - FLASH 1 or FLASH 2
Parameter
Min.
Typ.(1)
Max.
Unit
Remarks
Sector Erase Time
—
0.5
2.0
s
Excludes programming time
prior to erasure
Word Programming Time
Chip Programming Time
Erase/Program Cycle
—
—
6.0
—
100
200
—
µs
s
Excludes system-level
overhead
Excludes system-level
overhead
100,000
—
cycle
Note:
1. Typical Erase conditions TA = 25°C, VCCf_1 & VCCf_2 = 2.9V. Typical
Program conditions TA = 25°C, VCCf_1 & VCCf_2 = 2.9V. Data= Checker
36
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
PSRAM POWER DOWN PROGRAM KEY TABLE
Basic KEY Table
Definition
KEY
A16
A17
A18
A19
A20
Mode Select
Area Select
A18
A19 A20
AREA
(3)
L
L
L
H
L
L
X
X
H
BOTTOM
RESERVED
RESERVED
H
H
(2)
H
TOP
A16
L
A17
MODE
(4)
L
H
H
H
NAP
L
RESERVED
8M Partial
H
(4,5)
SLEEP
H
Available KEY Table
A16
A17
A18
A19
Area Select
X
A20
Data Retention
MODE
Mode Select
Area
NAP
None
X
L
L
H
H
H
L
X
L
Bottom 8M Only
Top 8M only
None
L
H
X
L
L
8M Partial
SLEEP
H
X
H
X
H
Notes:
1: The Power Down Program can be performed one time after compliance of Power-up timings and it should not be
re-programmed after regular Read or Write. Unspecified addresses, A0 to A15, can be either High or Low during
the programming. The RESERVED key should not be used.
2: TOP area is from the lowest address location. (i.e., A[20:0] = H))
3: BOTTOM area is from the highest address location. (i.e., A[20:0] = L)
4: NAP and SLEEP do not retain the data and Area Select is ignored.
5: Default state. Power Down Program to this SLEEP mode can be omitted.
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PRELIMINARY INFORMATION Rev. 00D
37
03/24/03
®
IS75V16F128GS32
ISSI
PSRAM READ OPERATIONS
Parameter
Symbol
Min
Max.
Unit
Read Cycle Time
t
RC
CE
OE
AA
OH
70
—
—
—
5
—
65
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable Access Time(1,3)
Output Enable Access Time(1)
Address Access Time(1,4)
t
t
40
t
65
Output Data Hold Time(1)
t
—
—
—
20
CE1r Low to Output Low-Z(2)
OE Low to Output Low-Z(2)
t
CLZ
OLZ
5
t
0
CE1r High to Output High-Z(2)
OE High to Output High-Z(2)
Address Setup Time to CE1r Low(5)
Address Setup Time to OE(3,6)
Address Setup Time to OE(7)
LB/UB Set up Time to CE1r Low(5)
LB/UB Set up Time to OE Low
Address Invalid Time(4)
t
CHZ
—
—
-5
tOHZ
20
t
ASC
ASO
—
—
—
—
—
5
t
25
10
-5
t
ASO
(
ABS
)
t
BSC
BSO
t
-10
—
70
45
-5
t
AX
Address Hold Time from CE1r Low(4)
Address Hold Time from OE Low(4,8)
Address Hold Time from CE1r High
Address Hold Time from OE High
LB/UB Hold Time to CE1r Low
LB/UB Hold Time to OE Low
CE1r Low to OE Low Delay Time(3,6,8,9)
OE Low to CE1r High Delay Time(8)
CE1r High Pulse Width
t
CLAH
OLAH
—
—
—
—
—
—
1000
—
—
1000
—
t
t
CHAH
OHAH
CHBH
OHBH
t
-5
t
-5
t
t
-5
t
CLOL
25
45
12
25
12
OLCH
t
CP
OP
ABS
OE High Pulse Width(6,8,9)
OE High Pulse Width(7)
t
t
OP
(
)
Notes:
1. The output load is 30 pF.
2. The output load is 5 pF.
3. The tCE is applicable if OE is brought to Low before CE1r goes Low and is also applicable if actual value of both
or either tASO or tCLOL is shorter than specified value.
4. Applicable only to A0 and A1 when both CE1r and OE are kept at Low for the address access.
5. Applicable if OE is brought to Low before CE1r goes Low.
6. The tASO, tCLOL (Min) and tOP (Min) are reference values when the access time is determined by tOE.
If the actual value of each parameter is shorter than the specified minimum value, tOE becomes longer by the amount
of subtracting actual value from specified minimum value.
For example, if actual tASO, tASO (actual) , is shorter than specified minimum value, tASO (Min) , during OE control
access (i.e., CE1r stays Low) , the tOE becomes tOE (Max) + tASO (Min) - tASO (actual) .
7. The tASO[ABS] and tOP[ABS] are the absolute minimum values during OE control access.
8. If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC (Min)
- tCLOL (actual) or tRC (Min) - tOP (actual) .
9. Maximum value is applicable if CE1r is kept at Low.
38
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
PSRAM WRITE OPERATIONS
Value
Parameter
Symbol
Min.
Max.
Unit
Write Cycle Time(1)
t
WC
70
0
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Time(2)
Address Hold Time(2)
CE1r Write Setup Time
CE1r Write Hold Time
WE Setup Time
t
AS
AH
CS
t
35
0
—
t
1000
1000
—
t
CH
0
t
WS
WH
0
WE Hold Time
t
0
—
LB adnd UB Setup Time
LB adnd UB Hold Time
OE Setup Time(3)
t
BS
-5
-5
0
—
t
BH
—
t
OES
OEH
1000
1000
—
OE Hold Time(3,4)
t
25
12
-5
-5
45
45
10
10
15
0
OE Hold Time(5)
t
OEH
OHCL
OHAH
(
ABS
)
OE High to CE1r Low Setup Time(6)
OE High to Address Hold Time(7)
CE1r Write Pulse Width(1,8)
WE Write Pulse Width(1,8)
CE1r Write Recovery Time(1,9)
WE Write Recovery Time(1,3,9)
Data Setup Time
t
—
t
—
t
CW
WP
—
t
—
t
WRC
WR
—
t
1000
—
t
DS
Data Hold Time
t
DH
—
CE1r High Pulse Width(9)
t
CP
12
—
Notes:
1. Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR).
2. New write address is valid from either CE1r or WE that is brought to High.
3. Maximum value is applicable if CE1r is kept at Low and both WE and OE are kept at High.
4. The tOEH is specified from end of tWC (Min), and is a reference value when access time is determined by tOE.
If actual value is shorter than specified minimum value, tOE becomes longer by the amount of subtracting actual
value from specified minimum value.
5. The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1r stay Low.
6. tOHCL (Min) must be satisfied if read operation is not performed prior to write operation.
In case OE is disabled after tOHCL (Min), WE Low must be asserted after tRC (Min) from CE1r Low.
In other words, read operation is initiated if tOHCL (Min) is not satisfied.
7. Applicable if CE1r stays Low after read operation.
8. tCW and tWP are applicable if write operation is initiated by CE1r and WE, respectively.
9. tWRC and tWR are applicable if write operation is terminated by CE1r and WE, respectively.
The tWR (Min) can be ignored if CE1r is brought to High together or after WE is brought to High.
In such a case, the tCP (Min) must be satisfied.
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PRELIMINARY INFORMATION Rev. 00D
39
03/24/03
®
IS75V16F128GS32
ISSI
PSRAM POWER DOWN PARAMETERS
Value
Parameter
Symbol
Min.
Max.
Unit
CE2r Low Setup Time for Power down Entry
CE2r Low Hold Time after Power down Entry
t
CSP
LP
10
70
—
—
ns
ns
tC
2
CE1r High Hold Time Following CE2r High after Power down Exit
SLEEP Mode only
t
CHH
350
1
—
—
µs
µs
CE1r High Setup Time following CE2r High after Power down Exit
(Except for SLEEP Mode)
t
CHHN
CE1r High Setup Time following CE2r High after Power down Exit
CE1r High to PE Low Setup Time (1)
t
CHS
EPS
EP
EPH
10
70
70
70
15
0
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
t
PE Power Down Program Pulse Width (1)
PE High to CE1r Low Hold Time (1)
t
t
t
t
Address Setup Time to PE High (1)
EAS
EAH
Address Setup Time from PE High (1)
Note:
1. Applies to Power Down Program.
PSRAM OTHER TIMING PARAMETERS
Value
Parameter
Symbol
Min.
Max.
Unit
CE1r High to OE Invalid for Standby Entry
CE1r High to WE Invalid for Standby Entry(1)
CE2r Low Hold Time after Power-up(2)
t
CHOX
CHWX
10
10
50
50
350
1
—
—
—
—
—
25
ns
ns
µs
µs
µs
ns
t
t
C
C
2
LH
HL
CE2r High Hold Time after Power-up(3)
CE1r High Hold Time Following CE2r High after Power-up(2)
Input Transition Time(4)
t
2
t
CHH
t
T
Notes:
1. Unintended data may be written into any address location if tCHWX is not satisfied.
2. Must satisfy tCHH (Min) after tC2LH (Min) .
3. Requires Power Down mode entry and exit after tC2HL.
4. Input Transition Time (tT) at AC testing is 5 ns as shown below. If actual tT is longer than 5 ns,
it may violate some timing parameters.
PSRAM AC TEST CONDITIONS
Parameter
Symbol
Condition
Value
Unit
Input High Level
V
IH
IL
REF
VCCr = 2.7V to 3.3V
VCCr = 2.7V to 3.3V
VCCr = 2.7V to 3.3V
Between VIL and VIH
2.3
0.4
1.3
5
V
V
Input Low Level
V
Input Timing Measurement Level
Input Transition Time
V
V
t
T
ns
40
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
PSRAM READ TIMING (OE Control Access)
t
RC
tRC
ADDRESS
ADDRESS VALID
ADDRESS VALID
t
ASO
t
OHAH
t
CE
t
OHAH
CE1r
t
OE
tOLCH
t
CLOL
t
OE
OE
t
ASO
t
OP
t
BSO
t
OHBH
t
BSO
t
OHBH
LB / UB
t
OHZ
t
OHZ
t
OH
tOH
t
OLZ
t
OLZ
DQ
(Output)
VALID DATA OUTPUT
VALID DATA OUTPUT
Note: CE2r, PE and WE must be High during read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low.
PSRAM READ TIMING (CE1r Control Access)
t
RC
tRC
ADDRESS
ADDRESS VALID
ADDRESS VALID
t
ASC
t
CHAH
t
CHAH
t
ASC
tCE
t
CE
CE1r
t
CP
OE
t
BSC
t
CHBH
t
BSC
t
CHBH
LB / UB
t
CHZ
t
CHZ
t
OH
tOH
t
CLZ
t
CLZ
DQ
(Output)
VALID DATA OUTPUT
VALID DATA OUTPUT
Note: CE2r, PE and WE must be High during read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low.
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PRELIMINARY INFORMATION Rev. 00D
41
03/24/03
®
IS75V16F128GS32
ISSI
PSRAM READ TIMING (Address Access after OE Control Access)
t
RC
tRC
ADDRESS VALID
(No Change)
ADDRESS
(A20-A3)
ADDRESS VALID
ADDRESS
(A2-A0)
ADDRESS VALID
ADDRESS VALID
t
OHAH
t
ASO
t
OLAH
tAA
t
AX
CE1r
t
OE
tOHZ
OE
t
BSO
tOHBH
LB / UB
t
OH
t
OH
t
OLZ
DQ
(Output)
VALID DATA OUTPUT
VALID DATA OUTPUT
Note: CE2r, PE and WE must be High during read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low.
PSRAM READ TIMING (Address Access after CE1r Control Access)
t
RC
tRC
ADDRESS VALID
(No Change)
ADDRESS
(A20-A3)
ADDRESS VALID
ADDRESS
(A2-A0)
ADDRESS VALID
ADDRESS VALID
t
CHAH
t
CLAH
tAA
t
ASC
t
AX
CE1r
t
CHZ
t
CE
OE
t
CHBH
t
BSC
UB, LB
t
OH
t
OH
t
CLZ
DQ
(Output)
VALID DATA OUTPUT
VALID DATA OUTPUT
Note: CE2r, PE and WE must be High during read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low.
42
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PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
PSRAM WRITE TIMING (CE1r Control)
t
WC
Address Valid
Address
t
AH
t
AS
t
AS
CE1r
t
WRC
t
CW
t
WS
t
WH
BH
t
WS
WE
t
BS
t
BS
t
UB, LB
OE
t
OHCL
t
DH
t
DS
DQ
(Input)
Valid Data Input
Note: CE2r and PE must be High during write cycle.
PSRAM WRITE TIMING (WE Control, Single Write Operation)
t
WC
Address Valid
Address
t
AH
t
AS
t
OHAH
t
AS
t
CH
CE1r
t
CP
t
WP
t
OHCL
t
CS
tWR
WE
t
BS
t
OHBH
tBH
UB, LB
OE
t
OES
t
DS
tDH
t
OHz
DQ
(Input)
Valid Data Input
Note: CE2r and PE must be High during write cycle.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
43
03/24/03
®
IS75V16F128GS32
ISSI
PSRAM WRITE TIMING (WE Control, Continuous Write Operation)
t
WC
ADDRESS
Address Valid
t
AH
tAS
t
OHAH
t
AS
CE1r
t
WR
t
OHCL
t
CS
tWP
WE
t
BH
tBS
t
BH
t
BS
UB, LB
t
OES
OE
t
DS
t
DH
t
OHz
DQ
(Input)
Valid Data Input
Note: CE2r and PE must be High during write cycle.
PSRAM READ / WRITE TIMING (CE1r Control)
t
WC
ADDRESS
Write Address
Read Address
t
ASC
t
CHAH
t
AS
tAH
CE1r
t
WRC
t
CP
t
CLOL
tWS
t
WH
BH
tWS
t
WH
t
CW
WE
t
BSO
t
t
BS
t
CHBH
UB, LB
OE
t
OHCL
t
CHZ
t
OLz
t
OH
t
DS
tDH
DQ
Read Data Output
Valid Data Input
Note: Write address is valid from either CE1r or WE of last falling edge.
44
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
PSRAM READ / WRITE TIMING (CE1r Control)
t
RC
ADDRESS
Read Address
Write Address
t
ASC
t
AS
t
WRC
t
CHAH
CE1r
t
WRC (Min)
WH
tCP
t
WS
t
tCE
t
WH
tWS
WE
t
BSC
t
CHBH
tBS
t
BH
UB, LB
OE
t
OEH
t
OHCL
t
CHZ
t
CLZ
t
DH
t
OH
DQ
Read Data Output
Write Data Input
Note: The tOEH is specified from the time satisfied oth tWRC and tWR(min).
PSRAM READ / WRITE TIMING (READ = OE Control, WRITE = WE Control)
t
WC
ADDRESS
Write Address
Read Address
t
AS
t
ASO
t
OHAH
t
AH
Low
CE1r
t
OEH
t
WP
tWR
WE
t
OHBH
t
BS
tBSO
t
BH
UB, LB
OE
t
OES
OHZ
t
t
DH
t
OLZ
tOH
t
DS
DQ
Write Data Input
Read Data Output
Note: CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is
exclusively controlled by OE.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
45
03/24/03
®
IS75V16F128GS32
ISSI
PSRAM READ / WRITE TIMING (READ = OE Control, WRITE = WE Control)
t
RC
Address
Write Address
Read Address
t
ASO
t
OHAH
tAS
Low
CE1r
t
OEH
t
WR
WE
t
OHBH
t
BH
t
BSO
t
BS
UB, LB
t
OE
tOES
OE
t
OHZ
t
DH
tOH
t
OLZ
DQ
Write Data Input
Read Data Output
Note: CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is
exclusively controlled OE.
46
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
PSRAM POWER DOWN TIMING
CE1r
t
EPH
t
EPS
t
EP
PE
t
EAS
t
EAH
KEY
ADDRESS
A20-A16
Note: CE2r must be High for Power Down Programming. Any other inputs not specified above can be either
High or Low.
PSRAM STANDBY ENTRY and EXIT TIMING
CE1r
t
CHS
CE2r
DQ
t
CHH (CHHN)
t
CSP
tC2LP
High - Z
Power Down Mode
Power Down Exit
Power Down Entry
Note: This Power Down mode can be also used for Power-up Timing #2 except that tCHHN can not be used at
Power-up Timing.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
47
03/24/03
®
IS75V16F128GS32
ISSI
PSRAM POWER UP TIMING 1
CE1r
tCHS
tCHH
tC2LH
CE2r
Vccr Min
Vccr
0V
Note: The tC2LH specifies after Vccr reaches specfied minimum level.
PSRAM POWER UP TIMING 2
CE1r
tCSP
tCHS
tC2HL
tC2LP
tCHH
CE2r
Vccr
tC2HL
Vccr Min
0 V
Note: The t
specifies from CE2r Low to High transition after Vccr reaches specified minimum level. CE1r must
be brought to High prior to or together with CE2r Low to High transition.
C2HL
48
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
PSRAM DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Conditions
Min. Max.
Unit
VDR
Vccr Data Retention Supply Voltage
CE1r = CE2r ≥ VCCr -0.2V OR,
CE1r = CE2r = VIH
2.1
3.3
V
IDR
Vccr Data Retention Supply Current
Vccr Data Retention Supply Current
2.1 V ≤ VCCr ≤ 2.7 V,≥
—
1.5
mA
VIN = VIH (1) or VIL
(1)
CE1r = CE2r = VIH
,
IOUT = 0 MA
IDR1
2.1 V ≤VCCr ≤ 2.7 V,≥
VIN ≤ 0.2 V or VIN ≥ VCCr -0.2 V,
CE1r = CE2r ≥ VCCr -0.2 V
IOUT = 0 mA
—
100
µA
tDRS
Data Retention SetupTime
Data Retention RecoveryTime
VCCR Voltage Transition Time
2.7 V ≤ VCCr ≤ 3.3 V,≥
At Data Retention Entry
0
—
—
—
ns
ns
tDRR
2.7 V ≤ VCCr ≤ 3.3 V,≥
After Data Retention
200
0.2
∆V/∆t
—
V/µs
Note:
1. 2.0 V ≤ VIN ≤ VCCr + 0.3
PSRAM DATA RETENTION TIMING
t
DRS
t
DRR
3.3V
2.7V
∆V/∆t
∆V/∆t
Vccr
2.1V
CE2r
CE1r = CE2r >Vccr - 0.2V or
CE1r
V
IH(1) Min
0.4V
GND
Data Retention Mode
Data bus must be in High-Z at data retention entry
Note:
1. 2.0 V ≤ VIH ≤ VCCr + 0.3 V
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
49
03/24/03
®
IS75V16F128GS32
PIN CAPACITANCE
ISSI
Symbol
Parameter
Conditions
VIN = 0 V
VOUT = 0 V
VIN = 0 V
Min. Max.
Unit
pF
C
C
C
IN
Input Capacitance
Output Capacitance
Control Pin Capacitance
-
-
-
20
25
25
OUT
pF
IN2
pF
Notes:
1. Test conditions T
A
= +25 °C, f = 1.0 MHz
HANDLING OF PACKAGE:
Please handle this package carefully because the sides of the package have acute angles.
CAUTION:
1) The high voltage (VID) cannot be applied to address pins and control pins except RESET. Exception is when
autoselect and sector group protection function are used. Then the high voltage (VID) can be applied to RESET.
2) Without the high voltage (VID) sector group protection can be achieved by using the “Extended Sector Group
Protection” command.
50
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
®
IS75V16F128GS32
ISSI
MINI BALL GRID ARRAY – 107-Ball BGA
PACKAGE CODE: B (9.00 mm x 10.00 mm Body, 0.8 mm Ball Pitch
)
ø 0.40 + 0.10/−0.05 (107X)
1 2 3 4 5 6 7 8 9 10
10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
e
G
H
J
G
H
J
D1
K
L
D
K
L
M
M
e
E1
E
A1
A
SEATING PLANE
Symbol
Min.
1.15
0.05
9.90
—
Typ.
1.25
0.10
10.00
8.80
9.00
7.20
0.80
Max.
1.40
0.15
10.10
—
Units
A
A1
D
mm
mm
mm
mm
mm
mm
mm
D1
E
8.90
—
9.10
—
E1
e
—
—
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
51
03/24/03
®
IS75V16F128GS32
ISSI
ORDERING INFORMATION
Industrial Range: -30oC to +85oC
Flash Bank
Organization
IS75V16F128GS32-7065BI User Configurable
Flash
Speed(ns)
PSRAM
Speed(ns)
Order Part No.
Package
70
65
107-ball BGA
52
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03
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