IS80LV52-40W [ISSI]
CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER; CMOS单芯片低电压8位微控制器
| 型号： | IS80LV52-40W |
| 厂家： | 
INTEGRATED SILICON SOLUTION, INC |
| 描述： | CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER |
| 文件： | 总48页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS80LV52
ISSI
IS80LV32
CMOS SINGLE CHIP
LOW VOLTAGE
ADVANCE INFORMATION
OCTOBER 1998
8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
FEATURES
The ISSI IS80LV52 and IS80LV32 are high-performance
microcontrollers fabricated using high-density CMOS
technology. The CMOS IS80LV52/32 is functionally
compatible with the industry standard 8052/32
microcontrollers.
• 80C51 based architecture
• 8K x 8 ROM (IS80LV52 only)
• 256 x 8 RAM
TheIS80LV52/32isdesignedwith8Kx8ROM(IS80LV52
only); 256 x 8 RAM; 32 programmable I/O lines; a serial
I/O port for either multiprocessor communications, I/O
expansionorfullduplexUART;three16-bittimer/counters;
an eight-source, two-priority-level, nested interrupt
structure; and an on-chip oscillator and clock circuit. The
IS80LV52/32 can be expanded using standard TTL
compatible memory.
• Three 16-bit Timer/Counters
• Full duplex serial channel
• Boolean processor
• Four 8-bit I/O ports, 32 I/O lines
• Memory addressing capability
– 64K ROM and 64K RAM
• Program memory lock
– Encrypted verify (32 bytes)
– Lock bits (2)
• Power save modes:
– Idle and power-down
T2/P1.0
T2EX/P1.1
P1.2
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
CC
• Eight interrupt sources
2
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
• Most instructions execute in 0.3 µs
• CMOS and TTL compatible
3
P1.3
4
• Maximum speed: 40 MHz @ Vcc = 3.3V
• Industrial temperature available
P1.4
5
P1.5
6
• Packages available:
– 40-pin DIP
P1.6
7
P1.7
8
– 44-pin PLCC
– 44-pin PQFP
RST
9
RxD/P3.0
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
WR/P3.6
RD/P3.7
XTAL2
XTAL1
GND
10
11
12
13
14
15
16
17
18
19
20
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
Figure 1. IS80LV52/32 Pin Configuration:
40-pin PDIP
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best
possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
INDEX
6
5
4
3
2
1
44
43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
P1.5
P1.6
P1.7
7
8
9
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
RST 10
RxD/P3.0 11
NC 12
NC
TOP VIEW
TxD/P3.1 13
INT0/P3.2 14
INT1/P3.3 15
T0/P3.4 16
T1/P3.5 17
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
18 19 20 21 22 23 24 25 26 27 28
Figure 2. IS80LV52/32 Pin Configuration: 44-pin PLCC
2
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ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
44
43 42 41 40 39 38
37 36 35 34
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
33
32
31
30
29
29
27
26
25
24
23
P1.5
P1.6
P1.7
RST
1
2
3
4
RxD/P3.0
NC
5
NC
6
ALE
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
7
PSEN
8
P2.7/A15
P2.6/A14
P2.5/A13
9
10
11
12 13 14 15 16 17 18 19 20 21 22
Figure 3. IS80LV52/32 Pin Configuration: 44-pin PQFP
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3
ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
P2.0-P2.7
P0.0-P0.7
P2
DRIVERS
P0
DRIVERS
VCC
GND
ADDRESS
DECODER
& 256
ADDRESS 2 LOCK BITS
DECODER
&
&
P2
LATCH
P0
LATCH
32 BYTES
ENCRYPTION
RAM ADDR
REGISTER
BYTES RAM
8K ROM
PROGRAM
ADDRESS
REGISTER
STACK
POINT
B
ACC
REGISTER
PROGRAM
COUNTER
PCON SCON TMOD TCON
T2CON
TL1
TH0
TH2
TL0
TL2 RCAP2H
IE IP
TH1
TMP2
TMP1
RCAP2L SBUF
INTERRUPT
SERIAL PORT
PC
INCREMENTER
ALU
AND TIMER BLOCK
PSW
BUFFER
DPTR
PSEN
TIMING
ALE
RST
EA
AND
CONTROL
P3
LATCH
P1
LATCH
OSCILLATOR
P3
DRIVERS
P1
DRIVERS
XTAL1
XTAL2
P3.0-P3.7
P1.0-P1.7
Figure 4. IS80LV52/32 Block Diagram
4
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ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
Table 1. Detailed Pin Description
Symbol
PDIP
PLCC
PQFP
I/O
Name and Function
ALE
30
33
27
I/O
AddressLatchEnable:Outputpulseforlatchingthelowbyte
of the address during an address to the external memory. In
normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external timing or
clocking. Note that one ALE pulse is skipped during each
access to external data memory.
EA
31
35
29
I
External Access enable: EA must be externally held low to
enablethedevicetofetchcodefromexternalprogrammemory
locations 0000H to FFFFH. If EA is held high, the device
executes from internal program memory unless the program
counter contains an address greater than 0FFFH.
P0.0-P0.7 39-32
43-36
37-30
I/O
Port0:Port0isan8-bitopen-drain, bidirectionalI/Oport. Port
0 pins that have 1s written to them float and can be used as
high-impedance inputs. Port 0 is also the multiplexed low-
order address and data bus during accesses to external
program and data memory. In this application, it uses strong
internal pullups when emitting 1s.
P1.0-P1.7
1-8
2-9
40-44
1-3
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal
pullups. Port1pinsthathave1swrittentothemarepulledhigh
by the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally pulled low will source current
because of the internal pullups. (See DC Characteristics: IIL).
The Port 1 output buffers can sink/source four TTL inputs.
Port 1 also receives the low-order address byte during ROM
verification.
1
2
2
3
40
41
I
I
T2(P1.0): Timer/Counter 2 external count input.
T2EX(P1.1): Timer/Counter 2 trigger input.
P2.0-P2.7 21-28
24-31
18-25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal
pullups. Port2pinsthathave1swrittentothemarepulledhigh
by the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally pulled low will source current
because of the internal pullups. (See DC Characteristics: IIL).
Port 2 emits the high order address byte during fetches from
external program memory and during accesses to external
datamemorythatused16-bitaddresses(MOVX@DPTR). In
this application, Port 2 uses strong internal pullups when
emitting 1s. During accesses to external data memory that
use 8-bit addresses (MOVX @ Ri [i = 0, 1]), Port 2 emits the
contents of the P2 Special Function Register.
Port 2 also receives the high-order bits and some control
signals during ROM verification.
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
Table 1. Detailed Pin Description (continued)
Symbol
PDIP
PLCC
PQFP
I/O
Name and Function
P3.0-P3.7 10-17
11, 13-19
5, 7-13 I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal
pullups. Port3pinsthathave1swrittentothemarepulledhigh
by the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally pulled low will source current
because of the internal pullups. (See DC Characteristics: IIL).
Port 3 also serves the special features of the IS80LV51/31, as
listed below:
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
I
O
I
I
I
I
O
O
RxD (P3.0): Serial input port.
TxD (P3.1): Serial output port.
INT0 (P3.2): External interrupt 0.
INT1 (P3.3): External interrupt 1.
T0 (P3.4): Timer 0 external input.
T1 (P3.5): Timer 1 external input.
WR (P3.6): External data memory write strobe.
RD (P3.7): External data memory read strobe.
9
10
11
12
13
PSEN
29
32
26
O
Program Store Enable: The read strobe to external program
memory. When the device is executing code from the external
program memory, PSEN is activated twice each machine
cycle except that two PSEN activations are skipped during
each access to external data memory. PSEN is not activated
during fetches from internal program memory.
RST
9
10
21
4
I
I
Reset: A high on this pin for two machine cycles while the
oscillator is running, resets the device. An internal MOS
resistor to GND permits a power-on reset using only an
external capacitor connected to Vcc.
XTAL 1
19
15
Crystal 1: Input to the inverting oscillator amplifier and
input to the internal clock generator circuits.
XTAL 2
GND
Vcc
18
20
40
20
22
44
14
16
38
O
I
Crystal 2: Output from the inverting oscillator amplifier.
Ground: 0V reference.
I
PowerSupply:Thisisthepowersupplyvoltageforoperation.
6
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ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
OPERATING DESCRIPTION
The detail description of the IS80LV52/32 included in this indirect addressing only. Figure 6 shows internal data
description are:
memory organization and SFR Memory Map.
•Memory Map and Registers
•Timer/Counters
The lower 128 bytes of RAM can be divided into three
segments as listed below and shown in Figure 7.
1. Register Banks 0-3: locations 00H through 1FH
(32 bytes). The device after reset defaults to register
bank0. Tousetheotherregisterbanks, theusermust
select them in software. Each register bank contains
eight 1-byte registers R0-R7. Reset initializes the
stack point to location 07H, and is incremented once
to start from 08H, which is the first register of the
second register bank.
•Serial Interface
•Interrupt System
•Other Information
MEMORY MAP AND REGISTERS
Memory
TheIS80LV52/32hasseparateaddressspacesforprogram
and data memory. The program and data memory can be
up to 64K bytes long. The lower 8K program memory can
reside on-chip. (IS80LV52 only) Figure 5 shows a map of
the IS80LV52/32 program and data memory.
2. BitAddressableArea:16byteshavebeenassigned
for this segment 20H-2FH. Each one of the 128 bits of
this segment can be directly addressed (0-7FH).
Each of the 16 bytes in this segment can also be
addressed as a byte.
3. Scratch Pad Area: 30H-7FH are available to the
user as data RAM. However, if the data pointer has
been initialized to this area, enough bytes should be
left aside to prevent SP data destruction.
The IS80LV52/32 has 256 bytes of on-chip RAM, plus
numbers of special function registers. The lower 128 bytes
can be accessed either by direct addressing or by indirect
addressing. The upper 128 bytes can be accessed by
Program Memory
(Read Only)
Data Memory
(Read/Write)
FFFFH:
FFFFH:
64K
External
Internal
FFH:
1FFFH:
8K
EA = 1
Internal
(IS80C52
Only)
EA = 0
External
00
0000
0000
PSEN
RD WR
Figure 5. IS80LV52/32 Program and Data Memory Structure
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ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFR's) are located in
upper128Bytesdirectaddressingarea.TheSFRMemory
Map in Figure 6 shows that.
Accumulator (ACC)
ACC is the Accumulator register. The mnemonics for
Accumulator-specific instructions, however, refer to the
Accumulator simply as A.
Not all of the addresses are occupied. Unoccupied
addresses are not implemented on the chip. Read
accesses to these addresses in general return random
data, and write accesses have no effect.
B Register (B)
TheBregisterisusedduringmultiplyanddivideoperations.
For other instructions it can be treated as another scratch
pad register.
Usersoftwareshouldnotwrite1stotheseunimplemented
locations,sincetheymaybeusedinfuturemicrocontrollers
to invoke new features. In that case, the reset or inactive
values of the new bits will always be 0, and their active
values will be 1.
ProgramStatusWord(PSW).ThePSWregistercontains
program status information.
The functions of the SFRs are outlined in the following
sections, and detailed in Table 2.
FFH
FFH
FF
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
B
F7
EF
E7
DF
D7
CF
C7
BF
B7
AF
A7
9F
97
ACC
Accessible
by Indirect
Addressing
Only
Accessible
by Direct
Addressing
Upper
128
PSW
T2CON
RCAP2L RCAP2H
TL2
TH0
TH2
TH1
IP
P3
IE
P2
SCON
P1
80H
7FH
80H
SBUF
Accessible
by Direct
and Indirect
Addressing
TCON
P0
8F
87
TMOD
SP
TL0
TL1
Ports,
Lower
128
PCON
DPL
DPH
Status and
Control Bits,
Timer,
Special
Function
Registers,
Stack Pointer,
Accumulator
(Etc.)
Bit
Registers
Addressable
0
Figure 6. Internal Data Memory and SFR Memory Map
8 BYTES
78
70
68
60
58
50
48
40
38
30
28
20
18
10
08
00
7F
77
6F
67
5F
57
4F
47
3F
37
2F
27
1F
17
0F
07
SCRATCH
PAD
AREA
BIT
...7F
ADDRESSABLE
SEGMENT
0 ...
BANK3
BANK2
BANK 1
BANK 0
REGISTER
BANKS
Figure 7. Lower 128 Bytes of Internal RAM
8
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ADVANCE INFORMATION MC019-0A
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IS80LV52
IS80LV32
®
ISSI
SPECIAL FUNCTION REGISTERS
(continued)
Stack Pointer (SP)
initiatesthetransmission.)WhendataismovedfromSBUF,
it comes from the receive buffer.
TheStackPointerRegisteriseightbitswide.Itisincremented
before data is stored during PUSH and CALL executions.
While the stack may reside anywhere in on-chip RAM, the
Stack Pointer is initialized to 07H after a reset. This causes
the stack to begin at location 08H.
Timer Registers
Register pairs (TH0, TL0), (TH1, TL1), and (TH2, TL2) are
the 16-bit Counter registers for Timer/Counters 0, 1, and 2,
respectively.
Data Pointer (DPTR)
The Data Pointer consists of a high byte (DPH) and a low
byte(DPL). Itsfunctionistoholda16-bitaddress. Itmaybe
manipulated as a 16-bit register or as two independent
8-bit registers.
Capture Registers
The register pair (RCAP2H, RCAP2L) are the Capture
registers for the Timer 2 Capture Mode. In this mode, in
response to a transition at the IS80LV52/32's T2EX pin,
TH2andTL2arecopiedintoRCAP2HandRCAP2L. Timer
2 also has a 16-bit auto-reload mode, and RCAP2H and
RCAP2L hold the reload value for this mode.
Ports 0 To 3
P0, P1, P2, and P3 are the SFR latches of Ports 0, 1, 2, and
3, respectively.
Control Registers
Serial Data Buffer (SBUF)
Special Function Registers IP, IE, TMOD, TCON, T2CON,
SCON, and PCON contain control and status bits for the
interrupt system, the Timer/Counters, and the serial port.
They are described in later sections of this chapter.
The Serial Data Buffer is actually two separate registers, a
transmit buffer and a receive buffer register. When data is
moved to SBUF, it goes to the transmit buffer, where it is
held for serial transmission. (Moving a byte to SBUF
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ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
Table 2: Special Function Register
Symbol
Description
Direct Address
Bit Address, Symbol, or Alternative Port Function
Reset Value
ACC(1)
B(1)
Accumulator
B register
E0H
F0H
83H
82H
E7
F7
E6
F6
E5
F5
E4
F4
E3
F3
E2
F2
E1
F1
E0
F0
00H
00H
00H
00H
DPH
DPL
Data pointer (DPTR) high
Data pointer (DPTR) low
AF
EA
AE
—
AD
ET2
AC
ES
AB
AA
A9
A8
IE(1)
IP(1)
P0(1)
Interrupt enable
Interrupt priority
Port 0
A8H
B8H
80H
ET1 EX1 ET0 EX0
BB BA B9 B8
PT1 PX1 PT0 PX0
83 82 81 80
0X000000B
XX000000B
FFH
BF
—
BE
—
BD
PT2
BC
PS
87
86
85
84
P0.7 P0.6
AD7 AD6
P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
AD5 AD4 AD3 AD2 AD1 AD0
97
96
95
94
93
92
91
90
P1(1)
P2(1)
Port 1
Port 2
90H
A0H
P1.7 P1.6
—
P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
—
FFH
FFH
—
—
—
—
T2EX T2
A1 A0
A7
A6
A5
A4
A3
A2
P2.7 P2.6
AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8
B7 B6 B5 B4 B3 B2 B1 B0
P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
P3(1)
Port 3
B0H
87H
FFH
RD
WR
T1
T0
INT1 INT0 TXD RXD
PCON
Power control
SMOD
—
—
—
GF1 GF0 PD
IDL
0XXX0000B
D7
CY
D6
AC
D5
F0
D4
D3
D2
OV
D1
—
D0
P
PSW(1)
SBUF
Program status word
Serial data buffer
D0H
99H
RS1 RS0
00H
XXXXXXXXB
9F
9E
9D
9C
9B
9A
99
TI
98
RI
SCON(1)
SP
Serial controller
Stack pointer
98H
81H
SM0 SM1
SM2 REN TB8 RB8
00H
07H
8F
TF1
8E
TR1
8D
TF0
8C
TR0
8B
IE1
8A
IT1
89
IE0
88
IT0
TCON(1)
TMOD
Timer control
Timer mode
88H
89H
00H
00H
GATE C/T
CF CE
M1
M0 GATE C/T M1
CC CB CA C9
M0
CD
C8
T2CON(1,2)
TH0
Timer/Counter 2
Timer high 0
Timer high 1
Timer high 2
Timer low 0
C8H
8CH
8DH
CDH
8AH
8BH
CAH
CBH
CCH
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
00H
00H
00H
00H
00H
00H
00H
00H
00H
TH1
TH2(2)
TL0
TL1
Timer low 1
RCAP2H(2)
RCAP2L(2)
TL2(2)
Capture high
Capture low
Timer low 2
Notes:
1. Denotes bit addressable.
2. SFRs are added to the 80C51 SFRs.
10
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ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
The detail description of each bit is as follows:
IE:
Interrupt Enable Register. Bit Addressable.
PSW:
Program Status Word. Bit Addressable.
7
6
5
4
3
2
1
0
EA
—
ET2
ES
ET1 EX1 ET0 EX0
7
6
5
4
3
2
1
0
CY AC
F0
RS1 RS0
OV
—
P
Register Description:
EA
IE.7
Disable all interrupts. If EA=0, no
interrupt will be acknowledged. If
EA=1, each interrupt source is
individually enabled or disabled by
setting or clearing its enable bit.
Register Description:
CY
AC
F0
PSW.7
PSW.6
PSW.5
Carry flag.
Auxiliary carry flag.
Flag 0 available to the user for
general purpose.
—
IE.6
Not implemented, reserve for future
use.(5)
RS1 PSW.4
RS0 PSW.3
Register bank selector bit 1.(1)
Register bank selector bit 0.(1)
Overflow flag.
ET2 IE.5
ES IE.4
Enables or disables timer 2 overflow
interrupt.
OV
—
P
PSW.2
PSW.1
PSW.0
Usable as a general purpose flag
Enable or disable the serial port
interrupt.
Parity flag. Set/Clear by hardware each
instruction cycle to indicate an odd/even
number of “1” bits in the accumulator.
ET1 IE.3
Enable or disable the timer 1 overflow
interrupt.
Note:
EX1 IE.2
ET0 IE.1
Enable or disable external interrupt 1.
1. The value presented by RS0 and RS1 selects the corre-
sponding register bank.
Enable or disable the timer 0 overflow
interrupt.
RS1
RS0
Register Bank
Address
EX0 IE.0
Enable or disable external interrupt 0.
0
0
1
1
0
1
0
1
0
1
2
3
00H-07H
08H-0FH
10H-17H
18H-1FH
Note:
To use any of the interrupts in the 80C51 Family, the following
three steps must be taken:
1. Set the EA (enable all) bit in the IE register to 1.
2. Set the coresponding individual interrupt enable bit in the IE
register to 1.
3. Begin the interrupt service routine at the corresponding
Vector Address of that interrupt (see below).
PCON:
Power Control Register. Not Bit Addressable.
7
6
5
4
3
2
1
0
Interrupt Source
Vector Address
0003H
SMOD —
—
—
GF1 GF0
PD IDL
IE0
TF0
000BH
Register Description:
IE1
0013H
SMOD
Doublebaudratebit. IfTimer1isusedtogenerate
baud rate and SMOD=1, the baud rate is doubled
when the serial port is used in modes 1, 2, or 3.
Not implemented, reserve for future use.(1)
Not implemented, reserve for future use.(1)
Not implemented, reserve for future use.(1)
General purpose flag bit.
TF1
001BH
RI & TI
TF2 and EXF2
0023H
—
002BH
—
4. In addition, for external interrupts, pins INT0 and INT1 (P3.2
and P3.3) must be set to 1, and depending on whether the
interrupt is to be level or transition activated, bits IT0 or IT1
in the TCON register may need to be set to 0 or 1.
ITX = 0 level activated (X = 0, 1)
ITX = 1 transition activated
5. User software should not write 1s to reserved bits. These bits
may be used in future products to invoke new features.
—
GF1
GF0
PD
General purpose flag bit.
Power-downbit.Settingthisbitactivatespower-
down operation in the IS80LV52/32.
IDL
Idlemodebit. Settingthisbitactivatesidlemode
operationintheIS80LV52/32.If1sarewrittento
PD and IDL at the same time, PD takes
precedence.
Note:
1. User software should not write 1s to reserved bits. These bits
may be used in future products to invoke new features.
Integrated Silicon Solution, Inc. — 1-800-379-4774
11
ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
IP:
TCON:
Interrupt Priority Register. Bit Addressable.
Timer/Counter Control Register. Bit Addressable
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
—
—
PT2
PS
PT1 PX1 PT0 PX0
TF1 TR1 TF0 TR0
Register Description:
IE1
IT1
IE0 IT0
Register Description:
—
—
IP.7
IP.6
Notimplemented,reserveforfutureuse(3)
Notimplemented,reserveforfutureuse(3)
Defines Timer 2 interrupt priority level
Defines Serial Port interrupt priority level
Defines Timer 1 interrupt priority level
Defines External Interrupt 1 priority level
Defines Timer 0 interrupt priority level
Defines External Interrupt 0 priority level
TF1 TCON.7 Timer1overflowflag.Setbyhardware
when the Timer/Counter 1 overflows.
Cleared by hardware as processor
vectorstotheinterruptserviceroutine.
PT2 IP.5
PS IP.4
TR1 TCON.6 Timer1runcontrolbit. Set/Clearedby
software to turn Timer/Counter 1 ON/
OFF.
PT1 IP.3
PX1 IP.2
PT0 IP.1
PX0 IP.0
Notes:
TF0 TCON.5 Timer0overflowflag.Setbyhardware
when the Timer/Counter 0 overflows.
Cleared by hardware as processor
vectorstotheinterruptserviceroutine.
1. In order to assign higher priority to an interrupt the
coresponding bit in the IP register must be set to 1. While an
interrupt service is in progress, it cannot be interrupted by a
lower or same level interrupt.
TR0 TCON.4 Timer0runcontrolbit. Set/Clearedby
software to turn Timer/Counter 0 ON/
OFF.
2. Priority within level is only to resolve simultaneous requests
of the same priority level. From high to low, interrupt sources
are listed below:
IE0
TF0
IE1 TCON.3 External Interrupt 1 edge flag. Set by
hardware when the External Interrupt
edgeisdetected.Clearedbyhardware
when interrupt is processed.
IE1
TF1
RI or TI
TF2 or EXF2
IT1
TCON.2 Interrupt1typecontrolbit.Set/Cleared
by software specify falling edge/low
level triggered External Interrupt.
3. User software should not write 1s to reserved bits. These bits
may be used in future products to invoke new features.
IE0 TCON.1 External Interrupt 0 edge flag. Set by
hardware when the External Interrupt
edgeisdetected.Clearedbyhardware
when interrupt is processed.
IT0
TCON.0 Interrupt0typecontrolbit.Set/Cleared
by software specify falling edge/low
level triggered External Interrupt.
12
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ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
TMOD:
Timer/Counter Mode Control Register.
Not Bit Addressable.
SCON:
Serial Port Control Register. Bit Addressable.
7
6
5
4
3
2
1
0
SM0 SM1 SM2 REN TB8 RB8
TI
RI
Timer 1
GATE C/T M1 M0
Timer 0
GATE C/T M1 M0
Register Description:
SM0 SCON.7 Serial port mode specifier.(1)
SM1 SCON.6 Serial port mode specifier.(1)
GATE WhenTRx(inTCON)issetandGATE=1,TIMER/
COUNTERx will run only while INTx pin is high
(hardware control). When GATE=0, TIMER/
COUNTERx will run only while TRx=1 (software
control).
SM2 SCON.5 Enable the multiprocessor com-
municationfeatureinmode2and3. In
mode 2 or 3, if SM2 is set to 1 then RI
will not be activated if the received 9th
data bit (RB8) is 0. In mode 1, if
SM2=1 then RI will not be activated if
valid stop bit was not received. In
mode 0, SM2 should be 0.
C/T
Timer or Counter selector. Cleared for Timer
operation (input from internal system clock). Set
for Counter operation (input from Tx input pin).
M1
M0
Mode selector bit.(1)
Mode selector bit.(1)
REN SCON.4 Set/Cleared by software to Enable/
Disable reception.
Note 1:
M1 M0 Operating mode
TB8 SCON.3 The 9th bit that will be transmitted in
mode 2 and 3. Set/Cleared by
software.
0
0
1
1
0
1
0
1
Mode 0. (13-bit Timer)
Mode 1. (16-bit Timer/Counter)
Mode 2. (8-bit auto-load Timer/Counter)
RB8 SCON.2 In modes 2 and 3, RB8 is the 9th data
bit that was received. In mode 1, if
Mode 3. (Splits Timer 0 into TL0 and
TH0. TL0 is an8-bitTimer/Countercon-
troller by the standard Timer 0 control
bits. TH0 is an 8-bit Timer and is con-
trolled by Timer 1 control bits.)
SM2=0, RB8 is the stop bit that was
received. In mode 0, RB8 is not used.
TI
RI
SCON.1 Transmit interrupt flag. Set by
hardware at the end of the 8th bit time
in mode 0, or at the beginning of the
stop bit in the other modes. Must be
cleared by software.
1
1
Mode 3. (Timer/Counter 1 stopped).
SCON.0 Receiveinterruptflag.Setbyhardware
at the end of the 8th bit time in mode
0, or halfway through the stop bit time
in the other modes (except see SM2).
Must be cleared by software.
Note:
SM0 SM1 MODE Description
Baud rate
Fosc/12
0
0
1
0
1
0
0
1
2
Shift register
8-bit UART
9-bit UART
Variable
Fosc/64 or
Fosc/32
1
1
3
9-bit UART
Variable
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13
ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
T2CON:
Timer/Counter 2 Control Register. Bit Addressable.
7
6
5
4
3
2
1
0
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
Register Description:
TF2 T2CON.7 Timer 2 overflow flag set by hardware
and cleared by software. TF2 cannot
be set when either RCLK = 1 or TCLK
= 1.
EXF2 T2CON.6 Timer2externalflagsetwheneithera
capture or reload is caused by a
negative transition on T2EX, and
EXEN2 = 1. When Timer 2 interrupt is
enabled, EXF2 = 1 causes the CPU to
vector to the Timer 2 interrupt routine.
EXF2 must be cleared by software.
RCLK T2CON.5 Receive clock flag. When set, causes
theSerialPorttouseTimer2overflow
pulses for its receive clock in modes 1
and 3. RCLK = 0 causes Timer 1
overflow to be used for the receive
clock.
TLCK T2CON.4 Transmitclockflag.Whenset,causes
theSerialPorttouseTimer2overflow
pulses for its transmit clock in modes
1 and 3. TCLK = 0 causes Timer 1
overflows to be used for the transmit
clock.
EXEN2 T2CON.3 Timer 2 external enable flag. When
set,allowsacaptureorreloadtooccur
as a result of negative transition on
T2EX if Timer 2 is not being used to
clock the Serial Port, EXEN2 = 0
causes Timer 2 to ignore events at
T2EX.
TR2 T2CON.2 Software START/STOP control for
Timer 2. A logic 1 starts the Timer.
C/T2 T2CON.1 Timer or Counter select. 0 = Internal
Timer. 1 = External Event Counter
(triggered by falling edge).
CP/RL2 T2CON.0 Capture/Reload flag. When set,
capturesoccuronnegativetransitions
at T2EX if EXEN2 = 1. When cleared,
auto-reloadsoccureitherwithTimer2
overflows or negative transitions at
T2EX when EXEN2 = 1. When either
RCLK = 1 or TCLK = 1, this bit is
ignored and the Timer is forced to
auto-reload on Timer 2 overflow.
Notes:
1. Timer 2 Operating Modes
RCLK + TCLKCP/RL2 TR2 MODE
0
0
1
X
0
1
1
1
1
0
16-Bit Auto-Reload
16-Bit Capture
Baud Rate Generator
(Off)
X
X
2. User software should not write 1s to reserved bits. These bits
may be used in future products to invoke new features.
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
TIMER/COUNTERS
Timer 0 and Timer 1
Timer/Counters0and1arepresentinboththeIS80LV51/
31 and IS80LV52/32. The Timer or Counter function is
selected by control bits C/T in the Special Function
Regiser TMOD. These two Timer/Counters have four
operatingmodes, whichareselectedbybitpairs(M1, M0)
in TMOD. Modes 0, 1, and 2 are the same for both Timer/
Counters, but Mode 3 is different. The four modes are
described in the following sections.
TheIS80LV52/32hasthree16-bitTimer/Counterregisters:
Timer 0, Timer 1, and in addition Timer 2. All three can be
configured to operate either as Timers or event Counters.
As a Timer, the register is incremented every machine
cycle. Thus, the register counts machine cycles. Since a
machine cycle consists of 12 oscillator periods, the count
rate is 1/12 of the oscillator frequency.
As a Counter, the register is incremented in response to
a 1-to-0 transition at its corresponding external input pin,
T0,T1,andT2.TheexternalinputissampledduringS5P2
of every machine cycle. When the samples show a high
in one cycle and a low in the next cycle, the count is
incremented. Thenewcountvalueappearsintheregister
during S3P1 of the cycle following the one in which the
transition was detected. Since two machine cycles (24
oscillator periods) are required to recognize a 1-to-0
transition, the maximum count rate is 1/24 of the oscillator
frequency. There are no restrictions on the duty cycle of
the external input signal, but it should be held for at least
one full machine cycle to ensure that a given level is
sampled at least once before it changes.
Mode 0:
BothTimersinMode0are8-bitCounterswithadivide-by-
32 prescaler. Figure 8 shows the Mode 0 operation as it
applies to Timer 1.
In this mode, the Timer register is configured as a 13-bit
register. As the count rolls over from all 1s to all 0s, it sets
the Timer interrupt flag TF1. The counted input is enabled
to the Timer when TR1 = 1 and either GATE = 0 or INT1
= 1. Setting GATE = 1 allows the Timer to be controlled by
externalinputINT1,tofacilitatepulsewidthmeasurements.
TR1 is a control bit in the Special Function Register
TCON. Gate is in TMOD.
The 13-bit register consists of all eight bits of TH1 and the
lower five bits of TL1. The upper three bits of TL1 are
indeterminate and should be ignored. Setting the run flag
(TR1) does not clear the registers.
In addition to the Timer or Counter functions, Timer 0 and
Timer 1 have four operating modes: (13-bit timer, 16-bit
timer, 8-bit auto-reload, split timer). Timer 2 in the
IS80LV52/32 has three modes of operation: Capture,
Auto-Reoload, and Baud Rate Generator.
Mode 0 operation is the same for Timer 0 as for Timer 1,
exceptthatTR0, TF0andINT0 replacethecorresponding
Timer 1 signals in Figure 8. There are two different GATE
bits, one for Timer 1 (TMOD.7) and one for Timer 0
(TMOD.3).
ONE MACHINE
CYCLE
ONE MACHINE
CYCLE
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1
P1P2 P1 P2
P2
OSC
(XTAL2)
OSC
DIVIDE 12
C/T = 0
TL1
TH1
INTERRUPT
TF1
(5 BITS) (8 BITS)
C/T = 1
T1 PIN
CONTROL
TR1
GATE
INT1 PIN
Figure 8. Timer/Counter 1 Mode 0: 13-Bit Counter
TIMER
CLOCK
TL1
(8 BITS)
TH1
(8 BITS)
TF1
OVERFLOW
FLAG
Figure 9. Timer/Counter 1 Mode 1: 16-Bit Counter
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15
ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
Mode 1:
Mode 3:
Mode 1 is the same as Mode 0, except that the Timer
register is run with all 16 bits. The clock is applied to the
combined high and low timer registers (TL1/TH1). As
clock pulses are received, the timer counts up: 0000H,
0001H, 0002H, etc. An overflow occurs on the FFFFH-to-
0000H overflow flag. The timer continues to count. The
overflow flag is the TF1 bit in TCON that is read or written
by software (see Figure 9).
Timer 1 in Mode 3 simply holds its count. The effect is the
same as setting TR1 = 0. Timer 0 in Mode 3 establishes
TL0 and TH0 as two separate counters. The logic for
Mode 3 on Timer 0 is shown in Figure 10. TL0 uses the
Timer0controlbits:C/T, GATE, TR0, INT0, andTF0. TH0
is locked into a timer function (counting machine cycles)
and over the use of TR1 and TF1 from Timer 1. Thus, TH0
now controls the Timer 1 interrupt.
Mode 3 is for applications requiring an extra 8-bit timer or
counter. With Timer 0 in Mode 3, the IS80LV51/31 can
appear to have three Timer/Counters, and an IS80LV52/
32 can appear to have four. When Timer 0 is in Mode 3,
Timer 1 can be turned on and off by switching it out of and
into its own Mode 3. In this case, Timer 1 can still be used
by the serial port as a baud rate generator or in any
application not requiring an interrupt.
Mode 2:
Mode 2 configures the Timer register as an 8-bit Counter
(TL1) with automatic reload, as shown in Figure 10.
OverflowfromTL1notonlysetsTF1, butalsoreloadsTL1
with the contents of TH1, which is preset by software. The
reload leaves the TH1 unchanged. Mode 2 operation is
the same for Timer/Counter 0.
OSC
DIVIDE 12
C/T = 0
C/T = 1
TL1
(8 BITS)
INTERRUPT
TF1
T1 PIN
RELOAD
CONTROL
TR1
GATE
TH1
(8 BITS)
INT0 PIN
Figure 10. Timer/Counter 1 Mode 2: 8-Bit Auto-Reload
OSC
DIVIDE 12
1/12F OSC
C/T = 0
1/12F OSC
TL0
(8 BITS)
INTERRUPT
TF0
C/T = 1
T0 PIN
CONTROL
TR0
GATE
INT0 PIN
TH0
(8 BITS)
1/12F OSC
TF1
INTERRUPT
TR1
CONTROL
Figure 11. Timer/Counter 0 Mode 3: Two 8-Bit Counters
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
Timer 2
captured into the RCAP2L and RCAP2H registers,
respectively. In addition, the transition at T2EX sets the
EXF2 bit in T2CON, and EXF2, like TF2, can generate an
interrupt.
Timer 2 is a 16-bit Timer/Counter present only in the
IS80LV52/32. This is a powerful addition to the other two
just discussed. Five extra special function registers are
added to accommodate Timer 2 which are: the timer
registers,TL2andTH2,thetimercontrolregister,T2CON,
and the capture registers, RCAP2L and RCAP2H. Like
Timers 0 and 1, it can operate either as a timer or as an
event counter, depending on the value of bit C/T2 in the
Special Function Register T2CON. Timer 2 has three
operating modes: capture, auto-reload, and baud rate
generator, which are selected by RCLK, TCLK, CP/RL2
and TR2.
The Capture Mode is illustrated in Figure 12.
In the auto-reload mode, the EXEN2 bit in T2CON also
selects two options. If EXEN2 = 0, then when Timer 2 rolls
overitsetsTF2andalsoreloadstheTimer2registerswith
the 16-bit value in the RCAP2L and RCAP2H registers,
which are preset by software. If EXEN2 = 1, then Timer 2
performs the same way, but a 1-to-0 transition at external
input T2EX also triggers the 16-bit reload and sets EXF2.
The auto-reload mode is illustrated in Figure 13.
IntheCaptureMode,theEXEN2bitinT2CONselectstwo
options. If EXEN2 = 0, then Timer 2 is a 16-bit timer or
counterwhoseoverflowsetsbitTF2, theTimer2overflow
bit, which can be used to generate an interrupt. If EXEN2
= 1, then Timer 2 performs the same way, but a 1-to-0
transition at external input T2EX also causes the current
value in the Timer 2 registers, TL2 and TH2, to be
The baud rate generator mode is selected by RCLK = 1
and/or TCLK = 1. This mode is described in conjunction
with the serial port (Figure 14).
OSC
DIVIDE 12
C/T2 = 0
C/T2 = 1
TL2
TH2
TF2
(8 BITS) (8 BITS)
CONTROL
TR2
CAPTURE
T2 PIN
TIMER 2
INTERRUPT
TRANSITION
DETECTOR
RCAP2L RCAP2H
T2EX PIN
EXF2
CONTROL
EXEN2
Figure 12. Timer 2 In Capture Mode
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17
ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
OSC
DIVIDE 12
C/T2 = 0
C/T2 = 1
TL2
TH2
(8 BITS) (8 BITS)
CONTROL
TR2
RELOAD
T2 PIN
TF2
RCAP2L RCAP2H
TRANSITION
DETECTOR
TIMER 2
INTERRUPT
T2EX PIN
EXF2
CONTROL
EXEN2
Figure 13. Timer 2 in Auto-Reload Mode
TIMER 1
OVERFLOW
NOTE: OSC FREQ.
IS DIV BY 2, NOT 12
DIVIDE 2
"0"
"1"
OSC
DIVIDE 2
C/T2 = 0
SMOD
RCLK
"1"
"1"
"0"
"0"
TL2
TH2
(8 BITS) (8 BITS)
C/T2 = 1
T2 PIN
CONTROL
TR2
DIVIDE 16
TCLK
DIVIDE 16
RX CLOCK
RELOAD
RCAP2L RCAP2H
TRANSITION
DETECTOR
TX CLOCK
TIMER 2
INTERRUPT
T2EX PIN
EXF2
CONTROL
EXEN2
Figure 14. Timer 2 in Baud Rate Generator Mode
Note:
1. T2EX can be used as an additional external interrupt.
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
Timer Set-Up
Table 5. Timer/Counter 1 Used as a Timer
Tables 3 through 6 give TMOD values that can be used to
set up Timers in different modes.
TMOD
Mode
Timer 1
Function
Internal
External
Control(1)
Control(2)
It assumes that only one timer is used at a time. If Timers
0 and 1 must run simultaneously in any mode, the value
in TMOD for Timer 0 must be ORed with the value shown
for Timer 1 (Tables 5 and 6).
0
1
2
3
13-Bit Timer
16-Bit Timer
00H
10H
20H
30H
80H
90H
A0H
B0H
For example, if Timer 0 must run in Mode 1 GATE
(external control), and Timer 1 must run in Mode 2
COUNTER, then the value that must be loaded into
TMOD is 69H (09H from Table 3 ORed with 60H from
Table 6).
8-Bit Auto-Reload
Does Not Run
Table 6. Timer/Counter 1 Used as a Counter
TMOD
Moreover, it is assumed that the user is not ready at this
point to turn the timers on and will do so at another point
in the program by setting bit TRx (in TCON) to 1.
Mode
Timer 1
Internal
External
Function
Control(1)
Control(2)
Table 3. Timer/Counter 0 Used as a Timer
TMOD
0
13-Bit Timer
16-Bit Timer
40H
50H
60H
—
C0H
D0H
E0H
—
1
Mode
Timer 0
Function
Internal
External
Control(1) Control(2)
2
3
8-Bit Auto-Reload
Not Available
0
1
2
3
13-Bit Timer
16-Bit Timer
00H
01H
02H
03H
08H
09H
0AH
0BH
Notes:
1. TheTimeristurnedON/OFFbysetting/clearingbitTR1inthe
software.
2. The Timer is turned ON/OFF by the 1 to 0 transition on INT1
(P3.3) when TR1 = 1 (hardware control).
8-Bit Auto-Reload
Two 8-Bit Timers
Table 4. Timer/Counter 0 Used as a Counter
TMOD
Mode
Timer 0
Function
Internal
External
Control(1)
Control(2)
0
13-Bit Timer
16-Bit Timer
04H
05H
06H
07H
0CH
0DH
0EH
0FH
1
2
3
8-Bit Auto-Reload
One 8-Bit Counter
Notes:
1. TheTimeristurnedON/OFFbysetting/clearingbitTR0inthe
software.
Integrated Silicon Solution, Inc. — 1-800-379-4774
19
ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
Timer/Counter 2 Set-Up
SERIAL INTERFACE
Exceptforthebaudrategeneratormode,thevaluesgiven
for T2C0N do not include the setting of the TR2 bit.
Therefore, bit TR2 must be set separately to turn the
Timer on.
The Serial port is full duplex, which means it can transmit
and receive simultaneously. It is also receive-buffered,
which means it can begin receiving a second byte before
apreviouslyreceivedbytehasbeenread fromthereceive
register. (However, if the first byte still has not been read
when reception of the second byte is complete, one of the
bytes will be lost.) The serial port receive and transmit
registers are both accessed at Special Function Register
SBUF. Writing to SBUF loads the transmit register, and
reading SBUF accesses a physically separate receive
register.
Table 7. Timer/Counter 2 Used as a Timer
T2CON
Mode
Internal
External
Control(1) Control(2)
16-Bit Auto-Reload
08H
00H
The serial port can operate in the following four modes:
16-Bit Capture
01H
34H
09H
36H
Mode 0:
Baud Rate Generator Receive
and Transmit Same Baud Rate
Serial data enters and exits through RXD. TXD outputs
the shift clock. Eight data bits are transmitted/received,
with the LSB first. The baud rate is fixed at 1/12 the
oscillator frequency (see Figure 15).
Receive Only
Transmit Only
24H
14H
26H
16H
Mode 1:
Tenbitsaretransmitted(throughTXD)orreceived(through
RXD): a start bit (0), eight data bits (LSB first), and a stop
bit (1). On receive, the stop bit goes into RB8 in Special
Function Register SCON. The baud rate is variable (see
Figure 16).
Table 8. Timer/Counter 2 Used as a Counter
TMOD
Mode
Internal
External
Control(1) Control(2)
Mode 2:
16-Bit Auto-Reload
0AH
02H
Eleven bits are transmitted (through TXD) or received
(through RXD): a start bit (0), eight data bits (LSB first), a
programmableninthdatabit, andastopbit(1). Ontransmit,
the ninth data bit (TB8 in SCON) can be assigned the value
of 0 or 1. Or, for example, the parity bit (P, in the PSW) can
be moved into TB8. On receive, the ninth data bit goes into
RB8 in Special Function Register SCON, while the stop bit
is ignored. The baud rate is programmable to either 1/32 or
1/64 the oscillator frequency (see Figure 17).
16-Bit Capture
03H
0BH
Notes:
1. Capture/Reload occurs only on Timer/Counter overflow.
2. Capture/ReloadoccursonTimer/Counteroverflowanda1to
0 transition on T2EX (P1.1) pin except when Timer 2 is used
in the baud rate generating mode.
Mode 3:
Eleven bits are transmitted (through TXD) or received
(through RXD): a start bit (0), eight data bits (LSB first), a
programmable ninth data bit, and a stop bit (1). In fact,
Mode 3 is the same as Mode 2 in all respects except the
baud rate, which is variable in Mode 3 (see Figure 18).
Inallfourmodes,transmissionisinitiatedbyanyinstruction
that uses SBUF as a destination register. Reception is
initiated in Mode 0 by the condition RI = 0 and REN = 1.
Reception is initiated in the other modes by the incoming
start bit if REN = 1.
20
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
Using the Timer 1 to Generate Baud Rates
MULTIPROCESSOR COMMUNICATIONS
When Timer 1 is the baud rate generator, the baud rates
in Modes 1 and 3 are determined by the Timer 1 overflow
rate and the value of SMOD according to the following
equation.
Modes2and3haveaspecialprovisionformultiprocessor
communications. In these modes, nine data bits are
received, followed by a stop bit. The ninth bit goes into
RB8; then comes a stop bit. The port can be programmed
such that when the stop bit is received, the serial port
interrupt is activated only if RB8 = 1. This feature is
enabled by setting bit SM2 in SCON.
Mode 1, 3
Baud Rate
2SMOD
32
=
(Timer 1 Overflow Rate)
X
The following example shows how to use the serial
interrupt for multiprocessor communications. When the
master processor must transmit a block of data to one of
several slaves, it first sends out an address byte that
identifies the target slave. An address byte differs from a
data byte in that the ninth bit is 1 in an address byte and
0 in a data byte. With SM2 = 1, no slave is interrupted by
a data byte. An address byte, however, interrupts all
slaves, so that each slave can examine the received byte
and see if it is being addressed. The addressed slave
clears its SM2 bit and prepares to receive the data bytes
that follows. The slaves that are not addressed set their
SM2 bits and ignore the data bytes.
TheTimer1interruptshouldbedisabledinthisapplication.
The Timer itself can be configured for either timer or
counter operation in any of its 3 running modes. In the
mosttypicalapplications,itisconfiguredfortimeroperation
in auto-reload mode (high nibble of TMOD = 0010B). In
this case, the baud rate is given by the following formula.
Mode 1,3
2SMOD
32
Oscillator Frequency
12x [256-(TH1)]
=
X
Baud Rate
ProgrammerscanachieveverylowbaudrateswithTimer
1 by leaving the Timer 1 interrupt enabled, configuring the
Timer to run as a 16-bit timer (high nibble of TMOD =
0001B), and using the Timer 1 interrupt to do a 16-bit
software reload.
SM2 has no effect in Mode 0 but can be used to check the
validity of the stop bit in Mode 1. In a Mode 1 reception, if
SM2 = 1, the receive interrupt is not activated unless a
valid stop bit is received.
Table9listscommonlyusedbaudratesandhowtheycan
be obtained from Timer 1.
Baud Rates
The baud rate in Mode 0 is fixed as shown in the following
equation.
Oscillator Frequency
Mode 0 Baud Rate =
12
The baud rate in Mode 2 depends on the value of the
SMOD bit in Special Function Register PCON. If SMOD
= 0 (the value on reset), the baud rate is 1/64 of the
oscillator frequency. If SMOD = 1, the baud rate is 1/32 of
theoscillatorfrequency,asshowninthefollowingequation.
2SMOD
Mode 2 Baud Rate =
x (Oscillator Frequency)
64
In the IS80LV51/31, the Timer 1 overflow rate determines
the baud rates in Modes 1 and 3. In the IS80LV52/32,
these baud rates can be determined by Timer 1, Timer 2,
or both (one for transmit and the other for receive).
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Using Timer 2 to Generate Baud Rates
Figure 13 shows Timer 2 as a baud rate generator. This
figure is valid only if RCLK + TCLK = 1 in T2CON. A
rollover in TH2 does not set TF2 and does no generate an
interrupt. Therefore, the Timer 2 interrupt does not have
to be disabled when Timer 2 is in the baud rate generator
mode. If EXEN2 is set, a 1-to-0 transition in T2EX sets
EXF2 but does not cause a reload from (RCAP2H,
RCAP2L) to (TH2, TL2). Thus, when Timer 2 is used as
a baud rate generator, T2EX can be used as an extra
external interrupt.
IntheIS80LV52/32,settingTCLKand/orRCLKinT2CON
selects Timer 2 as the baud rate generator. Under these
conditions, the baud rates for transmit and receive can be
simultaneously different. Setting RCLK and/or TCLK puts
Timer 2 into its baud rate generator mode, as shown in
Figure 14.
Thebaudrategeneratormodeissimilartotheauto-reload
mode, in that a rollover in TH2 reloads the Timer 2
registerswiththe16-bitvalueintheRCAP2HandRCAP2L
registers, which are preset by software.
When Timer 2 is running (TR2 = 1) as a timer in the baud
rate generator mode, programmers should not read from
or write to TH2 or TL2. Under these conditions, Timer 2 is
incremented every state time, and the results of a read or
write may not be accurate. The RCAP registers may be
read, but should not be written to, because a write might
overlap a reload and cause write and/or reload errors.
Turn Timer 2 off (clear TR2) before accessing the Timer
2 or RCAP registers, in this case.
Inthiscase,thebaudratesinMode1and3aredetermined
by the Timer 2 overflow rate according to the following
equation.
Timer 2 Overflow Rate
Modes 1, 3 Baud Rate =
16
Timer 2 can be configured for either timer or counter
operation. In the most typical applications, it is configured
fortimeroperation(C/T2=0).Normally,atimerincrements
everymachinecycle(thusat1/12theoscillatorfrequency),
buttimeroperationisadifferentforTimer2whenitisused
as a baud rate generator. As a baud rate generator, Timer
2 increments every state time (thus at 1/2 the oscillator
frequency). In this case, the baud rate is given by the
following formula.
Modes 1, 3
Baud Rate
Oscillator Frequency
=
32x [65536 – (RCAP2H, RCAP2L)]
Where (RCAP2H, RCAP2L) is the content of RCAP2H
and RCAP2L taken as a 16-bit unsigned integer.
Table 9. Commonly Used Baud Rates Generated by Timer 1
Timer 1
Mode
Baud Rate
fOSC
SMOD
C/T
X
X
0
Reload Value
X
Mode 0 Max: 1 MHz
12 MHz
X
1
1
1
0
0
0
0
0
0
0
X
X
2
2
2
2
2
2
2
2
1
Mode 2 Max: 375K
12 MHz
X
Modes 1, 3: 62.5K
12 MHz
FFH
19.2K
9.6K
4.8K
2.4K
1.2K
137.5
110
11.059 MHz
11.059 MHz
11.059 MHz
11.059 MHz
11.059 MHz
11.986 MHz
6 MHz
0
FDH
FDH
FAH
0
0
0
F4H
0
E8H
0
1DH
0
72H
110
12 MHz
0
FEEBH
22
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More About Mode 0
More About Mode 1
Serial data enters and exits through RXD. TXD outputs
the shift clock. Eight data bits are transmitted/received,
with the LSB first. The baud rate is fixed at 1/12 the
oscillator frequency.
Ten bits are transmitted (through TXD), or received
(through RXD): a start bit (0), eight data bits (LSB first),
and a stop bit (1). On receive, the stop bit goes into RB8
in SCON. In the IS80LV52/32 the baud rate is determined
either by the Timer 1 overflow rate, the Timer 2 overflow
rate,orboth.Inthiscase,oneTimerisfortransmit,andthe
other is for receive.
Figure 15 shows a simplified functional diagram of the
serial port in Mode 0 and associated timing.
Transmission is initiated by any instruction that uses
SBUF as a destination register. The "write to SBUF"
signal at S6P2 also loads a 1 into the ninth position of the
transmit shift register and tells the TX Control block to
begin a transmission. The internal timing is such that one
full machine cycle will elapse between "write to SBUF"
and activation of SEND.
Figure 16 shows a simplified functional diagram of the
serial port in Mode 1 and associated timings for transmit
and receive.
Transmission is initiated by any instruction that uses
SBUF as a destination register.
The "write to =SBUF" signal also loads a 1 into the ninth
bit position of the transmit shift register and flags the TX
controlunitthatatransmissionisrequested.Transmission
actuallycommencesatS1P1ofthemachinecyclefollowing
the next rollover in the divide-by-16 counter. Thus, the bit
times are synchronized to the divide-by-16 counter, not to
the "write to SBUF" signal.
SEND transfer the output of the shift register to the
alternate output function line of P3.0, and also transfers
SHIFT CLOCK to the alternate output function line of
P3.1. SHIFTCLOCKislowduringS3, S4, andS5ofevery
machine cycle, and high during S6, S1, and S2. At S6P2
of every machine cycle in which SEND is active, the
contents of the transmit shift register are shifted one
position to the right.
The transmission begins when SEND is activated, which
puts the start bit at TXD. One bit time later, DATA is
activated, whichenablestheoutputbitofthetransmitshift
register to TXD. The first shift pulse occurs one bit time
after that.
As data bits shift out to the right, 0s come in from the left.
When the MSB of the data byte is at the output position of
the shift register, the 1 that was initially loaded into the
ninthpositionisjusttotheleftoftheMSB, andallpositions
to the left of that contain 0s. This condition flags the TX
Control block to do one last shift, then deactivate SEND
andsetTI.BothoftheseactionsoccuratS1P1ofthetenth
machine cycle after "write to SBUF."
As data bits shift out to the right, 0s are clocked in from the
left. When the MSB of the data byte is at the output
position of the shift register, the 1 that was initially loaded
into the ninth position is just to the left of the MSB, and all
positions to the left of that contain 0s. This condition flags
the TX Control unit to do one last shift, then deactivate
SEND and set TI. This occurs at the tenth divide-by-16
rollover after "write to SBUF".
Reception is initiated by the condition REN = 1 and
RI = 0. At S6P2 of the next machine cycle, the RX Control
unit writes the bits 11111110 to the receive shift register
and activates RECEIVE in the next clock phase.
Reception is initiated by a 1-to-0 transition detected at
RXD. For this purpose, RXD is sampled at a rate of 16
times the established baud rate. When a transition is
detected, the divide-by-16 counter is immediately reset,
and 1FFH is written into the input shift register. Resetting
the divide-by-16 counter aligns its rollovers with the
boundaries of the incoming bit times.
RECEIVE enables SHIFT CLOCK to the alternate output
function line of P3.1. SHIFT CLOCK makes transitions at
S3P1 and S6P1 of every machine cycle. At S6P2 of every
machine cycle in which RECEIVE is active, the contents
of the receive shift register are shifted on position to the
left. Thevaluethatcomesinfromtherightisthevaluethat
wassampledattheP3.0pinatS5P2ofthesamemachine
cycle.
The 16 states of the counter divide each bit time into 16th.
Attheseventh, eighth, andninthcounterstatesofeachbit
time, thebitdetectorsamplesthevalueofRXD. Thevalue
accepted is the value that was seen in at least two of the
three samples. This is done to reject noise. In order to
reject false bits, if the value accepted during the first bit
time is not 0, the receive circuits are reset and the unit
continues looking for another 1-to-0 transition. If the start
bit is valid, it is shifted into the input shift register, and
reception of the rest of the frame proceeds.
As data bits come in from the right, 1s shift out to the left.
When the 0 that was initially loaded into the right-most
positionarrivesattheleft-mostpositionintheshiftregister,
it flags the RX Control block to do one last shift and load
SBUF. At S1P1 of the 10th machine cycle after the write
to SCON that cleared RI, RECEIVE is cleared and RI is
set.
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As data bits come in from the right, 1s shift to the left.
When the start bit arrives at the leftmost position in the
shift register, (which is a 9-bit register in Mode 1), it flags
the RX Control block to do one last shift, load SBUF and
RB8, and set RI. The signal to load SBUF and RB8 and to
set RI is generated if, and only if, the following conditions
are met at the time the final shift pulse is generated.
Reception is initiated by a 1-to-0 transition detected at
RXD. For this purpose, RXD is sampled at a rate of 16
times the established baud rate. When a transition is
detected, the divide-by-16 counter is immediately reset,
and 1FFH is written to the input shift register.
Attheseventh, eighth, andninthcounterstatesofeachbit
time, thebitdetectorsamplesthevalueofRXD. Thevalue
accepted is the value that was seen in at least two of the
three samples. If the value accepted during the first bit
time is not 0, the receive circuits are reset and the unit
continues looking for another 1-to-0 transition. If the start
bitprovesvalid, itisshiftedintotheinputshiftregister, and
reception of the rest of the frame proceeds.
1. RI = 0 and
2. Either SM2 = 0, or the received stop bit =1
If either of these two conditions is not met, the received
frame is irretrievably lost. If both conditions are met, the
stop bit goes into RB8, the eight data bits go into SBUF,
and RI is activated. At this time, whether or not the above
conditions are met, the unit continues looking for a 1-to-
0 transition in RXD.
As data bits come in from the right, Is shift out to the left.
When the start bit arrives at the leftmost position in the
shift register (which in Modes 2 and 3 is a 9-bit register),
itflagstheRXControlblocktodoonelastshift,loadSBUF
and RB8, and set RI. The signal to load SBUF and RB8
and to set RI is generated if, and only if, the following
conditions are met at the time the final shift pulse is
generated:
More About Modes 2 and 3
Eleven bits are transmitted (through TXD), or received
(through RXD): a start bit (0), 8 data bits (LSB first), a
programmable ninth data bit, and a stop bit (1). On
transmit, the ninth data bit (TB8) can be assigned the
valueof0or1.Onreceive,theninthdatabitgoesintoRB8
inSCON. Thebaudrateisprogrammabletoeither1/32or
1/64 of the oscillator frequency in Mode 2. Mode 3 may
have a variable baud rate generated from either Timer 1
or 2, depending on the state of TCLK and RCLK.
1. RI = 0, and
2. Either SM2 = 0 or the received 9th data bit = 1
If either of these conditions is not met, the received frame
is irretrievably lost, and RI is not set. If both conditions are
met,thereceivedninthdatabitgoesintoRB8,andthefirst
eight data bits go into SBUF. One bit time later, whether
the above conditions were met or not, the unit continues
looking for a 1-to-0 transition at the RXD input.
Figures 17 and 18 show a functional diagram of the serial
port in Modes 2 and 3. The receive portion is exactly the
sameasinMode1.ThetransmitportiondiffersfromMode
1 only in the ninth bit of the transmit shift register.
Note that the value of the received stop bit is irrelevant to
SBUF, RB8, or RI.
Transmission is initiated by any instruction that uses
SBUF as a destination register. The "write to SBUF"
signal also loads TB8 into the ninth bit position of the
transmit shift register and flags the TX Control unit that a
transmission is requested. Transmission commences at
S1P1 of the machine cycle following the next rollover in
the divide-by-16 counter. Thus, the bit times are
synchronized to the divide-by-16 counter, not to the "write
to SBUF" signal.
Table 10. Serial Port Setup
Mode
SCON
SM2Variation
0
1
2
3
0
1
2
3
10H
50H
90H
D0H
NA
Single Processor
Environment
(SM2 = 0)
The transmission begins when SEND is activated, which
puts the start bit at TXD. One bit timer later, DATA is
activated, whichenablestheoutputbitofthetransmitshift
register to TXD. The first shift pulse occurs one bit time
after that. The first shift clocks a 1 (the stop bit) into the
ninth bit position of the shift register. Thereafter, only 0s
are clocked in. Thus, as data bits shift out to the right, 0s
are clocked in from the left. When TB8 is at the output
position of the shift register, then the stop bit is just to the
left of TB8, and all positions to the left of that contain 0s.
ThisconditionflagstheTXControlunittodoonelastshift,
then deactivate SEND and set TI. This occurs at the 11th
divide-by-16 rollover after "write to SBUF".
Multiprocessor
Environment
(SM2 = 1)
70H
B0H
F0H
24
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ISSI
IS80LV52/32 INTERNAL BUS
WRITE
TO
SBUF
RXD
S
Q
D
P3.0 ALT
OUTPUT
FUNCTION
SBUF
CL
SHIFT
ZERO DETECTOR
TX CONTROL
START
SHIFT
SEND
S6
TX CLOCK
TXD
SERIAL
PORT
INTERRUPT
P3.1 ALT
OUTPUT
FUNCTION
SHIFT
CLOCK
RI
RX CLOCK
START
RECEIVE
SHIFT
RX CONTROL
REN
RI
1
1 1 1 1 1 1 0
RXD
P3.0 ALT
INPUT
INPUT SHIFT REG.
FUNCTION
LOAD
SBUF
SHIFT
SBUF
READ
SBUF
IS80LV52/32 INTERNAL BUS
S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1
ALE
WRITE TO SBUF
S6P2
SEND
SHIFT
D0
D1
D2
D3
D5
D6
D7
D4
RXD (DOUT
)
TRANSMIT
TXD (SHIFT CLOCK)
TI
S3P1 S6P1
WRITE TO SCON (CLEAR RI)
RI
RECEIVE
SHIFT
RECEIVE
D1
D2
D3
D5
D6
D7
D0
D4
RXD (DIN
)
S5P2
TXD (SHIFT CLOCK)
Figure 15. Serial Port Mode 0
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IS80LV52/32 INTERNAL BUS
TB8
TIMER 1
TIMER 2
OVERFLOW
OVERFLOW
WRITE
TO
SBUF
S
2
Q
D
SBUF
SMOD
= 1
TXD
CL
SMOD
= 0
ZERO DETECTOR
"0"
"1"
"1"
SHIFT
TX CONTROL
START
DATA
TCLK
RCLK
RX CLOCK
SEND
16
TI
SERIAL
"0"
PORT
INTERRUPT
16
SAMPLE
1-TO-0
LOAD
RI
RX CLOCK
START
SBUF
SHIFT
1FFH
RX CONTROL
TRANSITION
DETECTOR
BIT
DETECTOR
INPUT SHIFT REG.
(9 BITS)
RXD
LOAD
SBUF
SHIFT
SBUF
READ
SBUF
IS80LV52/32 INTERNAL BUS
TX CLOCK
WRITE TO SBUF
SEND
S1P1
TRANSMIT
DATA
SHIFT
START
BIT
D0
D1
D2
D3
D4
D5
D6
D7
STOP BIT
TXD
TI
RX
CLOCK
16 RESET
START
BIT
RXD
D0
D1
D2
D3
D4
D5
D6
D7
STOP BIT
BIT DETECTOR SAMPLE TIMES
RECEIVE
SHIFT
RI
Figure 16. Serial Port Mode 1
26
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IS80LV52/32 INTERNAL BUS
TB8
WRITE
TO
SBUF
S
Q
D
SBUF
TXD
CL
ZERO DETECTOR
PHASE 2 CLOCK
(1/2 fOSC)
STOP BIT GEN SHIFT
TX CONTROL
START
DATA
MODE 2
SMOD 1
TX CLOCK
SEND
16
TI
2
SERIAL
PORT
INTERRUPT
SMOD 0
16
(SMOD IS PCON. 7)
SAMPLE
1-TO-0
LOAD
RI
RX
CLOCK
SBUF
SHIFT
1FFH
START
BIT
TRANSITION
DETECTOR
RX CONTROL
DETECTOR
INPUT SHIFT REG.
(9 BITS)
RXD
LOAD
SBUF
SHIFT
SBUF
READ
SBUF
IS80LV52/32 INTERNAL BUS
TX
CLOCK
WRITE TO SBUF
SEND
S1P1
DATA
TRANSMIT
SHIFT
START
BIT
D0
D1
D2
D3
D4
D5
D6
D7
TB8
TXD
TI
STOP BIT
STOP BIT GEN
RX
CLOCK
16 RESET
START
BIT
RXD
D0
D1
D2
D3
D4
D5
D6
RB8
D7
STOP
BIT
BIT DETECTOR SAMPLE TIMES
RECEIVE
SHIFT
RI
Figure 17. Serial Port Mode 2
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IS80LV52/32 INTERNAL BUS
TB8
TIMER 1
TIMER 2
OVERFLOW
OVERFLOW
WRITE
TO
SBUF
S
2
Q
D
SBUF
SMOD
= 1
TXD
CL
SMOD
= 0
ZERO DETECTOR
"0"
"1"
"1"
SHIFT
TX CONTROL
START
DATA
TCLK
RCLK
RX CLOCK
SEND
16
TI
SERIAL
PORT
"0"
INTERRUPT
16
SAMPLE
1-TO-0
LOAD
RI
RX CLOCK
START
SBUF
SHIFT
1FFH
RX CONTROL
TRANSITION
DETECTOR
BIT
DETECTOR
INPUT SHIFT REG.
(9 BITS)
RXD
LOAD
SBUF
SHIFT
SBUF
READ
SBUF
IS80LV52/32 INTERNAL BUS
TX
CLOCK
WRITE TO SBUF
SEND
S1P1
DATA
TRANSMIT
SHIFT
START
BIT
D0
D1
D2
D3
D4
D5
D6
D7
TB8
TXD
TI
STOP BIT
STOP BIT GEN
RX
CLOCK
16 RESET
START
BIT
RXD
D0
D1
D2
D3
D4
D5
D6
RB8
D7
STOP
BIT
BIT DETECTOR SAMPLE TIMES
RECEIVE
SHIFT
RI
Figure 18. Serial Port Mode 3
28
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INTERRUPT SYSTEM
whentheserviceroutineisvectoredto. Infact, theservice
routinenormallymustdeterminewhetherRIorTIgenerated
the interrupt, and the bit must be cleared in software.
The IS80LV52/32 provides six interrupt sources: two
externalinterrupts, threetimerinterrupts, andaserialport
interrupt. These are shown in Figure 19.
In the IS80LV52/32, the Timer 2 Interrupt is generated by
the logical OR of TF2 and EXF2. Neither of these flags is
cleared by hardware when the service routine is vectored
to. In fact, the service routine may have to determine
whether TF2 or EXF2 generated the interrupt, and the bit
must be cleared in software.
The External Interrupts INT0 and INT1 can each be either
level-activated or transition-activated, depending on bits
IT0 and IT1 in Register TCON. The flags that actually
generate these interrupts are the IE0 and IE1 bits in
TCON. When the service routine is vectored to, hardware
clears the flag that generated an external interrupt only if
the interrupt was transition-activated. If the interrupt was
level-activated,thentheexternalrequestingsource(rather
than the on-chip hardware) controls the request flag.
Allofthebitsthatgenerateinterruptscanbesetorcleared
bysoftware, withthesameresultasthoughtheyhadbeen
set or cleared by hardware. That is, interrupts can be
generated and pending interrupts can be canceled in
software.
The Timer 0 and Timer 1 Interrupts are generated by TF0
and TF1, which are set by a rollover in their respective
Timer/Counter registers (except for Timer 0 in Mode 3).
Whenatimerinterruptisgenerated,theon-chiphardware
clears the flag that generated it when the service routine
is vectored to.
Eachoftheseinterruptsourcescanbeindividuallyenabled
or disabled by setting or clearing a bit in Special Function
RegisterIE(interruptenable)ataddress0A8H. Aswellas
individual enable bits for each interrupt source, there is a
global enable/disable bit that is cleared to disable all
interrupts or set to turn on interrupts (see SFR IE).
The Serial Port Interrupt is generated by the logical OR of
RI and TI. Neither of these flags is cleared by hardware
POLLING
HARDWARE
HIGH PRIORITY
INTERRUPT
REQUEST
IE.0
IE.7
IP.0
TCON.1
EXTERNAL
INT RQST 0
INT0
EX0
IE.1
PX0
IP.1
IE0
TCON.5
TIMER/COUNTER 0
SOURCE
VECTOR
I.D.
ET0
IE.2
PT0
IP.2
TF0
TCON.3
EXTERNAL
INT RQST 1
IE1
INT1
EX1
IE.3
PX1
IP.3
TCON.7
TIMER/COUNTER 1
ET1
IE.4
PT1
IP.4
TF1
LOW PRIORITY
INTERRUPT
REQUEST
SCON.0
INTERNAL
RI
SERIAL
SCON.1
TI
PORT
PS
ES
IE.5
IP.5
T2CON.7
TF2
TIMER/
COUNTER 2
T2EX
T2CON.6
EXF2
SOURCE
VECTOR
I.D.
ET2
EA
PT2
Figure 19. Interrupt System
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Priority Level Structure
in the Response Timer Section). If one of the flags was in
a set condition at S5P2 of the preceding cycle, the polling
cycle will find it and the interrupt system will generate an
LCALL to the appropriate service routine, provided this
hardware generated LCALL is not blocked by any of the
following conditions:
Eachinterruptsourcecanalsobeindividuallyprogrammed
to one of two priority levels by setting or clearing a bit in
SpecialFunctionRegisterIP(interruptpriority)ataddress
0B8H. IP is cleared after a system reset to place all
interrupts at the lower priority level by default. A low-
priority interrupt can be interrupted by a high-priority
interrupt but not by another low-priority interrupt. A high-
priority interrupt can not be interrupted by any other
interrupt source.
1. Aninterruptofequalorhigherprioritylevelisalready
in progress.
2. The current (polling) cycle is not the final cycle in the
execution of the instruction in progress.
If two requests of different priority levels are received
simultaneously, the request of higher priority level is
serviced.Ifrequestsofthesameprioritylevelarereceived
simultaneously, an internal polling sequence determines
which request is serviced. Thus, within each priority level
there is a second priority structure determined by the
polling sequence, as follows:
3. TheinstructioninprogressisRETIoranywritetothe
IE or IP registers.
Any of these three conditions will block the generation of
the LCALL to the interrupt service routine. Condition 2
ensures that the instruction in progress will be completed
beforevectoringtoanyserviceroutine.Condition3ensures
that if the instruction in progress is RETI or any access to
IEorIP,thenatleastonemoreinstructionwillbeexecuted
before any interrupt is vectored to.
Source
IE0
Priority Within Level
1.
2.
3.
4.
5.
6.
(Highest)
TF0
The polling cycle is repeated with each machine cycle,
and the values polled are the values that were present at
S5P2 of the previous machine cycle. If an active interrupt
flag is not being serviced because of one of the above
conditionsandisnotstillactivewhentheblockingcondition
is removed, the denied interrupt will not be serviced. In
otherwords,thefactthattheinterruptflagwasonceactive
but not serviced is not remembered. Every polling cycle is
new. The polling cycle/LCALL sequence is illustrated in
Figure 20.
IE1
TF1
RI + TI
TF2 + EXF2
(Lowest)
Note that the "priority within level" structure is only used
to resolve simultaneous requests of the same priority
level.
Note that if an interrupt of higher priority level goes active
priortoS5P2ofthemachinecyclelabeledC3inFigure20,
then in accordance with the above rules it will be serviced
during C5 and C6, without any instruction of the lower
priority routine having been executed.
How Interrupts Are Handled
The interrupt flags are sampled at S5P2 of every machine
cycle.Thesamplesarepolledduringthefollowingmachine
cycle (the Timer 2 interrupt cycle is different, as described
C1
C2
C3
C4
C5
S5P2
S6
E
INTERRUPTS
ARE POLLED
LONG CALL TO
INTERRUPT
VECTOR ADDRESS
INTERRUPT
ROUTINE
INTERRUPT
LATCHED
INTERRUPT
GOES ACTIVE
Figure 20. Interrupt Response Timing Diagram
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Thus, the processor acknowledges an interrupt request
by executing a hardware-generated LCALL to the
appropriate servicing routine. In some cases it also clears
the flag that generated the interrupt, and in other cases it
does not. It never clears the Serial Port or Timer 2 flags.
This must be done in the user's software. The processor
clears an external interrupt flag (IE0 or IE1) only if it was
transition-activated. The hardware-generated LCALL
pushes the contents of the Program Counter onto the
stack (but it does not save the PSW) and reloads the PC
with an address that depends on the source of the
interrupt being serviced, as follows:
SFR Register and
Bit Position
Interrupt
External 0
External 1
Timer 1
Flag
IE0
IE1
TF1
TF0
TI
TCON.1
TCON.3
TCON.7
Timer 0
TCON.5
Serial Port
SCON.1
Serial Port
TF2
RI
SCON.0Timer 2
T2CON.7
Timer 2
EXF2
T2CON.6
Whenaninterruptisacceptedthefollowingactionoccurs:
1. The current instruction completes operation.
2. The PC is saved on the stack.
Interrupt
Source
Interrupt
Request Bits
Cleared by
Hardware
Vector
Address
INT0
IE0
No (level)
Yes (trans.)
0003H
3. The current interrupt status is saved internally.
4. Interrupts are blocked at the level of the interrupts.
Timer 0
INT1
TF0
IE1
Yes
000BH
0013H
No (level)
Yes (trans.)
5. The PC is loaded with the vector address of the ISR
(interrupts service routine).
Timer 1
Serial Port
Timer 2
TF1
RI, TI
Yes
No
001BH
0023H
002BH
0000H
6. The ISR executes.
The ISR executes and takes action in response to the
interrupt.TheISRfinisheswithRETI(returnfrominterrupt)
instruction. This retrieves the old value of the PC from the
stack and restores the old interrupt status. Execution of
the main program continues where it left off.
TF2, EXF2
RST
No
System
Reset
Execution proceeds from that location until the RETI
instruction is encountered. The RETI instruction informs
the processor that this interrupt routine is no longer in
progress, then pops the top two bytes from the stack and
reloadstheProgramCounter.Executionoftheinterrupted
program continues from where it left off.
External Interrupts
The external sources can be programmed to be level-
activated or transition-activated by setting or clearing bit
IT1 or IT0 in Register TCON. If ITx= 0, external interrupt
x is triggered by a detected low at the INTx pin. If ITx = 1,
external interrupt x is edge-triggered. In this mode if
successive samples of the INTx pin show a high in one
cycle and a low in the next cycle, interrupt request flag IEx
in TCON is set. Flag bit IEx then requests the interrupt.
Note that a simple RET instruction would also have
returned execution to the interrupted program, but it
would have left the interrupt control system thinking an
interrupt was still in progress.
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Since the external interrupt pins are sampled once each
machinecycle, aninputhighorlowshouldholdforatleast
12 oscillator periods to ensure sampling. If the external
interruptistransition-activated, theexternalsourcehasto
hold the request pin high for at least one machine cycle,
and then hold it low for at least one machine cycle to
ensure that the transition is seen so that interrupt request
flag IEx will be set. IEx will be automatically cleared by the
CPU when the service routine is called.
Single-Step Operation
The IS80LV52/32 interrupt structure allows single-step
executionwithverylittlesoftwareoverhead.Aspreviously
noted, an interrupt request will not be serviced while an
interrupt of equal priority level is still in progress, nor will
it be serviced after RETI until at least one other instruction
has been executed. Thus, once an interrupt routine has
been entered, it cannot be reentered until at least one
instruction of the interrupted program is executed. One
way to use this feature for single-step operation is to
programoneoftheexternalinterrupts(forexample, INT0)
to be level-activated. The service routine for the interrupt
will terminate with the following code:
If the external interrupt is level-activated, the external
source has to hold the request active until the requested
interrupt is actually generated. Then the external source
must deactivate the request before the interrupt service
routine is completed, or else another interrupt will be
generated.
JNB
JB
P3.2,$
P3.2,$
;Wait Here Till INT0 Goes High
;Now Wait Here Till it Goes Low
RETI
;Go Back and Execute One
Instruction
Response Time
TheINT0andINT1levelsareinvertedandlatchedintothe
interrupt flags IE0 and IE1 at S5P2 of every machine
cycle. Similarly, the Timer 2 flag EXF2 and the Serial Port
flagsRIandTIaresetatS5P2.Thevaluesarenotactually
polled by the circuitry until the next machine cycle.
If the INT0 pin, which is also the P3.2 pin, is held normally
low, the CPU will go right into the External Interrupt 0
routine and stay there until INT0 is pulsed (from low-to-
high-to-low). ThenitwillexecuteRETI, gobacktothetask
program,executeoneinstruction,andimmediatelyreenter
the External Interrupt 0 routine to await the next pulsing of
P3.2. One step of the task program is executed each time
P3.2 is pulsed.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at
S5P2ofthecycleinwhichthetimersoverflow. Thevalues
are then polled by the circuitry in the next cycle. However,
the Timer 2 flag TF2 is set at S2P2 and is polled in the
same cycle in which the timer overflows.
If a request is active and conditions are right for it to be
acknowledged,ahardwaresubroutinecalltotherequested
service routine will be the next instruction executed. The
call itself takes two cycles. Thus, a minimum of three
complete machine cycles elapsed between activation of
anexternalinterruptrequestandthebeginningofexecution
of the first instruction of the service routine. Figure 19
shows response timings.
A longer response time results if the request is blocked by
oneofthethreepreviouslylistedconditions. Ifaninterrupt
of equal or higher priority level is already in progress, the
additional wait time depends on the nature of the other
interrupt's service routine. If the instruction in progress is
not in its final cycle, the additional wait time cannot be
more than three cycles, since the longest instructions
(MUL and DIV) are only four cycles long. If the instruction
in progress is RETI or an access to IE or IP, the additional
wait time cannot be more than five cycles (a maximum of
one more cycle to complete the instruction in progress,
plus four cycles to complete the next instruction if the
instruction is MUL or DIV).
Thus, in a single-interrupt system, the response time is
always more than three cycles and less than nine cycles.
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Table 11. Reset Values of the SFR's
OTHER INFORMATION
Reset
The reset input is the RST pin, which is the input to a
Schmitt Trigger.
SFR Name
PC
Reset Value
0000H
00H
ACC
B
00H
A reset is accomplished by holding the RST pin high for at
least two machine cycles (24 oscillator periods), while the
oscillator is running. The CPU responds by generating an
internal reset, with the timing shown in Figure 21.
PSW
SP
00H
07H
DPTR
P0-P3
IP
0000H
FFH
The external reset signal is asynchronous to the internal
clock. The RST pin is sampled during State 5 Phase 2 of
every machine cycle. The port pins will maintain their
current activities for 19 oscillator periods after a logic 1
has been sampled at the RST pin; that is, for 19 to 31
oscillator periods after the external reset signal has been
applied to the RST pin.
XX000000B
0X000000B
00H
IE
TMOD
TCON
T2CON
TH0
00H
00H
The internal reset algorithm writes 0s to all the SFRs
excepttheportlatches, theStackPointer, andSBUF. The
port latches are initialized to FFH, the Stack Pointer to
07H, and SBUF is indeterminate. Table 11 lists the SFRs
and their reset values.
00H
TL0
00H
TH1
00H
TL1
00H
TH2
00H
Then internal RAM is not affected by reset. On power-up
the RAM content is indeterminate.
TL2
00H
RCAP2H
RCAP2L
SCON
SBUF
PCON
00H
00H
00H
Indeterminate
0XXX0000B
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Power-on Reset
An automatic reset can be obtained when VCC goes
through a 10µF capacitor and GND through an 8.2K
resistor, providing the VCC rise time does not exceed
1 msec and the oscillator start-up time does not exceed
10 msec. This power-on reset circuit is shown in Figure
21. The CMOS devices do not require the 8.2K pulldown
resistor, although its presence does no harm.
Vcc
+
10 f
Vcc
IS80LV52/32
When power is turned on, the circuit holds the RST pin
highforanamountoftimethatdependsonthevalueofthe
capacitor and the rate at which it charges. To ensure a
goodreset,theRSTpinmustbehighlongenoughtoallow
the oscillator time to start-up (normally a few msec) plus
two machine cycles.
RST
8.2K Ω
Note that the port pins will be in a random state until the
oscillator has start and the internal reset algorithm has
written 1s to them.
GND
Withthiscircuit, reducingVCC quicklyto0causestheRST
pin voltage to momentarily fall below 0V. However, this
voltage is internally limited, and will not harm the device.
Figure 21. Power-On Reset Circuit
12 OSC. PERIODS
S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4
RST
INTERNAL RESET SIGNAL
SAMPLE
RST
SAMPLE
RST
ALE
PSEN
P0
INST ADDR INST ADDR
11 OSC. PERIODS
INST
ADDR
INST ADDR INST
ADDR
19 OSC. PERIODS
Figure 22. Reset Timing
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Power-Saving Modes of Operation
The IS80LV52/32 has two power-reducing modes. Idle
and Power-down. The input through which backup power
is supplied during these operations is Vcc. Figure 23
shows the internal circuitry which implements these
features.IntheIdlemode(IDL=1),theoscillatorcontinues
to run and the Interrupt, Serial Port, and Timer blocks
continue to be clocked, but the clock signal is gated off to
the CPU. In Power-down (PD = 1), the oscillator is frozen.
The Idle and Power-down modes are activated by setting
bits in Special Function Register PCON.
XTAL 2
XTAL 1
OSC
PD
INTERRUPT,
SERIAL PORT,
TIMER BLOCKS
CLOCK
GEN
CPU
IDL
Idle Mode
An instruction that sets PCON.0 is the last instruction
executed before the Idle mode begins. In the Idle mode,
the internal clock signal is gated off to the CPU, but not to
the Interrupt, Timer, and Serial Port functions. The CPU
status is preserved in its entirety: the Stack Pointer,
Program Counter, Program Status Word, Accumulator,
and all other registers maintain their data during Idle. The
port pins hold the logical states they had at the time Idle
was activated. ALE and PSEN hold at logic high levels.
Figure 23. Idle and Power-Down Hardware
Power-down Mode
An instruction that sets PCON.1 is the last instruction
executedbeforePower-downmodebegins. InthePower-
down mode, the on-chip oscillator stops. With the clock
frozen, allfunctionsarestopped, buttheon-chipRAMand
Special function Registers are held. The port pins output
the values held by their respective SFRs. ALE and PSEN
output lows.
There are two ways to terminate the Idle. Activation of any
enabled interrupt will cause PCON.0 to be cleared by
hardware, terminating the Idle mode. The interrupt will be
serviced, and following RETI the next instruction to be
executed will be the one following the instruction that put
the device into Idle.
In the Power-down mode of operation, Vcc can be reduced
to as low as 2V. However, Vcc must not be reduced before
thePower-downmodeisinvoked,andVccmustberestored
to its normal operating level before the Power-down mode
is terminated. The reset that terminates Power-down also
freestheoscillator. Theresetshouldnotbeactivatedbefore
Vccisrestoredtoitsnormaloperatinglevelandmustbeheld
active long enough to allow the oscillator to restart and
stabilize (normally less than 10 msec).
TheflagbitsGF0andGF1canbeusedtoindicatewhether
aninterruptoccurredduringnormaloperationorduringan
Idle. For example, an instruction that activates Idle can
also set one or both flag bits. When Idle is terminated by
an interrupt, the interrupt service routine can examine the
flag bits.
The only exit from power-down is a hardware reset. Reset
redefines all the SFRs but does not change the on-chip
RAM.
The other way of terminating the Idle mode is with a
hardware reset. Since the clock oscillator is still running,
the hardware reset must be held active for only two
machine cycles (24 oscillator periods) to complete the
reset.
The signal at the RST pin clears the IDL bit directly and
asynchronously. At this time, the CPU resumes program
execution from where it left off; that is, at the instruction
following the one that invoked the Idle Mode. As shown in
Figure 22, two or three machine cycles of program
executionmaytakeplacebeforetheinternalresetalgorithm
takes control. On-chip hardware inhibits access to the
internal RAM during his time, but access to the port pins
is not inhibited. To eliminate the possibility of unexpected
outputs at the port pins, the instruction following the one
thatinvokesIdleshouldnotwritetoaportpinortoexternal
data RAM.
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Table 12. Status of the External Pins During Idle and Power-down Modes.
Mode
Idle
Memory
Internal
External
Internal
External
ALE
PSEN
PORT 0
Data
PORT 1
Data
PORT 2
Data
PORT 3
1
1
0
0
1
1
0
0
Data
Data
Data
Data
Idle
Float
Data
Address
Data
Power-down
Power-down
Data
Data
Float
Data
Data
On-Chip Oscillators
Thecrystalspecificationsandcapacitancevalues(C1and
C2inFigure24)arenotcritical. 20pFto30pFcanbeused
in these positions at a12 MHz to 24 MHz frequency with
good quality crystals. (For ranges greater than 24 MHz
refer to Figure 26.) A ceramic resonator can be used in
place of the crystal in cost-sensitive applications. When a
ceramicresonatorisused,C1andC2arenormallyselected
to be of somewhat higher values. The manufacturer of the
ceramicresonatorshouldbeconsultedforrecommendation
on the values of these capacitors.
The on-chip oscillator circuitry of the IS80LV52/32 is a
single stage linear inverter, intended for use as a crystal-
controlled, positivereactanceoscillator (Figure24). Inthis
application the crystal is operated in its fundamental
response mode as an inductive reactance in parallel
resonancewithcapacitanceexternaltothecrystal (Figure
24). Examples of how to drive the clock with external
oscillator are shown in Figure 25.
C2
XTAL2
XTAL1
NC
XTAL2
C1
EXTERNAL
OSCILLATOR
SIGNAL
XTAL1
GND
GND
Figure 24. Oscillator Connections
Figure 25. External Clock Drive Configuration
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XTAL2
XTAL1
R
C2
C1
Figure 26. For High Speed (> 24 MHz)
Note:
When the frequency is higher than 24 MHz, please refer to Table 13 for recommended value of C1, C2, and R.
Table 13. Recommended Value for C1, C2, R
Frequency Range
4 MHz-24 MHz
20 pF-30 pF
20 pF-30 pF
Not Apply
30 MHz-40 MHz
3 pF-10 pF
3 pF-10 pF
6.2K-10K
C1
C2
R
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ROM Verification
The address of the program memory location to be read
is applied to Port 1 and pins P2.4-P2.0. The other pins
should be held at the “Verify” level are indicated in Figure
26. The contents of the addressed locations exits on Port
0.ExternalpullupsarerequiredonPort0forthisoperation.
Figure 26 shows the setup to verify the program memory.
+ 5V
A7-A0
P1
Vcc
10K x 8
A12-A8
P2.4-P2.0
1
1
1
0
0
0
RST
EA
ALE
PSEN
P2.7
P2.6
PGM
DATA
P0
XTAL1
4-6 MHz
XTAL2
GND
Figure 27. ROM Verification
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ROM Lock System
Encryption Array
The program lock system, when programmed, protects
the ROM code against software piracy. The IS80LV52/32
has a two-level program lock system (see Table 14) and
a 32-byte encryption table. No matter what lock bit is, the
user submits the encryption table with his or her code in
verify ROM mode. Both the lock-bit and encryption array
Within the ROM array are 32 bytes of Encryption Array
that are initially unprogrammed (all 1's). Every time that a
byte is addressed during verify, five address lines are
used to select a byte of the Encryption Array.This byte is
then exclusive-NOR'ed (XNOR) with the code byte,
creating an Encryption verify byte. The algorithm, with the
array in the unprogrammed state (all 1's), will return the
code in its original, unmodified form.
When using the encryption array, one important factor
needs to be considered. If a code byte has the value
0FFH, verifying the byte will produce the encryption byte
value. If a large block (> 32 bytes) of code is left
unprogrammed, a verification routine will display the
contents of the encryption array. For this reason, all
unused code bytes should be programmed with some
valueotherthan0FFH,andnotallofthemthesamevalue.
Table 14. Program Lock Bits
LB1
LB2
Protection Type
1
2
U
U
No Program Lock Features enabled. (Code verify will still be
encrypted by the Encryption Array if Programmed)
P
P
U
P
MOVC instructions executed from external program memory
are diabled form fetching code bytes from internal memory,
EA is sampled and latched on Reset.
3
Same as 2, also ROM verify is disabled.
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ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
–2.0 to +7.0
0 to +70
–65 to +125
1.5
Unit
V
VTERM
TBIAS
TSTG
PT
Terminal Voltage with Respect to GND(2)
Temperature Under Bias(3)
Storage Temperature
Power Dissipation
°C
°C
W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
thisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextended
periods may affect reliability.
2. Minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for
periods less than 20 ns. Maximum DC voltage on output pins is Vcc + 0.5V which may
overshoot to Vcc + 2.0V for periods less than 20 ns.
3. Operating temperature is for commercial products only defined by this specification.
OPERATING RANGE(1)
Range
Ambient Temperature
VCC
Oscillator Frequency
Commercial
0°C to +70°C
3.3V ± 10%
3.5 to 40 MHz
Industrial
–40°C to +85°C
3.3V ± 10%
3.5 to 40 MHz
Note:
1. Operating ranges define those limits between which the functionality of the device is guaranteed.
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DC CHARACTERISTICS
(TA = 0°C to 70°C; Vcc = 3.3V ± 10%; GND = 0V)
Symbol
Parameter
Test conditions
Min
Max
Unit
VIL
VIL1
VIH
Input low voltage (All except EA)
Input low voltage (EA)
–0.5
–0.5
0.2Vcc – 0.1
0.2Vcc – 0.3
Vcc + 0.5
V
V
V
Input high voltage
0.2Vcc + 0.9
(All except XTAL 1, RST)
VIH1
Input high voltage (XTAL 1)
0.7Vcc
0.7Vcc
Vcc + 0.5
Vcc + 0.5
V
V
VSCH+
RST positive schmitt-trigger
threshold voltage
VSCH–
Vol(1)
RST negative schmitt-trigger
threshold voltage
0
0.2Vcc
V
Output low voltage
(Ports 1, 2, 3)
Iol = 100 µA
IOL = 1.6 mA
IOL = 3.5 mA
IOL = 200 µA
IOL = 3.2 mA
IOL = 7.0 mA
—
—
0.3
0.45
1.0
V
V
V
V
V
V
V
—
VOL1(1)
Output low voltage
(Port 0, ALE, PSEN)
—
0.3
—
0.45
1.0
—
VOH
Output high voltage
IOH = –10 µA
0.9Vcc
—
(Ports 1, 2, 3, ALE, PSEN)
Vcc = 4.5V-5.5V
IOL = –25 µA
IOL = –60 µA
0.75Vcc
2.4
—
—
V
V
VOH1
Output high voltage
(Port 0, ALE, PSEN)
IOH = –80 µA
Vcc = 4.5V-5.5V
0.9Vcc
—
V
IOH = –300 µA
IOH = –800 µA
0.75Vcc
2.4
—
—
V
V
IIL
ILI
Logical 0 input current (Ports 1, 2, 3) VIN = 0.45V
—
–110
10
µA
µA
µA
Input leakage current (Port 0)
0.45V < VIN < Vcc
VIN = 2.0V
–10
—
ITL
Logical 1-to-0 transition current
(Ports 1, 2, 3)
–650
RRST
RST pulldown resister
50
300
KΩ
Note:
1. Under steady state (non-transient) conditions, Iol must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port
Port 0: 26 mA
Ports 1, 2, 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification.
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POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Power supply current(1)
Test conditions
Vcc = 5.0V
12 MHz
Min
Max
Unit
Icc
Active mode
—
—
—
—
—
—
—
—
—
—
—
—
—
20
26
32
38
50
62
5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
16 MHz
20 MHz
24 MHz
32 MHz
40 MHz
Idle mode
12 MHz
16 MHz
6
20 MHz
7.6
9
24 MHz
32 MHz
12
15
50
40 MHz
Power-down mode
VCC = 5V
Note:
1. See Figures 28, 29, 30, and 31 for Icc test conditiions.
Vcc
Vcc
Vcc
Icc
Icc
RST
Vcc
RST
Vcc
Vcc
Vcc
P0
EA
P0
EA
NC
NC
XTAL2
XTAL2
CLOCK
SIGNAL
CLOCK
SIGNAL
XTAL1
GND
XTAL1
GND
Figure 28. Active Mode
Figure 29. Idle Mode
Vcc
Icc
RST
Vcc
Vcc
P0
EA
NC
XTAL2
XTAL1
GND
Figure 30. Power-down Mode
42
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
AC CHARACTERISTICS
(TA = 0°C to 70°C; Vcc = 3.3V ± 10%; GND = 0V; Cl for Port 0, ALE and PSEN Outputs = 100 pF; Cl for other outputs = 80 pF)
t
CLCX
tCHCX
Vcc — 0.5V
0.45V
0.7Vcc
0.2Vcc — 0.1
t
CHCL
tCLCH
t
CLCL
Figure 31. Icc Test Conditions
Note:
1. Clock signal waveform for Icc tests in active and idle mode (tCLCH = tCHCL = 5 ns)
EXTERNAL MEMORY CHARACTERISTICS
24 MHz
Clock
40 MHz
Clock
Variable Oscillator
(3.5-24 MHz)
Symbol Parameter
Min Max
Min Max
Min
Max
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/tCLCL
tLHLL
tAVLL
tLLAX
tLLIV
Oscillator frequency
—
43
2
—
—
—
40
9
—
—
—
—
70
—
—
45
—
25
80
5
3.5
24
—
ALE pulse width
2tCLCL–40
tCLCL–40
tCLCL–35
—
Address valid to ALE low
Address hold after ALE low
ALE low to valid instr in
ALE low to PSEN low
PSEN pulse width
—
—
7
—
30
—
15
65
—
0
—
—
2
105
—
3tCLCL–20
—
tLLPL
tCLCL–40
3tCLCL–45
—
tPLPH
tPLIV
80
—
0
—
—
PSEN low to valid instr in
Input instr hold after PSEN
Input instr float after PSEN
Address to valid instr in
PSEN low to address float
RD pulse width
73
—
2tCLCL–10
—
tPXIX
0
tPXIZ
—
—
—
150
150
—
0
73
147
10
—
—
—
—
100
100
—
0
—
2tCLCL–10
4tCLCL–20
10
tAVIV
—
tPLAZ
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tQVWX
tWHQX
tQVWH
tRLAZ
tWHLH
—
—
—
90
—
50
150
180
6tCLCL–100
6tCLCL–100
—
—
WR pulse width
—
—
RD low to valid data in
Data hold after RD
114
—
5tCLCL–95
—
0
Data float after RD
—
—
—
75
77
2
63
244
285
175
—
—
—
—
—
2tCLCL–70
8tCLCL–90
9tCLCL–90
3tCLCL+50
—
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address to RD or WR low
Data valid to WR transition
Data hold after WR
—
—
60 95
3tCLCL–50
4tCLCL–90
tCLCL–40
tCLCL–40
7tCLCL–70
—
65
10
—
—
—
—
0
—
—
2
—
10
—
Data valid to WR high
RD low to address float
RD or WR high to ALE high
219
—
2
—
165
—
—
63
82
2tCLCL–20
tCLCL+40
15 35
tCLCL–40
Integrated Silicon Solution, Inc. — 1-800-379-4774
43
ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
EXTERNAL MEMORY CHARACTERISTICS
(Continued)
24 MHz
Clock
40 MHz
Clock
Variable Oscillator
(3.5-24 MHz)
Symbol Parameter
Min Max
Min Max
Min
Max
Unit
ns
tXLXL
Serial port clock cycle time
500
284
—
—
250
170
—
—
12tCLCL–10
10tCLCL–133
—
tQVXH
Output data setup to
clock rising edge
—
ns
tXHQX
tXHDX
tXHDV
Output data hold after
clock rising edge
33
0
—
—
33
0
—
—
2tCLCL–50
—
—
ns
ns
ns
Input data hold after
clock rising edge
0
Clock rising edge to
input data valid
—
284
—
117
—
10tCLCL–133
EXTERNAL CLOCK DRIVE
Symbol
1/tCLCL
tCHCX
wParameter
Min
Max
40
—
Unit
MHz
ns
Oscillator Frequency
High time
3.5
10
10
—
tCLCX
Low time
—
ns
tCLCH
Rise time
10
10
ns
tCHCL
Fall time
—
ns
ROM VERIFICATION CHARACTERISTICS
Symbol
1/tCLCL
tAVQV
Parameter
Min
2.5
—
Max
40
Unit
Oscillator Frequency
Address to data valid
ENABLE low to data valid
Data float after ENABLE
MHz
48tCLCL
48tCLCL
48tCLCL
tELQV
—
tEHQZ
0
44
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
TIMING WAVEFORMS
t
LHLL
ALE
PSEN
t
LLPL
t
PLPH
PLIV
t
AVLL
t
t
PLAZ
tPXIZ
t
LLAX
A7-A0
t
PXIX
PORT 0
INSTR IN
A7-A0
t
LLIV
AVIV
A15-A8
t
A15-A8
PORT 2
Figure 32. External Program Memory Read Cycle
ALE
t
WHLH
PSEN
t
LLDV
t
LLWL
tRLRH
RD
t
AVLL
t
RLAZ
LLAX
t
RHDZ
t
RLDV
t
t
RHDX
PORT 0
PORT 2
A7-A0 FROM RI OR DPL
DATA IN
A7-A0 FROM PCL
INSTR IN
t
AVWL
t
AVDV
A15-A8 FROM DPH
A15-A8 FROM PCH
Figure 33. External Data Memory Read Cycle
Integrated Silicon Solution, Inc. — 1-800-379-4774
45
ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
ALE
t
WHLH
PSEN
WR
t
LLWL
tWLWH
t
AVLL
t
WHQX
t
QVWX
DATA OUT
t
LLAX
PORT 0
PORT 2
A7-A0 FROM RI OR DPL
A7-A0 FROM PCL
INSTR IN
t
AVWL
A15-A8 FROM DPH
A15-A8 FROM PCH
Figure 34. External Data Memory Write Cycle
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
t
XLXL
CLOCK
DATAOUT
DATAIN
t
XHQX
t
QVXH
0
1
2
3
4
5
6
7
t
XHDX
SET TI
VALID
t
XHDV
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
Figure 35. Shift Register Mode Timing Waveform
46
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
ADDRESS
AVQV
DATA OUT
P1.0-P1.7
P2.0-P2.3
t
PORT 0
t
ELQV
tEHQZ
P2.7
Figure 36. External Clock Drive Waveform
t
CLCX
tCHCX
Vcc – 0.5V
0.45V
0.7Vcc
0.2Vcc – 0.1
t
CHCL
tCLCH
t
CLCL
Figure 37. ROM Verification Waveforms
Vcc - 0.5V
0.45V
0.2Vcc + 0.9V
0.2Vcc - 0.1V
Figure 38. AC Test Point
Note:
1. AC inputs during testing are driven at VCC – 0.5V for logic “1” and 0.45V for logic “0”.
Timing measurements are made at VIH min for logic “1” and max for logic “0”.
Integrated Silicon Solution, Inc. — 1-800-379-4774
47
ADVANCE INFORMATION MC019-0A
10/01/98
IS80LV52
IS80LV32
®
ISSI
ORDERING INFORMATION
COMMERCIAL TEMPERATURE: 0°C to +70°C
Speed
Order Part Number
Package
24 MHz
IS80LV52-24PL
IS80LV52-24PQ
IS80LV52-24W
PLCC – Plastic Leaded Chip Carrier
PQFP
600-mil Plastic DIP
40 MHz
24 MHz
40 MHz
IS80LV52-40PL
IS80LV52-40PQ
IS80LV52-40W
PLCC – Plastic Leaded Chip Carrier
PQFP
600-mil Plastic DIP
IS80LV32-24PL
IS80LV32-24PQ
IS80LV32-24W
PLCC – Plastic Leaded Chip Carrier
PQFP
600-mil Plastic DIP
IS80LV32-40PL
IS80LV32-40PQ
IS80LV32-40W
PLCC – Plastic Leaded Chip Carrier
PQFP
600-mil Plastic DIP
ORDERING INFORMATION
INDUSTRIAL TEMPERATURE: –40°C to +85°C
Speed
Order Part Number
Package
24 MHz
IS80LV52-24PLI
IS80LV52-24PQI
IS80LV52-24WI
PLCC – Plastic Leaded Chip Carrier
PQFP
600-mil Plastic DIP
40 MHz
24 MHz
40 MHz
IS80LV52-40PLI
IS80LV52-40PQI
IS80LV52-40WI
PLCC – Plastic Leaded Chip Carrier
PQFP
600-mil Plastic DIP
IS80LV32-24PLI
IS80LV32-24PQI
IS80LV32-24WI
PLCC – Plastic Leaded Chip Carrier
PQFP
600-mil Plastic DIP
IS80LV32-40PLI
IS80LV32-40PQI
IS80LV32-40WI
PLCC – Plastic Leaded Chip Carrier
PQFP
600-mil Plastic DIP
®
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Fax: (408) 588-0806
Toll Free: 1-800-379-4774
http://www.issiusa.com
48
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION MC019-0A
10/01/98
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