IXDI430YI [IXYS]
30 Amp Low-Side Ultrafast MOSFET / IGBT Driver; 30安培低端超快MOSFET / IGBT驱动器
| 型号： | IXDI430YI |
| 厂家： | 
IXYS CORPORATION |
| 描述： | 30 Amp Low-Side Ultrafast MOSFET / IGBT Driver |
| 文件： | 总12页 (文件大小：782K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IXDN430 / IXDI430 / IXDD430 / IXDS430
30 Amp Low-Side Ultrafast MOSFET / IGBT Driver
General Description
Features
• Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes
• Latch-UpProtected
• High Peak Output Current: 30A Peak
• Wide Operating Range: 8.5V to 35V
• Under Voltage Lockout Protection
• Ability to Disable Output under Faults
• High Capacitive Load
TheIXDN430/IXDI430/IXDD430/IXDS430arehighspeedhigh
current gate drivers specifically designed to drive MOSFETs
and IGBTs to their minimum switching time and maximum
practical frequency limits. The IXD_430 can source and sink
30A of peak current while producing voltage rise and fall times
of less than 30ns. The input of the drivers are compatible with
TTL or CMOS and are fully immune to latch up over the entire
operating range. Designed with small internal delays, cross
conduction/current shoot-through is virtually eliminated in all
configurations. Their features and wide safety margin in
operatingvoltageandpowermakethedriversunmatchedin
performanceandvalue.
Drive Capability: 5600 pF in <25ns
• Matched Rise And Fall Times
• Low Propagation Delay Time
• LowOutputImpedance
• LowSupplyCurrent
The IXD_430 incorporates a unique ability to disable the output
under fault conditions. The standard undervoltage lockout is at
12.5V which can also be set to 8.5V in the IXDS430SI. When a
logical low is forced into the Enable inputs, both final output
stage MOSFETs (NMOS and PMOS) are turned off. As a
result, the output of the IXDD430 enters a tristate mode and
enables a Soft Turn-Off of the MOSFET when a short circuit is
detected. This helps prevent damage that could occur to the
MOSFET if it were to be switched off abruptly due to a dv/dt
over-voltagetransient.
Applications
• DrivingMOSFETsandIGBTs
• MotorControls
• LineDrivers
• PulseGenerators
• Local Power ON / OFF Switch
• Switch Mode Power Supplies (SMPS)
• DCtoDCConverters
• PulseTransformerDriver
• Limiting di/dt Under Short Circuit
• Class D Switching Amplifiers
TheIXDN430isconfiguredasanoninvertinggatedriver, andthe
IXDI430isaninvertinggatedriver.TheIXDS430canbeconfigured
eitherasanoninvertingorinvertingdriver.TheIXD_430areavailable
inthestandard28-pinSIOC(SI-CT),5-pinTO-220(CI),andinthe
TO-263(YI)surfacemountpackages.CTor'CoolTab'forthe28-
pin SOIC package refers to the backside metal heatsink tab.
Ordering Information
Part Num ber
IXDD430YI
IXDD430CI
IXDI430YI
Package Type
5-pin TO -263
5-pin TO -220
5-pin TO -263
5-pin TO -220
5-pin TO -263
5-pin TO -220
Tem p. Range
Configuration
Non Inverting with
Enable
-55°C to +125°
-55°C to +125°
-55°C to +125°
Inverting
IXDI430CI
IXDN430YI
IXDN430CI
Non Inverting
Inverting / Non
Inverting with Enable
and UVSEL
-55°C to +125°
IXDS430SI
28-pin SO IC
Copyright © IXYS CORPORATION 2004
DS99045B(8/04)
First Release
IXDN430 / IXDI430 / IXDD430 / IXDS430
Figure 1A - IXDD430 (Non Inverting With Enable) Diagram
Vcc
Vcc
400k
OUT P
OUT N
1K
IN
EN
GND
Vcc
GND
Vcc
Figure1B-IXDN430(Non-Inverting)Diagram
OUT P
OUT N
1K
IN
GND
GND
Vcc
Figure 1C - IXDI430 (Inverting) Diagram
Vcc
IN
OUT P
OUT N
1K
GND
GND
Figure 1D - IXDS430 (Inverting and Non Inverting with Enable) Diagram
Vcc
Vcc
OUT P
OUT N
1K
IN
EN
400K
400K
INV
GND
GND
Note: Out P and Out N are connected together in the 5 lead TO-220 and TO-263 packages.
2
IXDN430 / IXDI430 / IXDD430 / IXDS430
Operating Ratings
Absolute Maximum Ratings (Note 1)
Param eter
Value
Parameter
Value
Maxim um Junction Tem perature
Operating Temperature Range
Therm al Impedance TO220 (CI), TO263 (YI)
θJC (Junction To Case)
o
150
C
Supply Voltage
All Other Pins
40 V
o
o
-0.3 V to V
+ 0.3 V
-55 C to 125 C
CC
o
Power Dissipation, TAMBIENT ≤25
TO220 (CI), TO263 (YI)
C
o
0.95 C/W
2W
o
θJA (Junction To Ambient)
62.5 C/W
Derating Factors (to Ambient)
Therm al Impedance 28 pin SOIC with Heat Slug (SI)
TO220 (CI), TO263 (YI)
o
o
θJC (Junction To Case)
0.016W/ C
3
C/W
Storage Temperature
Lead Temperature (10 sec)
o
o
-65 C to 150
C
o
300
C
Electrical Characteristics
Unless otherwise noted, TA = 25 oC, 8.5V ≤ VCC ≤ 35V .
All voltage measurements with respect to GND. IXDD430 configured as described in Test Conditions.
Symbol
VIH
VIL
VIN
IIN
Parameter
Test Conditions
4.5V ≤ VCC ≤ 18V
4.5V ≤ VCC ≤ 18V
Min
3.5
Typ
Max
0.8
VCC + 0.3
10
Units
V
V
V
µA
High input voltage
Low input voltage
Input voltage range
Input current
-5
-10
0V ≤ VIN ≤ VCC
VOH
VOL
ROH
High output voltage
Low output voltage
VCC - 0.025
V
V
Ω
0.025
0.4
Output resistance
VCC = 18V
VCC = 18V
VCC = 18V
0.3
0.2
30
@ Output high
ROL
IPEAK
IDC
Output resistance
@ Output Low
0.3
Ω
A
A
Peak output current
Continuous output
current
Enable voltage range
Limited by package power
dissipation
IXDD430 Only
IXDD430 Only
IXDD430 Only
IXDS430 Only
IXDS430 Only
IXDS430 Only
IXDS430 Only
8
VEN
- 0.3
2/3 Vcc
Vcc + 0.3
V
V
V
VENH
VENL
REN
VINV
VINVH
VINVL
RINV
tR
High En Input Voltage
Low En Input Voltage
EN Input Resistance
INV Voltage Range
High INV Input Voltage
Low INV Input Voltage
INV Input Resistance
Rise tim e
1/3 Vcc
Vcc + 0.3
1/3 Vcc
400
Kohm
V
V
V
Kohm
ns
ns
- 0.3
2/3 Vcc
IXDS430 Only
400
18
16
CL=5600pF Vcc=18V
CL=5600pF Vcc=18V
CL=5600pF Vcc=18V
20
18
45
tF
tONDLY
Fall time
On-time propagation
41
ns
delay
tOFFDLY
tENOH
Off-time propagation
delay
CL=5600pF Vcc=18V
IXDD430 Only, Vcc=18V
IXDD430 Only, Vcc=18V
35
39
47
ns
ns
ns
V
mA
µA
µA
Enable to output high
delay time
tDOLD
Disable to output low
delay time
120
35
VCC
ICC
Power supply voltage
8.5
18
1
0
Power supply current
VIN = 3.5V
VIN = 0V
3
10
10
V
IN = + VCC
Specifications Subject To Change Without Notice
Note 1: Operating the device beyond parameters with listed “absolute maximum ratings” may cause permanent
damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not
guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
3
IXDN430 / IXDI430 / IXDD430 / IXDS430
ElectricalCharacteristics
Unless otherwise noted, temperature over -55 oC to +125 oC, 4.5 ≤ VCC ≤ 35V .
All voltage measurements with respect to GND. IXDD430 configured as described in Test Conditions.
Symbol
VIH
VIL
VIN
ROH
Parameter
Test Conditions
4.5V ≤ VCC ≤ 18V
4.5V ≤ VCC ≤ 18V
Min
3.2
Typ
Max
Units
High input voltage
Low input voltage
Input voltage range
Output resistance
@ Output high
Output resistance
@ Output Low
Rise time
V
V
V
Ω
1.1
VCC + 0.3
0.46
-5
VCC = 18V
VCC = 18V
ROL
0.4
Ω
tR
tF
tONDLY
CL=5600pF Vcc=18V
CL=5600pF Vcc=18V
CL=5600pF Vcc=18V
20
18
58
ns
ns
ns
Fall time
On-time propagation
delay
tOFFDLY
VCC
Off-time propagation
delay
CL=5600pF Vcc=18V
51
35
ns
V
Power supply voltage
8.5
18
5-lead TO-220 Outline (IXD_430CI)
5-lead TO-263 Outline (IXD_430YI)
28-pin SOIC Outline (IXD_430SI)
NOTE: Mounting tabs, solder tabs, or heat sink metalization on all packages are connected to ground.
4
IXDN430 / IXDI430 / IXDD430 / IXDS430
Pin Configurations
Vcc 1
28 Vcc
Vcc 2
Vcc 3
27 Vcc
26 Vcc
Vcc 4
25 Vcc
N/C 5
28 Pin SOIC
(SI-CT)
24 OUT P
23 OUT P
22 OUT P
21 OUT N
20 OUT N
19 OUT N
18 GND
Vcc
OUT
GND
IN
1
2
3
4
5
UVSEL 6
N/C 7
IN 8
EN 9
EN *
INV 10
GND 11
GND 12
GND 13
GND 14
TO220(CI)
TO263(YI)
17 GND
16 GND
15 GND
Pin Description
SYMBOL
FUNCTION
DESCRIPTION
Positive power-supply voltage input. This pin provides power to the
entire chip. The range for this voltage is from 8.5V to 35V.
Input signal-TTL or CMOS compatible.
VCC
IN
Supply Voltage
Input
The system enable pin. This pin, when driven low, disables the chip,
forcing high impedance state to the output (IXDD430 Only).
Forcing INV low causes the IXDS430 to become non-inverted, while
forcing INV high causes the IXDS430 to become inverted.
Respective P and N driver outputs. For application purposes this pin
is connected, through a resistor, to Gate of a MOSFET/IGBT. The P
and N output pins are connected together in the TO-263 and TO-220
packages.
EN *
Enable
INV
Invert
OUT P
OUT N
Output
The system ground pin. Internally connected to all circuitry, this pin
provides ground reference for the entire chip. This pin should be
GND
Ground
connected to
performance.
a low noise analog ground plane for optimum
Select Under
Voltage Level
With UVSEL connected to Vcc, IXDS430 outputs go low at Vcc <
8.5V; With UVSEL open, under voltage level is set at Vcc < 12.5V
UVSEL
* This pin is used only on the IXDD430, and is N/C (not connected) on the IXDI430 and IXDN430.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures when
handling and assembling this component.
Figure 2 - Characteristics Test Diagram
.
.
Vcc
OUT
Vcc
+
C
BYPASS/
FILTER
-
IXDD430
GND
CLOAD
IN
EN
+
-
Vin
5
IXDN430 / IXDI430 / IXDD430 / IXDS430
Typical Performance Characteristics
Fig. 3
35
Fig. 4
30
Rise Times vs. Supply Voltage
Fall Times vs. Supply Voltage
30
25
20
15
10
5
25
20
15
10
5
15000 pF
15000 pF
10000 pF
5600 pF
10000 pF
5600 pF
1000 pF
1000 pF
0
0
10
15
20
25
30
35
10
15
20
25
30
35
Supply Voltage (V)
Supply Voltage (V)
Fig. 6
30
Output Fall Times vs. Load Capacitance
Fig. 5
Output Rise Times vs. Load Capacitance
13V
18V
35V
30
25
20
15
10
5
35V
18V
13V
25
20
15
10
5
0
1000
3000
5000
7000
9000
11000
13000
15000
1000
3000
5000
7000
9000
11000
13000
15000
Load Capacitance (pF)
Load Capacitance (pF)
Rise and Fall Times vs. Temperature
CL = 5600 pF, Vcc = 18V
Max / Min Input vs. Temperature
CL = 5600pF, Vcc = 18V
Fig. 7
Fig. 8
25
4
3.5
3
Min Input High
20
15
10
5
tR
Max Input Low
2.5
2
tF
1.5
1
0.5
0
0
-60
-10
40
90
140
190
-60
-10
40
90
140
190
Temperature (C)
Temperature (C)
6
IXDN430 / IXDI430 / IXDD430 / IXDS430
Supply Current vs. Load Capacitance
Vcc = 13V
Fig. 9
Supply Current vs. Frequency
Vcc = 13V
Fig. 10
1000
300
15000 pF
10000 pF
5600 pF
1000 pF
2 MHz
250
200
150
100
50
100
10
1
1 MHz
500 kHz
100 kHz
50 kHz
10 kHz
0.1
0
1
10
100
1000
10000
1000
10000
100000
Frequency (kHz)
Load Capacitance (pF)
Supply Current vs. Load Capacitance
Vcc = 18V
Fig. 11
Fig. 12
Supply Current vs. Frequency
Vcc = 18V
300
15000 pF
10000 pF
5600 pF
1000 pF
1000
2 MHz
1 MHz
250
200
150
100
50
100
10
1
500 kHz
100 kHz
50 kHz
10 kHz
0.1
1
0
1000
10
100
1000
10000
10000
100000
Frequency (kHz)
Load Capacitance (pF)
Supply Current vs. Frequency
Vcc = 25V
Fig. 14
Fig. 13
Supply Current vs. Load Capacitance
Vcc = 25V
15000 pF
10000 pF
5600 pF
1000 pF
1000
400
350
300
250
200
150
100
50
2 MHz
1 MHz
100
10
1
500 kHz
100 kHz
50 kHz
10 kHz
0
1000
0.1
1
10
100
1000
10000
10000
100000
Frequency (kHz)
Load Capacitance (pF)
7
IXDN430 / IXDI430 / IXDD430 / IXDS430
Fig. 15
Supply Current vs. Load Capacitance
Vcc = 35V
Fig. 16
Supply Current vs. Frequency
Vcc = 35V
15000 pF
10000 pF
5600 pF
1000 pF
400
1000
350
300
250
200
150
100
50
1 MHz
500 kHz
100
10
100 kHz
50 kHz
10 kHz
1
1
0
1000
10000
100000
10
100
1000
10000
Load Capacitance (pF)
Frequency (kHz)
Propagation Delay vs. Input Voltage
CL = 5600 pF Vcc = 18V
Fig. 18
Propagation Delay vs. Supply Voltage
CL = 5600 pF Vin = 15V@1kHz
Fig. 17
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
tONDLY
tONDLY
tOFFDLY
tOFFDLY
0
5
0
10
15
20
25
30
35
10
15
20
25
Supply Voltage (V)
Input Voltage (V)
Fig. 20
Quiescent Supply Current vs. Temperature
Vcc = 18V, Vin = 15V@1kHz, CL = 5600pF
Fig. 19
Propagation Delay Times vs. Temperature
CL = 5600pF, Vcc = 18V
0.6
70
60
50
40
30
20
10
0.5
0.4
0.3
0.2
0.1
tONDLY
tOFFDLY
0
0
-60
-10
40
90
140
190
-60
-10
40
90
140
190
Temperature (C)
Temperature (C)
8
IXDN430 / IXDI430 / IXDD430 / IXDS430
High State Output Resistance vs. Supply Voltage
Low State Output Resistance vs. Supply Voltage
Fig. 22
Fig. 21
0.25
0.2
0.15
0.1
0.05
0
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
10
15
20
25
30
35
40
10
15
20
25
30
35
40
Supply Voltage (V)
Supply Voltage (V)
Fig. 23
P Channel Output Current vs. Vcc
N Channel Output Current vs. Vcc
Fig. 24
0
70
-10
-20
-30
-40
-50
-60
-70
60
50
40
30
20
10
-80
10
0
15
20
25
30
35
40
10
15
20
25
30
35
40
Vcc (V)
Vcc (V)
P Channel Output Current vs. Temperature
Vcc = 18V
N Channel Output Current vs. Temperature
Vcc = 18V
Fig. 25
Fig. 26
45
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
0
0
-60
-10
40
90
140
190
-60
-10
40
90
140
190
Temperature (C)
Temperature (C)
9
IXDN430 / IXDI430 / IXDD430 / IXDS430
Figure 27 - Typical circuit to decrease di/dt during turn-off
Figure 28 - IXDD430 Application Test Diagram
+
VB
Ld
10uH
-
Rd
0.1ohm
IXDD430
VCC
Rg
VCCA
High_Power
OUT
VMO580-02F
Rs
IN
1ohm
Rsh
EN
1.5k ohm
+
-
+
-
VCC
VIN
GND
SUB
Low_Power
2N7002/PLP
Ls
R+
10kohm
20nH
One ShotCircuit
0
Rcomp
5kohm
Comp
LM339
+
V+
NAND
NOT2
C+
100pF
NOT1
CD4011A
CD4049A
V-
-
CD4049A
Ccomp
1pF
Ros
+
-
R
1Mohm
REF
Cos
1pF
Q
NOT3
NOR1
S
CD4049A
CD4001A
EN
NOR2
CD4001A
SR Flip-Flop
10
IXDN430 / IXDI430 / IXDD430 / IXDS430
APPLICATIONS INFORMATION
Short Circuit di/dt Limit
A short circuit in a high-power MOSFET module such as the
VM0580-02F, (580A, 200V), as shown in Figure 27, can cause
the current through the module to flow in excess of 1500A for
10µs or more prior to self-destruction due to thermal runaway.
For this reason, some protection circuitry is needed to turn off
the MOSFET module. However, if the module is switched off
too fast, there is a danger of voltage transients occuring on the
drain due to Ldi/dt, (where L represents total inductance in
series with drain). If these voltage transients exceed the
MOSFET's voltage rating, this can cause an avalanche break-
down.
In this way, the high-power MOSFET module is softly turned off
by the IXDD430, preventing its destruction.
Supply Bypassing and Grounding Practices,
Output Lead inductance
When designing a circuit to drive a high speed MOSFET
utilizing the IXDD430/IXDI430/IXDN430, it is very important to
keep certain design criteria in mind, in order to optimize
performance of the driver. Particular attention needs to be paid
to Supply Bypassing, Grounding, and minimizing the Output
Lead Inductance.
TheIXDD430hastheuniquecapabilitytosoftlyswitchoffthe
high-power MOSFET module, significantly reducing these
Ldi/dttransients.
Say, for example, we are using the IXDD430 to charge a 15nF
capacitive load from 0 to 25 volts in 25ns.
Thus, the IXDD430 helps to prevent device destruction from
both dangers; over-current, and avalanche breakdown due to
di/dt induced over-voltage transients.
Using the formula: I= C ∆V / ∆t, where ∆V=25V C=15nF &
∆t=25ns we can determine that to charge 15nF to 25 volts in
25ns will takeaconstantcurrent of 15A. (Inreality,thecharging
current won’t be constant, and will peak somewhere around
30A).
The IXDD430 is designed to not only provide ±30A under
normal conditions, but also to allow it's output to go into a high
impedance state. This permits the IXDD430 output to control
a separate weak pull-down circuit during detected overcurrent
shutdown conditions to limit and separately control dVGS/dt gate
turnoff. This circuit is shown in Figure 28.
SUPPLYBYPASSING
In order for our design to turn the load on properly, the IXDD430
must be able to draw this 5A of current from the power supply
in the 25ns. This means that there must be very low impedance
between the driver and the power supply. The most common
method of achieving this low impedance is to bypass the power
supply at the driver with a capacitance value that is a magnitude
larger than the load capacitance. Usually, this would be
achievedbyplacingtwodifferenttypesofbypassingcapacitors,
with complementary impedance curves, very close to the driver
itself. (These capacitors should be carefully selected, low
inductance, low resistance, high-pulse current-service
capacitors). Lead lengths may radiate at high frequency due
to inductance, so care should be taken to keep the lengths of
the leads between these bypass capacitors and the IXDD430
to an absolute minimum.
Referring to Figure 28, the protection circuitry should include
a comparator, whose positive input is connected to the source
of the VM0580-02. A low pass filter should be added to the input
of the comparator to eliminate any glitches in voltage caused
by the inductance of the wire connecting the source resistor to
ground. (Those glitches might cause false triggering of the
comparator).
The comparator's output should be connected to a SRFF(Set
Reset Flip Flop). The flip-flop controls both the Enable signal,
and the low power MOSFET gate. Please note that CMOS
4000-series devices operate with a VCC range from 3 to 15 VDC,
(with 18 VDC being the maximum allowable limit).
GROUNDING
A low power MOSFET, such as the 2N7000, in series with a
resistor, will enable the VMO580-02F gate voltage to drop
gradually. The resistor should be chosen so that the RC time
constant will be 100us, where "C" is the Miller capacitance of
theVMO580-02F.
In order for the design to turn the load off properly, the IXDD430
must be able to drain this 5A of current into an adequate
grounding system. There are three paths for returning current
that need to be considered: Path #1 is between the IXDD430
and it’s load. Path #2 is between the IXDD430 and it’s power
supply. Path #3 is between the IXDD430 and whatever logic is
driving it. All three of these paths should be as low in resistance
and inductance as possible, and thus as short as practical. In
addition, every effort should be made to keep these three
ground paths distinctly separate. Otherwise, (for instance), the
returning ground current from the load may develop a voltage
that would have a detrimental effect on the logic line driving the
IXDD430.
For resuming normal operation, a Reset signal is needed at
the SRFF's input to enable the IXDD430 again. This Reset can
be generated by connecting a One Shot circuit between the
IXDD430InputsignalandtheSRFFrestartinput. TheOneShot
will create a pulse on the rise of the IXDD430 input, and this
pulse will reset the SRFF outputs to normal operation.
When a short circuit occurs, the voltage drop across the low-
value, current-sensing resistor, (Rs=0.005 Ohm), connected
between the MOSFET Source and ground, increases. This
triggers the comparator at a preset level. The SRFF drives a
low input into the Enable pin disabling the IXDD430 output. The
SRFF also turns on the low power MOSFET, (2N7000).
11
IXDN430 / IXDI430 / IXDD430 / IXDS430
OUTPUTLEADINDUCTANCE
Of equal importance to Supply Bypassing and Grounding are
issues related to the Output Lead Inductance. Every effort
should be made to keep the leads between the driver and it’s
load as short and wide as possible. If the driver must be placed
farther than 2” from the load, then the output leads should be
treated as transmission lines. In this case, a twisted-pair
should be considered, and the return line of each twisted pair
should be placed as close as possible to the ground pin of the
driver, and connect directly to the ground terminal of the load.
A TTL or 5V CMOS logic low, V
=~<0.8V, input applied to the
Q1 emitter will drive it on. ThisTcTLaLuOWses the level translator
output, the Q1 collector output to settle to VCESATQ1
+
V
TTLLOW=<~2V, which is sufficiently low to be correctly interpreted
as a high voltage CMOS logic low (<1/3VCC=5V for VCC =15V given
in the IXDD430 data sheet.)
A TTL high, VTTLHIGH=>~2.4V, or a 5V CMOS high,
V5VCMOSHIGH=~>3.5V, applied to the EN input of the circuit in
Figure 29 will cause Q1 to be biased off. This results in Q1
collector being pulled up by R3 to V =15V, and provides a
high voltage CMOS logic high outpuCt.C The high voltage CMOS
logical EN output applied to the IXDD430 EN input will enable
it, allowing the gate driver to fully function as an 30 Amp
output driver.
TTL to High Voltage CMOS Level Translation
(IXDD430 Only)
The enable (EN) input to the IXDD430 is a high voltage
CMOS logic level input where the EN input threshold is ½
V , and may not be compatible with 5V CMOS or TTL input
leCvCels. The IXDD430 EN input was intentionally designed
for enhanced noise immunity with the high voltage CMOS
logic levels. In a typical gate driver application, V =15V
and the EN input threshold at 7.5V, a 5V CMOS lCoCgical high
input applied to this typical IXDD430 application’s EN input
will be misinterpreted as a logical low, and may cause
undesirable or unexpected results. The note below is for
optional adaptation of TTL or 5V CMOS levels.
The total component cost of the circuit in Figure 29 is less
than $0.10 if purchased in quantities >1K pieces. It is
recommended that the physical placement of the level
translator circuit be placed close to the source of the TTL or
CMOS logic circuits to maximize noise rejection.
The circuit in Figure 29 alleviates this potential logic level
misinterpretation by translating a TTL or 5V CMOS logic
input to high voltage CMOS logic levels needed by the
IXDD430 EN input. From the figure, VCC is the gate driver
power supply, typically set between 8V to 20V, and VDD is
the logic power supply, typically between 3.3V to 5.5V.
Resistors R1 and R2 form a voltage divider network so
that the Q1 base is positioned at the midpoint of the
expected TTL logic transition levels.
Figure 29 - TTL to High Voltage CMOS Level Translator
(From gate driver
power supply)
Vcc
Vdd
(From logic
power supply)
R3
10K
R1
10K
High Voltage
CMOS EN output
(To IXDD430 EN input)
Q1
2N3904
R2
10K
5V CMOS or TTL input
EN
IXYS Corporation
IXYS Semiconductor GmbH
3540 Bassett St; Santa Clara, CA 95054
Tel: 408-982-0700; Fax: 408-496-0670
www.ixys.com
Edisonstrasse15 ; D-68623; Lampertheim
Tel: +49-6206-503-0; Fax: +49-6206-503627
e-mail: marcom@ixys.de
e-mail: sales@ixys.net
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