IXTP90N075T2 [IXYS]

DC to DC Synchronous Converter Design; DC到DC同步转换器设计


型号：	IXTP90N075T2
厂家：	IXYS CORPORATION
描述：	DC to DC Synchronous Converter Design DC到DC同步转换器设计转换器
文件：	总11页 (文件大小：200K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DC to DC Synchronous Converter Design

Abdus Sattar, IXYS Corporation

IXAN0068

Modern power electronics products require small size and lighter weight of power

electronics parts. Filter inductor and capacitor sizes must be small. With the small filter,

the switching semiconductor devices must have small switching loss. And heat sink also

must be reduced. For the safe operation with the small heat sink, the switching

semiconductor devices must have small conduction loss. IXYS developed new generation

of Trench MOSFET (Trench2^TM), which has small gate charge and low on-resistance.

The MOSFET will be well suited for high power applications of synchronous DC to DC

converters used in various systems. The MOSFET is rugged and has avalanche energy

capability.

Table 1: Few Examples of IXYS TrenchT2^TMN-Channel Power MOSFETs

Vdss

(max) Tc=25C

(V) (A)

Rds(on)

Ciss

(pF)

(nC

)

trr @

Tj=

R(th)JC

(°C/W)

Package

Type

Part Number

E_AS

(mJ)

(W)

Tj=25°C

(Ω)

25°C

(ns)

600

300

400

600

300

400

IXTA220N04T2

IXTP220N04T2

IXTA90N055T2

IXTP90N055T2

IXTA110N055T2

IXTP110N055T2

IXTA200N055T2

IXTP200N055T2

IXTA70N075T2

IXTP70N075T2

IXTA90N075T2

IXTP90N075T2

360

150

180

360

150

180

TO‐263

TO‐220

TO‐263

TO‐220

TO‐263

TO‐220

TO‐263

TO‐220

TO‐263

TO‐220

TO‐263

TO‐220

220

0.0035

0.0084

0.0066

0.0042

0.012

6500 112

0.42

1.0

220

2670

3060

1.0

110

200

0.82

0.42

1.0

6800 109

2580

3100

0.012

1.0

0.010

0.82

0.010

DC-to-DC Synchronous Converter Design:

Figure 1: Synchronous Buck Converter using IXYS TrenchT2^TMPower MOSFET

DC to DC Synchronous Converter Design

Abdus Sattar, IXYS Corporation

IXAN0068

In Figure 1, the Q1 is called the high-side or control FET and Q2 is called the

low-side or sync FET applied in a step-down DC to DC synchronous converter

application. The ratio Vo /Vin is controlled by the duty cycle of Q1. To improve the

efficiency, it’s desirable to have Q2 turned ON when Q1 is turned OFF. A simplified

switch state diagram is shown in Figure 2 [2]. It depicts the switching sequence as A-B-

C-B-A where the state B called “dead time” when both Q1 and Q2 are OFF and the

Schottky diode, D1 is ON to provide the freewheeling operation in the inductive load

circuit. It’s desirable to reduce the dead time to a minimum to improve the efficiency.

However, if the dead time is lower than the turn-on or turn-off times of Q1 and Q2, the

circuit may go into state D, the shoot-through state when both Q1 and Q2 are ON at the

same time causing a short-circuit in the input voltage source, Vin. The state D is

undesirable since it would destroy transistors Q1 and Q2.

Figure 2: Circuit Switch State Diagram [2]

DC to DC Synchronous Converter Design

Abdus Sattar, IXYS Corporation

IXAN0068

Figure 3: Ideal Circuit waveforms (with no dead time)

The Switching Period, T_S= T_on+T_off, the Switching frequency, f_S=

T_S

T_on

T_ST_on+ T_off

Turn-off time, T_off= (1− D)T_S.

The duty cycle, D =

, Turn-on time, T_on= DT_S

Figure 4: Ideal synchronous buck converter inductor current

An output DC voltage with lowest ripple is considered the best solution. Ripple appears

in the output voltage as the L1 current’s ripple component, ΔI_L1(t) , which charges and

discharges the output capacitor, C1, as shown in Figure 4. C1 is charged during the

DC to DC Synchronous Converter Design

Abdus Sattar, IXYS Corporation

IXAN0068

period when I_L1(t) is greater than I_o. The charge (ΔQ ) that flows into C1 at this time

divided by the value of C1 is the output voltage ripple component.

Output Inductor Ripple Current and Voltage:

The inductor voltage can be defined as,

Δt(Vin −Vo)

V_L= L1 = Vin −Vo , or, Δi = ΔI_L1(t) =

, here, Δt = Ton = DTs

The inductor ripple current is,

Vin −Vo D(Vin −Vo)

ΔI_L1(t) = DTs

(1)

f_S• L1

The charge, ΔQ , indicated in Figure 5, can be determined by calculating the area of the

ΔI_L1(t)

triangle with height

and width

shown in Figure 5.

ΔI_L1(t) T_SΔI_L1(t) •T _SΔI_L1(t)

ΔQ =

•

8 f_S

The ripple voltage is,

ΔQ

D(1− D)VinTs²π ²(1− D)Vo

ΔI_L1(t)Ts

ΔV_L(t) =

(

^C)²= ΔV_O(t)

(2)

8C1

8L1C1

f_S

Where, f_C=

, Output low pass filter (LPF) resonant frequency, f_S= The

2π L1C1

switching frequency. The inductor value of L1 and the effective series resistance (ESR)

of the output capacitor, C1, affect the output ripple voltage, ΔV_L. A capacitor with the

lowest possible ESR is recommended for the application. For example, 4.7–10 uF

capacitors in X5R/X7R technology have ESR approximately 10 mΩ..

Summary of design equations:

Ripples voltage/current, Inductor and Capacitor:

ΔI_L1(t)Ts ΔI_L1(t)

Output ripple voltage, ΔV_L(t) =

(3)

8C1

8C1f_S

Inductor ripple current, ΔI_L1(t) = 8C1f_S• ΔV_L(t)

Vin −Vo D(Vin −Vo)

(4)

(5)

Output inductor, L1 ≥ DTs

ΔI_L1(t)

f_S• ΔI_L1(t)

ΔI_L1

8 f_sΔVo

ΔI_L1(t)

Output capacitor, C1 ≥

since ΔQ =

•

= C1• ΔVo (6)

Output filter cut-off frequency, f_C=

(7)

2π L1C1

DC to DC Synchronous Converter Design

Abdus Sattar, IXYS Corporation

IXAN0068

Overview of Synchronous Converter Power Loss: [1]

The losses in the synchronous converter’s power switches can be defined by:

= P + P + P + P_BD

(8)

Total

Gate

Where P_Cis the conduction loss, P_swis the switching power loss, P_Gateis the gate drive

loss and P_BDis the body diode loss. In addition, inductor equivalent DC resistance losses

and output capacitor’s ESR loss play significant role in the converter design.

MOSFET Q1 and Q2’s Power Loss: [1]

The conduction losses: (replace D to 1-D for Sync FET, Q2):

P = (I_OD) ²• R_DS(on)

(9)

The gate-charge losses:

P_g−C= V_GS•Q_g• f_s

(10)

The switching losses:

Figure 5: Transitions waveforms of MOSFET for inductive load

The switching loss is,

= P + P

Switching

t(on)

t(off )

[V_DS(max){I_DS(on)•t_t(on)+ I_{DS(off )}•t_{t(off )}}• f_s]

(11)

MOSFET Body Diode Loss: [1]

The body diode loss is a function of dead time and in every switching cycle; there are two

dead-time intervals, td1 and td2. The dead-time is defined as the time required when both

the MOSFETs Q1 and Q2 are OFF in order to prevent shoot-through.

DC to DC Synchronous Converter Design

Abdus Sattar, IXYS Corporation

IXAN0068

We can write as:

P_BD= P + P

(12)

td1

td 2

Where Ptd1 is the body diode loss during dead time td1 and Ptd2 is the body diode loss

during dead time td2.

ΔI_L

⎛

⎞

⎟

P = P + P = V • I −

•td1• f + •V • I •t • f

(13)

(14)

⎜

td1

cd1

rr1

⎝

⎠

ΔI_L

⎛

⎞

⎟

= P

(

= 0

)

= V • I +

•td2 • f

⎜

td 2

cd 2

rr2

⎝

⎠

PWM Gate Driver Power loss: [1]

The power dissipation in the driver is defined by,

P_DRIVER= Q_G(onl)•V_DD• f_S

(15)

where Q_g(onl)is the total gate charge of the MOSFET and V_DDis the driver power supply.

The gate “point of voltage” is,

I_O

V_SP= V_TH

(16)

g _fs

The driver current is,

V_DD−V_SP

R_{DRIVER(PULL−UP)}+ R_Gate

V_DD−V_SP

I_{DRIVER(L−H )}

I_{DRIVER(H −L)}

(17)

(18)

R_{DRIVER(PULL−DOWN )}+ R_Gate

The rise time is,

Q_G(on)

t_t(on)

(19)

(20)

I_{DRIVER(L−H )}

The fall time is,

Q_G(on)

t_{t(off )}

I_{DRIVER(H −L)}

If an external Schottky diode (D1) is used across Q2, the Schottky’s capacitance needs to

be charged during Q1 turn-on. The power loss to charge the Schottky’s capacitance is,

C_SCHOTTKY•V_IN²• f_S

(21)

C(SCHOTTKY )

DC to DC Synchronous Converter Design

Abdus Sattar, IXYS Corporation

IXAN0068

Design Example 1:

Assume design parameters as VIN=12V, VO=3.3V and Io=12A.

Table 1: Design Consideration 1 for synchronous buck converter

Input Voltage, Vin

Output Voltage, Vo

Output Current, Io

12V

3.3V

12A

Assume the output ripple voltage is within ± 1% of Vo. For Vo =3.3V, the output ripple

is limited within, ΔV_L(t) ≤ 0.033V . When the output capacitor (C1) is 10uF, the inductor

L1 values for the range of switching frequencies from 100 kHz to 500 kHz are given in

Table: 2 based on equations 3-7.

Table 2: When C1= 10uF

Vin Vo

(V) (V)

ΔV_L

(V)

(kHz)

(uF)

ΔΙ_L1

(A)

(uH)

(kHz)

12 3.3 0.275 0.033

100

0.264

45.31

30.20

22.65 10.60

18.12 11.83

5.31

7.48

9.16

200

300

400

500

0.528

0.792

1.056

1.32

Synchronous Driver Controller: ISL6594D from Intersil:

Based on equation 18 and 19, From ISL6594D driver datasheet, given high-side: tr=26nS,

tf=18nS and source/sink current = 1.25/2A (max). For low-side, trr=18nS, tf=12nS and

source/sink current = 2/3.0 A (max):

Table 4: from Datasheet

High-Side

Rise time

Source Current (A) Required Qg(on)

Source

Sink

26 ns

18 ns

1.25

32.5nC

36nC

Low-Side

Rise time

Source Current (A) Required Qg(on)

Source

Sink

18nS

12ns

36nC

DC to DC Synchronous Converter Design

Abdus Sattar, IXYS Corporation

IXAN0068

ISL6594D Specification:

Recommended devices for this application:

1. IXTA90N055T2

VDS = 55V, Id25=90A

Qg(on) = 42nC, Qgs = 14nC, Qgd = 8.5nC,

td(on) = 19nS, tr = 21nS, td(off) = 39nS, tf = 19nS.

Rds(on) = 8.4mΩ

Vgs(th) = 2-4V, g_fs= 43

Ciss = 2670pF, Coss = 420pF, Crss = 100pF

Or,

1. IXTA110N055T2

Vds = 55V, Id25=110A

Qg(on) = 57nC, Qgs = 16nC, Qgd = 11nC,

td(on) = 18nS, tr = 25nS, td(off) = 40nS, tf = 23nS.

Rds(on) = 6.6mΩ , Vgs(th) = 2-4V, g_fs= 49

Ciss = 3060pF, Coss = 497pF, Crss = 105pF

Analysis based on Above IXTA90N055T2:

14nC

Q_{G(SW )}= 8.5nC +

= 15.5nC

I_O

The “point of voltage” is defined by, V_SP= V_TH

= 3 +

= 3.35V

g _fs

The driver current is,

V_DD−V_SP

R_{DRIVER(PULL−UP)}+ R_Gate

10 − 3.35 6.65

I_{DRIVER(L−H )}

= 1.33A

3 + 2

DC to DC Synchronous Converter Design

Abdus Sattar, IXYS Corporation

IXAN0068

V_DD−V_SP

R_{DRIVER(PULL−DOWN )}+ R_Gate

10 − 3.35

2.2 + 2

I_{DRIVER(H −L)}

= 1.58A

The rise time is, t_t(on)= 26nS +10nS = 36nS

The fall time is, t_{t(off )}= 18ns +10nS = 28nS

High-Side MOSFET loss (Q1=IXTA90N055T2):

The conduction loss is,

= I_O²• R_{DS (on)}• D

Cond _ Q1

= 12²• 0.0084 • 0.275 = 0.332 = 332mW

The Gate-Charge losses: (assume fs = 200 kHz)

P_{GC _ Q1}= V_GS• Q_g• f_s= 10.0x42x10⁻⁹x200x10³= 84mW

And estimated switching loss is,

[V_DS(max){I_{DS (on)}•t_t(on)+ I_{DS (off )}•t_{t(off )}}• f_s]

Pt =

12 •12

• (36 + 28)x10⁻⁹x200x10³= 0.921W=921mW

Total high-side losses: 332mW+84mW+921mW = 1337mW=1.337W

Low-Side MOSFET loss (Q2):

The conduction loss is,

= I_O²• R_DS(on)• (1− D)

Cond _ Q2

= 12²• 0.0084 • 0.725 = 0.877W = 877mW

The Gate-Charge loss:

P_{GC _ Q1}= V_GS• Q_g• f_s= 10.0x42x10⁻⁹x200x10³= 84mW

Total low-side losses: 877mW+84mW =961mW

ISL6594D Driver loss:

From datasheet: V_DD= 5V

Table 6: IXS839 Driver Output Stage from datasheet

Driver pull up resistance

Driver pull down resistance R_{DRIVER(PULL_DOWN)}2.2Ω

Driver gate resistance R_GATE2Ω

R_{DRIVER(PULL_UP)}

3.0Ω

DC to DC Synchronous Converter Design

Abdus Sattar, IXYS Corporation

IXAN0068

The power dissipation in the driver is defined by,

T_J− T_a

R_thJC

P_DRIVER

= Q_G(total)•V_DD• f_SW

where V_DD= 10V and f_S= 200 kHz (assume for this case)

The estimated driver power dissipation, P_D≈ 42 •10⁻⁹•10 • 200 •10³= 84mW

Dead-Time Power Loss: [3]

The dead-time is defined as the time required when both the MOSFETs are off in order to

prevent shoot-through. In this period, the Schottky diode (or integral body diode is

forward-biased and provided a power loss defined by,

Driver IXS839 provides delay time in the datasheet,

t_{Delay _Time}(nS) = C_Delay(pF) • (0.5nS / pF)

(22)

Assume, t_d1= t_{d 2}= 100nS , which provides C_Delay( pF) = 200pF

The Delay-Time loss is define in (11-13) as

ΔI_L

⎛

⎞

P = P + P = V • I −

•td1• f + •V • I •t • f

⎜

⎟

td1

cd1

rr1

⎝

⎠

0.528

⎛

⎝

⎞

⎟

= 0.85• 12 −

•100x10⁻⁹• 200x10³+ •12 • 2.2 •37x10⁻⁹• 200x10³

⎜

⎠

= 0.19905+0.09768= 0.297W= 297mW

ΔI_L

⎛

⎞

⎟

= P

(

= 0

)

= V • I +

•td2 • f

⎜

td 2

cd 2

rr2

⎝

⎠

0.528

⎛

⎝

⎞

⎟

= 0.85• 12 +

•100x10⁻⁹• 200x10³=0.208W= 208mW

⎜

⎠

P_BD= P + P = 297mW + 208mW = 505mW

td1

td 2

Synchronous Converter Efficiency:

If we neglect inductor’s DC power loss and capacitor’s ESR loss then the total

estimated power loss, P_loss= 1337mW+1007mW+84mW+505mW=2933mW= 2.933W

Given output power, Po = Vo*Io = 3.3*12= 39.6W

Estimated input power, Pin= 39.6+2.933=42.6W

VoIo

The efficiency is defined as, η =

(23)

Vin • Iin Pin

DC to DC Synchronous Converter Design

Abdus Sattar, IXYS Corporation

IXAN0068

39.6

The estimated efficiency, η =

= 0.93 = 93% %,

42.6

Estimated input current:

If we assume only 93% efficiency, then the estimated input current can be obtained,

VoIo

3.3•12

Vin •η 12 • 0.93

Estimated input current, I_in=

= 3.5A A

Bootstrap Circuit Design: [3]

Selecting bootstrap circuit components are done with consideration of the electrical rating

and characteristics of the high-side MOSFET (Q1).

The capacitance is defined by datasheet of IXS839 driver,

Q_G(total)

C_BST

(24)

ΔV_BST

Where Q_G(total)is the total gate charge of high-side MOSFET (Q₁), and ΔVBST is the

allowable voltage droop in Q₁. Assume this voltage droop equal to 0.1V.

42nC

C_BST

= 0.210uF

200mV

The bootstrap diode and capacitor voltage rating should be

V_{Bootstrap _ DiodeandCapacitor}> V_IN+V_DD

The average forward current is defined by,

I_{F ( Avg)}= Q_G(total)• f_SW

(25)

= 42 •10⁻⁹• 250 •10³= 10.5mA

Bibliography

[1] “Synchronous Buck MOSFETs loss calculation” AN-6005, Jon Klein, Fairchild

Semiconductor, 01/04/2006, www.fairchildsemi.com

[2] “Examination of reverse recovery losses in a synchronous buck converter circuit”

Application Note from Silicon Semiconductor, 2003, www.siliconsemi.com

[3] Datasheet for ISL6594D “Advanced Synchronous Rectified Buck MOSFET Driver”

from Intersil Corporation, 2007, www.intersil.com

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