PDM31034SA9TSOTY [IXYS]

Standard SRAM, 128KX8, 9ns, CMOS, PDSO32, 0.300 INCH, PLASTIC, SOJ-32;
PDM31034SA9TSOTY
型号: PDM31034SA9TSOTY
厂家: IXYS CORPORATION    IXYS CORPORATION
描述:

Standard SRAM, 128KX8, 9ns, CMOS, PDSO32, 0.300 INCH, PLASTIC, SOJ-32

静态存储器 光电二极管 内存集成电路
文件: 总8页 (文件大小:309K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
PRELIMINARY  
PDM31034  
1 Megabit 3.3V Static RAM  
128K x 8-Bit  
Revolutionary Pinout  
1
2
Description  
Features  
The PDM31034 is a high-performance CMOS static  
RAM organized as 131,072 x 8 bits. Writing is  
accomplished when the write enable (WE) and the  
chip enable (CE) inputs are both LOW. Reading is  
accomplished when WE remains HIGH and CE and  
OE are both LOW.  
High-speed access times  
Com’l: 9, 10, 12, 15 and 20 ns  
Ind’l.: 12, 15 and 20 ns  
Automotive: 15 and 20 ns  
Low power operation (typical)  
- PDM31034SA  
3
The PDM31034 operates from a single +3.3V power  
supply and all the inputs and outputs are fully TTL-  
compatible.  
Active: 200 mW  
Standby: 15 mW  
Single +3.3V (±0.3V) power supply  
TTL-compatible inputs and outputs  
Packages  
4
The PDM31034 is available in a 32-pin 400 mil plas-  
tic SOJ and 300 mil plastic SOJ, and a 32-pin plastic  
TSOP (II) package in revolutionary pinout.  
Plastic SOJ (400 mil) - SO  
Plastic SOJ (300 mil) - TSO  
Plastic TSOP (II) - T  
5
6
Functional Block Diagram  
7
A8  
A0  
Memory  
Array  
512 x 256 x 8  
Row  
Address  
Buffer  
Row  
Decoder  
Addresses  
8
(1,048,576)  
I/O0  
I/O7  
9
Input  
Data  
Control  
Column I/O  
Column Decoder  
10  
11  
12  
Column Address  
Buffer  
A16  
A9  
CE  
Control  
WE  
OE  
Rev. 1.3  
1
PRELIMINARY  
PDM31034  
Pin Configuration  
Pin Description  
SOJ  
TSOP  
A4  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
A3  
A2  
1
2
3
4
5
6
7
8
A3  
A2  
A1  
A0  
CE  
I/O0  
I/O1  
Vcc  
Vss  
I/O2  
I/O3  
WE  
A16  
A15  
A14  
A13  
32  
A4  
A5  
A6  
A7  
OE  
I/O7  
I/O6  
Vss  
Vcc  
I/O5  
I/O4  
A8  
A5  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A6  
A1  
Name  
Description  
A7  
A0  
A16-A0  
I/O7-I/O0  
OE  
Address Inputs  
Data Inputs/Outputs  
Output Enable Input  
Write Enable Input  
Chip Enable Input  
No Connect  
OE  
I/O7  
I/O6  
Vss  
CE  
28  
27  
26  
25  
I/O0  
I/O1  
Vcc  
Vss  
I/O2  
I/O3  
WE  
A16  
A15  
A14  
A13  
WE  
24 Vcc  
23 I/O5  
9
9
CE  
10  
11  
12  
13  
14  
15  
16  
10  
11  
12  
13  
14  
NC  
I/O4  
22  
21 A8  
20 A9  
V
V
Power (+3.3V)  
Ground  
CC  
SS  
A9  
A10  
A11  
A12  
19  
18  
17  
A10  
A11  
A12  
15  
16  
(1)  
Truth Table  
CE  
OE  
WE  
I/O  
MODE  
L
L
L
X
H
X
H
L
D
Read  
Write  
OUT  
D
IN  
L
H
X
Hi-Z  
Output Disable  
Standby  
H
Hi-Z  
NOTE: 1. H = V , L = V , X = DON’T CARE  
IH  
IL  
(1)  
Absolute Maximum Ratings  
Symbol  
Rating  
Com’l.  
Ind.  
Auto.  
Unit  
V
Terminal Voltage with Respect to V  
Temperature Under Bias  
Storage Temperature  
–0.5 to +4.6  
–55 to +125  
–55 to +125  
900  
–0.5 to +4.6  
–65 to +135  
–65 to +150  
900  
–0.5 to +4.6  
–65 to +145  
–65 to +150  
900  
V
°C  
TERM  
BIAS  
STG  
SS  
T
T
°C  
P
Power Dissipation  
mW  
mA  
°C  
T
I
DC Output Current  
50  
50  
50  
OUT  
(2)  
T
Maximum Junction Temperature  
125  
125  
125  
j
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may  
cause permanent damage to the device. This is a stress rating only and functional  
operation of the device at these or any other conditions above those indicated in the  
operational sections of this specification is not implied. Exposure to absolute maxi-  
mum rating conditions for extended periods may affect reliability.  
2. Appropriate thermal calculations should be performed in all cases and specifically for  
those where the chosen package has a large thermal resistance (e.g., TSOP). The cal-  
culation should be of the form: T = T + P * θ where T is the ambient temperature, P  
j
a
ja  
a
is average operating power and θ the thermal resistance of the package. For this  
ja  
product, use the following θ values:  
ja  
o
SOJ: 72 C/W  
o
TSOP: 95 C/W  
2
Rev. 1.3  
PRELIMINARY  
PDM31034  
Recommended DC Operating Conditions  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
1
2
V
V
Supply Voltage  
3.0  
0
3.3  
0
3.6  
0
V
V
CC  
SS  
Supply Voltage  
Industrial  
Ambient Temperature  
Ambient Temperature  
–40  
–0  
25  
25  
85  
70  
°C  
°C  
Commercial  
3
DC Electrical Characteristics (V = 3.3V ± 0.3V)  
CC  
Symbol  
Parameter  
Test Conditions  
Min.  
Max.  
Unit  
I
Input Leakage Current  
V
= Max., V = V to V  
CC  
Com’l/  
Ind.  
–5  
5
µA  
LI  
CC  
IN  
SS  
4
I
Output Leakage Current  
V
= Max.,  
Com’l/  
Ind.  
–5  
5
µA  
LO  
CC  
CE = V , V  
= V to V  
SS CC  
IH OUT  
(1)  
V
V
V
V
Input Low Voltage  
Input High Voltage  
Output Low Voltage  
Output High Voltage  
–0.3  
2.2  
0.8  
Vcc+0.3  
0.4  
V
V
V
V
IL  
5
IH  
I
I
= 8 mA, V = Min.  
CC  
OL  
OH  
OL  
= –4 mA, V = Min.  
2.4  
OH  
CC  
6
NOTE:1.V (min) = –3.0V for pulse width less than 20 ns  
IL  
7
Power Supply Characteristics  
(1)  
(1)  
-9  
-10  
-12  
-15  
-20  
Symbol Parameter  
Operating Current  
CE = V  
Com’l.  
Com’l. Com’l Ind. Com’l Ind. Auto. Com’l Ind. Auto. Unit  
8
I
125  
115  
110  
115  
100  
105  
110  
90  
95  
110  
mA  
CC  
IL  
f = f  
= 1/t  
RC  
MAX  
V
= Max.  
= 0 mA  
CC  
9
I
OUT  
I
Standby Current  
CE = V  
20  
5
20  
5
20  
5
20  
5
20  
5
20  
5
30  
10  
20  
5
20  
5
30  
10  
mA  
mA  
SB  
IH  
f = f  
V
= 1/t  
RC  
MAX  
10  
11  
12  
= Max.  
CC  
I
Full Standby Current  
CE V – 0.2V  
SB1  
CC  
f = 0  
V
V
= Max.,  
CC  
V – 0.2V or 0.2V  
IN  
CC  
NOTES: All values are maximum guaranteed values.  
1. V = 3.3V + 5%  
CC  
Rev. 1.3  
3
PRELIMINARY  
PDM31034  
(1)  
Capacitance (T = +25°C, f = 1.0 MHz)  
A
Symbol  
Parameter  
Max.  
Unit  
C
C
Input Capacitance  
Output Capacitance  
8
8
pF  
pF  
IN  
OUT  
NOTE:1. This parameter is determined by device characterization but is not production tested.  
AC Test Conditions  
Input pulse levels  
V
to 3.0V  
2.5 ns  
1.5V  
SS  
Input rise and fall times  
Input timing reference levels  
Output reference levels  
Output load  
1.5V  
See Figures 1 and 2  
+3.3V  
+3.3V  
317  
317Ω  
DOUT  
351Ω  
DOUT  
351Ω  
30 pF  
5 pF  
Figure 2. Output Load Equivalent  
(for t , t , t , t , t  
Figure 1. Output Load Equivalent  
,
LZCE HZCE LZWE HZWE LZOE  
t
)
HZOE  
4
Rev. 1.3  
PRELIMINARY  
PDM31034  
(4, 5)  
Read Cycle No. 1  
t
RC  
1
2
ADDR  
t
AA  
t
OH  
D
PREVIOUS DATA VALID  
DATA VALID  
OUT  
3
(2, 4, 6)  
Read Cycle No. 2  
t
RC  
4
ADDR  
t
AA  
t
ACE  
CE1  
CE2  
5
t
t
HZCE  
LZCE  
6
OE  
t
t
HZOE  
LZOE  
D
OUT  
DATA VALID  
7
t
AOE  
8
AC Electrical Characteristics  
Description  
-9  
-10  
-12  
-15  
-20  
9
READ Cycle  
Sym  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units  
READ cycle time  
t
9
10  
12  
15  
20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address access time  
t
9
9
10  
10  
12  
12  
15  
15  
20  
20  
AA  
10  
11  
12  
Chip enable access time  
Output hold from address change  
t
ACE  
t
3
3
3
3
3
3
3
3
3
3
OH  
(1,3)  
Chip enable to output in low Z  
t
LZCE  
HZCE  
(1,2,3)  
Chip disable to output in high Z  
t
5
6
7
8
9
(3)  
Chip enable to power up time  
t
t
0
0
0
0
0
0
0
0
0
0
PU  
PD  
(3)  
Chip disable to power down time  
Output enable access time  
9
5
10  
6
12  
7
15  
8
20  
9
t
AOE  
LZOE  
HZOE  
(1,3)  
(1,3)  
Output Enable to output in low Z  
t
Output disable to output in high Z  
t
5
6
7
8
9
Rev. 1.3  
5
PRELIMINARY  
PDM31034  
Write Cycle No. 1 (Write Enable Controlled)  
t
WC  
ADDR  
t
t
AH  
AW  
t
CW  
CE  
t
AS  
t
WP  
WE  
t
t
DH  
DS  
D
IN  
DATA VALID  
t
HZWE  
t
LZWE  
HIGH-Z  
D
OUT  
Write Cycle No. 2 (Write Enable Controlled)  
t
WC  
ADDR  
t
t
AH  
AW  
t
CW  
CE  
t
AS  
t
WP  
WE  
t
t
DH  
DS  
D
IN  
DATA VALID  
HIGH-Z  
D
OUT  
NOTE: Output Enable (OE) is inactive (high)  
6
Rev. 1.3  
PRELIMINARY  
PDM31034  
Write Cycle No. 3 (Chip Enable Controlled)  
t
WC  
1
2
ADDR  
t
t
AH  
AW  
t
t
AS  
CW  
CE  
t
WP  
t
WE  
3
t
DS  
DH  
D
IN  
DATA VALID  
4
HIGH-Z  
D
OUT  
NOTE: Output Enable (OE) is inactive (high)  
5
AC Electrical Characteristics  
6
Description  
-9  
-10  
-12  
-15  
-20  
WRITE Cycle  
Sym  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units  
WRITE cycle time  
t
t
9
8
8
0
0
7
5
0
0
10  
9
12  
10  
10  
0
15  
11  
11  
0
20  
12  
12  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
7
WC  
Chip enable active time  
Address valid to end of write  
Address setup time  
CW  
t
9
AW  
t
0
AS  
AH  
WP  
8
Address hold from end of write  
Write pulse width  
t
0
0
0
0
t
t
8
9
10  
8
11  
9
Data setup time  
t
6
7
DS  
9
Data hold time  
0
0
0
0
DH  
(1,3)  
(1,3)  
Write disable to output in low Z  
t
0
0
0
0
LZWE  
HZWE  
Write enable to output in high Z  
t
6
7
7
8
9
10  
11  
12  
NOTES: (For two previous Electrical Characteristics tables)  
1. The parameter is tested with C = 5 pF as shown in Figure 2. Transition is measured ±200 mV from steady state voltage.  
L
2. At any given temperature and voltage condition, t  
3. This parameter is sampled.  
is less than t  
.
HZCE  
LZCE  
4. WE is high for a READ cycle.  
5. The device is continuously selected. Chip Enable is held in their active state.  
6. The address is valid prior to or coincident with the latest occuring Chip Enable.  
Rev. 1.3  
7
PRELIMINARY  
PDM31034  
Ordering Information  
XXXXX  
X
XX  
X
X
X
Speed  
Device Type Power  
Package  
Type  
Process  
Temp. Range  
Preferred  
Shipping  
Container  
Blank Tubes  
TR  
TY  
Tape & Reel  
Tray  
Blank  
I
Commercial (0° to +70°C)  
Industrial (–40°C to +85°C)  
Automotive (–40°C to +105°C)  
A
SO 32-pin 400 mil Plastic SOJ  
TSO 32-pin 300 mil Plastic SOJ  
T
32-pin Plastic TSOP (II)  
9
Commercial Only  
10  
12  
15  
20  
SA  
Standard Power  
PDM31034 - (128Kx8) Static RAM  
Faster Memories for a FasterWorld ™  
8
Rev. 1.3  

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