PDM34078SA8TQATY [IXYS]
SRAM;
| 型号： | PDM34078SA8TQATY |
| 厂家： | 
IXYS CORPORATION |
| 描述： | SRAM 静态存储器 |
| 文件： | 总14页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PDM34078
3.3V 32K x 32 Fast CMOS
Synchronous Static RAM
with Burst Counter
1
2
and Output Register
Description
Features
The PDM34078 is a 1,048,576 bit synchronous
random access memory organized as 32,768 x 32
bits. This device designed with burst mode
capability and interface controls to provide high-
performance in second level cache designs for x86,
Pentium, 680x0, and PowerPC microprocessors.
Addresses, write data and all control signals except
output enable are controlled through positive edge-
triggered registers. Write cycles are self-timed and
are also initiated by the rising edge of the clock.
Controls are provided to allow burst reads and
writes of up to four words in length. A 2-bit burst
address counter controls the two least-significant
bits of the address during burst reads and writes.
The burst address counter selectively uses the 2-bit
counting scheme required by the x86 and Pentium
or 680x0 and PowerPC microprocessors as con-
trolled by the mode pin. Individual write strobes
provide byte write for the four 8-bit bytes of data.
An asynchronous output enable simplifies interface
to high-speed buses.
■ Interfaces directly with the x86, Pentium™, 680X0
and PowerPC™ processors
(100, 80, 66, 60, 50 MHz)
■ Single 3.3V power supply
■ Mode selectable for interleaved or linear burst:
Interleaved for x86 and Pentium
Linear for 680x0 and PowerPC
■ High-speed clock cycle times:
10, 12.5, 15, 16.7 and 20 ns
■ High-density 32K x 32 architecture with burst
address counter and output register
■ Fully registered inputs and outputs for pipelined
operation
3
4
5
■ High-output drive: 30 pF at rated T
A
■ Asynchronous output enable
■ Self-timed write cycle
■ Separate byte write enables and one global write
enable
■ Internal burst read/write address counter
■ Internal registers for address, data, controls
■ Output data register
7
■ Burst mode selectable
■ Sleep mode
■ Packages:
8
100-pin QFP - (Q)
100-pin TQFP - (TQ)
9
10
11
12
TM
i486, Pentium are trademarks of Intel Corp. PowerPC is a trademark of the International Business Machines Corporation.
Rev 1.0 - 5/01/98
1
PDM34078
Functional Block Diagram
15
A14-A0
15
13
15
ADDRESS
REGISTER
A1,A0
A0'
MODE
ADV
Q0
Q1
BURST
COUNTER
AND LOGIC
CLK
A1'
CLR
ADSC
ADSP
8
8
8
8
BW1
8
8
8
8
BYTE 1
WRITE REGISTER
BYTE 4
WRITE DRIVER
BW2
BYTE 2
WRITE REGISTER
BYTE 3
WRITE DRIVER
32K x 32
MEMORY
ARRAY
32
32
OUTPUT
REGISTERS
OUTPUT
BUFFER
DQ32-DQ1
BW3
BYTE 3
WRITE REGISTER
BYTE 2
WRITE DRIVER
BW4
BWE
BYTE 4
WRITE REGISTER
BYTE 1
WRITE DRIVER
GW
ENABLE
REGISTER
CE
CE2
CE2
OE
INPUT
REGISTERS
2
Rev 1.0 - 5/01/98
PDM34078
PDM34078 Pinout
1
2
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
DQ17
DQ18
VCCQ
DQ16
DQ15
VCCQ
3
V
SSQ
V
SSQ
DQ14
DQ13
DQ12
DQ11
DQ19
DQ20
DQ21
DQ22
4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SSQ
V
SSQ
VCCQ
DQ10
DQ9
VCCQ
DQ23
DQ24
FT
VCC
NC
5
V
SS
NC
VCC
ZZ
DQ8
DQ7
VCCQ
V
SS
DQ25
DQ26
VCCQ
7
V
SSQ
V
SSQ
DQ6
DQ5
DQ4
DQ3
DQ27
DQ28
DQ29
DQ30
8
V
SSQ
V
SSQ
VCCQ
DQ2
DQ1
NC
VCCQ
DQ31
DQ32
NC
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
10
11
12
Rev 1.0 - 5/01/98
3
PDM34078
Pinout
Name
I/O
Description
Name
I/O
Description
A14-A2
A1, A0
DQ1-DQ32
NC
I
Address Inputs A14-A2
Address Inputs A1 & A0
Read/Write Data
CE, CE2, CE2
BWE
I
I
Chip Enables
I
Byte Write Enable
Byte Write Enables
Output Enable
Clock
I/O
BW1-BW4
OE
I
—
No Connect
I
(1)
MODE
I
I
I
I
I
I
Burst Sequence Select
Burst Counter Advance
Controller Address Status
Processor Address Status
Global Write
CLK
I
ADV
ZZ
I
Sleep Mode
ADSC
ADSP
GW
V
V
V
V
—
—
—
—
Power Supply (+3.3V)
CC
Output Power for DQ’s (+3.3V ±5%)
Array Ground
CCQ
SS
(1)
FT
Must be tied HIGH for
proper operation
Output Ground for DQ’s
SSQ
NOTE: 1.MODE and FT are DC operated pins. Do not alter input state while device is operating.
Burst Sequence Table
(1)
Interleaved
(2)
Linear
Mode = V
Burst Sequence
Mode = NC or
SS
V
CC
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A14-A2, A1, A0
A14-A2, A1, A0
A14-A2, A1, A0
A14-A2, A1, A0
A14-A2,0,0
A14-A2,0,1
A14-A2,1,0
A14-A2,1,1
A14-A2,0,1
A14-A2,1,0
A14-A2,1,1
A14-A2,0,0
A14-A2,1,0
A14-A2,1,1
A14-A2,0,0
A14-A2,0,1
A14-A2,1,1
A14-A2,0,0
A14-A2,0,1
A14-A2,1,0
Note: 1. Interleaved = x86 and Pentium.
2. Linear = 680x0 and Power PC compatible.
Partial Truth Table for Writes
Asynchronous Truth Table
Operation
ZZ
OE I/O Status
GW BWE BW1 BW2 BW3 BW4
Function
Read
L
L
L
L
H
L
H
X
X
X
Data Out
H
H
H
H
L
H
L
L
L
X
X
H
L
X
H
H
L
X
H
H
L
X
H
H
L
READ
Read
High-Z
READ
Write
High-Z: Write Data In
High-Z
WRITE Byte 1
WRITE All Bytes
WRITE All Bytes
Deselected
Sleep
L
High-Z
X
X
X
X
NOTE: 1. L = Low, H = High, X = Don’t Care.
2. For a write operation following a read operation,
OE must be high before the input data required
setup time and held high through the input data
hold time.
NOTE: 1. L = Low, H = High, X = Don’t Care.
2. Using BWE and BW1 through BW4, any one or
more bytes may be written.
3. This device contains circuitry that will ensure
the outputs will be in high-Z during powerup.
4
Rev 1.0 - 5/01/98
PDM34078
Synchronous Truth Table (See Notes 1 through 3)
CE CE2 CE2 ADSP ADSC ADV BWx CLK
Address
Operation
H
L
X
X
H
X
H
L
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
L
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
N/A
N/A
Deselected
1
2
Deselected
L
X
L
L
N/A
Deselected
L
H
H
L
N/A
Deselected
L
X
H
H
X
X
X
X
H
X
X
X
X
L
N/A
Deselected
L
X
L
External
External
Next
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Begin Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
L
L
H
H
X
H
X
H
H
X
H
H
3
X
H
X
H
L
X
X
X
X
L
H
H
H
H
L
L
Next
H
H
X
L
Current
Current
External
Next
4
X
H
X
H
X
X
X
X
H
H
H
H
L
L
L
Next
5
H
H
L
Current
Current
L
NOTES:
1. X = Don’t Care, H = logic High, L = logic Low, BWx = any one or more byte write enable signals (BW1, BW2, BW3, BW4)
and BWE are low, or GW is low.
2. BW1 enables BWx to Byte 1 (DQ1-DQ8). BW2 enables BWx to Byte 2 (DQ9-DQ16).
BW3 enables BWx to Byte 3 (DQ17-DQ24), BW4 enables BWx to Byte 4 (DQ25-DQ32).
3. ADV must always be high at the rising edge of the first clock after an ADSP cycle is initiated if a write cycle is desired (to
ensure use of correct address).
7
8
9
10
11
12
Rev 1.0 - 5/01/98
5
PDM34078
Burst Mode Operation
This is a synchronous part. All activities are initiated by the positive, low-to-high edge of the clock (CLK). This part can
perform burst reads and writes with burst lengths of up to four words. The four-word burst is created by using a burst
counter to drive the two least-significant bits of the internal RAM address. The burst counter is loaded at the start of the
burst and is incremented for each word of the burst. The sequence is given in the Burst Sequence Table.
Burst transfers are initiated by the ADSC or ADSP signals. When the ADSP and CE signals are sampled low, a read cycle
is started (independent of BW1, BW2, BW3, or BW4; BWE, GW and ADSC), and prior burst activity is terminated. ADSP
is gated by CE, so both must be active for ADSP to load the address register and to initiate a read cycle. The address and
the chip enable input (CE) are sampled by the same edge that samples ADSP. Read data is valid at the output after the
specified delay from the clock edge.
When ADSC is sampled low and ADSP is sampled high, a read or write cycle is started depending on the state of BW1,
BW2, BW3 or BW4; BWE, and GW. If BW1, BW2, BW3, BW4, BWE, and GW are all sampled high, a read cycle is started,
as described above. If BW1, BW2, BW3, or BW4; BWE, and GW is sampled low, a write cycle is begun. The address,
write data, and the chip enable inputs (CE, CE2 and CE2) are sampled by the same edge that samples ADSC and BW1–
BW4, BWE and GW. The ADV line is held high for this clock edge to maintain the correct address for the internal write
operation which will follow this second clock edge.
After the first cycle of the write burst, the state of BW1–BW4, BWE and GW determines whether the next cycle is a read
or write cycle, and ADV controls the advance of the address counter. The ADV signal advances the address counter.
This increments the address to the next available RAM address. You write the next word in the burst by taking ADV low
and presenting the write data at the positive edge of the clock. If ADV is sampled low, the burst counter advances and
the write data (which is sampled by the same clock) is written into the internal RAM during the time following the clock
edge.
(1)
Absolute Maximum Ratings
Symbol
Rating
Com’l.
Ind.
Unit
V
Terminal Voltage with Respect to V
Temperature Under Bias
Storage Temperature
–0.5 to +4.6
–55 to +125
–55 to +125
1.0
–0.5 to +4.6
–65 to +135
–65 to +150
1.0
V
°C
°C
W
TERM
BIAS
STG
SS
T
T
P
Power Dissipation
T
I
DC Output Current
50
50
mA
°C
OUT
(2)
T
Maximum Junction Temperature
125
125
j
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXI-
MUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated
in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all
cases and specifically for those where the chosen package
has a large thermal resistance (e.g., TSOP). The calculation
should be of the form: T = T + P * θ where T is the ambient
j
a
ja
a
temperature, P is average operating power and θ the ther-
ja
mal resistance of the package. For this product, use the
following θ values:
ja
o
TQFP: 50 C/W
o
QFP: 50 C/W
6
Rev 1.0 - 5/01/98
PDM34078
Recommended DC Operating Conditions
Symbol
Description
Min.
Typ.
Max.
Unit
1
2
V
V
V
Supply Voltage
3.0
3.0
0
3.3
3.3
0
3.6
3.6
0
V
V
CC
Supply voltage
CCQ
SS
Supply Voltage
V
Commercial
Ambient Temperature
0
25
70
°C
3
DC Electrical Characteristics (V = 3.3V ± 0.3V, All Temperature Ranges)
CC
Symbol
|I |
Description
Test Conditions
= 0V to V
Min.
Max.
Unit
4
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Input HIGH Voltage
V
–2
–2
2
2
µA
µA
V
LI
IN
CC
|I
|
Outputs Disabled, V = 0V to V
I/O CC
LO
V
V
V
V
V
= Min., I = 8 mA
—
0.4
OL
CC
CC
OL
= Min., I = –5 mA
2.4
2.0
—
V
OH
IH
OH
5
Vcc+0.3
V
(1)
V
Input LOW Voltage
–0.3
0.8
V
IL
NOTES: 1. Undershoots to –2.0 for 10 ns are allowed once per cycle.
2. MODE, FT and ZZ pins have an internal pullup and exhibit an input leakage current of ±400 µA.
7
Power Supply Characteristics
Symbol Description
Test Conditions
-6 ns
-7 ns
-8 ns
-10 ns
-12 ns
Unit
I
Active Supply Current
Device Deselected
350
300
250
230
210
mA
8
CC
SB
V
≤ V or ≥ V
I
= 0
IN
IL
IH, I/O
I
Standby Current:
Standby Current:
Standby Current:
Device Deselected
≤ V or ≥ V 0 MHz
20
3
20
3
20
3
20
3
20
3
mA
mA
mA
mA
V
IN
IL
IH,
All inputs static
9
I
I
I
Device Deselected
SB1
SB2
SB3
V
≤ 0.2V or ≥ V – 0.2V
CC
IN
All inputs static, 0 MHz
Device Deselected
60
3
55
3
50
3
45
3
40
3
10
11
12
V
≤ V or ≥ V
IL IH,
IN
All inputs static
Sleep Mode
Standby Current:
Device Deselected
ZZ ≥ V – 0.2V
CCQ
Rev 1.0 - 5/01/98
7
PDM34078
Capacitance (T = +25°C, f = 1.0 MHz)
A
Symbol
Parameter
Conditions
= 0V
Max.
Unit
C
C
Input Capacitance
Output Capacitance
V
6
8
pF
pF
IN
IN
V
= 0V
OUT
OUT
NOTES: 1. Characterized values, not currently tested.
AC Test Conditions
Input pulse levels
V
to 3.0V
SS
Input rise and fall times
Input timing reference levels
Output reference levels
Output load
1.5 ns
1.5V
1.5V
See Figures 1 and 2
+3.3V
317Ω
DATAOUT
ZOUT = 50Ω
50Ω
I/O
VL = 1.5V
351Ω
5 pF*
30 pF
Figure 2. Output Load
, t , t , t
Figure 1. Output Load
t
CQ OLZ OHZ CZ
8
Rev 1.0 - 5/01/98
PDM34078
AC Electrical Characteristics
Parameter
Symbol
-6 ns
-7 ns
-8 ns
-10 ns
-12 ns
Type
Units
Cycle time
t
10
12.5
15
16.7
20
Min.
ns
CYC
1
2
Clock access time (0 pF load)
Clock to output valid (Std. load)
t
5
6
6
7
7
8
9
11
12
Max.
Max.
ns
ns
CQ0
t
10
CQ
Clock to output invalid
Clock to output high-Z
t
2
2
2
2
2
2
2
2
2
2
Min.
Min.
Max.
Min.
Min.
Min.
Min.
Max.
Max.
Min.
ns
ns
CQX
t
CHZ
10
4
12.5
5
15
5
16.7
6
20
6
Clock pulse width high
Clock pulse width low
OE to output valid
t
ns
ns
ns
ns
ns
ns
ns
CH
t
4
5
5
6
6
CL
3
t
5
5
5
6
6
OE
OE to output low-Z
OE to output high-Z
ZZ standby time
t
0
0
0
0
0
OLZ
OHZ
t
5
5
5
6
6
t
100
100
100
100
100
100
100
100
100
100
ZZS
4
ZZ recovery time
t
ZZREC
SETUP TIMES
Address
t
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
3
3
3
3
3
3
Min.
Min.
Min.
Min.
Min.
Min.
ns
ns
ns
ns
ns
ns
AS
Address status (ADSC, ADSP)
Address advance setup (ADV)
Write signals (BWx, GW)
Data in
t
t
5
AAS
AAS
t
WS
t
DS
Chip enables (CE, CE2, CE2)
HOLD TIMES
t
CES
Address
t
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Min.
Min.
Min.
Min.
Min.
Min.
ns
ns
ns
ns
ns
ns
AH
Address status (ADSC, DSP)
Address advance (ADV)
Write eignals (BWx, GW)
Data in
t
ADSH
7
t
AAH
t
WH
t
DH
Chip enables (CE, CE2, CE2)
t
CEH
8
9
10
11
12
Rev 1.0 - 5/01/98
9
PDM34078
Read Timing Diagram
t
CYC
CLK
t
t
CL
t
CH
ADSS
ADSP
t
ADSH
ADSC
t
AS
ADDRESS
A1
A2
AAS
A3
t
AH
t
ADV
t
AAH
GW, BWE
BW4-BW1
t
t
WS
CES
t
WH
CE
t
CZ
t
CEH
t
OE
OE
t
OHZ
t
t
CZ
t
CQ
OLZ
DATAOUT
Q1A1
Q1A2
Q2 A2
Q3 A3
Q3 A2
Q4 A2
Q2 A2
t
CQX
NOTES: 1. Qn(A2) refers to output from address A2. Q1–4 refers to outputs according to burst sequence.
2. CE2 and CE2 have timing identical to CE. In this diagram, when CE is low, CE2 is low and CE2 is high. When CE is high,
CE2 is high and CE2 is low.
10
Rev 1.0 - 5/01/98
PDM34078
Write Timing Diagram
t
CYC
1
2
CLK
t
t
CL
t
CH
ADSS
ADSP
t
ADSH
ADSC
t
AS
ADDRESS
A1
A2
A3
3
t
t
AH
AAS
ADV
t
AAH
4
t
WS
(3)
BWE
BW4-BW1
t
WS
t
WH
(2)
GW
5
t
WH
t
CES
CE
t
CEH
OE
t
DS
DATAIN
D1 A1
D1 A2
D2 A2
D2 A2
D3 A2
D4 A2
D1 A3
D2 A3
D3 A3
D1 A1
7
t
DH
t
OHZ
DATAOUT
8
NOTES: 1. CE2 and CE2 have timing identical to CE. On this diagram, when CE is low, CE2 is low and CE2 is high. When CE is
high, CE2 is high and CE2 is low.
2. Full width write can be initiated by GW low or GW high and BWE, BW1-BW4 low.
3
BWE is low when any one or more byte write enables (BW1-BW4) are low in this diagram.
9
10
11
12
Rev 1.0 - 5/01/98
11
PDM34078
Read/Write Timing Diagram
t
CYC
CLK
t
t
CL
t
CH
ADSS
ADSP
t
ADSH
ADSC
t
AS
ADDRESS
A1
A2
A3
t
AH
ADV
BWE
BW4-BW1
t
CES
CE
OE
t
CEH
t
DH
t
DS
DATAIN
D1A2
t
CQ
t
t
OLZ
OHZ
t
CQX
DATAOUT
Q1A1
Q1A2
Q2 A2
Q3 A3
NOTES: 1. CE2 and CE2 have timing identical to CE. On this diagram, when CE is low, CE2 is low and CE2 is high. When CE is
high, CE2 is high and CE2 is low.
2. GW is high.
12
Rev 1.0 - 5/01/98
PDM34078
Sleep Mode Timing Diagram
SNOOZE
1
2
CLK
ADSP
ADSC
ZZ
t
t
ZZREC
3
ZZS
NOTES: 1. Data retention is guaranteed when ZZ is asserted and clock remains active.
2. ADSC and ADSP must not be asserted for at least 100 ns after leaving ZZ state.
4
Sequential Non-burst Read and Write Timing Diagram
5
CLK
ADSP
ADSC
7
ADDR
A
B
C
D
E
F
G
H
8
ADV
CE1
WE
9
OE
10
11
12
DQ
Q(A)
Q(B)
Q(C)
Q(D)
Q(E)
Q(F)
Q(G)
Q(H)
READS
WRITES
NOTES:
1. ADSP = high, ADSC = low, ADV = high, CE1 = low.
2. H ≥ V , L ≤ V .
IH
IL
Rev 1.0 - 5/01/98
13
PDM34078
Ordering Information
XXXXX
X
XX
Speed
X
X
X
Device Type Power
Package
Type
Process
Temp. Range
Preferred
Shipping
Container
Blank Tubes
TR
TY
Tape & Reel
Tray
Blank
I
A
Commercial (0° to +70°C)
Industrial (–40°C to +85°C)
Automotive (–40°C to +105°C)
Q
TQ
100-pin QFP
100-pin TQFP
6
Commercial Only
Commercial Only
7
8
10
12
SA /S Standard Power
PDM34078 - (32Kx32) Sync. Static RAM
Faster Memories for a Faster World ™
14
Rev 1.0 - 5/01/98
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