Z80C3008PSC_技术文档

Z80C30/Z85C30

CMOS SCC Serial

Communications

Controller

Product Specification

PS011705-0608

®

www.Zilog.com

CMOS SCC Serial Communications Controller

Product Specification

ii

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PS011705-0608

CMOS SCC Serial Communications Controller

Product Specification

iii

Revision History

Each instance in Revision History reflects a change to this document from its previous

revision. For more details, refer to the corresponding pages and appropriate links in the

table below.

Date

Revision Level Description

Page No

June

2008

05

Updated Zilog logo, Zilog Text, All

Disclaimer as per latest

template.

September

2004

01

Original issue

All

PS011705-0608

Revision History

CMOS SCC Serial Communications Controller

Product Specification

iv

Table of Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Other Features for Z85C30 Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Z85C30/Z80C30 Common Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Z85C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Z80C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

I/O Interface Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Z85C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Z80C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Z85C30/Z80C30 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Z85C30 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Z80C30 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Z80C30/Z85C30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Z85C30 Read/Write Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Part Number Suffix Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

PS011705-0608

Table of Contents

CMOS SCC Serial Communications Controller

Product Specification

1

Overview

The features of Zilog’s Z80C30 and Z85C30 devices include:

•

Z85C30 — Optimized for Non-Multiplexed Bus Microprocessors.

Z80C30 — Optimized for Multiplexed Bus Microprocessors.

Pin Compatible to NMOS Versions.

Two Independent, 0 to 4.1 Mbit/Second, Full-Duplex Channels. Each channel with

Separate Crystal Oscillator, Baud Rate Generator (BRG), and Digital Phase-Locked

Loop (DPLL) for Clock Recovery.

•

Multi-Protocol Operation under Program Control; Programmable for NRZ, NRZI, or

FM Data Encoding.

Asynchronous Mode with Five to Eight Bits and One, One and One-Half, or Two

Stop Bits Per Character, Programmable Clock Factor, Break Detection and

Generation; Parity, Overrun, and Framing Error Detection.

•

Synchronous Mode with Internal or External Character Synchronization on One or

Two Synchronous Characters and CRC Generation and Checking with CRC-16 or

CRC-CCITT Preset to either 1s or 0s.

SDLC/HDLC Mode with Comprehensive Frame-Level Control, Automatic Zero

Insertion and Deletion, I-Field Residue Handling, Abort Generation and Detection,

CRC Generation and Checking, and SDLC Loop.

•

Software Interrupt Acknowledge Feature (not available with NMOS).

Local Loopback and Auto Echo Modes.

Supports T1 Digital Trunk.

Enhanced DMA Support (not available with NMOS) 10 x 19-Bit Status FIFO 14-Bit

Byte Counter.

•

Speeds:

–

Z85C3O — 8.5, 10, 16.384 MHz

Z80C3O — 8, 10 MHz

PS011705-0608

Overview

CMOS SCC Serial Communications Controller

Product Specification

2

Other Features for Z85C30 Only

Some of the features listed below are available by default. Some of them (features with

*) are disabled on default to maintain compatibility with the existing Serial

Communications Controller (SCC) design, and “program to enable through WR7”:

•

New programmable WR7 (Write register 7 prime) to enable new features.

Improvements to support SDLC mode of synchronous communication:

–

Improve functionality to ease sending back-to-back frames.

Automatic SDLC opening Flag transmission.*

Automatic Tx Underrun/EOM Latch reset in SDLC mode.*

Automatic RTS deactivation.*

TxD pin forced High in SDLC NRZI mode after closing flag.*

Complete CRC reception.*

Improved response to Abort sequence in status FIFO.

Automatic Tx CRC generator preset/reset.

Extended Read for Write registers.*

Write data set-up timing improvement.

•

Improved AC timing:

–

3 to 3.6 PCLK access recovery time.

Programmable DTR/REQ timing.*

Write data to falling edge of WR setup time requirement is now eliminated.

Reduced INT timing.

Other features include:

–

Extended Read function to read back the written value to the Write registers.*

Latching RRO during read.

RRO, bit D7 and RR10, bit D6 now has reset default value.

PS011705-0608

Overview

CMOS SCC Serial Communications Controller

Product Specification

3

PS011705-0608

Overview

CMOS SCC Serial Communications Controller

Product Specification

4

General Description

The Z80C30/Z85C30 Serial Communications Controller (SCC), is a pin and software

compatible CMOS member of the SCC family introduced by Zilog^®in 1981. It is a dual

channel, multi-protocol data communications peripheral that easily interfaces with CPU’s

with either multiplexed or non-multiplexed address/data buses.

The advanced CMOS process offers lower power consumption, higher performance, and

superior noise immunity. The programming flexibility of the internal registers allow the

SCC to be configured to various serial communications applications.

Figure 1 displays a block diagram of the SCC.

The many on-chip features such as Baud Rate Generators (BRG), Digital Phase Locked

Loops (DPLL), and crystal oscillators reduce the need for an external logic.

Additional features include a 10 x 19-bit status FIFO and 14-bit byte counter to support

high speed SDLC transfers using DMA controllers.

The SCC handles asynchronous formats, synchronous byte-oriented protocols such as

IBM Bisync, and synchronous bit-oriented protocols such as HDLC and IBM SDLC. This

device supports virtually any serial data transfer application (for example, cassette,

diskette, tape drives, etc.).

The device generates and checks CRC codes in any synchronous mode and can be

programmed to check data integrity in various modes. The SCC also contains facilities for

modem controls in both channels. In applications where these controls are not required,

the modem controls can be used for general-purpose I/O. The daisy-chain interrupt hierar-

chy is also supported.

PS011705-0608

General Description

CMOS SCC Serial Communications Controller

Product Specification

5

Transmit Logic

Transmit MUX

TxDA

Transmit

Buffer

Data Encoding & CRC

Generation

Channel A

Exploded View

TRxCA

RTxCA

Receive and Transmit Clock Multiplexer

Crystal

Oscillator

Amplifier

Digital

Phase-Locked

Loop

Baud Rate

Generator

CTSA

DCDA

Modem/Control Logic

SYNCA

RTSA

DTRA/REQA

Receive Logic

Rec. Status

FIFO 3 Byte

Receive MUX

RxDA

FIFO 3 Byte

CRC Checker

Data Decode &

Sync Character

Detection

SDLC Frame Status FIFO

10 X 19

Interrupt

Control

Logic

Channel A

Register

Channel A

Channel B

Databus

Control

CPU & DMA

Bus Interface

INT

Interrupt

Control

Logic

INTACK

Channel B

Register

Interrupt

Control

IEI

IEO

Figure 1. SCC Block Diagram

PS011705-0608

General Description

CMOS SCC Serial Communications Controller

Product Specification

6

Pin Descriptions

Z85C30/Z80C30 Common Pin Functions

The following sections describe the pin functions common to Z85C30 and

Z80C30 devices:

•

CTSA, CTSB

DCDA, DCDB

DTR/REQA, DTR/REQB

IEI

IEO

INT

INTACK

PCLK

RxDA, RxDB

RTxCA, RTxCB

RTSA, RTSB

SYNCA, SYNCB

TxDA, TxDB

TRxCA, TRxCB

W/REQA, W/REQB

Each pin function is described below.

CTSA, CTSB

Clear To Send (inputs, active Low) — If these pins are programmed for Auto Enable, a

Low on the inputs enables the respective transmitters. If not programmed as Auto Enable,

these pins can be used as general-purpose inputs. Both inputs are Schmitt-trigger buffered

to accommodate slow rise-time inputs. The SCC detects pulses on these inputs and can

interrupt the CPU on both logic level transitions.

DCDA, DCDB

Data Carrier Detect (inputs, active Low) — These pins function as receiver enables if

programmed for Auto Enable. Otherwise, these pins are used as general-purpose input

pins. Both pins are Schmitt-trigger buffered to accommodate slow rise-time signals.

The SCC detects pulses on these pins and can interrupt the CPU on both logic level

transitions.

PS011705-0608

General Description

CMOS SCC Serial Communications Controller

Product Specification

7

DTR/REQA, DTR/REQB

Data Terminal Ready/Request (outputs, active Low) — These outputs follow the state

programmed into the DTR bit. They can also be used as general-purpose outputs or as

Request lines for a DMA controller.

IEI

Interrupt Enable In (input, active High) — IEI is used with IEO to form an interrupt

daisy-chain when there is more than one interrupt driven device. A high IEI indicates that

no other higher priority device has an interrupt under service or is requesting an interrupt.

IEO

Interrupt Enable Out (output, active High) — IEO is High only if IEI is High and the

CPU is not servicing the SCC interrupt or the SCC is not requesting an interrupt (interrupt

Acknowledge cycle only). IEO is connected to the next lower priority device’s IEI input

and thus inhibits interrupts from lower priority devices.

INT

Interrupt Request (output, open-drain, active Low) — This signal activates when the

SCC requests an interrupt.

INTACK

Interrupt Acknowledge (input, active Low) — This signal indicates an active Interrupt

Acknowledge cycle. During this cycle, the SCC interrupt daisy chain settles. When RD is

active, the SCC places an interrupt vector on the data bus (if IEI is High). INTACK is

latched by the rising edge of PCLK.

PCLK

Clock (input) — This is the master SCC clock used to synchronize internal signals. PCLK

is a TTL level signal. PCLK is not required to have any phase relationship with the master

system clock. The maximum transmit rate is 1/4 PCLK.

RxDA, RxDB

Receive Data (inputs, active High) — These signals receive serial data at standard TTL

levels.

RTxCA, RTxCB

Receive/Transmit Clocks (inputs, active Low) — These pins can be programmed in

several different operating modes. In each channel, RTxC can supply the receive clock, the

transmit clock, clock for the Baud Rate Generator, or the clock for the Digital Phase-

Locked Loop. These pins can also be programmed for use with the respective SYNC pins

as a crystal oscillator. The receive clock can be 1, 16, 32, or 64 times the data rate in Asyn-

chronous modes.

PS011705-0608

General Description

CMOS SCC Serial Communications Controller

Product Specification

8

RTSA, RTSB

Request To Send (outputs, active Low) — When the Request To Send (RTS) bit in

Write Register 5 (see Figure 9 on page 19) is set, the RTS signal goes Low. When the RTS

bit is reset in the Asynchronous mode and Auto Enable is ON, the signal goes High after

the transmitter is empty. In Synchronous mode, it strictly follows the state of the RTS bit.

When Auto Enable is OFF, the RTS pins can be used as general-purpose outputs.

SYNCA, SYNCB

Synchronization (inputs or outputs, active Low) — These pins function as inputs,

outputs, or part of the crystal oscillator circuit. In the Asynchronous Receive mode (crystal

oscillator option not selected), these pins are inputs similar to CTS and DCD. In this

mode, transitions on these lines affect the state of the Synchronous/Hunt status bits in

Read Register 0 (see Figure 8 on page 17) but have no other function.

In External Synchronization mode with the crystal oscillator not selected, these lines also

act as inputs. In this mode, SYNC must be driven Low for two receive clock cycles after

the last bit in the synchronous character is received. Character assembly begins on the

rising edge of the receive clock immediately preceding the activation of SYNC.

In the Internal Synchronization mode (Monosync and Bisync) with the crystal oscillator

not selected, these pins act as outputs and are active only during the part of the receive

clock cycle in which synchronous characters are recognized. This synchronous condition

is not latched. These outputs are active each time a synchronization pattern is recognized

(regardless of character boundaries). In SDLC mode, these pins act as outputs and are

valid on receipt of a flag.

TxDA, TxDB

Transmit Data (outputs, active High) — These output signals transmit serial data at

standard TTL levels.

TRxCA, TRxCB

Transmit/Receive Clocks (inputs or outputs, active Low) — These pins can be

programmed in several different operating modes. TRxC may supply the receive clock or

the transmit clock in the input mode or supply the output of the Digital Phase-locked loop,

the crystal oscillator, the Baud Rate Generator, or the transmit clock in the output mode.

W/REQA, W/REQB

Wait/Request (outputs, open-drain when programmed for a Wait function, driven

High or low when programmed for a Request function) — These dual-purpose outputs

can be programmed as Request lines for a DMA controller or as Wait lines to synchronize

the CPU to the SCC data rate. The reset state is Wait.

PS011705-0608

General Description

CMOS SCC Serial Communications Controller

Product Specification

9

Z85C30

A/B

Channel A/Channel B (input) — This signal selects the channel in which the Read or

Write operation occurs.

CE

Chip Enable (input, active Low) — This signal selects the SCC for a Read or Write

operation.

D7–D0

Data Bus (bidirectional, tri-state) — These lines carry data and command to and from

the SCC.

D/C

Data/Control Select (input) — This signal defines the type of information transferred to

or from the SCC. A High indicates a data transfer; a Low indicates a command.

RD

Read (input, active Low) — This signal indicates a Read operation and when the SCC is

selected, enables the SCC’s bus drivers. During the Interrupt Acknowledge cycle, this

signal gates the interrupt vector onto the bus if the SCC is the highest priority device

requesting an interrupt.

WR

Write (input, active Low) — When the SCC is selected, this signal indicates a Write

operation. The coincidence of RD and WR is interpreted as a reset.

Z80C30

AD7–AD0

Address/Data Bus (bidirectional, active High, Tri-state) — These multiplexed lines

carry register addresses to the SCC as well as data or control information.

AS

Address Strobe (input, active Low) — Addresses on AD7–AD0 are latched by the

rising edge of this signal.

CS0

Chip Select 0 (input, active Low) — This signal is latched concurrently with the

addresses on AD7–AD0 and must be active for the intended bus transaction to occur.

PS011705-0608

General Description

CMOS SCC Serial Communications Controller

Product Specification

10

CS1

Chip Select 1 (input, active High) — This second select signal must also be active before

the intended bus transaction can occur. CS1 must remain active throughout the

transaction.

DS

Data strobe (input, active Low) — This signal provides timing for the transfer of data

into and out of the SCC. If AS and DS coincide, this confluence is interpreted as a reset.

R/W

Read/Write (input) — This signal specifies whether the operation to be performed is a

Read or a Write.

Figure 2 displays the pin assignments for Z85C30 and Z80C30 DIP package.

D1

D3

1

2

3

4

5

AD1

AD3

AD5

AD7

INT

1

2

3

4

5

40

39

38

37

36

40

39

38

37

36

D0

D2

D4

D6

RD

AD0

AD2

AD4

AD6

DS

D5

D7

INT

IEO

IEI

6

7

IEO

IEI

6

7

35

34

35

34

WR

A/B

AS

R/W

INTACK

+5v

8

9

INTACK

+5v

8

9

33

32

33

32

CE

CS0

CS1

D/C

W/REQA

SYNCA

RTxCA

RxDA

10

11

12

13

W/REQA

SYNCA

RTxCA

RxDA

10

11

12

13

31

30

29

28

31

30

29

28

GND

Z85C30

Z80C30

W/REQB

SYNCB

RTxCB

W/REQB

SYNCB

RTxCB

TRxCA

TxDA

14

15

16

17

18

19

TRxCA

TxDA

14

15

16

17

18

19

27

26

25

24

23

22

27

26

25

24

23

22

RxDB

TRxCB

TxDB

TRxCB

TxDB

DTR/REQA

RTSA

DTR/REQA

RTSA

DTR/REQB

RTSB

DTR/REQB

RTSB

CTSA

DCDA

CTSB

PCLK

20

PCLK

20

21

DCDB

Figure 2. Z85C30 and Z80C30 DIP Pin Assignments

PS011705-0608

General Description

CMOS SCC Serial Communications Controller

Product Specification

11

Figure 3 displays the pin assignments for Z85C30 and Z80C30 PLCC package.

6

5

4

3

2

1

44 43 42 41 40

39

6

5

4

3

2

1

44 43 42 41 40

39

7

IEO

IEI

IEO

IEI

A/B

CE

R/W

CS0

CS1

38

37

36

35

34

33

32

31

30

29

38

37

36

35

34

33

32

31

30

29

8

INTACK

9

D/C

9

+5V

10

11

12

13

14

15

16

10

11

12

13

14

15

16

NC

W/REQA

SYNCA

W/REQA

SYNCA

GND

Z85C30

Z80C30

W/REQB

SYNCB

RTxCB

RxDB

W/REQB

SYNCB

RTxCB

RxDB

RTxCA

RxDA

TRxCA

TxDA

NC

RTxCA

RxDA

TRxCA

TxDA

NC

TRxCB

TxDB

TRxCB

TxDB

17

18 19 20 21 22 23 24 25 26 27 28

Figure 3. Z85C30 and Z80C30 PLCC Pin Assignments

Figure 4 displays the pin functions for the Z85C30 device.

TxDA

D7

D6

D5

D4

D3

D2

D1

D0

Serial

Data

RxDA

TRxCA

Channel

Clocks

RTxCA

Data Bus

SYNCA

W/REQA

DTR/REQA

RTSA

CH-A

Channel

Controls

for Modem,

DMA and

Other

CTSA

RD

Bus Timing

and Reset

DCDA

WR

Z85C30

TxDB

RxDB

A/B

Serial

Data

Control

CE

TRxCB

D/C

Channel

Clocks

RTxCB

SYNCB

INT

INTACK

IEI

Interrupt

CH-B

W/REQB

DTR/REQB

RTSB

Channel

Controls

for Modem,

DMA and

Other

IEO

CTSB

DCDB

Figure 4. Z85C30 Pin Functions

PS011705-0608

General Description

CMOS SCC Serial Communications Controller

Product Specification

12

Figure 5 displays the pin functions for the Z80C30 device.

TxDA

RxDA

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

Serial

Data

TRxCA

Channel

Clocks

RTxCA

Data Bus

SYNCA

W/REQA

DTR/REQA

RTSA

CH-A

Channel

Controls

for Modem,

DMA and

Other

CTSA

AS

DS

Bus Timing

and Reset

DCDA

Z80C30

TxDB

RxDB

R/W

Serial

Data

Control

CS1

CS0

TRxCB

Channel

Clocks

RTxCB

SYNCB

INT

INTACK

IEI

Interrupt

CH-B

W/REQB

DTR/REQB

RTSB

Channel

Controls

for Modem,

DMA and

Other

IEO

CTSB

DCDB

Figure 5. Z80C30 Pin Functions

PS011705-0608

General Description

CMOS SCC Serial Communications Controller

Product Specification

13

Functional Description

The architecture of the SCC is described below:

•

As a data communications device which transmits and receives data in various

protocols.

As a microprocessor peripheral in which the SCC offers valuable features

such as vectored interrupts and DMA support.

The SCC’s peripheral and data communication are described in the following sections.

Figure 1 on page 5 displays the SCC block diagram.

Figure 6 and Figure 7 display the details of the communications between the receive and

transmit logic to the system bus. The features and data path for each of the SCC’s A and B

channels are identical.

Internal Data Bus

To Other Channel

Internal TXD

TX Buffer

1 Byte

WR6

Register

WRB

WR7

SYNC

Register

SYNC

Final TX

MUX

TXD

20-Bit TX Shift Register

Sync

Transmit

MUX & 2-Bit

Delay

NRZ

Encode

Zero Insert

(5 Bits)

SDLC

Transmit Clock

CRC-Gen

From Receiver

Figure 6. SCC Transmit Data Path

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

14

CPU/I/O

I/O Data buffer

Internal Data Bus

Status FIFO

10 X 19 Frame

Rec. Error FIFO

3 Byte Deep

Upper Byte (WR13)

Time Constant

Lower Byte (WR12)

Time Constant

Rec. Error FIFO

3 Byte Deep

BRG

Input

BRG

Output

16-Bit Down Counter

DIV 2

14-Bit Counter

Rec. Error Logic

Hunt Mode (BISYNC)

DPLL

IN

DPLL

OUT

SYNC Register

& Zero Delete

Receive Shift

Register

DPLL

3-Bit

Internal TXD

MUX

CRC Delay

Register (8 bits)

SYNC

CRC

RXD

1-Bit

NRZI Decode

MUX

CRC

Checker

SDLC-CRC

To Transmit Section

CRC Result

Figure 7. SCC Receive Data Path

I/O Interface Capabilities

System communication to and from the SCC is performed through the SCC’s register set.

There are sixteen Write registers and eight Read registers.

Table 1 and Table 2 list the SCC registers and provide a brief description of their

functions.

Throughout this document, Write and Read registers are referenced with the following

notation:

•

‘WR’ for Write Register

‘RR’ for Read Register

For example,

WR4A Write Register 4 for channel A

RR3

Read Register 3 for either/both channels

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

15

Table 1. SCC Read Register Functions

Register

RR0

Function

Transmit/Receive buffer status and External status

Special Receive Condition status

RR1

RR2

Modified interrupt vector (Channel B only) Unmodified

interrupt vector (Channel A only)

RR3

Interrupt Pending bits (Channel A only)

Receive Buffer

RR8

RR10

RR12

RR13

RR15

Miscellaneous status

Lower byte of Baud Rate Generator time constant

Upper byte of Baud Rate Generator time constant

External/Status interrupt information

Table 2. SCC Write Register Functions

Register

Function

WR0

CRC initialize, initialization commands for the various

modes, register pointers

WR1

Transmit/Receive interrupt and data transfer mode

definition

WR2

WR3

WR4

Interrupt vector (accessed through either channel)

Receive parameters and control

Transmit/Receive miscellaneous parameters and

modes

WR5

WR6

WR7

WR7*

Transmit parameters and controls

Sync characters or SDLC address field

Sync character or SDLC flag

Extended Feature and FIFO Control (WR7 Prime)

85C30 Only

WR8

WR9

Transmit buffer

Master interrupt control and reset (accessed through

either channel)

WR10

Miscellaneous transmitter/receiver control bits

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

16

Table 2. SCC Write Register Functions (continued)

Register

WR11

WR12

WR13

WR14

WR15

Function

Clock mode control

Lower byte of Baud Rate Generator time constant

Upper byte of Baud Rate Generator time constant

Miscellaneous control bits

External/Status interrupt control

Following three methods move data, status, and control information in and out of

the SCC:

•

Polling

Interrupts (vectored and non-vectored)

CPU/DMA Block Transfer — The BLOCK TRANSFER mode can be implemented

under CPU or DMA control.

Polling

When polling, all interrupts are disabled. Three status registers in the SCC are automati-

cally updated when any function is performed. For example, End-Of-Frame in SDLC

mode sets a bit in one of these status registers. The purpose of polling is for the CPU to

periodically read a status register until the register contents indicate the need for data to be

transferred. Only one register is read, and depending on its contents, the CPU either writes

data, reads data, or continues. Two bits in the register indicate the need for data transfer.

An alternative is a poll of the Interrupt Pending register to determine the source of an

interrupt. The status for both channels resides in one register.

Interrupts

The SCC’s interrupt structure supports vectored and nested interrupts. Nested interrupts

are supported with the interrupt acknowledge feature (INTACK pin) of the SCC.

This allows the CPU to recognize the occurrence of an interrupt, and re-enable higher pri-

ority interrupts. Because an INTACK cycle releases the INT pin from the active state, a

higher priority SCC interrupt or another higher priority device can interrupt the CPU.

When an SCC responds to an Interrupt Acknowledge signal (INTACK) from the CPU, an

interrupt vector can be placed on the data bus. This vector is written in WR2 and can be

read in RR2A or RR2B. To speed interrupt response time, the SCC can modify three bits

in this vector to indicate status. If the vector is read in Channel A, status is never included.

If the vector is read in Channel B, status is always included.

Each of the six sources of interrupts in the SCC (Transmit, Receive, and External/Status

interrupts in both channels) has three bits associated with the interrupt source.

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

17

Interrupt Pending (IP), Interrupt Under Service (IUS), and Interrupt Enable (IE). Opera-

tion of the IEbit is straight forward. If the IEbit is set for a given interrupt source, then

that source can request interrupts. The exception is when the MIE (Master Interrupt

Enable) bit in WR9 is reset and no interrupts can be requested. The IE bits are Write only.

The other two bits are related to the interrupt priority chain (see Figure 8). As a micropro-

cessor peripheral, the SCC can request an interrupt only when no higher priority device is

requesting one, that is, when IEI is High. If the device in question requests an interrupt, it

pulls down INT. The CPU responds with INTACK, and the interrupting device places the

vector on the data bus.

Peripheral

+5 V

IEI D7–D0 INT INTACK IEO

IEI D7–D0 INT INTACK

IEI D7–D0 INT INTACK IEO

+5 V

D7–D0

INT

INTACK

Figure 8. SCC Interrupt Priority Schedule

The SCC can also execute an interrupt acknowledge cycle through software. In some CPU

environments, it is difficult to create the INTACK signal with the necessary timing to

acknowledge interrupts and allow the nesting of interrupts. In these cases, the INTACK

signal can be created with a software command to the SCC.

In the SCC, the Interrupt Pending (IP) bit signals a need for interrupt servicing. When an

IP bit is 1 and the IEI input is High, the INT output is pulled Low, requesting an interrupt.

In the SCC, if the IEbit is not set by enabling interrupts, then the IP for that source is

never set. The IPbits are readable in RR3A.

The IUS bits signal that an interrupt request is being serviced. If an IUS is set, all interrupt

sources of lower priority in the SCC and external to the SCC are prevented from request-

ing interrupts.

The internal interrupt sources are inhibited by the state of the internal daisy chain, while

lower priority devices are inhibited by the IEO output of the SCC being pulled Low and

propagated to subsequent peripherals. An IUS bit is set during an Interrupt Acknowl-

edge cycle, if there are no higher priority devices requesting interrupts.

There are three types of interrupts:

•

Transmit

Receive

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

18

•

External/Status

Each interrupt type is enabled under program control with Channel A having higher

priority than Channel B, and with Receiver, Transmit, and External/Status interrupts

prioritized in that order within each channel.

When enabled, the receiver interrupts the CPU in one of three ways:

•

Interrupt on First Receive Character or Special Receive Condition

Interrupt on All Receive Characters or Special Receive Conditions

Interrupt on Special Receive Conditions Only

Interrupt on First Character or Special Condition and Interrupt on Special Condition Only

are typically used with the Block Transfer mode. A special Receive Condition is one of the

following. receiver overrun, framing error in Asynchronous mode, end-of-frame in SDLC

mode and, optionally, a parity error. The Special Receive Condition interrupt is different

from an ordinary receive character available interrupt only by the status placed in the vec-

tor during the Interrupt Acknowledge cycle. In Interrupt on First Receive Character, an

interrupt occurs from Special Receive Conditions anytime after the first receive character

interrupt.

The main function of the External/Status interrupt is to monitor the signal transitions of

the CTS, DCD, and SYNC pins, however, an External/Status interrupt is also caused by a

Transmit Underrun condition; a zero count in the Baud Rate Generator; by the detection of

a Break (Asynchronous mode), Abort (SDLC mode) or EOP (SDLC Loop mode)

sequence in the data stream. The interrupt caused by the Abort or EOP has a special fea-

ture allowing the SCC to interrupt when the Abort or EOP sequence is detected or termi-

nated. This feature facilitates the proper termination of the current message, correct

initialization of the next message, and the accurate timing of the Abort condition in exter-

nal logic in SDLC mode. In SDLC Loop mode, this feature allows secondary stations to

recognize the primary station regaining control of the loop during a poll sequence.

Software Interrupt Acknowledge

On the CMOS version of the SCC, the SCC interrupt acknowledge cycle can be initiated

through software. If Write Register 9 (WR9) bit D5 is set, Read Register 2 (RR2) results in

an interrupt acknowledge cycle to be executed internally. Like a hardware INTACK cycle,

a software acknowledge causes the INT pin to return High, the IEO pin to go low and set

the IUS latch for the highest priority interrupt pending.

Similar to using the hardware INTACK signal, a software acknowledge cycle requires that

a Reset Highest IUS command be issued in the interrupt service routine. Whenever an

interrupt acknowledge cycle is used, hardware or software, a reset highest IUS command

is required. If RR2 is read from channel A, the unmodified vector is returned. If RR2 is

read from channel B, then the vector is modified to indicate the source of the interrupt.

The Vector Includes Status (VIS) and No Vector (NV) bits in WR9 are ignored when bit

05 is set to 1.

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

19

When the INTACK and IEI pins are not being used, they should be pulled up to V_CC

through a resistor (10 KΩ typical).

CPU/DMA Block Transfer

The SCC provides a Block Transfer mode to accommodate CPU block transfer functions

and DMA controllers. The Block Transfer mode uses the WAIT/REOUEST output in con-

junction with the Wait/Requestbits in WR1. The WAIT/REOUEST output can be

defined under software control as a WAIT line in the CPU Block Transfer mode or as a

REQUEST line in the DMA Block Transfer mode.

To a DMA controller, the SCC REQUEST output indicates that the SCC is ready to trans-

fer data to or from memory To the CPU, the WAIT line indicates that the ESCC is not

ready to transfer data, thereby requesting that the CPU extend the I/O cycle. The DTR/

REQUEST line allows full-duplex operation under DMA control.

SCC Data Communications Capabilities

The SCC provides two independent full-duplex programmable channels for use in any

common asynchronous or synchronous data communication protocols (see Figure 9 on

page 19). Each data communication channel has identical feature and capabilities.

Parity

Start

Stop

Marking Line

Data

Asynchronous

SYNC

Data

CRC1

CRC2

Monosync

Bisync

SYNC

Data

Signal

CRC1

External Sync

Address

Information

SDLC/HDLC/X.25

Information

Flag

Figure 9. Some SCC Protocols

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

20

Asynchronous Modes

Send and Receive is accomplished independently on each channel with five to eight bits

per character, plus optional even or odd parity. The transmitters can supply one, one-and-

a-half, or two stop bits per character and can provide a break output at any time. The

receiver break-detection logic interrupts the CPU both at the start and at the end of a

received break.

Reception is protected from spikes by a transient spike-rejection mechanism that checks

the signal one-half a bit time after a Low level is detected on the receive data input (RxDA

or RxDB pins). If the Low does not persist (a transient), the character assembly process

does not start.

Framing errors and overrun errors are detected and buffered together with the partial char-

acter on which they occur. Vectored interrupts allow fast servicing or error conditions

using dedicated routines. A built-in checking process avoids the interpretation of a fram-

ing error as a new start bit. A framing error results in the addition of one-half a bit time to

the point at which the search for the next start bit begins.

The SCC does not require symmetric transmit and receive clock signals - a feature allow-

ing use of the wide variety of clock sources. The transmitter and receiver handle data at a

rate supplied to the receive and transmit clock inputs. In Asynchronous modes, the SYNC

pin can be programmed as an input used for functions such as monitoring a ring indicator.

Synchronous Modes

The SCC supports both byte and bit-oriented synchronous communication. Synchronous

byte-oriented protocols are handled in several modes. They allow character synchroniza-

tion with a 6-bit or 8-bit sync character (Monosync), and a 12-bit or 16-bit synchroniza-

tion pattern (Bisync), or with an external sync signal. Leading sync characters are

removed without interrupting the CPU.

5- or 7-bit synchronous characters are detected with 8- or 16-bit patterns in the SCC by

overlapping the larger pattern across multiple incoming synchronous characters as

displayed in Figure 10.

7 Bits

SYNC

Data

SYNC

Data

SYNC

8

16

Figure 10. Detecting 5- or 7-Bit Synchronous Characters

CRC checking for Synchronous byte-oriented modes is delayed by one character time so

that the CPU can disable CRC checking on specific characters. This feature permits the

implementation of protocols such as IBM Bisync.

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

21

Both CRC-16 (X¹⁶+ X¹⁵+ X¹²+1) and CCITT (X¹⁶+ X¹²+ X⁵+ 1) error-checking

polynomials are supported. Either polynomial can be selected in all Synchronous modes.

You can preset the CRC generator and checker to all 1’s or all 0’s. The SCC also provides

a feature that automatically transmits CRC data when no other data is available for trans-

mission. This feature allows for high speed transmissions under DMA control, with no

need for CPU intervention at the end of a message.

When there is no data or CRC to send in Synchronous modes, the transmitter inserts 6-,8-,

or 16-bit sync characters, regardless of the programmed character length.

SDLC Mode

The SCC supports Synchronous bit-oriented protocols, such as SDLC and HDLC, by

performing automatic flag sending, zero insertion, and CRC generation. A special

command is used to abort a frame in transmission. At the end of a message, the SCC auto-

matically transmits the CRC and trailing flag when the transmitter underruns. The trans-

mitter can also be programmed to send an idle line consisting of continuous flag characters

or a steady marking condition.

If a transmit underrun occurs in the middle of a message, an external/status interrupt warns

the CPU of this status change, issuing an abort. The SCC can also be programmed to send

an abort itself in case of an underrun, relieving the CPU of this task. One to eight bits per

character can be sent, allowing reception of a message with no prior information about the

character structure in the information field of a frame.

The receiver automatically acquires synchronization on the leading flag of a frame in

SDLC or HDLC and provides a synchronization signal on the SYNC pin (an interrupt can

also be programmed). The receiver can be programmed to search for frames addressed by

a single byte (or four bits within a byte) of a user-selected address or to a global broadcast

address. In this mode, frames not matching either the user-selected or broadcast address

are ignored.

The number of address bytes are extended under software control. For receiving data, an

interrupt on the first received character, or an interrupt on every character, or on special

condition only (end-of-frame) can be selected. The receiver automatically deletes all 0’s

inserted by the transmitter during character assembly CRC is also calculated and is auto-

matically checked to validate frame transmission. At the end of transmission, the status of

a received frame is available in the status registers. In SDLC mode, the SCC must be pro-

grammed to use the SDLC CRC polynomial, but the generator and checker can be preset

to all 1’s or all 0’s. The CRC inverts before transmission and the receiver checks against

the bit pattern 0001110100001111.

NRZ, NRZI or FM coding can be used in any 1 x mode. The parity options available in

Asynchronous modes are available in Synchronous modes.

SDLC Loop Mode

The SCC supports SDLC Loop mode in addition to normal SDLC. In an SDLC Loop, a

primary controller station manages the message traffic flow on the loop and any number of

secondary stations. In SDLC Loop mode, the SCC performs the functions of a secondary

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

22

station while an SCC operating in regular SDLC mode acts as a controller (see Figure 11

on page 22). The SDLC loop mode can be selected by setting WR10 bit D1.

Controller

Secondary #1

Secondary #4

Secondary #2

Secondary #3

Figure 11. An SDLC Loop

A secondary station in an SDLC Loop is always listening to the messages sent around the

loop and passes these messages to the rest of the loop by retransmitting them with a one-

bit-time delay. The secondary station places its own message on the loop only at specific

times.

The controller signals that secondary stations can transmit messages by sending a special

character, called an End Of Poll (EOP), around the loop. The EOP character is the bit

pattern 11111110. Because of zero insertion during messages, this bit pattern is unique

and easily recognized.

When a secondary station contains a message to transmit and recognizes an EOP on the

line, it changes the last binary 1 of the EOP to a 0 before transmission. This change has the

effect of turning the EOP into a flag sequence. The secondary station now places its mes-

sage on the loop and terminates the message with an EOP. Any secondary stations further

down the loop with messages to transmit append their messages to the message of the first

secondary station by the same process. Any secondary stations without messages to send

echo the incoming message and are prohibited from placing messages on the loop (except

when recognizing an EOP). In SDLC Loop mode, NRZ, NRZI, and FM coding can be

used.

The SCC’s ability to receive high speed back-to-back SDLC frames is maximized by a 10-

deep by 19-bit wide status FIFO. When enabled (through WR15, bit D2), it provides the

DMA the ability to continue to transfer data into memory so that the CPU can examine the

message later. For each SDLC frame, a 14-bit byte count and 5 status/error bits are stored.

The byte count and status bits are accessed through Read Registers 6 and 7. Read Regis-

ters 6 and 7 are only accessible when the SDLC FIFO is enabled. The 10 x 19 status FIFO

is separate from the 3-byte receive data FIFO.

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

23

Baud Rate Generator

Each channel in the SCC contains a programmable Baud Rate Generator (BRG). Each

generator consists of two 8-bit time constant registers that form a 16-bit time constant, a

16-bit down counter, and a flip-flop on the output producing a square wave. On startup,

the output flip-flop is set in a High state, the value in the time constant register is loaded

into the counter, and the counter starts counting down. The output of the BRG toggles

when reaching 0, the value in the time constant register is loaded into the counter, and the

process is repeated. The time constant can be changed at any time, but the new value does

not take effect until the next load of the counter.

The output of the BRG can be used as either the transmit clock, the receive clock, or both.

It can also drive the Digital Phase-locked loop (see Digital Phase-Locked Loop).

If the receive clock or transmit clock is not programmed to come from the TRxC pin, the

output of the BRG can be echoed out through the TRxC pin. The following formula relates

the time constant to the baud rate where PCLK or RTxC is the BRG input frequency in

Hertz. The clock mode is 1, 16, 32, or 64, as selected in Write Register 4, bits D6 and D7.

Synchronous operation modes select 1 and Asynchronous modes select 16, 32 or 64.

PCLK or RTxC Frequency

-2

Time Constant =

2(Baud Rate)(Clock Mode)

Digital Phase-Locked Loop

The SCC contains a Digital Phase-Locked Loop (DPLL) to recover clock information

from a data stream with NRZI or FM encoding. The DPLL is driven by a clock that is

nominally 32 (NRZI) or 16 (FM) times the data rate. The DPLL uses this clock, along with

the data stream, to construct a clock for the data. This clock is used as the SCC receive

clock, the transmit clock, or both. When the DPLL is selected as the transmit clock source,

it provides a jitter-free clock output that is the DPLL input frequency divided by the

appropriate divisor for the selected encoding technique.

For NRZI encoding, the DPLL counts the 32x clock to create nominal bit times. As the

32x clock is counted, the DPLL is searching the incoming data stream for edges (either 1

to 0, or 0 to 1). Whenever an edge is detected, the DPLL makes a count adjustment (during

the next counting cycle), producing a terminal count closer to the center of the bit cell.

For FM encoding, the DPLL again counts from 0 to 31, but with a cycle corresponding to

two bit times. When the DPLL is locked, the clock edges in the data stream occur between

counts 15 and 16 and between counts 31 and 0. The DPLL looks for edges only during a

time centered on the 15 to 16 counting transition.

The 32x clock for the DPLL can be programmed to come from either the RTxC input or

the output of the BRG. The DPLL output can be programmed to be echoed out of the SCC

through the TRxC pin (if this pin is not being used as an input).

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

24

Data Encoding

The SCC can be programmed to encode and decode the serial data in four different

methods (Figure 12). In NRZ encoding, a 1 is represented by a High level and a 0 is

represented by a Low level. In NRZI encoding, a 1 is represented by no change in level

and a 0 is represented by a change in level.

In FM1 (more properly, bi-phase mark), a transition occurs at the beginning of every bit

cell. A 1 is represented by an additional transition at the center of the bit cell and a 0 is

represented by no additional transition at the center of the bit cell.

In FM0 (bi-phase space), a transition occurs at the beginning of every bit cell. A 0 is

represented by an additional transition at the center of the bit cell, and a 1 is represented by

no additional transition at the center of the bit cell.

In addition to these four methods, the SCC can be used to decode Manchester (bi-phase

level) data by using the DPLL in the FM mode and programming the receiver for NRZ

data. Manchester encoding always produces a transition at the center of the bit cell. If the

transition is 0 to 1, the bit is a 0. If the transition is 1 to 0, the bit is a 1.

1

0

Data

NRZ

0

NRZI

FM1

FM0

Manchester

Figure 12. Data Encoding Methods

Auto Echo and Local Loopback

The SCC is capable of automatically echoing everything it receives. This feature is useful

mainly in Asynchronous modes, but works in Synchronous and SDLC modes as well.

Auto Echo mode (Tx0 is Rx0) is used with NRZI or FM encoding with no additional delay

because the data stream is not decoded before retransmission. In Auto Echo mode, the

CTS input is ignored as a transmitter enable (although transitions on this input can still

cause interrupts if programmed to do so). In this mode, the transmitter is actually bypassed

and the programmer is responsible for disabling transmitter interrupts and WAIT/

REQUEST on transmit.

The SCC is also capable of local loopback. In this mode, TxD or RxD is similar to Auto

Echo mode. However, in Local Loopback mode the internal transmit data is tied to the

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

25

internal receive data and RxD is ignored (except to be echoed out through TxD). The CTS

and DCD inputs are also ignored as transmit and receive enables. However, transitions on

these inputs can still cause interrupts. Local Loopback works in Asynchronous, Synchro-

nous and SDLC modes with NRZ, NRZI or FM coding of the data stream.

SDLC FIFO Frame Status FIFO Enhancement

The SCC’s ability to receive high speed back-to-back SDLC frames is maximized by a

10-deep by 19-bit wide status FIFO. When enabled (through WR15, bit D2), it provides

the DMA the ability to continue to transfer data into memory so that the CPU can examine

the message later. For each SDLC frame, a 14-bit byte count and 5 status/error bits are

stored. The byte count and status bits are accessed through Read Registers 6 and 7. Read

Registers 6 and 7 are only accessible when the SDLC FIFO is enabled. The 10x19 status

FIFO is separate from the 3-byte receive data FIFO.

When the enhancement is enabled, the status in Read Register 1 (RR1) and byte count for

the SDLC frame are stored in the 10 x 19 bit status FIFO. This arrangement allows the

DMA controller to transfer the next frame into memory while the CPU verifies that the

message was properly received.

Summarizing the operation; data is received, assembled, and loaded into the eight byte

FIFO before being transferred to memory by the DMA controller. When a flag is received

at the end of an SDLC frame, the frame byte count from the 14-bit counter and five status

bits are loaded into the status FIFO for verification by the CPU. The CRC checker auto-

matically resets in preparation for the next frame which can begin immediately. Since the

byte count and status are saved for each frame, the message integrity is verified at a later

time. The status information for up to 10 frames is stored before a status FIFO overrun

occurs.

If a frame is terminated with an ABORT, the byte count is loaded to the status FIFO and

the counter resets for the next frame.

FIFO Detail

For more details on the FIFO operation details, see Figure 13 on page 26.

Enable/Disable

This FIFO is implemented is enabled when WR15, bit D2, is set and the SCC is in the

SDLC/HDLC mode. Otherwise, the status register contents bypass the FIFO and go

directly to the bus interface (the FIFO pointer logic is reset either when disabled or

through a channel or Power-On Reset). When the FIFO mode is disabled, the SCC is

downward compatible with the NMOS Z8530. The FIFO mode is disabled on power-up

(WR15 D2 is set to 0 on reset). The effects of backward compatibility on the register set

are that RR4 is an image of RR0, RR5 is an image of RR1, RR6 is an image of RR2 and

RR7 is an image of RR3. For more details on the added registers, see Figure 16 on page

30. The status of the FIFO Enable signal is obtained by reading RR15, bit D2. If the FIFO

is enabled, the bit is set to 1; otherwise, it resets.

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

26

Read Operation

When WR15 bit D2 sets and the FIFO is not empty, the next read to status register RR1 or

registers RR7 and RR6, is from the FIFO. Reading status register RR1 causes one location

of the FIFO to become empty. Status is read after reading the byte count, otherwise the

count is incorrect. Before the FIFO underflows, it is disabled. In this case, the multiplexer

is switched allowing status to read directly from the status register. Reads from RR7 and

RR6 contain bits that are undefined. Bit D6 of RR7 (FIFO Data Available) determines if

status data is coming from the FIFO or directly from the status register, which sets to 1

when the FIFO is not empty. Not all status bits are stored in the FIFO. The All Sent, Parity,

and EOF bits bypass the FIFO. Status bits sent through the FIFO are Residue Bits (3),

Overrun, and CRC Error.

Frame Status FIFO Circuitry

Reset on Flag Detect

SCC Status Reg

Residue Bits (3)

Overrun, CRC Error

RR1

Byte Counter

Increment on Byte Detection

Enable Count in SDLC

End of Frame Signal

Status Read Comp

5 Bits

14 Bits

FIFO Array

10 Deep by 19 Bits Wide

Tail Pointer

4-Bit Counter

Head Pointer

4-Bit Counter

4-Bit Comparator

Over

Equal

5 Bits

EOF = 1

6 Bits

8 Bits

EN

6-Bit MUX

Bit 7 Bit 6 Bits 5-0

RR6

2 Bits

6 Bits

RR1

FIFO Enable

WR(15) Bit 2

Set Enables

Status FIFO

RR7 D5-D0 + RR6 D7-D0

Byte Counter Contains 14 bits

for a 16 KByte maximum count

Interface

to SCC

RR7 D6

FIFO Data available status bit Status Bit set to 1

When reading from FIFO

RR7 D7

FIFO Overflow Status Bit

MSB pf RR(7) is set on Status FIFO overflow

In SDLC Mode the following definitions apply

– All Sent bypasses MUX and equals contents of SCC Status Register

– Parity Bits bypasses MUX and does the same

– EOF is set to 1 whenever reading from the FIFO

Figure 13. SDLC Frame Status FIFO

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

27

The sequence for operation of the byte count and FIFO logic is to read the registers in the

following order. RR7, RR6, and RR1 (reading RR6 is optional). Additional logic prevents

the FIFO from being emptied by multiple reads from RR1. The read from RR7 latches the

FIFO empty/full status bit (D6) and steers the status multiplexer to read from the SCC

megacell instead of the status FIFO (since the status FIFO is empty). The read from RR1

allows an entry to be read from the FIFO (if the FIFO was empty, logic was added to

prevent a FIFO underflow condition).

Write Operation

When the end of an SDLC frame (EOF) is received and the FIFO is enabled, the contents

of the status and byte-count registers are loaded into the FIFO. The EOF signal is used to

increment the FIFO. If the FIFO overflows, RR7, bit D7 (FIFO Overflow) sets to indicate

the overflow. This bit and the FIFO control logic is reset by disabling and re-enabling the

FIFO control bit (WR15, bit 02). For details of FIFO control timing during an SDLC

frame, see Figure 14.

0

F

7

0

F

0

F

7

0

F

A

D

C

D

C

A

D

C

D

C

Internal Byte Strobe

Increments Counter

Internal Byte Strobe

Increments Counter

Don’t Load

Counter On

1st Flag

Reset Byte

Counter Here

Reset

Byte Counter

Load Counter

Into FIFO and

Increment PTR

Byte Counter

Load Counter

Into FIFO and

Increment PTR

Figure 14. SDLC Byte Counting Detail

Programming

The SCC contains Write registers in each channel that are programmed by the system

separately to configure the functional personality of the channels.

Z85C30

In the SCC, the data registers are directly addressed by selecting a High on the D/C pin.

With all other registers (except WR0 and RR0), programming the Write registers requires

two Write operations and reading the read registers requires both a Write and a Read oper-

ation. The first write is to WR0 and contains three bits that point to the selected register.

The second write is the actual control word for the selected register, and if the second

operation is read, the selected Read register is accessed. All the SCC registers, including

the data registers, can be accessed in this fashion. The pointer bits are automatically

cleared after the Read or Write operation so that WR0 (or RR0) is addressed again.

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

28

Z80C30

All SCC registers are directly addressable. A command issued in WR0B controls how the

SCC decodes the address placed on the address/data bus at the beginning of a Read or

Write cycle. In the Shift Right mode, the channel select A/B is taken from AD0 and the

state of AD5 is ignored. In the Shift Left mode, the channel select A/B is taken from AD5

and the state of AD0 is ignored. AD7 and AD6 are always ignored as address bits and the

register address occupies AD4-AD1.

Z85C30/Z80C30 Setup

Initialization

The system program first issues a series of commands to initialize the basic mode of

operation. This is followed by other commands to qualify conditions within the selected

mode. For example, in the Asynchronous mode, character length, clock rate, number of

stop bits, and even or odd parity must be set first. The interrupt mode is set, and finally, the

receiver and transmitter are enabled.

Write Registers

The SCC contains 15 Write registers for the 80C30, while there are 16 for the 85C30 (one

more additional Write register if counting the transmit buffer) in each channel. These

Write registers are programmed separately to configure the functional ‘personality’ of the

channels. There are two registers (WR2 and WR9) shared by the two channels that are

accessed through either of them. WR2 contains the interrupt vector for both channels,

while WR9 contains the interrupt control bits and reset commands. Figure 15 through

Figure 18 display the format of each Write register.

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

29

Write Register 1

Write Register 0 (non-multiplexed bus mode)

D7 D6 D5 D4 D3 D2 D1 D0

Ext Int Enable

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Register 0

Register 1

Register 2

Register 3

Register 4

Register 5

Register 6

Register 7

Register 8

Register 9

Register 10

Register 11

Register 12

Register 13

Register 14

Register 15

Tx Int Enable

Parity is Special Condition

0

1

0

1

Rx Int Disable

0

1

0

1

0

1

Rx Int on First Character or Special Condition

Int on all Rx Characters or Special Condition

Rx Int on Special Condition Only

WAIT/DMA Request on

Receive /Transmit

*

WAIT/DMA Request Function

WAIT/DMA Request

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Null Code

Point High

Write Register 2

Reset Ext/Status Interrupts

D7 D6 D5 D4 D3 D2 D1 D0

Send Abort (SDLC)

Enable Int on Next Rx Character

Reset Tx Int Pending

Error Reset

V0

V1

V2

V3

V4

V5

V6

Reset Highest IUS

0

1

Null Code

0

1

0

1

Reset Rx CRC Checker

Reset Tx CRC Generator

Reset Tx Underrun/EOM Latch

Interrupt

Vector

* With Point High Command

Write Register 0 (multiplexed bus mode)

D7 D6 D5 D4 D3 D2 D1 D0

V7

Write Register 3

D7 D6 D5 D4 D3 D2 D1 D0

Null Code

0

1

0

1

0

1

Null Code

Select Shift Left Mode

Select Shift Right Mode

*

Rx Enable

Sync Character Load Inhibit

Address Search Mode (SDLC)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Null Code

Rx CRC Enable

Enter Hunt Mode

Reset Ext/Status Interrupts

Send Abort

Enable Int on Next Rx Character

Reset Tx Int Pending

Error Reset

Auto Enables

Reset Highest IUS

0

1

0

1

0

1

Rx 5 Bits/Character

Rx 7 Bits/Character

0

1

0

1

Null Code

0

1

Rx 6 Bits/Character

Reset Rx CRC Checker

Reset Tx CRC Checker

Rx 8 Bits/Character

Reset Tx Underrun/EOM Latch

* B Channel Only

Figure 15. Write Register Bit Functions

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

30

Write Register 4

Write Register 5

D7 D6 D5 D4 D3 D2 D1 D0

Parity Enable

Tx CRC Enable

RTS

Parity EVEN/ODD

SDLC/CRC-16

Tx Enable

0

1

0

1

Sync Modes Enable

0

1

1 Stop Bit/Character

1 1/2 Stop Bits/Character

2 Stop Bits/Character

Send Break

0

1

0

1

0

1

Tx 5 Bits (or Less)/Character

Tx 7 Bits/Character

Tx 6 Bits/Character

Tx 8 Bits/Character

8-Bit Sync Character

16-Bit Sync Character

SDLC Mode (01111110 Flag)

External Sync Mode

0

1

0

1

0

1

DTR

0

1

0

1

X1 Clock Mode

X16 Clock Mode

X32 Clock Mode

X64 Clock Mode

0

1

Figure 16. Write Register Bit Functions

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

31

Write Register 6

D7 D6 D5 D4 D3 D2 D1 D0

Sync4

Sync7 Sync6 Sync5

Sync3

1

ADR3

x

Sync1

Sync0 Monosync, 8 Bits

Sync2

1

ADR2

x

Sync0 Sync5 Sync4

Sync6 Sync5 Sync4

Sync2 Sync1 Sync0

Monosync, 6 Bits

Sync0

Sync1

Sync7

Sync3

ADR7 ADR6 ADR5

Sync1 Sync0

Bisync, 16 Bits

1

ADR1

x

1

Bisync, 12 Bits

ADR4

ADR0 SDLC

x

SDLC (Address Range)

Write Register 7

D7 D6 D5 D4 D3 D2 D1 D0

Sync6 Sync5

Monosync, 8 Bits

Monosync, 6 Bits

Bisync, 16 Bits

Bisync, 12 Bits

SDLC

Sync7

Sync4

Sync2

Sync12

Sync8

1

Sync1

x

Sync9

Sync5

1

Sync3 Sync2

Sync1 Sync0

Sync0

x

Sync8

Sync4

0

Sync3

Sync5 Sync4

Sync15 Sync14

Sync13

Sync10

Sync6

1

Sync11

Sync7

1

Sync11

0

Sync10 Sync9

1

WR 7’ Prime (85C30 only)

D7 D6 D5 D4 D3 D2 D1 D0

Auto Tx Flag

Auto EOM Reset

Auto RTS Deactivation

Force TxD High

DTR/REQ Fast Mode

Complete CRC Reception

Extended Read Enable

Reserved (Program as 0)

Figure 17. Write Register Bit Functions

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

32

Write Register 9

Write Register 12

D7 D6 D5 D4 D3 D2 D1 D0

VIS

TC0

TC1

TC2

NV

DLC

MIE

TC3

Lower Byte of

Time Constant

Status High/Status Low

Software INTACK Enable

TC4

TC5

TC6

No Reset

0

1

0

1

0

1

TC7

Channel Reset B

Channel Reset A

Force Hardware Reset

Write Register 13

D7 D6 D5 D4 D3 D2 D1 D0

Write Register 10

D7 D6 D5 D4 D3 D2 D1 D0

TC8

TC9

6-Bit/8-Bit Sync

Loop Mode

TC10

TC11

Upper Byte of

Time Constant

Abort/Flag on Underrun

Mark/Flag Idle

TC12

TC13

TC14

Go Active on Poll

TC15

0

1

0

1

NRZ

NRZI

FM1 (Transition = 1)

FM1 (Transition = 0)

0

1

Write Register 14

D7 D6 D5 D4 D3 D2 D1 D0

CRC Preset I/O

BR Generator Enable

BR Generator Source

DTR/Request Function

Auto Echo

Write Register 11

D7 D6 D5 D4 D3 D2 D1 D0

Local Loopback

TRxC Out = Xtal Output

TRxC Out = Transmit Clock

TRxC Out = BR Generator Output

TRxC Out = DPLL Output

0

1

0

1

0

1

Null Command

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Enter Search Mode

Reset Missing Clock

Disable DPLL

TRxC O/I

Set Source = BR Generator

Set Source = RTxC

Set FM Mode

Set NRZI Mode

0

1

0

1

Transmit Clock = RTxC Pin

Transmit Clock = TRxC Pin

Transmit Clock = BR Generator Output

Transmit Clock = DPLL Output

0

1

Write Register 15

0

1

0

1

Receive Clock = RTxC Pin

Receive Clock = TRxC Pin

Receive Clock = BR Generator Output

Receive Clock = DPLL Output

0

1

D7 D6 D5 D4 D3 D2 D1 D0

0

RTxC Xtal/No Xtal

Zero Count IE

SDLC FIFO Enable

DCD IE

Sync/Hunt IE

CTS IE

Tx Underrun/EOM IE

Break/Abort IE

Figure 18. Write Register Bit Functions

Read Registers

The SCC contains ten Read registers (eleven, counting the receive buffer (RR8) in each

channel). Four of these can be read to obtain status information (RR0, RR1, RR10, and

RR15). Two registers (RR12 and RR13) are read to learn the Baud Rate Generator time

constant. RR2 contains either the unmodified interrupt vector (Channel A) or the vector

modified by status information (Channel B). RR3 contains the Interrupt Pending (IP) bits

(Channel A only – Figure 19). RR6 and RR7 contain the information in the SDLC Frame

Status FIFO, but is only read when WR15 D2 is set (see Figure 19 and Figure 20).

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

33

Read Register 3

Read Register 0

D7 D6 D5 D4 D3 D2 D1 D0

Channel B Ext/Status IP

Rx Character Available

Channel B Tx IP

Channel B Rx IP

Zero Count

Tx Buffer Empty

DCD

*

Channel A Ext/Status IP

Channel A Tx IP

Channel A Rx IP

0

Sync/Hunt

CTS

Tx Underrun/EOM

0

Break/Abort

* Always 0 in B Channel

Read Register 1

D7 D6 D5 D4 D3 D2 D1 D0

Read Register 10

D7 D6 D5 D4 D3 D2 D1 D0

All Sent

Residue Code 2

Residue Code 1

Residue Code 0

Parity Error

0

On Loop

0

Rx Overrun Error

CRC/Framing Error

End of Frame (SDLC)

Loop Sending

0

Two Clocks Missing

One Clocks Missing

Read Register 2

Read Register 12

D7 D6 D5 D4 D3 D2 D1 D0

V0

TC0

V1

V2

TC1

TC2

V3

Interrupt

Vector *

TC3

V4

V5

V6

V7

Lower Byte

of Time Constant

TC4

TC5

TC6

TC7

* Modified in B Channel

Figure 19. Read Register Bit Functions

Read Register 13

Read Register 15

D7 D6 D5 D4 D3 D2 D1 D0

TC8

0

TC9

Zero Count IE

0

TC10

TC11

TC12

TC13

TC14

DCD IE

Upper Byte

of Time Constant

Sync/Hunt IE

CTS IE

Tx Underrun/EOM IE

TC15

Break/Abort IE

Figure 20. Read Register Bit Functions

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

34

Z85C30 Timing

The SCC generates internal control signals from the WR and RD that are related to PCLK.

PCLK has no phase relationship with WR and RD, the circuitry generating the internal

control signals provides time for meta-stable conditions to disappear. This gives rise to a

recovery time related to PCLK. The recovery time applies only between bus transactions

involving the SCC.

The recovery time required for proper operation is specified from the falling edge of WR

or RD in the first transaction involving the SCC to the falling edge of WR or RD in the

second transaction involving the SCC. This time must be at least 3 PCLKs regardless of

which register or channel is being accessed.

The Z85C30 timings are described below:

•

Read Cycle Timing

Write Cycle Timing

Interrupt Acknowledge Cycle Timing

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

35

Read Cycle Timing

Figure 21 displays Read cycle timing. Addresses on A/ B and D/C and the status on

INTACK must remain stable throughout the cycle. If CE falls after RD falls, or if CE rises

before RD rises, the effective RD is shortened.

A/B, D/C

Address Valid

INTACK

CE

RD

Data Valid

D7–D0

Figure 21. Read Cycle Timing

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

36

Write Cycle Timing

Figure 22 displays Write cycle timing. Addresses on A/B and D/C and the status on

INTACK must remain stable throughout the cycle. If CE falls after WR falls, or if CE rises

before WR rises, the effective WR is shortened. Data must be valid before the rising edge

of WR.

A

_AddAddress Valid

Ad

A/B, D/C

INTACK

CE

WR

D7-D0

Data Valid

Figure 22. Write Cycle Timing

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

37

Interrupt Acknowledge Cycle Timing

Figure 23 displays an Interrupt Acknowledge cycle timing. Between the time INTACK

goes Low and the falling edge of RD, the internal and external IEI/IEO daisy chains settle.

If there is an interrupt pending in the SCC and IEI is High when RD falls, the Acknowl-

edge cycle is intended for the SCC. In this case, the SCC can be programmed to respond to

RD Low by placing its interrupt vector on D7-D0. It then sets the appropriate Interrupt-

Under-Service latch internally.

If the external daisy chain is not used, AC parameter #38 is required to settle the interrupt

priority daisy chain internal to the SCC. If the external daisy chain is used, you must

follow the equation in AC Characteristics, Read/Write Timing Table 6 on page 47, Note 5

for calculating the required daisy-chain settle time.

INTACK

RD

D7–D0

Vector

Figure 23. Interrupt Acknowledge Cycle Timing

Z80C30 Timing

The SCC generates internal control signals from AS and DS that are related to PCLK.

Because PCLK has no phase relationship with AS and DS, the circuitry generating these

internal control signals must provide time for metastable conditions to disappear. This

gives rise to a recovery time related to PCLK. The recovery time applies only between bus

transactions involving the SCC. The recovery time required for proper operation is speci-

fied from the falling edge of DS in the first transaction involving the SCC to the falling

edge of DS in the second transaction involving the SCC. The timings for Z80C30 device is

described below:

•

Read Cycle Timing

Write Cycle Timing

Interrupt Acknowledge Cycle Timing

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

38

Read Cycle Timing

Figure 24 displays the Read cycle timing. The address on AD7–AD0 and the state of CS0

and INTACK are latched by the rising edge of AS. R/W must be High to indicate a Read

cycle. CS1 must also be High for the Read cycle to occur. The data bus drivers in the SCC

are then enabled while DS is Low.

AS

CS0

INTACK

AD7–AD0

R/W

Address

Data Valid

CS1

DS

Figure 24. Read Cycle Timing

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

39

Write Cycle Timing

Figure 25 displays the Write cycle timing. The address on AD7–AD0 and the state of CS0

and INTACK are latched by the rising edge of AS. R/ must be Low to indicate a Write

W

cycle. CS1 must be High for the Write cycle to occur DS Low strobes the data into the

SCC.

AS

CS0

INTACK

AD7–AD0

R/W

Address

Data

CS1

DS

Figure 25. Write Cycle Timing

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

40

Interrupt Acknowledge Cycle Timing

Figure 26 displays the Interrupt Acknowledge cycle timing. The address on AD7–AD0

and the state of CS0 and INTACK are latched by the rising edge of AS. If INTACK is

Low, the address and CS0 are ignored. The state of the R/W and CS1 are also ignored for

the duration of the Interrupt Acknowledge cycle. Between the rising edge of AS and the

falling edge of DS, the internal and external IEI/IEO daisy chains settle. If there is an

interrupt pending in the SCC, and IEI is High when DS falls, the Acknowledge cycle was

intended for the SCC. In this case, the SCC is programmed to respond to RD Low by

placing its interrupt vector on D7-D0 and internally setting the appropriate Interrupt-

Under-Service latch.

AS

CS0

(Ignored)

INTACK

AD7–AD0

(Ignored)

Vector

DS

Figure 26. Interrupt Acknowledge Cycle Timing

PS011705-0608

Functional Description

CMOS SCC Serial Communications Controller

Product Specification

41

Electrical Characteristics

The electrical characteristics of the Z80C30 and the Z85C30 devices are described in the

following sections.

Absolute Maximum Ratings

Stresses greater than those listed in Table 3 may cause permanent damage to the device

This is a stress rating only. Operation of the device at any condition above those indicated

in the operational sections of these specifications is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Table 3. Absolute Maximum Ratings

Vcc Supply Voltage range

-0.3 V to +7.0 V

Voltages on all pins with respect to GND

-3 V to VCC +0.3 V

See Ordering Information

-65 °C to +150 °C

T Operating Ambient Temperature

A

Storage Temperature

Standard Test Conditions

The DC Characteristics and capacitance sections below apply for the following standard

test conditions, unless otherwise noted. All voltages are referenced to GND. Positive

current flows into the referenced pin. See Figure 27 and Figure 28.

•

+4.50 V ≤ V_cc≤ + 5.50 V

GND = 0 V

T_Aas specified in Ordering Information

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

42

2.1 KΩ

From Output

Under Test

100 pF

250 μA

Figure 27. Standard Test Load

2.2 KΩ

From Output

50 pF

Figure 28. Open-Drain Test Load

Capacitance

Table 4 lists the input, output, and bidirectional capacitance.

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

43

Table 4. Capacitance

Symbol Parameter

Min

Max Unit

Test Condition

1

C

Input Capacitance

10

15

20

pF

Unmeasured Pins

Returned to Ground

IN

2

Output Capacitance

Bidirectional Capacitance

OUT

I/O

Notes

1. pF = 1 MHz, over specified temperature range.

2. Unmeasured pins returned to Ground.

Miscellaneous

The Gate Count is 6800.

DC Characteristics

Z80C30/Z85C30

Table 5 lists the DC characteristics for the Z80C30/Z85C30 devices.

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

44

Table 5. Z80C30/Z85C30 DC Characteristics

Symbol Parameter

Min

2.2

Typ Max

Unit

V

Condition

1

V

Input High Voltage

Input Low Voltage

Output High Voltage

V

+0.3

IH

CC

-0.3

2.4

0.8

V

IL

V

I

= -1.6 mA

OH1

OH2

OH

V

-

V

= -250 μA

CC

OH

0.8

V

I

Output Low Voltage

Input Leakage

0.4

V

I

= +2.0 mA

OL

±10.0

μA

mA

0.4 V + 2.4 V

IN

IL

I

Output Leakage

0.4 V

+ 2.4 V

OUT

OL

2

V

Supply Current

7

9

4

12 (10 MHz)

V

= 5 V V = 4.8 V = 0

CC IH IL

CC1

CC

15 (16.384 MHz) mA

mA

Crystal Oscillator off

Current for each OSC in

addition to I

3

I

Crystal OSC Current

CCOSC

CC1

Notes

1. VCC = SV t10% unless otherwise specified, over specified temperature range.

2. Typical I

was measured with oscillator off.

CC

(OSC) max is specified due to dependency on external circuit and frequency of oscillation.

3. No I

CC

AC Characteristics

Z85C30 Read/Write Timing Diagrams

Figure 29 through Figure 32 display the Z85C30 Read/Write timing diagrams.

Table 6 lists the Z85C30 Read/Write timing parameters.

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

45

1

PCLK

2

3

4

5

6

A/B, D/C

7

10

9

12

INTACK

CE

11

10

15

14

13

18

16

RD

19

22

20

21

D7–D0

Read

Active

Valid

24

23

17

26

25

27

WR

28

D7–D0

Write

31

30

29

W/REQ

Wait

32

35

W/REQ

Request

33

DTR/REQ

Request

34

36

INT

37

Figure 29. Z85C30 Read/Write Timing Diagram

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

46

PCLK

INTACK

RD

15

10

38

10

14

24

38

23

D7–D0

Valid

Active

26

40

41

42

IEI

IEO

INT

44

43

45

Figure 30. Z85C30 Interrupt Acknowledge Timing Diagram

49b

PCLK

CE

49a

RD or WR

Figure 31. Z85C30 Cycle Timing Diagram

WR

RD

48

47

Figure 32. Z85C30 Reset Timing Diagram

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

47

Table 6. Z85C30 Read/Write Timing

8.5 MHz

10 MHz

16 MHz

No Symbol

Parameter

Min

45

Max

2000

10

Min

40

Max

2000

10

Min Max

1

2

3

4

5

6

TwPCI

TwPCh

TfPC

PCLK Low Width

PCLK High Width

PCLK Fall Time

PCLK Rise Time

PCLK Cycle Time

26

2000

5

45

40

TrPC

10

5

TcPC

118

66

4000

100

50

4000

61

35

4000

TsA(WR)

Address to WR Fall

Setup Time

7

8

9

ThA(WR)

TsA(RD)

ThA(RD)

Address to WR Rise

Hold Time

0

Address to RD Fall

Setup Time

66

0

50

0

35

0

Address to RD Rise

Hold Time

10 TsiA(PC)

11 TsiAi(WR)

12 ThIA(WR)

INTACK to PCLK Rise 20

Setup Time

20

120

0

15

70

0

a

INTACK to WR Fall

Setup Time

140

INTACK to WR Rise

Hold Time

0

1

13 TsiAi(RD)

14 ThIA(RD)

15 ThIA(PC)

INTACK to RD Fall

Setup Time

140

0

120

0

70

0

INTACK to RD Rise

Hold Time

INTACK to PCLK Rise 38

Hold Time

30

0

15

0

16 TsCEI(WR)

17 ThCE(WR)

18 TsCEh(WR)

CE Low to WR Fall

Setup Time

0

CE to WR Rise Hold

Time

0

CE High to WR Fall

Setup Time

58

50

30

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

48

Table 6. Z85C30 Read/Write Timing (continued)

8.5 MHz

10 MHz

16 MHz

No Symbol

Parameter

Min

Max

Min

Max

Min Max

1

19 TsCEI(RD)

CE Low to RD Fall

Setup Time

0

1

20 ThCE(RD)

CE to RD Rise Hold

Time

0

1

21 TsCEh(RD)

CE High to RD Fall

Setup Time

58

50

30

1

22 TwRDI

RD Low Width

145

0

125

0

70

0

23 TdRD(DRA)

24 TdRDr(DR)

25 TdRDI(DR)

26 TdRD(DRz)

27 TdA(DR)

RD Fall to Read Data

Active Delay

RD Rise to Data Not

Valid Delay

0

RD Fall to Read Data

Valid Delay

135

38

120

35

70

30

100

RD Rise to Read Data

Float Delay

Addr to Read Data

Valid Delay

210

160

28 TwWRI

WR Low Width

145

125

0

75

20

29 TdWR(DW)

WR Fall to Write Data

Valid Delay

35

30 ThDW(WR)

Write Data to WR Rise 0

Hold Time

0

b

31 TdWR(W)

WR Fall to Wait Valid

Delay

168

100

50

70

2

32 TdRD(W)

RD Fall to Wait Valid

Delay

168

100

33 TdWRf(REQ) WR Fall to W/REQ Not

Valid Delay

168

120

c

34 TdRDf(REQ) RD Fall to W/REQ Not

168

120

Valid Delay

35a TdWRr(REQ) WR Fall to DTR/REQ

Not Valid

4TcPc

168

4TcPc

100

4TcPc

70

3

35b TdWRr(REQ) WR Fall to DTR/REQ

Not Valid

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

49

Table 6. Z85C30 Read/Write Timing (continued)

8.5 MHz

Min

10 MHz

Min

16 MHz

No Symbol

Parameter

Max

Min Max

36 TdRDrrREQ) RD Rise to DTR/REQ

Not Valid Delay

NA

37 TdPC(INT)

PCLK Fall to INT Valid

Delay

500

320

175

d

38 TdIAi(RD)

INTACK to RD Fall

(Ack) Delay

145

90

50

75

70

50

0

39 TwRDA

RD (Acknowledge)

Width

125

120

80

40 TdRDA(DR)

41 TsiEI(RDA)

42 ThIEI(RDA)

RD Fall (Ack) to Read 135

Data Valid Delay

IEI to RD Fall (Ack)

Setup Time

95

IEI to RD Rise (Ack)

Hold Time

0

43 TdIElrIEO)

44 TdPC(IEO)

IEI to IEO Delay Time

95

80

45

80

PCLK Rise to IEO

Delay

195

175

2

45 TdRDA(INT)

RD Fall to INT Inactive

Delay

480

320

200

46 TdRDrWRQ) RD Rise to WR Fall

Delay for No Reset

15

10

75

47 TdWRQ(RD) WR Rise to RD Fall

Delay for No Reset

15

48 TwRES

WR and RD Low for

Reset

145

100

e

49a Trc

Valid Access Recovery 3.5TcPc

Time

3.5TcPc 3.5TcPc

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

50

Table 6. Z85C30 Read/Write Timing (continued)

8.5 MHz

10 MHz

16 MHz

No Symbol

Parameter

Min

Max

Min

Max

Min Max

f

49b Trci

RD or WR Fall to PC

Fall Setup Time

0

a. Parameter does not apply to Interrupt Acknowledge transactions.

b. Open-drain output, measured with open-drain test load.

c. Parameter applies to enhanced Request mode oniy (WR7’ D4 = 1).

d. Parameter is system dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of

TdPC(IEO) for the highest priority device in the daisy chain. TsiEI(RDA) for the SCC and TdIEI(IEO) for each device

separating them in the daisy chain.

e. Parameter applies only between transactions involving the Z85C30 SL1480, if WR/RD falling edge is

synchronized to PCLK falling edge, then TrC = 3TcPc.

f. This specification is only applicable when Valid Access Recovery Time is less than 35 PCLK.

Figure 33 displays the Z85C30 general timing diagram.

Table 7 lists the Z85C30 general timing characteristics.

Figure 34 displays the Z85C30 system timing.

Table 8 lists the Z85C30 system timing characteristics .

Table 9 provides the Z85C30 Read/Write timing characteristics.

Figure 35 through Figure 37 display the Z80C30 Read/Write timing, interrupt

acknowledge timing, and reset timing, respectively.

Table 10 provides the Z80C30 Read/Write timing characteristics.

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

51

PCLK

1

W/REQ

Request

2

W/REQ

Wait

3

CTS/TRxC,

RTxC

Receive

4

5

6

7

RxD

9

8

SYNC

External

CTS/TRxC,

RTxC

10

Transmit

11

12

TxD

13

CTS/TRxC

Output

14

15

RTxC

16

17

CTS/TRxC

19

18

20

CTS/TRxC

DCD

22

SYNC

Input

22

Figure 33. Z85C30 General Timing Diagram

Table 7. Z85C30 General Timing Table

8.5 MHz

10 MHz

16 MHz

No

1

Symbol

Parameter

Min

Max Min

Max

80

TdPC(REQ)

TdPC(W)

PCLK to W/REQ Valid

PCLK to Wait Inactive

RxC to PCLK Setup Time

250

350

150

250

2

180

a,b

3

TsRXC(PC)

TsRXD(RXCr)

ThRXD(RxCr)

N/A

150

N/A

125

N/A

50

1

4

RxD to RxC Setup Time

0

1

5

RxD to /RXC Hold Time

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

52

Table 7. Z85C30 General Timing Table (continued)

8.5 MHz

10 MHz

16 MHz

No

6

Symbol

Parameter

Min

0

Max Min

Max

1,c

1

TsRXD(RXCf)

ThRXD(RXCf)

TsSY(RXC)

ThSY(RXC)

TsTXC(PC)

TdTXCf(TXD)

TdTxCr(TXD)

TdTXD(TRX)

RxD to /RXC Setup Time

0

1,3

7

RxD to /RXC Hold Time

150 1

-200

5TcPc

N/A

25

50

8

SYNC to RxC Setup Time

-150

5TcPc

N/A

-100

5TcPc

N/A

1

9

SYNC to RxC Hold Time

d,e

10

11

12

13

TxC to PCLK Setup Time

4

TxC to TxD Delay

200

150

140

80

4,3

TxC to TxD Delay

TxD to TRxC Delay

f

14a TwRTXh

14b TwRTXh(E)

15a TwRTXI

15b TwRTXI(E)

16a TcRTX

RTxC High Width

150

50

120

40

80

g

RTxC High Width

15.6

80

6

TRxC Low Width

150

50

120

40

7

RTxC Low Width

15.6

244

31.25

h

i

6,

7

RTxC Cycle Time

488

125

150

488

200

400

100

16b TcRTX(E)

17

18

19

20

21

22

TcRTXX

TwTRXh

TwTRXI

TcTRX

Crystal Osc. Period

1000 100

120

1000 62

180

1000

6

TRxC High Width

6

TRxC Low Width

120

80

6,8

TRxC Cycle Time

400

244

70

TwEXT

TwSY

DCD or CTS Pulse Width

SYNC Pulse Width

120

70

a. RxC is RTxC or TRxC, whichever is supplying the receive clock.

b. Synchronization of RxC to PCLK is eliminated in divide by four operation.

c. Parameter applies only to FM encoding/decoding.

d. TxC is TRxC or /RTxC, whichever is supplying the transmit clock.

e. External PCLK to RTxC or TxC synchronization requirement eliminated for PCLK divide-by-four operation.TRxC

and RTxC rise and fall times are identical to PCLK. Reference timing specs TfPC and TrPC.Tx and Rx input clock

slew rates should be kept to a maximum of 30 nsec. All parameters related to input CLK edges must be referenced at

the point at which the transition begins or ends, whichever is worst case.

f. Parameter applies only for transmitter and receiver; DPLL and Baud Rate Generator timing requirements are

identical to case PCLK requirements.

g. Enhanced Feature — RTxC used as input to internal DPLL only.

h. The maximum receive or transmit data rate is 1/4 PCLK.

i. Both RTxC and SYNC have 30 pF capacitors to ground connections.

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

53

RTxC, TRxC

Receive

W/REQ

Request

1

W/REQ

Wait

2

SYNC

Output

3

INT

4

TRxC, RTxC

Transmit

W/REQ

Request

6

W/REQ

Wait

6

DTR/REQ

Request

7

INT

8

CTS, DCD

SYNC

Input

9

INT

10

Figure 34. Z85C30 System Timing Diagram

Table 8. Z85C30 System Timing Table

8.5 MHz

10 MHz

16 MHz

No Symbol

Parameter

Min

8

Max

Min

8

Max

12

14

7

Min Max

a,b

1

2

3

TdRXC(REQ)

RxC High to W/REQ Valid

12

14

7

8

4

12

14

70

1,2,c

TdRXC(W)

RxC High to Wait Inactive

8

1,2

TdRdXC(SY)

RxC High to SYNC Valid

4

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

54

Table 8. Z85C30 System Timing Table (continued)

8.5 MHz

10 MHz

16 MHz

No Symbol

Parameter

Min

10

5

Max

Min

10

5

Max

16

8

Min Max

1,2,3

4

5

6

7

8

TsRXC(INT)

RxC High to INT Valid

16

8

10 16

2,d

TdTXC(REQ)

TdTXC(W)

TxC Low to W/REQ Valid

5

4

6

2

8

2,3,4

TxC Low to Wait Inactive

5

11

7

5

11

7

11

7

3,4

TdTXC(DRQ)

TdTXC(INT)

TxC Low to DTR/REQ Valid

4

2,3,4

TxC Low to INT Valid

6

10

6

10

6

10

6

2,3

9a TdSY(INT)

9b TdSY(INT)

10 TdEXT(INT)

SYNC to INT Valid

2

2,3,e

SYNC to INT Valid

2

3

2

3

2,3

DCD or CTS to INT Valid

2

6

2

6

a. RxC is RTxC or TRxC, whichever is supplying the receive clock.

b. Units equal to TcPc.

c. Open-drain output, measured with open-drain test load.

d. TxC is TRxC or RTxC whichever is supplying the transmit clock.

e. Units equal to AS.

Table 9. Z85C30 Read/Write Timing

8.5 MHz

10 MHz

16 MHz

No Symbol

Parameter

Min

45

Max Min

Max

2000

5

1

2

3

4

5

6

7

8

9

TwPCI

TwPCh

TfPC

PCLK Low Width

2000 40

2000 26

PCLK High Width

45

2000 40

2000 26

PCLK Fail Time

10

TrPC

PCLK Rise Time

10

5

TcPC

PCLK Cycle Time

118

66

0

4000 100

4000 61

4000

TsA(WR)

ThA(WR)

TsA(RD)

ThA(RD)

Address to WR Fail Setup Time

Address to WR Rise Hold Time

Address to RD Fall Setup Time

Address to RD Rise Hold Time

INTACK to PCLK Rise Setup Time

50

0

35

0

66

0

50

0

35

0

10 TsiA(PC)

20

15

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

55

AS

CS0

CS1

2

4

7

4

6

14

INTACK

7

8

R/W

Read

9

10

R/W

Write

12

DS

12

13

18

20

23

AD7–AD0

Write

16

15

17

AD7–AD0

Read

19

21

22

24

W/REQ

Wait

25

W/REQ

Request

26

DTR/REQ

Request

27

INT

44

PCLK

41

40

43

44

42

Figure 35. Z80C30 Read/Write Timing Diagram

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

56

AS

7

INTACK

8

DS

29

30

20

19

AD7–AD0

31

22

32

33

IEI

IEO

INT

35

34

36

Figure 36. Z80C30 Interrupt Acknowledge Timing Diagram

AS

DS

37

38

35

Figure 37. Z80C30 Reset Timing Diagram

Table 10. Z80C30 Read/Write Timing^a

8 MHz

10 MHz

No

1

Symbol

Parameter

Min

35

15

0

Max

Min

30

10

0

Max

TwAS

AS Low Width

b

2

TdDS(AS)

TsCSO(AS)

ThCSO(AS)

DS Rise to AS Fall Delay

2

3

CS0 to AS Rise Setup Time

2

4

CS0 to AS Rise Hold Time

30

20

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

57

Table 10. Z80C30 Read/Write Timing^a(continued)

8 MHz

10 MHz

No

5

Symbol

Parameter

Min

65

30

10

150

65

0

Max

Min

50

20

10

125

50

0

Max

2

TsCS1(DS)

ThCS1(DS)

TsiA(AS)

CS1 to DS Fall Setup Time

2

6

CS1 to DS Rise Hold Time

7

INTACK to AS Rise Setup Time

INTACK to AS Rise Hold Time

R/W (Read) to DS Fall Setup Time

R/W to DS Rise Hold Time

R/W (Write) to DS Fall Setup Time

AS Rise to DS Fall Delay

8

ThIA(AS)

TsRWR(DS)

ThRW(DS)

TsRWW(DS)

TdAS(DS)

TwDSI

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

0

30

150

4TcPC

10

25

15

0

20

125

4TcPC

10

20

10

0

DS Low Width

c

TrC

Valid Access Recovery Time

2

TsA(AS)

Address to AS Rise Setup Time

2

ThA(AS)

Address to AS Rise Hold Time

TsDW(DS)

ThDW(DS)

TdDS(DA)

TdDSr(DR)

TdDSf(DR)

TdAS(DR)

TdDS(DRz)

TdA(DR)

Write Data to DS Fall Setup Time

Write Data to DS Rise Hold Time

DS Fall to Data Active Delay

0

DS Rise to Read Data Not Valid Delay 0

DS Fall to Read Data Valid Delay

AS Rise to Read Data Valid Delay

0

140

250

40

120

190

35

d

DS Rise to Read Data Float Delay

Address Required Valid to Read Data

Valid Delay

260

210

e

25

26

27

28

29

TdDS(W)

DS Fall to Wait Valid Delay

170

160

TdDSf(REQ)

TdDSr(REQ)

TdAS(INT)

TdAS(DSA)

DS Fall to W/REQ Not Valid Delay

DS Fall to DTR/REQ Not Valid Delay

170

160

4TcPC

500

4TcPC

500

5

AS Rise to INT Valid Delay

AS Rise to DS Fall (Acknowledge)

250

150

225

125

f

Delay

30

TwDSA

DS (Acknowledge) Low Width

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

58

Table 10. Z80C30 Read/Write Timing^a(continued)

8 MHz

Min

10 MHz

Min

No

Symbol

Parameter

Max

31

TdDSA(DR)

DS Fall (Acknowledge) to Read Data

Valid Delay

140

120

32

33

TsiEI(DSA)

ThIEI(DSA)

IEI to DS Fall (Acknowledge) Setup

Time

80

0

80

0

IEI to DS Rise (Acknowledge) Hold

Time

34

35

36

TdIEI(IEO)

TdAS(IEO)

TdDSA(INT)

IEI to IEO Delay

90

g

AS Rise to IEO Delay

200

450

175

450

DS Fall (Acknowledge) to INT Inactive

5

Delay

37

38

39

40

41

42

43

44

TdDS(ASQ)

TdASQ(DS)

TwRES

TwPCI

DS Rise to AS Fall Delay for No Reset 15

AS Rise to DS Fall Delay for No Reset 20

15

h

AS and DS Coincident Low for Reset 150

100

40

PCLK Low Width

PCLK High Width

PCLK Cycle Time

PCLK Rise Time

PCLK Fall Time

50

1000

2000

10

1000

2000

10

TwPCh

TcPC

50

40

125

100

TrPC

TfPC

10

a. Units in nanoseconds (ns) unless otherwise noted.

b. Parameter does not apply to Interrupt Acknowledge transactions.

c. Parameter applies only between transactions involving the SCC.

d. Float delay is defined as the time required for a ±0.5 V change in the output with a maximum DC load and a

minimum AC load.

e. Open-drain output, measured with open-drain test load.

f. Parameter is system dependent. For any Z-SCC in the daisy chain. TdAS(DSA) must be greater than the sum of

TdAS(IEO) for the highest priority device in the daisy chain TsiEI(DSA) for the Z-SCC, and TdIElf(IEO) for each device

separating them in the daisy chain.

g. Parameter applies only to a Z-SCC pulling INT Low at the beginning of the Interrupt Acknowledge transaction.

h. Internal circuitry allows for the reset provided by the ZB to be recognized as a reset by the Z-SCC. All timing

references assume 20 V for a logic “1” and 08 V for a logic “0”.

Figure 38 displays Z80C30 general timing and Table 11 lists the associated general timing

characteristics. Figure 39 displays the Z80C30 system timing with the associated

parameters listed in Table 12.

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

59

PCLK

1

W/REQ

Request

2

W/REQ

Wait

3

RTxC, TRxC

Receive

4

5

7

6

RxD

8

9

SYNC

External

10

TRxC, RTxC

Transmit

11

12

TxD

13

TRxC

Output

14

15

RTxC

16

17

TRxC

18

19

20

CTS, DCD

22

SYNC

Input

22

Figure 38. Z80C30 General Timing Diagram

Table 11. Z80C30 General Timing^a

8 MHz

Min

10 MHz

Min

No

1

Symbol

Parameter

Max

250

350

NA

Max

200

300

NA

TdPC(REQ)

TsPC(W)

PCLK Low to W/REQ Valid

PCLK Low to Wait Inactive

RxC High to PCLK High Setup Time

2

b,c

3

TsRXC(PC)

NA

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

60

Table 11. Z80C30 General Timing^a(continued)

8 MHz

10 MHz

No

4

Symbol

Parameter

Min

0

Max

Min

0

Max

TsRXD(RXCr)

ThRXD(RxCr)

TsRXD(RXCf)

ThRXD(RXCf)

TsSY(RXC)

ThSY(RXC)

TsTXC(PC)

TdTXCf(TXD)

TdTxCr(TXD)

TdTXD(TRX)

TwRTXh

RxD to RxC High Setup Time

2

5

RxD to RxC High Hold Time

150

0

125

0

2,d

6

RxD to RxC Low Setup Time

2,4

7

RxD to RxC Low Hold Time

150

-200

5TcPc

NA

125

-150

5TcPc

NA

2

8

SYNC to RxC High Setup Time

2

9

SYNC to RxC High Hold Time

e,3

10

11

12

13

14

15

TxC Low to PCLK High Setup Time

5

TxC Low to TxD Delay

190

200

150

140

5,4

TxC High to TxD Delay

TxD to TRxC Delay

f

RTxC High Width

130

472

59

120

400

50

6

TwRTXI

TRxC Low Width

6,g

16a TcRTX

RTxC Cycle Time

7,h

16b TxRx (DPLL)

DPLL Cycle Time Min

i

17

18

19

20

21

22

TcRTXX

TwTRXh

TwTRXI

TcTRX

Crystal Osc. Period

118

130

472

200

1000

100

120

400

120

1000

6

TRxC High Width

6

TRxC Low Width

6,7

TRxC Cycle Time

TwEXT

TwSY

DCD or CTS Pulse Width

SYNC Pulse Width

a. Units in nanoseconds (ns) otherwise noted.

b. RxC is RTxC or (TRxC, whichever is supplying the receive clock.

c. Synchronization of RxC to PCLK is eliminated in divide by four operation.

d. Parameter applies only to FM encoding/decoding.

e. TxC is TRxC or RTxC, whichever is supplying the transmit clock.

f. Parameter applies only for transmitter and receiver; DPLL and Baud Rate Generator timing requirements are

identical to case PCLK requirements.

g. The maximum receive or transmit data rate is 1/4 PCLK.

h. Applies to DPLL clock source oniy Maximum data rate of 1/4 PCLK still applies DPLL clock should have a 50% duty

cycle.

i. Both RTxC and SYNC have 30 pf capacitors to ground connected to them.

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

61

PCLK

1

W/REQ

Request

2

W/REQ

Wait

3

RTxC, TRxC

Receive

4

7

6

5

RxD

9

8

SYNC

External

10

TRxC, RTxC

Transmit

11

12

TxD

10

TRxC

Output

14

15

RTxC

18

17

TRxC

18

19

20

CTS, DCD

21

22

21

22

SYNC

Input

Figure 39. Z80C30 System Timing Diagram

Table 12. Z80C30 System Timing

8 MHz

10 MHz

No

1

Symbol

Parameter

Min

8

Max

12

14

7

Min

8

Max

12

14

7

a,b

TdRXC(REQ)

TdRXC(W)

TdRdXC(SY)

TdRXC(INT)

RxC High to W/REQ Valid

RxC High to Wait Inactive

1,2,c

2

8

1,2

3

RxC High to SYNC Valid

4

1,2,3

4

RxC High to INT Valid

8

12

8

12

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

62

Table 12. Z80C30 System Timing (continued)

8 MHz

10 MHz

No

Symbol

Parameter

Min

2

Max

3

Min

2

Max

3

d,2

Note

e,2

5

6

7

8

TdTXC(REQ)

TdTXC(W)

TxC Low to W/REQ Valid

5

8

5

8

1,2,3

TxC Low to Wait Inactive

5

11

7

5

11

7

2,3

TdTXC(DRQ)

TdTXC(INT)

TxC Low to DTR/REQ Valid

4

1,2

TxC Low to INT Valid

4

6

4

6

2,4

Note

2

3

2

3

2,3

9a

9b

10

TdSY(INT)

TdEXT(INT)

SYNC to INT Valid

2

6

2

6

2,3,4

SYNC to INT Valid

2

3

2

3

2,3,4

Note

2

3

2

3

a. RxC is RTxC or TRxC whichever is supplying the receive clock.

b. Units equal to TcPc.

c. Open-drain output, measured with open-drain test load.

d. Units equal to AS.

e. TxC is TRxC or RTxC, whichever is supplying the transmit clock.

PS011705-0608

Electrical Characteristics

CMOS SCC Serial Communications Controller

Product Specification

63

Packaging

Figure 40 displays the 40-pin DIP package available for Z80C30 and Z85C30 devices.

Figure 40. 40-Pin DIP Package Diagram

PS011705-0608

Packaging

CMOS SCC Serial Communications Controller

Product Specification

64

Figure 41 displays the 44-pin Plastic Leaded Chip Carriers (PLCC) package diagram

available for Z80C30 and Z85C30 devices.

Figure 41. 44-Pin PLCC Package Diagram

PS011705-0608

Packaging

CMOS SCC Serial Communications Controller

Product Specification

65

Ordering Information

Table 13 provides ordering information for the Z80C30 and the Z85C30 devices.

Table 13. Z80C30/Z85C30 Ordering Information

8 MHz

10 MHz

16 MHz

Z80C3008PSC

Z80C3008VSC

Z85C3008PSC/PEC

Z85C3008VSCNEC

Z80C3010PSC

Z80C3010VSC

Z85C3010PSC/PEC

Z85C3010VSCNEC

Z85C3016PSC

Z85C3016VSC

For complete details on Z80C30 and Z85C30 devices, development tools and

downloadable software, visit www.zilog.com.

PS011705-0608

Packaging

CMOS SCC Serial Communications Controller

Product Specification

66

Part Number Suffix Designations

Zilog^®part numbers consist of a number of components, as indicated in the following

example:

Example

Part number Z80C3016PSG is a Z80C30, 16 MHz, PLCC, 0 ºC to +70 ºC, Lead Free

Z

80C30 16

P

S

G

Environmental Flow

G = Lead Free

Temperature Range

S = 0 ºC to +70 ºC

E = Extended, –40 °C to +100 °C

Package

P = Plastic DIP

V = Plastic Leaded Chip Carrier

D = Ceramic DIP

Speed

8 = 8 MHz

10 = 10 MHz

16 = 16 MHz

Product Number

®

Zilog Prefix

PS011705-0608

Packaging

CMOS SCC Serial Communications Controller

Product Specification

67

Customer Support

For answers to technical questions about the product, documentation, or any other issues

with Zilog’s offerings, please visit Zilog’s Knowledge Base at

http://www.zilog.com/kb.

For any comments, detail technical questions, or reporting problems, please visit Zilog’s

Technical Support at http://support.zilog.com.

PS011705-0608

Customer Support


型号：	Z80C3008PSC
厂家：	IXYS CORPORATION
描述：	Multi Protocol Controller, 2 Channel(s), 0.5125MBps, CMOS, PDIP40, PLASTIC, DIP-40 通信时钟数据传输先进先出芯片光电二极管外围集成电路
文件：	总71页 (文件大小：1137K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Z80C3008PSC [IXYS]

相关型号：

Z80C3008PSCXXXX

Z80C3008PSG

Z80C3008VSC

Z80C3008VSG

Z80C3008VSG

Z80C3010DSC

Z80C3010DSCXXXX

Z80C3010PSC

Z80C3010PSC

Z80C3010PSCXXXX

Z80C3010PSG

Z80C3010VSC