Z86E133PZ016SG [IXYS]
Microcontroller, 8-Bit, OTPROM, 16MHz, CMOS, PDIP28, DIP-28;型号: | Z86E133PZ016SG |
厂家: | IXYS CORPORATION |
描述: | Microcontroller, 8-Bit, OTPROM, 16MHz, CMOS, PDIP28, DIP-28 可编程只读存储器 时钟 微控制器 光电二极管 外围集成电路 |
文件: | 总150页 (文件大小:2695K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
The MUZE Family of
Z8 Microcontrollers
MAXIMUM MEMORY WITH UART
AND ZILOG EXPANDABLE EPROM
Product Specification
PRELIMINARY
PS004005-1100
ZiLOG Worldwide Headquarters • 910 E. Hamilton Avenue • Campbell, CA 95008
Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com
©2000 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applica-
tions, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC.
DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF
THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG
ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT
RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY
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information, devices, or technology as critical components of life support systems is not authorized. No
licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
P R E L I M I N A R Y
PS004005-1100
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
iii
Table of Contents
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
MUZE Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Expanded Register File, Bank 0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
ASCI Registers—Expanded Register File, Bank Ah . . . . . . . . . . . . . . . . . . 61
Expanded Register File, Bank Fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
One-Time Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Universal Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . . . 105
ASCI Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
ASCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
In-Circuit Serial Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
In-Circuit Serial Programming Block Diagram . . . . . . . . . . . . . . . . . . . . . . 125
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Part Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Document Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Document Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Change Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
MUZE Product Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Customer Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Product Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Return Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Problem Description or Suggestion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
PS004005-1100
P R E L I M I N A R Y
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
iv
List of Figures
Figure 1. MUZE Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. 20-Pin DIP/SOIC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. 20-Pin DIP/SOIC Pin Configuration—ICSP Mode . . . . . . . . . . . . . . . 6
Figure 4. 28-Pin DIP/SOIC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. 28-Pin DIP/SOIC Pin Configuration—ICSP Mode . . . . . . . . . . . . . . . 9
Figure 6. 40-Pin DIP/SOIC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. 40-Pin DIP/SOIC Pin Configuration—ICSP Mode . . . . . . . . . . . . . . 13
Figure 8. 44-Pin PQFP Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. 44-Pin PQFP Pin Configuration—ICSP Mode . . . . . . . . . . . . . . . . . 17
Figure 10. Port 0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11. Port 1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Port 2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. Port 3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 14. Port 3 Configuration—PCON Register Detail . . . . . . . . . . . . . . . . . 27
Figure 15. Program Memory Map for the MUZE Family . . . . . . . . . . . . . . . . . . 30
Figure 16. Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17. Register Pointer—Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 18. Expanded Register File Architecture . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 19. Counter/Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 20. Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 21. Stop-Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 22. Resets and Watch-Dog Timer Example . . . . . . . . . . . . . . . . . . . . . 48
Figure 23. Typical Low-Voltage Protection vs. Temperature . . . . . . . . . . . . . . 49
Figure 24. Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 25. External I/O or Memory Read and Write Timing . . . . . . . . . . . . . . . 86
Figure 26. Additional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 27. Input Handshake Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 28. Output Handshake Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 29. Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 30. Receive Data Register FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 31. FIFO Overrun Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 32. Clear FIFO Overrun Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 33. ASCI Interface Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 34. ASCI Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
PS004005-1100
P R E L I M I N A R Y
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
v
Figure 35. Multiprocessor Mode Serial Data Format . . . . . . . . . . . . . . . . . . . 115
Figure 36. ICSP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 37. ICSP Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 38. 20-Pin DIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 39. 20-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 40. 28-Pin DIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 41. 28-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 42. 40-Pin DIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 43. 44-Pin PQFP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 132
PS004005-1100
P R E L I M I N A R Y
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
vi
List of Tables
Table 1. MUZE Family Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. 20-Pin DIP/SOIC Pin Identification . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. 20-Pin DIP/SOIC Pin Identification—ICSP Mode . . . . . . . . . . . . . . . 6
Table 4. 28-Pin DIP/SOIC Pin Identification . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. 28-Pin DIP/SOIC Pin Identification—ICSP Mode . . . . . . . . . . . . . . . 9
Table 6. 40-Pin DIP/SOIC Pin Identification . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. 40-Pin DIP/SOIC Pin Identification—ICSP Mode . . . . . . . . . . . . . . 13
Table 8. 44-Pin PQFP Pin Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 9. 44-Pin PQFP Pin Identification—ICSP Mode . . . . . . . . . . . . . . . . . 17
Table 10. Port 3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. Register Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 12. Interrupt Types, Sources, and Vectors . . . . . . . . . . . . . . . . . . . . . . 36
Table 13. IRQ Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 14. Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 15. Stop-Mode Recovery Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 16. Stop-Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 17. Stop-Mode Recovery Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 18. Stop-Mode Recovery Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 19. Watch-Dog Timer Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 20. WDT Time Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 21. Maximum (V ) Conditions: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
LV
Table 22. Expanded Register File Registers—Reset States . . . . . . . . . . . . . . 50
Table 23. Timer Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 24. Counter/Timer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 25. Prescaler 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 26. Counter/Timer 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 27. Prescaler 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 28. Port 2 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 29. Port 3 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 30. Ports 0 and 1 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 31. Interrupt Priority Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 32. Interrupt Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 33. Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 34. Flags Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PS004005-1100
P R E L I M I N A R Y
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
vii
Table 35. Register Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 36. Stack Pointer High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 37. Stack Pointer Low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 38. Expanded Register File Registers—Reset States 61
Table 39. Transmit Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 40. Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 41. Control Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 42. Control Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 43. Extension Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 44. Time Constant Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 45. Time Constant Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 46. Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 47. Expanded Register File Registers—Reset States 68
Table 48. Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 49. Verify Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 50. Stop-Mode Recovery Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 51. Stop-Mode Recovery Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 52. Watch-Dog Timer Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 53. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 54. DC Electrical Characteristics at Standard Temperature . . . . . . . . . 76
Table 55. DC Electrical Characteristics at Extended Temperature . . . . . . . . . 81
Table 56. Memory Read and Write Timing—Standard Temperature . . . . . . . 87
Table 57. Memory Read and Write Timing—Extended Temperature . . . . . . . 89
Table 58. Additional Timing at Standard Temperature . . . . . . . . . . . . . . . . . . 92
Table 59. Additional Timing at Extended Temperature . . . . . . . . . . . . . . . . . . 95
Table 60. Handshake Timing1 at Standard Temperature . . . . . . . . . . . . . . . . 98
Table 61. Handshake Timing1 at Extended Temperature . . . . . . . . . . . . . . . . 99
Table 62. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 63. Option Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 64. ASCI Interrupt Conditions and Sources . . . . . . . . . . . . . . . . . . . . . 110
Table 65. Transmit Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 66. Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 67. Control Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 68. ASCI Data Format Mode Control Bits . . . . . . . . . . . . . . . . . . . . . . 113
Table 69. Control Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 70. Clock Source and Speed Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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P R E L I M I N A R Y
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
viii
Table 71. Extension Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 72. Time Constant Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 73. Time Constant Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 74. Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 75. Baud Rate List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 76. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
PS004005-1100
P R E L I M I N A R Y
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
1
Architectural Overview
®
ZiLOG’s large Z8 family of 8-bit microcontrollers now includes the MUZE product
line, featuring 4 KB to 64 KB of In-Circuit Serially-Programmable (ICSP) OTP
memory, an industry-standard Universal Asynchronous Receiver/Transmitter
(UART), enhanced wake-up circuitry, programmable Watch-Dog Timers (WDT),
and low-noise/EMI options. Each of the new enhancements to the Z8 offers a
more efficient, cost-effective design and provides the user with increased design
flexibility over the standard Z8 microcontroller core. The low-power-consumption
OTP microcontroller offers fast execution, efficient use of memory, sophisticated
interrupts, input/output bit manipulation capabilities, and easy hardware/software
system expansion.
The MUZE family features an Expanded Register File (ERF) to allow access to
register-mapped peripheral and I/O circuits. Four basic address spaces are avail-
able to support this wide range of configurations: Program Memory, Register File,
Data Memory, and ERF.The Register File is composed of 236 bytes contained
within one general-purpose register (GPR), 4 I/O port registers, 15 control regis-
ters, and status registers. The ERF consists of 12 control registers.
For applications demanding powerful I/O capabilities, the Z86E122/E123/E124/
E125/E126 offers 16 pins, the Z86E132/E133/E134/E135/E136 offers 24 pins,
and the Z86E142/E143/144/E145/E146 offers 32 pins dedicated to input and out-
put.These lines are configurable under software control to provide timing, status
signals, parallel I/O with or without handshake, and address/data bus for interfac-
ing external memory.
The MUZE family operates at 16MHz with a voltage range of 4.5 to 5.5V and
DC
up to 12MHz with a voltage range of 3.0 to 5.5V
.
DC
To unburden the system from coping with real-time tasks such as counting/timing
and data communication, the Z8 offers two on-chip counter/timers with a large
number of user-selectable modes and a hardware UART.
With ROM/ROMless selectivity, the Z86E142/E143/E144/E145/E146 provides
®
both external memory and ICSP, which enables this Z8 MCU to be used in high-
volume applications, or where code flexibility is required.
Note:
All signals with an overline are active Low. For example, B/W, for which
WORD is active Low, and B/W, for which BYTE is active Low.
Power connections follow these conventional descriptions:
Connection
Power
Circuit
Device
V
V
CC
DD
SS
Ground
GND
V
PS004005-1100
P R E L I M I N A R Y
Architectural Overview
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
2
MUZE Features
Table 1. MUZE Family Features
Speed 4.5V to 5.5V
(MHz—Standard
Speed 3.0V to 5.5V
(MHz—Standard
OTP
(KB)
RAM*
(Bytes)
Device
and Extended Temperature)
Temperature Only)
Z86E122
Z86E123
Z86E124
Z86E125
Z86E126
Z86E132
Z86E133
Z86E134
Z86E135
Z86E136
Z86E142
Z86E143
Z86E144
Z86E145
Z86E146
4
8
236
236
236
236
236
236
236
236
236
236
236
236
236
236
236
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
16
32
64
4
8
16
32
64
4
8
16
32
64
Note: *General-Purpose.
•
•
•
•
•
•
•
•
4 KB to 64 KB OTP Memory
Full-Duplex UART Asynchronous Serial Communications Interface (ASCI)
Dedicated 16-Bit Baud Rate Generator (BRG)
In-Circuit Serial Programming Interface
20-Pin DIP and 20-Pin SOIC (E122, E123, E124, E125, E126)
28-Pin DIP and 28-Pin SOIC (E132, E133, E134, E135, E136)
40-Pin DIP and 44-Pin PQFP Packages (E142, E143, E144, E145, E146)
3.0- to 5.5-Volt Operating Range
PS004005-1100
P R E L I M I N A R Y
Architectural Overview
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
3
•
Operating Temperature Ranges:
Standard: 0ºC to 70ºC
Extended: –40ºC to +105ºC
Note:
The extended temperature range is only for the 4.5- to 5.5-volt part, at 16-
MHz max. operation.
•
•
Expanded Register File (ERF)
16 Input/Output Lines (E122, E123, E124, E125, E126)
24 Input/Output Lines (E132, E133, E134, E135, E136)
32 Input/Output Lines (E142, E143, E144, E145, E146)
•
•
•
Vectored, Prioritized Interrupts with Programmable Polarity
Two Analog Comparators
Two Programmable 8-Bit Counter/Timers, each with a 6-Bit Programmable
Prescaler
•
•
•
VBO/Power-On Reset (POR)
Clock-Free Watch-Dog Timer (WDT) Reset
On-Chip Oscillator that accepts a Crystal, Ceramic Resonator, LC, RC, or
External Clock
•
•
RAM and EPROM Protect
Optional 32-kHz Oscillator
PS004005-1100
P R E L I M I N A R Y
Architectural Overview
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
4
Functional Block Diagram
Figure 1. MUZE Functional Block Diagram
(E142/E143/E144/
E145/E146 Only)
Output Input
VCC
GND
XOUT
XIN
AS DS R/W RESET
Machine
Port 3
Timing & Inst.
Control
Counter/
Timers (2)
RESET
WDT, POR
ALU
Interrupt
Control
In-Circuit
Serial Prog
FLAG
Two Analog
Comparators
Register
Pointer
Program
Memory
Full-Duplex
UART
Register File
Program
Counter
16-Bit Baud
Rate Generator
Port 2
Port 0
Port 1
8
4
4
I/O
Address or I/O
(Nibble Programmable)
(Bit Programmable)
Address/Data or I/O
(Byte Programmable)
(E142/E143/E144/E145/E416 Only)
PS004005-1100
P R E L I M I N A R Y
Architectural Overview
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
5
Pin Description
Figure 2. 20-Pin DIP/SOIC Pin Configuration
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
P24
P25
P26
P27
P23
P22
P21
P20
GND
P02
P01
P00
P30
P37
Z86E122
Z86E123
Z86E124
Z86E125
Z86E126
V
CC
X
OUT
X
IN
P31
P32
P33
9
10
Table 2. 20-Pin DIP/SOIC Pin Identification
Pin #
1–4
5
Symbol
Function
Direction
P24–P27
Port 2, Bits 4,5,6,7
Power Supply
Crystal Oscillator
Crystal Oscillator
Port 3, Bits 1,2,3
Port 3, Bit 7
Input/Output
V
X
X
CC
OUT
IN
6
Output
7
Input
8–10
11
P31–P33
P37
Fixed Input
Fixed Output
Fixed Input
Input/Output
12
P30
Port 3, Bit 0
13–15
16
P00–P02
GND
Port 0, Bits 0,1,2
Ground
17–20
P20–P23
Port 2, Bits 0,1,2,3
Input/Output
PS004005-1100
P R E L I M I N A R Y
Pin Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
6
Figure 3. 20-Pin DIP/SOIC Pin Configuration—ICSP Mode
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
NC
NC
NC
NC
NC
NC
NC
NC
Z86E122
Z86E123
Z86E124
Z86E125
Z86E126
V
GND
ICSP_RESET
SDIO
SCK
NC
CC
NC
NC
NC
NC
NC
9
10
NC
Table 3. 20-Pin DIP/SOIC Pin Identification—ICSP Mode
Pin #
1–4
5
Symbol
Function
Direction
NC
No Connection
Power Supply
No Connection
Serial ICSP Clock
Serial Data
V
CC
6–12
13
NC
SCK
Input
14
SDIO
ICSP_RESET
GND
Input/Output
Input
15
ICSP Reset
Ground
16
17–20
NC
No Connection
PS004005-1100
P R E L I M I N A R Y
Pin Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
7
Figure 4. 28-Pin DIP/SOIC Pin Configuration
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
P25
P26
P27
P04
P05
P06
P07
P24
P23
P22
P21
P20
P03
GND
P02
P01
P00
P30
P36
P37
P35
Z86E132
Z86E133
Z86E134
Z86E135
Z86E136
V
CC
X
9
OUT
10
11
12
13
14
X
IN
P31
P32
P33
P34
Table 4. 28-Pin DIP/SOIC Pin Identification
Pin #
1–3
2
Symbol
P25
Function
Direction
Port 2, Bit 5
Port 2, Bit 6
Port 2, Bit 7
Port 0, Bit 4
Port 0, Bit 5
Port 0, Bit 6
Port 0, Bit 7
Power Supply
Crystal Oscillator
Crystal Oscillator
Port 3, Bit 1
Port 3, Bit 2
Port 3, Bit 3
Port 3, Bit 4
Port 3, Bit 5
Port 3, Bit 7
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
P26
3
P27
4
P04
5
P05
6
P06
7
P07
8
V
X
X
CC
OUT
IN
9
Output
10
11
12
13
14
15
16
Input
P31
P32
P33
P34
P35
P37
Fixed Input
Fixed Input
Fixed Input
Fixed Output
Fixed Output
Fixed Output
PS004005-1100
P R E L I M I N A R Y
Pin Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
8
Table 4. 28-Pin DIP/SOIC Pin Identification (Continued)
Pin #
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
P36
P30
P00
P01
P02
GND
P03
P20
P21
P22
P33
P24
Function
Direction
Port 3, Bit 6
Port 3, Bit 0
Port 0, Bit 0
Port 0, Bit 0
Port 0, Bit 2
Ground
Fixed Output
Fixed Input
Input/Output
Input/Output
Input/Output
Port 0, Bit 3
Port 2, Bit 0
Port 2, Bit 1
Port 2, Bit 2
Port 2, Bit 3
Port 2, Bit 4
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
PS004005-1100
P R E L I M I N A R Y
Pin Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
9
Figure 5. 28-Pin DIP/SOIC Pin Configuration—ICSP Mode
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
Z86E132
Z86E133
Z86E134
Z86E135
Z86E136
GND
ICSP_RESET
SDIO
SCK
NC
NC
NC
NC
V
CC
NC
NC
NC
NC
NC
NC
9
10
11
12
13
14
Table 5. 28-Pin DIP/SOIC Pin Identification—ICSP Mode
Pin #
1
Symbol
NC
Function
Direction
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
Power Supply
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
2
NC
3
NC
4
NC
5
NC
6
NC
7
NC
8
V
CC
9
NC
NC
NC
NC
NC
NC
NC
NC
NC
10
11
12
13
14
15
16
17
PS004005-1100
P R E L I M I N A R Y
Pin Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
10
Table 5. 28-Pin DIP/SOIC Pin Identification—ICSP Mode (Continued)
Pin #
18
19
20
21
22
23
24
25
26
27
28
Symbol
NC
Function
Direction
No Connection
Serial ICSP Clock
Serial Data
SCK
SDIO
ICSP_RESET
GND
NC
Input
Input/Output
Input
ICSP Reset
Ground
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
NC
NC
NC
NC
NC
PS004005-1100
P R E L I M I N A R Y
Pin Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
11
Figure 6. 40-Pin DIP/SOIC Pin Configuration
R/W
P25
P26
P27
P04
P05
P06
P14
P15
P07
DS
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
P24
P23
P22
P21
P20
P03
P13
P12
GND
P02
P11
P10
P01
P00
P30
P36
P37
P35
RESET
Z86E142
Z86E143
Z86E144
Z86E145
Z86E146
9
10
11
12
13
14
15
16
17
18
19
20
V
CC
P16
P17
X
OUT
X
IN
P31
P32
P33
P34
AS
Table 6. 40-Pin DIP/SOIC Pin Identification
Pin #
1
Symbol
R/W
P25
P26
P27
P04
P05
P06
P14
P15
P07
Function
Direction
READ/WRITE
Port 2, Bit 5
Port 2, Bit 6
Port 2, Bit 7
Port 0, Bit 4
Port 0, Bit 5
Port 0, Bit 6
Port 1, Bit 4
Port 1, Bit 5
Port 0, Bit 7
Power Supply
Port 1, Bit 6
Port 1, Bit 7
Output
2
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
3
4
5
6
7
8
9
10
11
12
13
V
CC
P16
P17
Input/Output
Input/Output
PS004005-1100
P R E L I M I N A R Y
Pin Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
12
Table 6. 40-Pin DIP/SOIC Pin Identification (Continued)
Pin #
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Symbol
Function
Direction
Output
X
X
Crystal Oscillator
Crystal Oscillator
Port 3, Bit 1
Port 3, Bit 2
Port 3, Bit 3
Port 3, Bit 4
Address Strobe
Reset
OUT
IN
Input
P31
P32
P33
P34
AS
Input
Input
Input
Output
Output
RESET
P35
P37
P36
P30
P00
P01
P10
P11
P02
GND
P12
P13
P03
P20
P21
P22
P23
P24
DS
Input
Port 3, Bit 5
Port 3, Bit 7
Port 3, Bit 6
Port 3, Bit 0
Port 0, Bit 0
Port 0, Bit 1
Port 1, Bit 0
Port 1, Bit 1
Port 0, Bit 2
Ground
Output
Output
Output
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Port 1, Bit 2
Port 1, Bit 3
Port 0, Bit 3
Port 2, Bit 0
Port 2, Bit 1
Port 2, Bit 2
Port 2, Bit 3
Port 2, Bit 4
Data Strobe
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
PS004005-1100
P R E L I M I N A R Y
Pin Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
13
Figure 7. 40-Pin DIP/SOIC Pin Configuration—ICSP Mode
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Z86E142
Z86E143
Z86E144
Z86E145
Z86E146
9
NC
10
11
12
13
14
15
16
17
18
19
20
GND
ICSP_RESET
NC
V
CC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SDIO
SCK
NC
NC
NC
NC
RESET
Table 7. 40-Pin DIP/SOIC Pin Identification—ICSP Mode
Pin #
1
Symbol
NC
Function
Direction
No connection
No connection
No connection
No connection
No connection
No connection
No connection
No connection
No connection
No connection
Power Supply
No connection
No connection
2
NC
3
NC
4
NC
5
NC
6
NC
7
NC
8
NC
9
NC
10
11
12
13
NC
V
CC
NC
NC
PS004005-1100
P R E L I M I N A R Y
Pin Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
14
Table 7. 40-Pin DIP/SOIC Pin Identification—ICSP Mode (Continued)
Pin #
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Symbol
NC
Function
Direction
No connection
No connection
No connection
No connection
No connection
No connection
No connection
Reset
NC
NC
NC
NC
NC
NC
RESET
NC
Input
No connection
No connection
No connection
No connection
Serial ICSP Clock
Serial Data
NC
NC
NC
SCK
SDIO
NC
Input
Input/Output
No Connection
No Connection
ICSP Reset
NC
ICSP_RESET
GND
NC
Input
Ground
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
NC
NC
NC
NC
NC
NC
NC
NC
PS004005-1100
P R E L I M I N A R Y
Pin Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
15
Figure 8. 44-Pin PQFP Pin Configuration
3332 3130 2928 27262524 23
P21
P22
P23
P24
DS
P30
P36
P37
P35
RESET
R/RL
AS
P34
P33
P32
P31
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
Z86E142
Z86E143
Z86E144
Z86E145
Z86E146
NC
R/W
P25
P26
P27
P04
1 2 3 4 5 6 7 8 9 10 11
Table 8. 44-Pin PQFP Pin Identification
Pin #
1
Symbol
P05
Function
Direction
Port 0, Bit 5
Port 0, Bit 5
Port 1, Bit 4
Port 1, Bit 5
Port 0, Bit 7
Power Supply
Power Supply
Port 1 Bit 6
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
2
P06
3
P14
4
P15
5
P07
6
V
V
CC
7
CC
8
P16
P17
Input/Output
Input/Output
Output
Input
9
Port 1 Bit 7
10
11
12
13
14
X
X
Crystal Oscillator
Crystal Oscillator
Port 3, Bit 1
Port 3, Bit 2
Port 3, Bit 3
OUT
IN
P31
P32
P33
Input
Input
Input
PS004005-1100
P R E L I M I N A R Y
Pin Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
16
Table 8. 44-Pin PQFP Pin Identification (Continued)
Pin #
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Symbol
P34
AS
Function
Direction
Output
Port 3, Bit 4
Address Strobe
ROM/ROMless Control
Reset
Output
R/RL
RESET
P35
P37
P36
P30
P00
P01
P10
P11
P02
GND
GND
P12
P13
P03
P20
P21
P22
P23
P24
DS
Input
Input
Port 3, Bit 5
Port 3, Bit 7
Port 3, Bit 6
Port 3, Bit 0
Port 0, Bit 0
Port 0, Bit 0
Port 1, Bit 0
Port 1, Bit 1
Port 0, Bit 2
Ground
Output
Output
Output
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Ground
Port 1, Bit 2
Port 1, Bit 3
Port 0, Bit 3
Port 2, Bit 0
Port 2, Bit 1
Port 2, Bit 2
Port 2, Bit 3
Port 2, Bit 4
Data Strobe
Not Connected
READ/WRITE
Port 2, Bit 5
Port 2, Bit 6
Port 2, Bit 7
Port 0, Bit 4
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
NC
R/W
P25
P26
P27
P04
Output
Input/Output
Input/Output
Input/Output
Input/Output
PS004005-1100
P R E L I M I N A R Y
Pin Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
17
Figure 9. 44-Pin PQFP Pin Configuration—ICSP Mode
3332 3130 2928 27262524 23
34
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RESET
NC
NC
NC
NC
22
21
20
19
18
17
16
15
14
13
12
35
36
37
38
39
40
41
42
43
44
Z86E142
Z86E143
Z86E144
Z86E145
Z86E146
NC
NC
1 2 3 4 5 6 7 8 9 10 11
Table 9. 44-Pin PQFP Pin Identification—ICSP Mode
Pin #
1
Symbol
NC
Function
Direction
No Connection
No Connection
No Connection
No Connection
No Connection
Power Supply
Power Supply
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
2
NC
3
NC
4
NC
5
NC
6
V
V
CC
CC
7
8
NC
NC
NC
NC
NC
NC
9
10
11
12
13
PS004005-1100
P R E L I M I N A R Y
Pin Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
18
Table 9. 44-Pin PQFP Pin Identification—ICSP Mode (Continued)
Pin #
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Symbol
NC
Function
Direction
No Connection
No Connection
No Connection
No Connection
Reset
NC
NC
NC
RESET
NC
Input
No Connection
No Connection
No Connection
No Connection
Serial Clock
NC
NC
NC
SCK
SDIO
NC
Input
Serial Data
Input/Output
No Connection
No Connection
NC
ICSP_RESET Programming Mode
Input
GND
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Ground
Ground
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
PS004005-1100
P R E L I M I N A R Y
Pin Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
19
Table 9. 44-Pin PQFP Pin Identification—ICSP Mode (Continued)
Pin #
42
Symbol
NC
Function
Direction
No Connection
No Connection
No Connection
43
NC
44
NC
PS004005-1100
P R E L I M I N A R Y
Pin Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
20
Pin Functions
The following pages describe the function of each available MUZE family pin.
R/RL (input). The ROM/ROMless pin, when connected to GND, disables the inter-
nal ROM and forces the device to function as a ROMless Z8. (Available for
devices in the 44-pin PQFP package only.)
Notes:
When left unconnected or pulled High to V , the device functions
CC
normally as a Z8 ROM version. When using the device in ROM mode in a
high-EMI (noisy) environment, the ROMless pins must be connected
directly to V
.
CC
DS (output, active Low). The Data Strobe is activated one time for each external
memory transfer. For a READ operation, data must be available prior to the trail-
ing edge of DS. For WRITE operations, the falling edge of DS indicates that out-
put data is valid. (Not available for devices in the 28-pin package.)
AS (output, active Low). The Address Strobe is pulsed one time at the beginning
of each machine cycle for external memory transfer. Address output is from Port
0/Port 1 for all external programs. Memory address transfers are valid at the trail-
ing edge of AS. Under program control, AS is placed in the high-impedance state
along with Ports 0 and 1, Data Strobe, and READ/WRITE. (Not available for
devices in the 28-pin package.)
X
Crystal Input. This pin connects a parallel-resonant crystal, ceramic resonator,
IN
LC, or RC network, or an external single-phase clock to the on-chip oscillator
input.
X
Crystal Output. This pin connects a parallel-resonant crystal, ceramic reso-
OUT
nant, LC, or RC network to the on-chip oscillator output.
R/W (output, WRITE Low). The READ/WRITE signal is High when the Z8 reads
from external program or data memory. The signal is Low when the Z8 writes to
external data memory. (Not available for devices in the 28-pin package.)
Port 0 (P00–P07). Port 0 is an 8-bit, bidirectional, CMOS-compatible port. These
eight I/O lines are configured under software control as a nibble I/O port (P03–
P00 input/output and P07–P04 input/output), or as an address port for interfacing
external memory.The input buffers are Schmitt-triggered and nibble-programmed
as outputs and can be globally programmed as either push-pull or open-drain.
Low-EMI output buffers are globally programmed by the software. Port 0 may be
placed under handshake control. In this configuration, Port 3, lines P32 and P35
are used as the handshake control DAV0 and RDY0. Handshake signal direction
is dictated by the I/O direction (input or output) of Port 0 of the upper nibble P04–
P07. The lower nibble must indicate the same direction as the upper nibble.
For external memory references, Port 0 provides address bits A11–A8 (lower nib-
ble) and A15–A8 (lower and upper nibble) depending on the required address
PS004005-1100
P R E L I M I N A R Y
Pin Functions
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
21
space. If the address range requires 12 bits or less, the upper nibble of Port 0 is
programmed independently as I/O while the lower nibble is used for addressing. If
one or both nibbles are required for I/O operation, they are configured by writing to
the Port 0 mode register.
In ROMless mode, after a hardware RESET, Port 0 is configured as address lines
A15–A8, and extended timing is set to accommodate slow memory access. The
initialization routine can include reconfiguration to eliminate this extended timing
mode. (In ROM mode, Port 0 is defined as input after RESET.)
Port 0 can be placed in a high-impedance state along with Port 1, AS, DS and R/
W, allowing the Z8 to share common resources in multiprocessor and DMA appli-
cations (Figure 10).
Figure 10. Port 0 Configuration
4
4
Port 0
(I/O or A15–A8)
Z8
Handshake Controls
DAV0 and RDY0
(P32 and P35)
Open-Drain
OE
Pull-Up
Transistor Enable
(Programmable Option)
PAD
Out
In
1.5
2.3 Hysteresis @ VCC = 5.0V
Auto Latch
(mask option)
R ≈ 500KΩ
PS004005-1100
P R E L I M I N A R Y
Pin Functions
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
22
Port 1 (P17–P10). Port 1 is an 8-bit, bidirectional, CMOS- compatible port
(Figure 11), with multiplexed Address (A7–A0) and Data (D7–D0) ports.These 8 I/
O lines are programmed as inputs or outputs, or can be configured under software
control as an Address/Data port for interfacing external memory.The input buffers
are Schmitt-triggered and byte-programmed as outputs and can be globally pro-
grammed as either push-pull or open-drain. Low-EMI output buffers are globally
programmed by the software.
Note:
Port 1 is not available on the devices in the 28-pin package, and P01M
Register must set bit D4,D3 as 00. Low-EMI mode is not supported on the
emulator for Port1. PCON register D4 must be 1.
Port 1 may be placed under handshake control. In this configuration, Port 3, lines
P33 and P34 are used as the handshake controls RDY1 and DAV1 (Ready and
Data Available).
Memory locations greater than the internal ROM address are referenced through
Port 1, except for the Z86E146 (due to its 64 KB of internal memory). To interface
external memory, Port 1 must be programmed for multiplexed Address/Data
mode. If more than 256 external locations are required, Port 0 outputs the addi-
tional lines.
Port 1 can be placed in the high-impedance state along with Port 0, AS, DS, and
R/W, allowing the Z8 to share common resources in multiprocessor and DMA
applications.
PS004005-1100
P R E L I M I N A R Y
Pin Functions
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
23
Figure 11. Port 1 Configuration
Port 1
(I/O or AD7–AD0)
8
Z8
Handshake Controls
DAV1 and RDY1
(P33 and P34)
Open Drain
OE
Pull-Up
Transistor Enable
(Programmable Option)
PAD
Out
1.5
2.3 Hysteresis @ VCC = 5.0V
In
Auto Latch
(mask option)
R ≈ 500 KΩ
Port 2 (P27–P20). Port 2 is an 8-bit, bidirectional, CMOS-compatible I/O port.
These eight I/O lines are configured under software control as an input or output,
independently. Port 2 is always available for I/O operation.The input buffers are
Schmitt-triggered. Bits programmed as outputs may be globally programmed as
either push-pull or open-drain. Low-EMI output buffers are globally programmed
by the software.
Port 2 may be placed under handshake control. In HANDSHAKE mode, Port 3
lines P31 and P36 are used as the handshake control lines DAV2 and RDY2. The
handshake signal assignment for Port 3 lines P31 and P36 is dictated by the
direction (input or output) assigned to bit 7, Port 2 (Figure 12).
PS004005-1100
P R E L I M I N A R Y
Pin Functions
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
24
Figure 12. Port 2 Configuration
Port 2 (I/O)
Z8
Handshake Controls
DAV2 and RDY2
(P31 and P36)
Open Drain
OE
Pull-Up
Transistor Enable
(Programmable Option)
PAD
Out
In
1.5
2.3 Hysteresis @ V
CC = 5.0V
Auto Latch
(mask option)
R ≈ 500 KΩ
Port 3 (P37–P30). Port 3 is an 8-bit, CMOS-compatible port, with four fixed inputs
(P33–P30) and four fixed outputs (P34–P37). Port 3 is configured under software
control for Input/Output, Counter/Timers, interrupt, UART, port handshake, and
Data Memory functions. Port 3, bit 0 input is Schmitt-triggered, and pins P31, P32,
and P33 are standard CMOS inputs (no autolatches). Pins P34, P35, P36, P37
are push-pull output lines. Low-EMI output buffers are globally programmed by
the software.
Two onboard comparators process analog signals on P31 and P32 with reference
to the voltage on P33.The analog function is enabled by programming Port 3
Mode Register (P3M bit 1). For interrupt functions, Port 3, bit 0 and pin 3 are fall-
ing-edge interrupt inputs. P31 and P32 are programmable as rising, falling, or
both edge-triggered interrupts (IRQ register bits 6 and 7). P33 is the comparator
reference voltage input when in Analog mode. Access to Counter/Timer 1 is made
PS004005-1100
P R E L I M I N A R Y
Pin Functions
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
25
through P31 (T ) and P36 (T
). Handshake lines for Ports 0, 1, and 2 are avail-
IN
OUT
able on P31 through P36.
Port 3 also provides the following control functions: handshake for Ports 0, 1, and
2 (DAV and RDY); four external interrupt request signals (IRQ3–IRQ0); timer input
and output signals (T and T
); Data Memory Select (DM, see Table 10 and
IN
OUT
Figure 13).
P34 output is software-programmed to function as a Data Memory Select (DM).
The Port 3 Mode Register (P3M) bit D3,D4 selects this function. When accessing
external data memory, P34 goes active Low; when accessing external program
memory, P34 goes High.
An onboard UART (ASCI) is enabled by software by setting the RE and TE bits of
the ASCI Control Register A (CNTLA). When enabled, P30 is the receive input
and P37 is the transmit output.
Table 10.Port 3 Pin Assignments
Control
Timer
Pin
P30
P31
P32
P33
P34
P35
P36
P37
Notes:
I/O
IN
Analog
Interrupt
IRQ3
P0 HS P1 HS P2 HS
Ext
UART
RX
IN
T
AN1
AN2
IRQ2
D/R
IN
IN
IRQ0
D/R
D/R
R/D
R/D
R/D
IN
REF
IRQ1
OUT
OUT
OUT
OUT
AN1–OUT
DM
T
OUT
AN2–OUT
TX
HS = Handshake Signals
D = DAV
R = RDY
Comparator Inputs and Outputs. Port 3, pins P31 and P32 each feature a compar-
ator front end. The comparator reference voltage, pin P33, is common to both
comparators. In ANALOG mode, the P31 and P32 are the positive inputs to the
comparators, and P33 is the reference voltage supplied to both comparators. In
DIGITAL mode, pin P33 is used as a P33 register input or IRQ1 source. P34 and
P37 can provide the comparator output directly by software-programming the
PCON register bit D0 to 1 (see Figure 14).
PS004005-1100
P R E L I M I N A R Y
Pin Functions
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
26
The user must add a two-NOP delay after setting the P3M bit D1 to 1
before the comparator output is valid. IRQ0, IRQ1, and IRQ2 must be
cleared in the IRQ register when the comparator is enabled or disabled.
Note:
Figure 13. Port 3 Configuration
P30
P31
P32
P33
Port 3
(I/O or Control)
Z8
P34
P35
P36
P37
Auto Latch
(Progammable option)
R ≈ 500KΩ
P30 Data
Latch IRQ3
P30
R247 = P3M
1 = Analog
0 = Digital
D1
DIG.
AN.
P31 (AN1)
+
IRQ2, T , P31 Data Latch
IN
–
P32 (AN2)
+
IRQ0, P32 Data Latch
IRQ1, P33 Data Latch
P33 (REF)
–
From Stop-Mode
Recovery Source
PS004005-1100
P R E L I M I N A R Y
Pin Functions
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
27
Figure 14. Port 3 Configuration—PCON Register Detail
P34
PAD
P34 OUT
P31
+
–
REF (P33)
P37
PAD
P37 OUT
P32
+
–
REF (P33)
PCON
0 P34, P37 Standard Output
1 P34, P37 Comparator Output
D0
Autolatch. The autolatch places valid CMOS levels on all CMOS inputs (except
P33–P31) that are not externally driven. Whether this level is 0 or 1 cannot be
determined. A valid CMOS level, rather than a floating node, reduces excessive
supply current flow in the input buffer. Autolatches are available on Port 0, Port 1,
Port 2, and P30. There are no autolatches on P31, P32, and P33.
Note:
Deletion of all port autolatches is available as an option when the device is
programmed.The AUTOLATCH DISABLE option is selected by the
customer when the device is programmed.
RESET (input/output, active Low). Initializes the MCU. RESET occurs through
Power-On Reset, Watch-Dog Timer reset, Stop-Mode Recovery, or external reset.
During Power-On Reset and Watch-Dog Reset, the internally-generated reset
drives the RESET pin Low for the POR time. Pull-up is provided internally.
Any devices driving the reset line must be open-drain to avoid damage
from a possible conflict during reset conditions. RESET depends on os-
cillator operation to achieve full reset conditions, except for conditions
wherein the reset is caused by a WDT time-out.
Caution:
Note:
The RESET pin is not available on devices in the 28-pin package.
PS004005-1100
P R E L I M I N A R Y
Pin Functions
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
28
After the POR time, RESET is a Schmitt-triggered input. During the RESET cycle,
DS is held active Low while AS cycles at a rate of T C ÷ 2. Program execution
P
begins at location 000Ch, after the RESET is released. For Power-On Reset, the
reset output time is T
ms.
POR
When program execution begins, AS and DS toggles only for external memory
accesses.The Z8 does not reset WDTMR, SMR, P2M, PCON, and P3M registers
on a Stop-Mode Recovery operation or from a WDT reset out of STOP mode.
PS004005-1100
P R E L I M I N A R Y
Pin Functions
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
29
Functional Description
®
The Z8 MCU incorporates the following functions that enhance the standard Z8
architecture and provide the user with increased design flexibility:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Reset
Program Memory
Data Memory
EPROM Protect
RAM Protect
Working Register File
Expanded Register File
General-Purpose Registers
Stack Pointer
Counter/Timers
Interrupts
Clock
Power-On Reset
HALT and STOP Modes
Port Configuration Register
Comparator
Stop-Mode Recovery
Watch-Dog Timer
Voltage Comparator
RESET. The device is reset in one of the following conditions:
•
•
•
•
•
Power-On Reset
Watch-Dog Timer
Stop-Mode Recovery Source
External Reset
Low Voltage Recovery
PS004005-1100
P R E L I M I N A R Y
Functional Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
30
Automatic Power-On Reset circuitry is built into the Z8, eliminating the require-
ment for an external reset circuit to reset upon power-up. The internal pull-up
resistor is on the RESET pin, so a pull-up resistor is not required; however, in a
high-EMI (noisy) environment, it is recommended that a low-value pull-up resistor
be used.
Note:
The RESET pin is not available on devices in the 28-pin package.
Program Memory. The first 12 bytes of program memory are reserved for the inter-
rupt vectors. These locations contain six 16-bit vectors that correspond to the six
available interrupts. For ROM mode, address 12 to address FFFFh (E136/E146)/
7FFFh (E135/E145)/3FFF (E134/E144) consists of programmable EPROM.The
Z86E142/E143/E144/E145 can access external program and data memory from
addresses 4000h/8000h to FFFFh. See Figure 15.
Figure 15. Program Memory Map for the MUZE Family
FFFFh
External/Internal
ROM and RAM
3FFFh/7FFFh
3FFEh/7FFEh
Location of
First Byte of
Instruction
Executed
On-Chip
ROM
12
11
10
9
After RESET
IRQ5
IRQ5
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQ0
IRQ0
8
7
Interrupt
Vector
(Lower Byte)
6
5
4
Interrupt
Vector
(Upper Byte)
3
2
1
0
PS004005-1100
P R E L I M I N A R Y
Functional Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
31
Data Memory (DM). The ROMless version addresses up to 64 KB of external data
memory. External data memory may be included with, or separated from, the
external program memory space. DM, an optional I/O function that is programmed
to appear on pin P34, is used to distinguish between data and program memory
space (Figure 16). The state of the DM signal is controlled by the type of instruc-
tion being executed. An LDC Op Code references PROGRAM (DM inactive)
memory, and an LDE instruction references data (DM active Low) memory. The
user must configure Port 3 Mode Register (P3M) bits D3 and D4 for this mode.
This feature is not usable for devices in 28-pin package.
Note:
When used in ROM mode, the Z86E146 cannot access any external data
or program memory. The Z86E14X series of Z8 MCUs can access
external program and data memory from addresses 4000h/8000h to
FFFFh.
Figure 16. Data Memory Map
FFFFh
FFFFh
External
Data
Memory
External
Data
Memory
4000h/8000h
3FFFh/7FFFh
Not Addressable
EPROM Mode
0
0
ROMless Mode
PS004005-1100
P R E L I M I N A R Y
Functional Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
32
EPROM Protect. EPROM PROTECT provides an additional security function.
When the device is programmed with the EPROM PROTECT option bit selected,
and it is executing out of External Program Memory, instructions LDC, LDCI, LDE,
and LDEI cannot read Internal Program Memory.
When the EPROM PROTECT option bit is selected, and executing out of Internal
Program Memory, instructions LDC, LDCI, LDE, and LDEI can read Internal Pro-
gram Memory.
RAM Protect. The upper portion of the RAM’s address spaces 80h to EFh (exclud-
ing the control registers) can be protected from writing. The RAM Protect option
bit can be selected when the device is programmed. After the mask option is
selected, the user activates this feature from the internal ROM code to turn off/on
the RAM Protect by loading either a 0 or a 1 into the IMR register, bit D6. A 1 in bit
D6 enables the RAM Protect option.
Working Register File. The Z8 standard register file contains 4 I/O port registers,
236 general-purpose registers, and 15 control and status registers. Expanded
register file Fh contains 3 system-configuration registers. Expanded register file
Ah contains 8 ASCI control registers. The working registers are accessed directly
or indirectly via an 8-bit address field. As a result, a short 4-bit register address
can use the Register Pointer (Table 11 and Figure 17). In the 4-bit mode, the
working register file is divided into 16 working register groups, each occupying 16
continuous locations. The Register Pointer addresses the starting location of the
active working register group.
Throughout this document, the Z8 Standard Register File is referred to as a Bank.
Table 11.Register Pointer Register—RP FDh/R253 Bank 0h: READ/WRITE
Bit
D7
R/W
0
D6
R/W
0
D5
R/W
0
D4
R/W
0
D3
R/W
0
D2
R/W
0
D1
R/W
0
D0
R/W
0
R/W
Reset
Note: R = Read, W = Write, X = Indeterminate.
Bit
Bit
Position Field
R/W
State Description
D7–D4
D3–D0
Working Registers
ERF
R/W
0
Working Register Group
Pointer
R/W
0
Expanded Register File
Expanded Register File (ERF). The Z8 register file is expanded to allow for addi-
tional system control registers, and for mapping of additional peripheral devices,
along with the I/O ports, into the register address area. The Z8 register address
space R0 through R15 is implemented as 16 groups of 16 registers per bank (Fig-
PS004005-1100
P R E L I M I N A R Y
Functional Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
33
ures 17 and 18 ).These register groups are known as the Expanded Register File
(ERF). Bits 7–4 of register RP select the Working Register Group. Bits 3–0 of reg-
ister RP select the Expanded Register File. Five system configuration registers
reside in the Expanded Register File at Bank Fh—PCON, VFY, SMR, SMR2, and
WDTMR. The 8 control registers for the ASCI are located in the Expanded Regis-
ter File Bank Ah. The remainder of the Expanded Register is not physically imple-
mented, and is open for future expansion.
Figure 17. Register Pointer—Detail
R253
(Register Pointer)
r7 r6 r5 r4
r3 r2 r1 r0
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group.
FF
Register Bank Fh
F0
EF
80
7F
70
6F
60
5F
50
4F
The lower nibble
of the register
file address
40
3F
Specified Working
Register File
provided by the
instruction points
to the specified
register.
30
2F
20
1F
Register File1
R15 to R0
10
0F
R15 to R4*
R3 to R0*
Register File 0
I/O Ports
00
* Expanded Register File 0 is selected
in this figure by handling bits D3 to D0
as "0" in Register R253 (RP).
PS004005-1100
P R E L I M I N A R Y
Functional Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
34
General-Purpose Registers (GPR). General-purpose registers are undefined after
the device is powered up. These registers keep the most recent value after any
RESET, as long as the RESET occurs in the V voltage-specified operating
CC
range. General-purpose registers are not guaranteed to keep their most recent
state from a Low-Voltage Protection (V ) RESET if V drops below 1.8V.
LV
CC
Note:
Register Bank E0–EF is only accessed via working register and indirect
addressing modes.
Stack Pointer. The Z8 internal register file is used for the stack. The 16-bit Stack
Pointer (SPH and SPL) is used for the external stack, which can reside anywhere
in the data memory for ROMless mode. An 8-bit Stack Pointer (SPL) is used for
the internal stack that resides within the 236 general-purpose registers. Stack
Pointer High (SPH) is used as a general-purpose register only when using an
internal stack. The devices in the 28-pin and 40-pin packages can only use the 8-
bit stack pointer (SPL) for the internal stack.
Note:
SPH and SPL are set to 00h after any RESET or Stop-Mode Recovery.
Counter/Timers. There are two 8-bit programmable counter/timers (T0–T1), each
driven by its own 6-bit programmable prescaler.The T1 prescaler is driven by
internal or external clock sources; however, the T0 prescaler is driven by the inter-
nal clock only (Figure 19).
The 6-bit prescalers can divide the input frequency of the clock source by any
integer number from 2to 64. Each prescaler drives its counter, which decrements
the value (1 to 256) that is loaded into the counter. When the counter reaches the
end of the count, a timer interrupt request, IRQ4 (T0) or IRQ5 (T1), is generated.
The counters are programmed to START, STOP, restart to CONTINUE, or restart
from the initial value. The counters can also be programmed to STOP upon reach-
ing 0 (SINGLE-PASS mode) or to automatically reload the initial value and con-
tinue counting (MODULO–N CONTINUOUS mode).
The counters, but not the prescalers, are read at any time without disturbing their
value or count mode.The clock source for T1 is user-definable and is either the
internal microprocessor clock divide-by-four, or an external signal input through
Port 3. The Timer Mode Register configures the external timer input (P31) as an
external clock, a trigger input that is retriggerable or nonretriggerable, or as a gate
input for the internal clock.The counter/timers are cascaded by connecting the T0
output to the input of T1. T mode is enabled by setting PRE1 bit D1 to 0.
IN
PS004005-1100
P R E L I M I N A R Y
Functional Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
35
Figure 18. Expanded Register File Architecture
Z8® Standard Control Registers
Reset Condition
Expanded Register File 0h
Working Register Group 0
D7 D6 D5 D4 D3 D2 D1 D0
FFh
FEh
FDh
FCh
FBh
FAh
F9h
F8h†
F7h*
F6h*
F5h
F4h
F3h
F2h
F1h
F0h
SPL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register Pointer
SPH
RP
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
FLAGS
IMR
X
0
X
X
0
X
X
0
X
X
0
X
X
0
X
X
0
X
X
0
X
X
0
Working Register
Group Pointer
Expanded Register
File Pointer
IRQ
0
IPR
X
0
X
X
0
X
0
X
1
X
1
X
0
X
1
P01M
P3M
P2M
PRE0
T0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
X
0
X
X
X
X
0
X
X
X
X
0
X
X
X
X
0
X
X
X
X
0
X
X
X
X
0
X
X
0
0
X
0
Z8 Working Register File
FFh
PRE1
T1
FOh
X
0
X
0
TMR
Reserved
Expanded Register File Fh
Working Register Group 0
Reset Condition
0Fh*
0Eh
0
X
0
1
X
0
1
X
0
0
0
0
1
0
0
WDTMR
X
X
X
Reserved
70h
0Dh*
0Ch
0Bh**
0Ah
09h
X
X
X
SMR2
Reserved
SMR
0
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCON
08h
07h
06h
0Fh
00h
05h
04h
03h
02h
01h
00h
1
1
1
1
1
1
1
0
Expanded Register File Ah
Working Register Group 0
Reset Condition
ASCI
Control
Registers
0Fh*
0Eh*
Reserved
Reserved
Reserved
X
0Dh
0Ch
Reserved
Reserved
Reserved
GPR
0Bh*
0Ah*
09hX
Notes:
X = Indeterminate.
*Is not reset via Stop-Mode Recovery.
**Is not reset via Stop-Mode Recovery, excet for bit D0.
†The ROMless reset condition: 10110110.
XNot available on 28-pin packages.
08h
STAT
0
1
0
1
1
0
0
0
X
X
0
1
1
0
0
0
X
X
0
1
1
0
0
1
X
X
0
1
1
0
0
0
X
X
0
1
1
0
1
0
X
X
0
1
1
1
1
0
X
X
0
1
1
0
1
0
X
X
07h*
06h*
05hX
ASTH
ASTL
1
ASEXT
CNTLB
CNTLA
RDR
X
0
04h
03h*
02h*
01hX
0
X
X
TDR
00h
Reserved
PS004005-1100
P R E L I M I N A R Y
Functional Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
36
Figure 19. Counter/Timer Block Diagram
OSC
Internal Data Bus
D1 (SMR)
Write
Write
Read
2
PRE0
T0
T0
Initial Value
Register
Initial Value
Register
Current Value
Register
D0 (SMR)
6-Bit
Down
8-bit
Down
16
÷4
Counter
Counter
IRQ4
Internal
Clock
TOUT
P36
÷2
External Clock
Clock
Logic
6-Bit
Down
Counter
8-Bit
Down
Counter
IRQ5
÷4
Internal Clock
Gated Clock
Triggered Clock
PRE1
Initial Value
Register
T1
T1
Initial Value
Register
Current Value
Register
TIN P31
Write
Write
Read
Internal Data Bus
Interrupts. The Z8 features six different interrupts from six different sources.
These interrupts are maskable and prioritized (Figure 24). The 6 sources are
divided as follows: 4 sources are claimed by Port 3 lines P33–P30, and 2 are
claimed by counter/timers (Table 12).The Interrupt Mask Register globally or indi-
vidually enables or disables the six interrupt requests.
Table 12.Interrupt Types, Sources, and Vectors
Vector
Name Source
Location Comments
IRQ0
IRQ1,
IRQ2
DAV0, IRQ0
0,1
2,3
4,5
External (P32), Rising and Falling Edges Triggered
IRQ1
External (P33), Falling Edge Triggered
DAV2, IRQ2, T
External (P31), Rising and Falling Edges Triggered
IN
PS004005-1100
P R E L I M I N A R Y
Functional Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
37
Table 12.Interrupt Types, Sources, and Vectors (Continued)
Vector
Name Source
Location Comments
IRQ3
IRQ4
IRQ5
UART (ASCI)
6,7
External (P30), Falling Edge Triggered
T0
T1
8,9
Internal
Internal
10,11
When more than one interrupt is pending, priorities are resolved by a programma-
ble priority encoder that is controlled by the Interrupt Priority register. An interrupt
machine cycle activates when an interrupt request is granted.This action disables
all subsequent interrupts, saves the Program Counter and Status Flags, and then
branches to the program memory vector location reserved for that interrupt.
All Z8 interrupts are vectored through locations in the program memory. This
memory location and the next byte contain the 16-bit address of the interrupt ser-
vice routine for that particular interrupt request. To accommodate polled interrupt
systems, interrupt inputs are masked and the Interrupt Request register is polled
to determine which of the interrupt requests require service.
When in ANALOG mode, an interrupt resulting from COMPARATOR1 maps to
IRQ2, and an interrupt from COMPARATOR2 maps to IRQ0. Interrupts IRQ2 and
IRQ0 may be rising, falling, or both edge-triggered, and are programmed in the
IRQ register. The software polls to identify the state of the pin. When in ANALOG
mode, IRQ1 is generated by the Stop-Mode Recovery source selected by SMR
Register bits D4, D3, D2, or SMR2 D1 or D0.
Programming bits for the Interrupt Edge Select are located in the IRQ register, bits
D7 and D6.The configuration is indicated in Table 13.
Table 13.IRQ Register*
IRQ
Interrupt Edge
P31 P32
D7
0
D6
0
F
F
0
1
F
R
R
F
1
0
1
1
R/F
R/F
Notes:
F = Falling Edge
R = Rising Edge
PS004005-1100
P R E L I M I N A R Y
Functional Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
38
Clock. The Z8 on-chip oscillator features a high-gain, parallel-resonant amplifier
for connection to a crystal, LC, RC, ceramic resonator, or any suitable external
clock source (X = INPUT, X
= OUTPUT). The crystal should be AT-cut, 16
IN
OUT
MHz maximum, with a series resistance (RS) of less than or equal to 100Ω when
oscillating from 1MHz to 16MHz.
The crystal should be connected across X and X
using the vendor’s recom-
OUT
IN
mended capacitor values from each pin directly to the device Ground pin to
reduce ground-noise injection into the oscillator. The RC oscillator option can be
selected when the device is programmed.
Note:
The RC option is available up to 8 MHz.The RC oscillator configuration
must be an external resistor connected from X to XOUT, with a frequency-
IN
setting capacitor from X to Ground (Figure 20).
IN
For better noise immunity, the capacitors should be tied directly to the
device Ground pin (V ).
SS
Figure 20. Oscillator Configuration
XIN
XIN
XIN
XIN
C1
C1
C1
L
R
VSS**
VSS**
VSS**
XOUT
XOUT
XOUT
XOUT
C2
C2
VSS**
VSS**
Ceramic Resonator or
Crystal
LC
RC
External Clock
C1, C2 = 22 pF
@ 5V VCC (Typ.)
C1, C2 = 47 pF Typ.*
f = 8 MHz
L = 130 µH *
f = 3 MHz *
C1 = 33 pF*
R = 1 KB*
f = 6 MHz*
*Preliminary value, including pin parasitics.
**Device ground pin.
Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscilla-
tor is used for the Power-On Reset (POR) timer function. The POR time allows
V
and the oscillator circuit to stabilize before instruction execution begins.
CC
The POR timer circuit is a one-shot timer triggered by one of three conditions:
1. Power fail to Power OK status.
2. Stop-Mode Recovery (if D5 of SMR = 1).
3. WDT time-out.
PS004005-1100
P R E L I M I N A R Y
Functional Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
39
The POR time is specified as TPOR. Bit 5 of the Stop-Mode Register determines
whether the POR timer is bypassed after Stop-Mode Recovery (typical for exter-
nal clock, RC/LC oscillators).
HALT. HALT turns off the internal CPU clock, but not the CRYSTAL oscillation.
The counter/timers, UART, and external interrupts IRQ0, IRQ1, IRQ2, and IRQ3
remain active.The devices are recovered by interrupts and are either externally or
internally generated. An interrupt request must be enabled and executed to exit
HALT mode. After the interrupt service routine, the program continues from the
instruction after the HALT.
In order to enter STOP (or HALT) mode, it is necessary to first flush the instruc-
tion pipeline to avoid suspending execution in mid-instruction. Therefore, the user
must execute a NOP (Op Code = FFh) immediately before the appropriate sleep
instruction. For example:
FF NOP ; clear the pipeline
6F STOP ; enter STOP mode
or
FF NOP ; clear the pipeline
7F HALT ; enter HALT mode
STOP. This instruction turns off the internal clock and external crystal oscillation.
The STOP instruction also reduces the standby current to 10 µA or less. STOP
mode is terminated by a RESET only, either by WDT time-out, POR, Stop-Mode
Recovery, or external reset. As a result, the processor restarts the application pro-
gram at address 000Ch. A WDT time-out in STOP mode affects all registers the
same as if a Stop-Mode Recovery occurred via a selected Stop-Mode Recovery
source except that the POR delay is enabled even if the delay is selected for dis-
able.
Note:
If a permanent WDT is selected, the WDT runs in all modes and cannot be
stopped or disabled if the onboard RC oscillator is selected to drive the
WDT.
Port Configuration Register (PCON). The PCON register configures the ports indi-
vidually; comparator output on Port 3, open-drain on Port 0 and Port 1, low EMI on
Ports 0, 1, 2, and 3, and low-EMI oscillator. The PCON register is located in the
expanded register file at Bank F, location 00h (Table 14).
PS004005-1100
P R E L I M I N A R Y
Functional Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
40
Table 14.Port Configuration Register—PCON 00h/R0 Bank Fh:WRITE ONLY
Bit
D7
W
1
D6
W
1
D5
W
1
D4
W
1
D3
W
1
D2
W
1
D1
W
1
D0
W
0
R/W
Reset
Note: R = Read, W = Write, X = Indeterminate.
Bit
Position Field
Oscillator
Bit
R/W
State Description
Low-EMI Oscillator
D7
D6
D5
D4
D3
D2
D1
D0
W
1
1
1
1
1
1
1
0
0: Low EMI
1: Standard
Port 3 I/O
Port 2 I/O
Port 1 I/O
Port 0 I/O
Port 0 I/O
Port 1 I/O
Port 3
W
W
W
W
W
W
W
Port 3
0: Low EMI
1: Standard
Port 2
0: Low EMI
1: Standard
Port 1
0: Low EMI
1: Standard
Port 0*
0: Low EMI
1: Standard
Port 0
0: Open-Drain
1: Push-Pull Active
Port 1*
0: Open-Drain
1: Push-Pull Active
Port 3 Comparator Output
0: P34, P37 Standard Output
1: P34, P37 Comparator Output
Note: Must be set to 1 for devices in 28-pin packages.
Comparator
Comparator Output Port 3 (D0). Bit 0 controls the comparator use in Port 3. A 1 in
this location brings the comparator outputs to P34 and P37, and a 0 releases the
Port to its standard I/O configuration. The default value is 0.
Port 1 Open-Drain (D1). Port 1 is configured as an open-drain by resetting this bit
(D1 = 0) or configured as push-pull active by setting this bit (D1 = 1).The default
value is 1. The user must set D1 = 1 for devices in 28-pin packages.
PS004005-1100
P R E L I M I N A R Y
Functional Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
41
Port 0 Open-Drain (D2). Port 0 is configured as an open-drain by resetting this bit
(D2 = 0) or configured as push-pull active by setting this bit (D2 = 1).The default
value is 1.
Low-EMI Port 0 (D3). Port 0 is configured as a low-EMI port by resetting this bit (D3
= 0) or configured as a Standard Port by setting this bit (D3 = 1).The default value
is 1.
Low-EMI Port 1 (D4). Port 1 is configured as a low-EMI port by resetting this bit (D4
= 0) or configured as a Standard Port by setting this bit (D4 = 1).The default value
is 1. The user must set D4 = 1 for devices in 28-pin packages.
Note:
For emulator, this bit must be set to 1.
Low-EMI Port 2 (D5). Port 2 is configured as a low-EMI port by resetting this bit (D5
= 0) or configured as a Standard Port by setting this bit (D5 = 1).The default value
is 1.
Low-EMI Port 3 (D6). Port 3 is configured as a low-EMI port by resetting this bit (D6
= 0) or configured as a Standard Port by setting this bit (D6 = 1).The default value
is 1.
Low-EMI OSC (D7). This bit of the PCON register controls the low-EMI noise oscil-
lator. A 1 in this location configures the oscillator, DS, AS and R/W with standard
drive, while a 0 configures the oscillator, DS, AS and R/W with low noise drive.
LOW-EMI mode reduces the drive of the oscillator (OSC). The default value is 1.
Note:
Maximum external clock frequency of 4 MHz when running in LOW-EMI
OSCILLATOR mode.
Low-EMI Emission. The Z8 is programmed to operate in a low-EMI emission mode
in the PCON register. The oscillator and all I/O ports is programmed as LOW-EMI
EMISSION mode independently. Use of this feature results in:
•
•
•
•
The pre-drivers slew rate reduced to 10 ns (typical)
Low-EMI output drivers exhibit resistance of 200Ω (typical)
Low-EMI Oscillator
Internal SCLK = CRYSTAL operation limited to a maximum of 4 MHz–250 ns
cycle time, when LOW EMI OSCILLATOR is selected and system clock (SMR
Register Bit D1 = 1)
Stop-Mode Recovery
Stop-Mode Recovery Registers (SMR1 and SMR2). These registers select the clock
divide value and determine the mode of Stop-Mode Recovery (Tables 15 and 18).
All bits are WRITE ONLY, except bit 7 of SMR1, which is READ ONLY. SMR1 bit
7 is a flag bit that is set by hardware on a Stop-Mode Recovery condition and
PS004005-1100
P R E L I M I N A R Y
Functional Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
42
reset by a power-on cycle. For SMR1, bit 6 controls whether a Low level or a High
level is required from the recovery source. Bit 5 controls the reset delay after
Stop-Mode Recovery. Bits 2, 3, and 4 of the SMR1 register specify the source of
the Stop-Mode Recovery signal. Bits 0 and 1 determine the time-out period of the
WDT. The SMR registers are located in Bank F of the Expanded Register File at
addresses 0Bh and 0Dh, respectively.
For SMR2, bits 7 to 2 are reserved. Bits 1 and 0 of the SMR2 register specify the
source of the Stop-Mode Recovery signal.
Table 15.Stop-Mode Recovery Register 1—SMR1 0Bh/R11 Bank Fh: WRITE ONLY,
except Bit D7, which is READ ONLY
Bit
D7
R
D6
W
0
D5
W
1
D4
W
0
D3
W
0
D2
W
0
D1
W
0
D0
W
0
R/W
Reset
0
Note: R = Read, W = Write, X = Indeterminate.
Bit
Bit
Position Field
R/W
State Description
D7
STP
R
0
0
1
0
Stop Flag
0: POR
1: Stop-Mode Recovery
D6
SMR
W
W
W
Stop-Mode Recovery Level
0: Low
1: High
D5
STPDLY
CLK
Stop Delay
0: Off
1: On
D0
SCLK ÷ TCLK Divide-by-16
1
0: Off
1: On
Notes:
1. Do not use in conjunction with SMR2 Source.
2. Cleared by RESET and SMR.
PS004005-1100
P R E L I M I N A R Y
Functional Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
43
D4–D2
SMRSRC
W
000 Stop-Mode Recovery Source2
000: POR only and/or external RESET
001: P30
010: P31
011: P32
100: P33
101: P27
110: P2 NOR 0–3
111: P2 NOR 0–7
D1
EXTCLK
CLK
W
W
0
0
External Clock Divide-by-2
0: SCLK ÷ TCLK = Crystal ÷ 2
1: SCLK = Crystal
D0
SCLK ÷ TCLK Divide-by-16
1
0: Off
1: On
Notes:
1. Do not use in conjunction with SMR2 Source.
2. Cleared by RESET and SMR.
SCLK ÷ TCLK Divide-by-16 Select (D0). Bit D0 of the SMR controls a divide-by-16
prescaler of SCLK ÷ TCLK. The purpose of this control is to selectively reduce
device power consumption during normal processor execution (SCLK control)
and/or HALT mode (where TCLK sources counter/timers and interrupt logic). This
bit is reset to D0 = 0 after a Stop-Mode Recovery.
External Clock Divide-by-Two (D1). This bit can eliminate the oscillator divide-by-
two circuitry. When this bit is 0, the system clock (SCLK) and timer clock (TCLK)
are equal to the external clock frequency divided by 2.The SCLK is equal to the
external clock frequency when this bit is set (D1 = 1). Using this bit together with
D7 of PCON further helps lower EMI (that is, D7 (PCON) = 0, D1 (SMR) = 1). The
default setting is 0. Maximum external clock frequency is 4 MHz when SMR bit D1
= 1 where SCLK ÷ TCLK = Crystal.
Stop-Mode Recovery Source (D2, D3, and D4). These three bits of the SMR specify
the wake-up source of the Stop-Mode Recovery (Figure 21 and Table 16). When
the Stop-Mode Recovery Sources are selected in this register, then SMR2 regis-
ter bits D0,D1 must be set to 0.
Note:
If the Port 2 pin is configured as an output, this output level is read by the
SMR circuitry.
PS004005-1100
P R E L I M I N A R Y
Functional Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
44
Figure 21. Stop-Mode Recovery Source
SMR2 D1 D0
0
0
VDD
SMR2 D1 D0
SMR2 D1 D0
0
1
1
0
P20
P23
P20
P27
SMR D4 D3 D2
0
0
0
VDD
SMR D4 D3 D2 SMR D4 D3 D2 SMR D4 D3 D2
SMR D4 D3 D2
SMR D4 D3 D2
0
0
0
0
1
1
1
0
1
1
0
0
1
0
1
1
1
0
1
1
1
P20
P20
P30
P31
P32
P33
P27
P23
P27
To POR
RESET
Stop-Mode Recovery Edge
Select (SMR)
To P33 Data
Latch and IRQ1
MUX
P33 From Pads
Digital/Analog Mode
Select (P3M)
Table 16.Stop-Mode Recovery Source
SMR[4–2]
D4
0
D3
0
D2
0
Operation/Description of Action
POR and/or external reset recovery
P30 transition
0
0
1
0
1
0
P31 transition (not in ANALOG mode)
P32 transition (not in ANALOG mode)
P33 transition (not in ANALOG mode)
P27 transition
0
1
1
1
0
0
1
0
1
1
1
0
Logical NOR of P20 through P23
Logical NOR of P20 through P27
1
1
1
PS004005-1100
P R E L I M I N A R Y
Functional Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
45
Stop-Mode Recovery Delay Select (D5). This bit, if High, enables the T
RESET
POR
delay after Stop-Mode Recovery. The default configuration of this bit is 1. If the
fast wake up is selected, the Stop-Mode Recovery source must be kept active for
at least 5 T C. Code execution begins after T
(see Tables 58 and 59).
P
EDELAY
Stop-Mode Recovery Edge Select (D6). A 1 in this bit position indicates that a high
level on any one of the recovery sources wakes the Z8 from STOP mode. A 0 indi-
cates low-level recovery.The default is 0 on POR (Table 17).This bit is used for
either SMR or SMR2.
Cold or Warm Start (D7). This bit is set by the device upon entering STOP mode. A
0 in this bit (cold) indicates that the device resets by POR/WDT RESET. A 1 in this
bit (warm) indicates that the device awakens by a Stop-Mode Recovery source.
Note:
If the Port 2 pin is configured as an output, this output level is read by the
SMR2 circuitry.
Stop-Mode Recovery Register 2 (SMR2). This register contains additional Stop-
Mode Recovery sources. When the Stop-Mode Recovery sources are selected in
this register then SMR register bits D2, D3, and D4 must be 0.
Table 17. Stop-Mode Recovery Register 2
SMR1–0
D1
0
D0
0
Operation/Description of Action
POR and/or external reset recovery
Logical AND of P20 through P23
Logical AND of P20 through P27
0
1
1
0
Table 18.Stop-Mode Recovery Register 2—SMR2 0Dh/R13 Bank Fh:WRITE ONLY
Bit
D7
W
X
D6
W
X
D5
W
X
D4
W
X
D3
W
X
D2
W
X
D1
W
0
D0
W
0
R/W
Reset
Note: R = Read, W = Write, X = Indeterminate.
Bit/
Bit
Field
Position
R/W
W
State Description
D7–D2 Reserved
X
Reserved—must be 0
D1–D0 STOP Mode
W
00
Stop-Mode Recovery Source 2*
00: POR only
01: AND P20, P21, P22, P23
10: AND P20, P21, P22, P23, P24, P25,
P26, P27
Note: *Do not use in conjunction with SMR Source.
P R E L I M I N A R Y
PS004005-1100
Functional Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
46
Watch-Dog Timer
Watch-Dog Timer Mode Register (WDTMR). The WDT is a retriggerable one-shot
timer that resets the Z8 if it reaches its terminal count. The WDT is initially
enabled by executing the WDT instruction and refreshed on subsequent execu-
tions of the WDT instruction.The WDT circuit is driven by an onboard RC oscilla-
tor or external oscillator from the X pin. The POR clock source is selected with
IN
bit 4 of the WDT register (Table 19).
WDT instruction affects the Z (Zero), S (Sign), and V (Overflow) flags. The
WDTMR must be written to within the first 64 internal system clocks. After that,
the WDTMR is WRITE-protected.
Note:
WDT time-out while in STOP mode does not reset SMR, PCON, WDTMR,
P2M, P3M, Ports 2 & 3 Data Registers, but the POR delay counter is still
enabled even though the SMR stop delay is disabled.
Table 19.Watch-Dog Timer Mode Register—WDTMR 0Fh/R15: WRITE ONLY
Bit
D7
W
X
D6
W
X
D5
W
X
D4
W
0
D3
W
1
D2
W
1
D1
W
0
D0
W
1
R/W
Reset
Note: R = Read, W = Write, X = Indeterminate.
Bit/
Bit
Field
Position
R/W
W
State Description
D7–D5 Reserved
X
0
Reserved—must be 0
D4
X
W
XIN/INT RC Select for WDT
0: On-Board RC
IN
1: Crystal
D3
D2
WDT
WDT
W
W
W
1
1
WDT During STOP
WDT During HALT
D1–D0 WDT Tap
01
WDT Tap Int RC OSC System Clock
00:
01:
10:
11:
3.5ms
10.0 ms
14.0 ms
56.0 ms
128 SCLK
256 SCLK
512 SCLK
2048 SCLK
Note: Not used in conjunction with SMR Source.
PS004005-1100
P R E L I M I N A R Y
Functional Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
47
WDT Time Select (D0,D1). Selects the WDT time period and is configured as indi-
cated in Table 20.
Table 20. WDT Time Select
Timeout of
Timeout of
D1
0
D0
0
Internal RC OSC
System Clock
3.5 ms min
7 ms min
128 SCLK
256 SCLK
512 SCLK
2048 SCLK
0
1
1
0
14 ms min
56 ms min
1
1
Note: SCLK = system bus clock cycle. The default on RESET is 7 ms. Values provided are for
= 5.0V.
V
CC
WDTMR During HALT (D2). This bit determines whether or not the WDT is active
during HALT mode. A 1 indicates active during HALT. The default is 1.
WDTMR During STOP (D3). This bit determines whether or not the WDT is active
during STOP mode. Because the CRYSTAL clock is stopped during STOP mode,
the on-board RC must be selected as the clock source to the POR counter. A 1
indicates active during STOP. The default is 1.
Note:
If the permanent WDT programming option is selected, the WDT runs in all
modes and cannot be stopped or disabled if the on board RC oscillator is
selected as the clock source for WDT.
Clock Source for WDT (D4). This bit determines which oscillator source is used to
clock the internal POR and WDT counter chain. If the bit is a 1, the internal RC
oscillator is bypassed and the POR and WDT clock source is driven from the
external pin, X .The default configuration of this bit is 0 which selects the internal
IN
RC oscillator.
WDTMR Register Accessibility. The WDTMR register is accessible only during the
first 64 internal system clock cycles from the execution of the first instruction after
Power-On Reset, Watch-Dog Reset, or Stop-Mode Recovery. After this point, the
register cannot be modified by any means, intentional or otherwise. The WDTMR
cannot be read and is located in Bank Fh of the Expanded Register File at
address location 0Fh (Figure 22).
Note:
The WDT is permanently enabled (automatically enabled after RESET)
through a programmable option.The option is selected when the device is
programmed. In this mode, WDT is always activated when the device
comes out of RESET. Execution of the WDT instruction serves to refresh the
WDT time-out period. WDT operation in the HALT and STOP modes is
controlled by WDTMR programming. If this option is not selected when the
PS004005-1100
P R E L I M I N A R Y
Functional Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
48
device is programmed, the WDT must be activated by the user through the
WDT instruction and is always disabled by any reset to the device.
Figure 22. Resets and Watch-Dog Timer Example
Reset
4 Clock
Filter
Clear
CLK
18 Clock RESET
Generator
RESET
Internal
RESET
WDT Select
(WDTMR)
WDT TAP SELECT
CLK Source
Select
(WDTMR)
15ms 25ms 100ms
5ms
5ms POR
CK
XTAL
M
U
X
WDT/POR Counter Chain
CLR
Internal
RC OSC.
2V Operating
Voltage Det.
VDD
VLV
+
–
WDT
From Stop
Mode
Recovery
Source
Stop Delay
Select (SMR)
Voltage Comparator
Low-Voltage Protection. An onboard Voltage Comparator checks that V is at the
CC
required level to ensure correct operation of the device. RESET is globally driven
if V is below the specified voltage (Low-Voltage Protection). The minimum oper-
CC
ating voltage varies with the temperature and operating frequency, while the Low-
Voltage Protection (V ) varies with temperature only.
LV
The Low-Voltage Protection trip voltage (V ) is less than 3V and more than 1.4V
LV
under the following conditions.
The device functions normally at or above 4.5V under all conditions. Below 4.5V,
the device functions normally until the Low-Voltage Protection trip point (V ) is
LV
reached, for the temperatures and operating frequencies in Case 1 and Case 2, in
Table 21.The device is guaranteed to function normally at supply voltages above
PS004005-1100
P R E L I M I N A R Y
Functional Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
49
the Low-Voltage Protection trip point. The actual Low-Voltage Protection trip point
is a function of temperature and process parameters (Figure 23).
Figure 23. Typical Low-Voltage Protection vs.Temperature
VCC
(Volts)
3.80
3.60
3.40
3.20
3.00
2.80
2.60
2.40
A
B
RUN/HALT Mode
STOP Mode
V
(Typical)
LV
B
A
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature (ºC)
Table 21.Maximum (V ) Conditions:
LV
Case 1:
Case 2:
T = –40ºC, +105ºC, Internal Clock Frequency equal or less than 4 MHz
A
T = –40ºC, +85ºC, Internal Clock Frequency equal or less than 6 MHz
A
Note:
The internal clock frequency relationship to the CRYSTAL clock is
dependent on SMR Bit 0 1 setting.
PS004005-1100
P R E L I M I N A R Y
Functional Description
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
50
Control Registers
The MUZE family of Z8 parts offers 3 banks of registers, including eight ASCI reg-
isters in Bank Ah, as detailed in the following pages.
Expanded Register File, Bank 0h
Bank 0h of the Expanded Register File contains 15 registers that perform the
Timer, Prescaler, Port, Interrupt, Flag, and Pointer functions, as shown in Tables
23 through 37.These 15 registers are not reset by a Stop-Mode Recovery.
Table 22 lists the reset states of all 15 Bank 0h registers.
Table 22.Expanded Register File Registers—Reset States
D7
D6
D5
D4
D3
D2
D1
D0
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
Reserved
TMR*
T1*
0
X
X
X
X
1
0
0
X
0
0
X
0
0
0
0
X
X
X
X
1
0
1
X
0
X
X
0
0
0
0
X
X
X
X
1
0
0
X
0
X
X
0
0
0
0
X
X
X
X
1
0
0
X
0
X
X
0
0
0
0
X
X
X
X
1
0
1
X
0
X
X
0
0
0
0
X
X
X
X
1
0
1
X
0
X
X
0
0
0
0
X
0
X
X
1
0
0
X
0
X
X
0
0
0
0
X
0
X
0
1
0
1
X
0
X
X
0
0
0
PRE1*
T0*
PRE0*
P2M*
P3M*
P01M*
IPR*
IRQ*
IMR*
FLAGS*
RP*
SPH*
SPL*
Note: *Not reset with a Stop-Mode Recovery.
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
51
Timer Mode Register
The Timer Mode Register, TMR, controls timing and counter functions. READ/
WRITE and reset states for bits D7–D0 are listed in Table 23.
Table 23.Timer Mode Register—TMR F1h/R241 Bank 0h: READ/WRITE
Bit
D7
R/W
0
D6
R/W
0
D5
R/W
0
D4
R/W
0
D3
R/W
0
D2
R/W
0
D1
R/W
0
D0
R/W
0
R/W
Reset State
Note: R = Read, W = Write.
Bit
Bit
Position Field
R/W
State Description
D7–D6
D5–D4
T
T
Mode
R/W
00
T
Mode
OUT
OUT
00: Off
01: T0 Output
10: T1 Output
11: Internal Clock Output
T Mode
IN
Mode
R/W
00
IN
00: External Clock Input
01: Gate Input
10: Trigger Input (nonretriggerable)
11: Trigger Input (retriggerable)
D3
D2
D1
D0
T1 Count
T1
R/W
R/W
R/W
R/W
0
0
0
0
T1 Count
0: Disable
1: Enable
T1
0: No Function
1: Load T1
T0 Count
T0
T0 Count
0: Disable
1: Enable
T0
0: No Function
1: Load T0
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
52
Counter/Timer 1 Register
The Counter/Timer 1 Register, T1, controls timing and counter functions. READ/
WRITE and reset states for bits D7–D0 are listed in Table 24.
Table 24.Counter/Timer 1 Register—T1 F2h/R242 Bank 0h: READ/WRITE
Bit
D7
R/W
X
D6
R/W
X
D5
R/W
X
D4
R/W
X
D3
R/W
X
D2
R/W
X
D1
R/W
X
D0
R/W
X
R/W
Reset State
Note: R = Read, W = Write, X = Indeterminate.
Bit
Position Field
D7–D0 T1
Bit
R/W
R
State Description
X
X
T1 Current Value
W
T1 Automatic Reload Value
Range = 1–256 decimal; 01h–00h
Prescaler 1 Register
The Prescaler 1 Register, PRE1, controls clocking functions. READ/WRITE and
reset states for bits D7–D0 are listed in Table 25.
Table 25.Prescaler 1 Register—PRE1 F3h/R243 Bank 0h: WRITE ONLY
Bit
D7
W
X
D6
W
X
D5
W
X
D4
W
X
D3
W
X
D2
W
X
D1
W
0
D0
W
0
R/W
Reset State
Note: W = Write, X = Indeterminate.
Bit
Bit
Position Field
R/W
State Description
D7–D2
D1
Prescaler
W
X
Prescaler Modulo
Range = 1–64 decimal; 01h–00h
Clock
Count
W
W
0
Clock Source
0: T1 External Timing Input (T ) Mode
1: T1 Internal
IN
D0
0
Count Mode
0: T1 Single Pass
1: T1 Modulo N
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
53
Counter/Timer 0 Register
The Counter/Timer 0 Register, T0, controls timing and counter functions. READ/
WRITE and reset states for bits D7–D0 are listed in Table 26.
Table 26.Counter/Timer 0 Register—T0 F4h/R244 Bank 0h: READ/WRITE
Bit
D7
R/W
X
D6
R/W
X
D5
R/W
X
D4
R/W
X
D3
R/W
X
D2
R/W
X
D1
R/W
X
D0
R/W
X
R/W
Reset State
Note: R = Read, W = Write, X = Indeterminate.
Bit
Position Field
D7–D0 T0
Bit
R/W
R
State Description
X
X
T0 Current Value
W
T0 automatic Reload Value
Range = 1–256 decimal
Prescaler 0 Register
The Prescaler 0 Register PRE0 controls clocking functions. WRITE and reset
states for bits D7–D0 are listed in Table 27.
Table 27.Prescaler 0 Register—PRE0 F5h/R245 Bank 0h: WRITE ONLY
Bit
D7
W
X
D6
W
X
D5
W
X
D4
W
X
D3
W
X
D2
W
X
D1
W
X
D0
W
0
R/W
Reset State
Note: W = Write, X = Indeterminate.
Bit
Bit
Position Field
R/W
State Description
D7–D2
Prescaler
W
X
Prescaler Modulo
Range = 1–64 decimal; 01h–00h
D1
D0
Reserved
Count
W
W
X
0
Reserved—must be 0
Count Mode
0: T0 Single Pass
1: T0 Modulo N
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
54
Port 2 Mode Register
The Port 2 Mode Register, P2M, controls Port 2 I/O functions. WRITE and reset
states for bits D7–D0 are listed in Table 28.
Table 28.Port 2 Mode Register—P2M F6h/R246 Bank 0h: WRITE ONLY
Bit
D7
W
1
D6
W
1
D5
W
1
D4
W
1
D3
W
1
D2
W
1
D1
W
1
D0
W
1
R/W
Reset State
Note: W = Write.
Bit
Position Field
D7–D0 P20–P27
Bit
R/W
State Description
W
1
P20–P27 I/O Definition
0: Defines bit as Output
1: Defines bit as Input
Port 3 Mode Register
The Port 3 Mode Register P3M controls Port 3 I/O functions. WRITE and reset
states for bits D7–D0 are listed in Table 29.
Table 29.Port 3 Mode Register—P3M F7h/R247 Bank 0h: WRITE ONLY
Bit
D7
W
0
D6
W
0
D5
W
0
D4
W
0
D3
W
0
D2
W
0
D1
W
0
D0
W
0
R/W
Reset State
Note: W = Write.
Bit
Bit
Position Field
R/W
State Description
D7–D6
D5
Reserved
W
W
00
0
Reserved—must be 00
Port 3
Port 3
0: P31 = Input (T )
IN
P36 = Output (T
)
OUT
1: P31 = DAV2/RDY2
P36 = RDY2/DAV2
D4–D3
Port 3
W
00
Port 3
00: P33 = Input; P34 = Output
01: P33 = Input; P34 = DM
10: P33 = Input; P34 = DM
11: P33 = DAV1/RDY1;
P34 = RDY1/DAV1
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
55
Bit
Bit
Position Field
R/W
State Description
D2
Port 3
W
0
Port 3
0: P32 = Input; P35 = Output
1: P32 = DAV0/RDY0;
P35 = RDY0/DAV0
D1
D0
Port 3
Port 2
W
W
0
0
Port 3
0: P31, P32 DIGITAL mode
1: P31, P32 ANALOG mode
Port 2
0: Open-Drain
1: Push-Pull
Ports 0 and 1 Mode Register
The Ports 0 and 1 Mode Register, P01M, controls port and timing functions for
Ports 0 and 1. WRITE and reset states for bits D7–D0 are listed in Table 30.
Table 30.Ports 0 and 1 Mode Register—P01M F8h/R248 Bank 0h: WRITE ONLY
Bit
D7
W
0
D6
W
1
D5
W
0
D4
W
0
D3
W
1
D2
W
1
D1
W
0
D0
W
1
R/W
Reset State
Note: W = Write.
Bit
Bit
Position Field
R/W
State Description
D7–D6
P04–P07
W
01
P04–P07 Mode*
00: Output
01: Input
1X: A15–A12 (Z86E14x only)
D5
Timing
W
W
0
External Memory Timing
0: Normal
1: Extended
D4–D3
P10–P17
01
P10–P17 Mode*
00: Byte Output
01: Byte Input
10: AD7–AD0
11: High-Impedance AD7–AD0, AS, DS, R/
W, A11–A8, A15–A12, if selected
Note: *For 20- and 28-pin devices, the user must set D7=0, D4=0, D2=1, and D1=0.
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
56
Bit
Bit
Position Field
R/W
State Description
D2
Stack
W
1
Stack Selection*
0: External
1: Internal
D1–D0
P00–P03
W
01
P00–P03 Mode*
00: Output
01: Input
1X: A11–A8 (Z86E14x only)
Note: *For 20- and 28-pin devices, the user must set D7=0, D4=0, D2=1, and D1=0.
Interrupt Priority Register
The Interrupt Priority Register, IPR, prioritizes interrupt functions. WRITE and
reset states for bits D7–D0 are listed in Table 31.
Table 31.Interrupt Priority Register—IPR F9h/R249 Bank 0h: WRITE ONLY
Bit
D7
W
X
D6
W
X
D5
W
X
D4
W
X
D3
W
X
D2
W
X
D1
W
X
D0
W
X
R/W
Reset State
Note: W = Write, X = Indeterminate.
Bit
Bit Position Field
R/W
State Description
D7–D6
D5
Reserved
IRQ3, IRQ5
W
W
XX
X
Reserved—must be 0
IRQ3, IRQ5 Priority (Group A)
0: IRQ5 > IRQ3
1: IRQ3 > IRQ5
D4,D3,D0 Interrupt
W
XXX Interrupt Group Priority
000: Reserved
001: C > A > B
010: A > B > C
011: A > C > B
100: B > C > A
101: C > B > A
110: B > A > C
111: Reserved
D2
IRQ0, IRQ2
W
X
IRQ0, IRQ2 Priority (Group B)
0: IRQ2 > IRQ0
1: IRQ0 > IRQ2
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
57
Bit
Bit Position Field
R/W
State Description
D1
IRQ1, IRQ4
W
X
IRQ1, IRQ4 Priority (Group C)
0: IRQ1 > IRQ4
1: IRQ4 > IRQ1
Interrupt Request Register
The Interrupt Request Register, IRQ, controls interrupt functions. READ/WRITE
and reset states for bits D7–D0 are listed in Table 32.
Table 32.Interrupt Request Register—IRQ FAh/R250 Bank 0h: READ/WRITE
Bit
D7
R/W
0
D6
R/W
0
D5
R/W
0
D4
R/W
0
D3
R/W
0
D2
R/W
0
D1
R/W
0
D0
R/W
0
R/W
Reset
Note: R = Read, W = Write.
Bit
Bit
Position Field
R/W
State Description
D7–D6
Interrupt
R/W
00
Interrupt Edge
Edge
IRQ5
IRQ4
IRQ3
IRQ2
00: P31
01: P31
10: P31
↓
↓
↑
P32
P32
P32
↓
↑
↓
11: P31 ↑↓ P32 ↑↓
D5
D4
D3
D2
R/W
R/W
R/W
R/W
0
0
0
0
Interrupt
IRQ5 = T1
0: No Interrupt pending
1: Interrupt pending
Interrupt
IRQ4 = T0
0: No Interrupt pending
1: Interrupt pending
Interrupt
IRQ3 = P30 Input/UART
0: No Interrupt pending
1: Interrupt pending
Interrupt
IRQ2 = P31 Input
0: No Interrupt pending
1: Interrupt pending
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
58
Bit
Bit
Position Field
R/W
State Description
D1
D0
IRQ1
R/W
0
Interrupt
IRQ1 = P33 Input
0: No Interrupt pending
1: Interrupt pending
IRQ0
R/W
0
Interrupt
IRQ0 = P32 Input
0: No Interrupt pending
1: Interrupt pending
Interrupt Mask Register
The Interrupt Mask Register, IMR, controls interrupt functions. READ/WRITE and
reset states for bits D7–D0 are listed in Table 33.
Table 33.Interrupt Mask Register—IMR FBh/R251 Bank 0h: READ/WRITE
Bit
D7
R/W
0
D6
R/W
X
D5
R/W
X
D4
R/W
X
D3
R/W
X
D2
R/W
X
D1
R/W
X
D0
R/W
X
R/W
Reset
Note: R = Read, W = Write, X = Indeterminate.
Bit
Bit
Position Field
R/W
State Description
D7
MIE
R/W
0
X
X
Master Interrupt Enable
1: Enable interrupts
0: Disable interrupts
D6
RAM Protect
IRQ5–IRQ0
R/W
R/W
RAM Protect
1: Enable RAM Protect
0: Disable RAM Protect
D5–D0
Interrupt Request
1: Enable IRQ0–IRQ5
0: Disable IRQ0–IRQ5
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
59
Flags Register
The CPU sets flags in the Flags Register, FLAGS, to allow the user to perform
tests based on differing logical states. READ/WRITE and reset states for bits D7–
D0 are listed in Table 34.
Table 34.Flags Register—FLAGS FCh/R252 Bank 0h: READ/WRITE
Bit
D7
R/W
X
D6
R/W
X
D5
R/W
X
D4
R/W
X
D3
R/W
X
D2
R/W
X
D1
R/W
X
D0
R/W
X
R/W
Reset
Note: R = Read, W = Write, X = Indeterminate.
Bit
Bit
Position Field
R/W
R/W
State
X
Description
Carry Flag
Zero Flag
D7
D6
D5
D4
D3
D2
D1
D0
Carry
Zero
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
Sign
X
Sign Flag
Overflow
Decimal Adjust
Half Carry
User
X
Overflow Flag
X
Decimal Adjust Flag
Half Carry Flag
User Flag F2*
X
X
User
X
User Flag F1*
Note: *Not affected by RESET.
Register Pointer Register
The Register Pointer Register, RP, controls pointer functions in the working regis-
ters. READ/WRITE and reset states for bits D7–D0 are listed in Table 35.
Table 35.Register Pointer—RP FDh/R253 Bank 0h: READ/WRITE
Bit
D7
R/W
0
D6
R/W
0
D5
R/W
0
D4
R/W
0
D3
R/W
0
D2
R/W
0
D1
R/W
0
D0
R/W
0
R/W
Reset
Note: R = Read, W = Write.
Bit
Position Field
D7–D4 Working
Bit
R/W
State Description
Working Register Pointer
R/W
0
Register
Pointer
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
60
Bit
Position Field
D3–D0 Expanded
Bit
R/W
State Description
R/W
0
Expanded Register File Bank
Register File
Bank
Stack Pointer High Register
The Stack Pointer High Register, SPH, controls pointer functions in the upper
byte. READ/WRITE and reset states for bits D7–D0 are listed in Table 36.
Table 36.Stack Pointer High—SPH FEh/R254 Bank 0h: READ/WRITE
Bit
D7
R/W
0
D6
R/W
0
D5
R/W
0
D4
R/W
0
D3
R/W
0
D2
R/W
0
D1
R/W
0
D0
R/W
0
R/W
Reset
Note: R = Read, W = Write.
Bit
Position Field
D7–D0 SPH
Bit
R/W
R/W
State Description
Stack Pointer Upper Byte* (SP15–SP8)
0
Note: *This register can be employed as a GPR for 20- and 28-pin devices.
Stack Pointer Low Register
The Stack Pointer Low Register, SPL, controls pointer functions in the lower byte.
READ/WRITE and reset states for bits D7–D0 are listed in Table 37.
Table 37.Stack Pointer Low—SPL FFh/R255 Bank 0h: READ/WRITE
Bit
D7
R/W
0
D6
R/W
0
D5
R/W
0
D4
R/W
0
D3
R/W
0
D2
R/W
0
D1
R/W
0
D0
R/W
0
R/W
Reset
Note: R = Read, W = Write.
Bit
Position Field
D7–D0 SPL
Bit
R/W
State Description
Stack Pointer Lower Byte (SP7–SP0)
R/W
0
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
61
ASCI Registers—Expanded Register File, Bank Ah
Bank Ah of the Expanded Register File includes registers that perform ASCI func-
tions.The 8 available registers are the Transmit Data, Receive Data, Multiproces-
sor Control, Extension, Time Constant, and Status registers, as shown in Tables
39 through 46.These eight registers are not reset by a Stop-Mode Recovery. An
additional register, 09h, is available for general purposes. Table 38 lists the reset
states of all 16 ASCI registers.
Table 38.Expanded Register File Registers—Reset States
D7
D6
D5
D4
D3
D2
D1
D0
00h
Reserved
TDR
01h*
02h*
03h*
04h*
05h*
06h*
07h*
08h*
09h
X
X
X
X
0
0
0
1
1
0
X
X
0
0
0
1
1
0
X
X
1
0
0
1
1
0
X
X
0
0
0
1
1
0
X
X
0
1
0
1
1
0
X
X
0
1
1
1
1
0
X
X
0
1
0
1
1
0
RDR
CNTLA
0
CNTLB
0
ASEXT
P30
1
ASTL
ASTH
1
STAT
0
General-Purpose
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
Note: *Not reset with a Stop-Mode Recovery.
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
62
Transmit Data Register
The Transmit Data Register, TDR, monitors data transmission functions in the
FIFO. READ/WRITE and reset states for bits D7–D0 are listed in Table 39.
Table 39.Transmit Data Register—TDR 01h/R1 Bank Ah: READ/WRITE
Bit
D7
R/W
X
D6
R/W
X
D5
R/W
X
D4
R/W
X
D3
R/W
X
D2
R/W
X
D1
R/W
X
D0
R/W
X
R/W
Reset
Note: R = Read, W = Write, X = Indeterminate.
Bit
Position Field
D7–D0 TDR
Bit
R/W
State Description
Transmit Data Register
R/W
X
Receive Data Register
The Receive Data Register, RDR, monitors data receive functions in the FIFO.
READ/WRITE and reset states for bits D7–D0 are listed in Table 40.
Table 40.Receive Data Register—RDR 02h/R2 Bank Ah : READ/WRITE
Bit
D7
R/W
X
D6
R/W
X
D5
R/W
X
D4
R/W
X
D3
R/W
X
D2
R/W
X
D1
R/W
X
D0
R/W
X
R/W
Reset
Note: R = Read, W = Write, X = Indeterminate.
Bit
Position Field
D7–D0 RDR
Bit
R/W
State Description
Receive Data Register
R/W
X
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
63
Control Register A
Control Register A, CNTLA, controls data transmit, receive, and clocking func-
tions. READ/WRITE and reset states for bits D7–D0 are listed in Table 41.
Table 41.Control Register A—CNTLA 03h/R3 Bank Ah: READ/WRITE
Bit
D7
R/W
0
D6
R/W
0
D5
R/W
0
D4
R/W
1
D3
R/W
0
D2
R/W
0
D1
R/W
0
D0
R/W
0
R/W
Reset
Note: R = Read, W = Write.
Bit
Bit
Position Field
R/W
State Description
D7
D6
MPE
RE
R/W
0
Multiprocessor Enable
0: Receive all bytes
1: Filter bytes with MPB = 0
R/W
R/W
0
Receiver Enable
0: ASCI Receiver Disabled
(P30 = Input)
1: ASCI Receiver Enabled
(P30 = RX)
D5
TE
0
Transmitter Enable
0: ASCI Transmitter Disabled
(P37 = Output)
1: ASCI Transmitter Enabled
(P37 = TX)
D4
D3
Reserved
MPBR
EFR
R/W
R
1
0
Reserved
Multiprocessor Bit Received
W
Error Flag Reset
0: Clear Error Latches
1: No Effect
D2–D0
MOD2–0
R
0
Mode Select
MOD2—Number of Data Bits
0: 7 Data Bits
1: 8 Data Bits
Mode Select
MOD1—Parity Enabled
0: No Parity
1: With Parity
Mode Select
MOD0—Number of Stop Bits
0: 1 Stop Bit
1: 2 Stop Bits
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
64
Control Register B
Control Register B, CNTLB, controls multiprocessor, parity, and clock sourcing
functions. READ/WRITE and reset states for bits D7–D0 are listed in Table 42.
Table 42.Control Register B—CNTLB 04h/R4 Bank Ah: READ/WRITE
Bit
D7
R/W
0
D6
R/W
0
D5
R/W
0
D4
R/W
0
D3
R/W
0
D2
R/W
1
D1
R/W
1
D0
R/W
1
R/W
Reset
Note: R = Read, W = Write.
Bit
Bit
Position Field
R/W
State Description
D7
D6
MPBT
MP
R/W
0
Multiprocessor Bit Transmitter
0: Transmit 0 in MPB
1: Transmit 1 in MPB
R/W
0
Multiprocessor Mode
0: MULTIPROCESSOR mode disabled
1: MULTIPROCESSOR mode enabled
(no parity)
D5
D4
D3
D2
PR
W
R/W
R/W
R
0
0
0
1
Prescale
0: BRG ÷ 10
1: BRG ÷ 30
PEO
DR
Parity Even/Odd
0: Even Parity
1: Odd Parity
Divide Ratio
0: Divide by 16
1: Divide by 64
SS2
Clock Source and Speed Bits
SS2
0: ÷1, ÷2, ÷4, ÷8
1: ÷16, ÷32, ÷64, Reserved
D1
D0
SS1
SS0
R
R
1
1
Clock Source and Speed Bits
SS1
0: ÷1, ÷2, ÷16, ÷32
1: ÷4, ÷8, ÷64, Reserved
Clock Source and Speed Bits
SS0
0: ÷1, ÷4, ÷16, ÷64
1: ÷2, ÷8, ÷32, Reserved
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
65
ASCI Extension Control Register
The ASCI Extension Control Register, ASEXT, controls ASCI transmission func-
tions. READ/WRITE and reset states for bits D7–D0 are listed in Table 43.
Table 43.Extension Control Register—ASEXT 05h/R5 Bank Ah: READ/WRITE
Bit
D7
R
D6
R/W
0
D5
R/W
0
D4
R/W
0
D3
R/W
0
D2
R/W
0
D1
R
D0
R/W
0
R/W
Reset
X
1
Note: R = Read, W = Write.
Bit
Bit
Position Field
R/W
R
State Description
D7
D6
D5
D4
D3
RX
X
0
0
0
0
RX Data State
Reserved
Reserved
Reserved
Reserved
BRG
R/W
R/W
R/W
R/W
Reserved
Reserved (must be 0)
Baud Rate Generator Mode
0: Use SS Selection
1: Use ASTH or ASTL Value
D2
D1
D0
RIS
BD
SB
R/W
R
0
1
0
RX Interrupt on Start Bit
0: No IRQ on Start Bit
1: IRQ3 on Start Bit
Break Detect
0: Valid Data Byte
1: Break Detected
R/W
Send Break
0: Normal Operation
1: Send Break
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
66
ASCI Time Constant Low Register
The ASCI Time Constant Low Register, ASTL, controls transmission functions in
the lower byte. READ/WRITE and reset states for bits D7–D0 are listed in
Table 44.
Table 44.Time Constant Low Register—ASTL 06h/R6 Bank Ah: READ/WRITE
Bit
D7
R/W
1
D6
R/W
1
D5
R/W
1
D4
R/W
1
D3
R/W
1
D2
R/W
1
D1
R/W
1
D0
R/W
1
R/W
Reset
Note: R = Read, W = Write.
Bit
Position Field
D7–D0 ASTL
Bit
R/W
State Description
ASCI Time Constant Low
R/W
1
ASCI Time Constant High Register
The ASCI Time Constant High Register, ASTH, controls transmission functions in
the upper byte. READ/WRITE and reset states for bits D7–D0 are listed in
Table 45.
Table 45.Time Constant Register High—ASTH 07h/R7 Bank Ah: READ/WRITE
Bit
D7
R/W
1
D6
R/W
1
D5
R/W
1
D4
R/W
1
D3
R/W
1
D2
R/W
1
D1
R/W
1
D0
R/W
1
R/W
Reset
Note: R = Read, W = Write.
Bit
Position Field
D7–D0 ASTH
Bit
R/W
State Description
ASCI Time Constant High
R/W
1
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
67
ASCI Status Register
The ASCI Status Register, STAT, controls status functions. READ/WRITE and
reset states for bits D7–D0 are listed in Table 46.
Table 46.Status Register—STAT 08h/R8 Bank Ah: READ/WRITE
Bit
D7
R
D6
R
D5
R
D4
R
D3
R/W
0
D2
R/W
0
D1
R
D0
R/W
0
R/W
Reset
0
0
0
0
0
Note: R = Read, W = Write.
Bit
Bit
Position Field
R/W
State Description
D7
D6
D5
D4
D3
RDRNE
R
0
0
0
0
0
Receive Data Register Not Empty
0: Receive FIFO Empty
1: Receive FIFO contains 1 or more bytes
OE
PE
FE
R
R
Overrun Error
0: Receive OK
1: Next byte is a FIFO overrun
Parity Error
0: Parity OK
1: Parity Error
R
Framing Error
0: Receive OK
1: Framing Error
RIE
R/W
Receive Interrupt Enable
0: No IRQ on Receive
1: Enable Receiver Interrupt
D2
D1
Reserved
TDRE
R/W
R
0
0
Reserved
Transmit Data Register Empty
0: Transmitter Working
1: Transmit Buffer Empty
D0
TIE
R/W
0
Transmit Interrupt Enable
0: No IRQ on Transmit
1: IRQ3 on TDRE
↑
Expanded Register File, Bank Fh
Expanded Register File Fh Bank 0h contains 5 registers that perform the Port
Configuration, Verify, Stop-Mode Recovery, and Watch-Dog Timer Mode func-
tions, as shown in Tables 49 through 52.These 5 registers are not reset by a
Stop-Mode Recovery. Table 47 lists the reset states of all 5 Bank 0h registers.
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
68
Table 47.Expanded Register File Registers—Reset States
D7
D6
D5
D4
D3
D2
D1
D0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
PCON*
1
1
1
1
1
1
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMR*
0
X
X
0
X
X
1
X
X
0
X
0
0
X
1
0
X
1
0
0
0
0
0
1
Reserved
SMR2*
Reserved
WDTMR*
Note: *Not reset with a Stop-Mode Recovery.
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
69
Port Configuration Register
The Port Configuration Register, PCON, controls the configurations of Ports 0, 1,
2, and 3. WRITE and reset states for bits D7–D0 are listed in Table 48.
Table 48.Port Configuration Register—PCON 00h/R0 Bank Fh:WRITE ONLY
Bit
D7
W
1
D6
W
1
D5
W
1
D4
W
1
D3
W
1
D2
W
1
D1
W
1
D0
W
0
R/W
Reset
Note: W = Write.
Bit
Bit
Position Field
R/W
State Description
Low-EMI Oscillator
D7
Oscillator
W
1
1
1
1
1
1
1
0
0: Low EMI
1: Standard
D6
Port 3 I/O
W
W
W
W
W
W
W
Port 3
0: Low EMI
1: Standard
D5
Port 2 I/O
Port 1 I/O
Port 0 I/O
Port 0 I/O
Port 1 I/O
Port 3
Port 2
0: Low EMI
1: Standard
D4
Port 1*
0: Low EMI
1: Standard
D3
Port 0†
0: Low EMI
1: Standard
D2
Port 0
0: Open-Drain
1: Push-Pull Active
†
D1
Port 1*
0: Open-Drain
1: Push-Pull Active
D0
Port 3 Comparator Output
0: P34, P37 Standard Output
1: P34, P37 Comparator Output
Notes:
1. Must be set to 1 when using an emulator.
2. Must be set to 1 for both 20- and 28-pin devices.
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
70
Verify Register
The Verify Register, VFY, is only available after the ICSP unlock sequence exe-
cutes. READ and reset states for bits D7–D0 are listed in Table 49. For more infor-
mation on the VFY register, please see the MUZE Programming Specification.
Table 49.Verify Register—VFY 09h/R09 Bank Fh: READ ONLY
Bit
D7
R
D6
R
D5
R
D4
R
D3
R
D2
R
D1
R
D0
R
R/W
Reset
X
X
X
X
X
X
X
X
Note: R = Read, X = Indeterminate.
Bit
Bit
Position Field
R/W
R
State Description
D7–D2
D1
Reserved
X
X
Reserved
VFY1
R
Verify 1
Programming verification result is output at
this register
D0
VFY0
R
X
Verify 0
Programming verification result is output at
this register
Stop-Mode Recovery Register
The Stop-Mode Recovery Register, SMR, controls clocking functions. READ/
WRITE and reset states for bits D7–D0 are listed in Table 50.
Table 50.Stop-Mode Recovery Register—SMR 0Bh/R11 Bank Fh:READ/WRITE
Bit
D7
R
D6
W
0
D5
W
1
D4
W
0
D3
W
0
D2
W
0
D1
W
0
D0
W
0
R/W
Reset
0
Note: R = Read, W = Write.
Bit
Bit
Position Field
R/W
State Description
D7
Stop
R
0
Stop Flag
0: POR
1: Stop Recovery
Notes:
1. For the Stop-Mode Recovery Source, either SMR or SMR2 can be selected. If SMR is used to
select the Stop-Mode Recovery Source, bits D1–D0 of SMR2 must be 0.
2. Cleared by RESET and SMR.
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
71
Bit
Bit
Position Field
R/W
State Description
D6
Stop-Mode
W
0
Stop-Mode Recovery Level
Recovery
0: Low
1: High
D5
Stop Delay
W
W
1
Stop Delay
0: Off
1: On
D4–D2
Stop Mode
000 Stop-Mode Recovery Source*
000: POR only and/or external RESET
001: P30
010: P31
011: P32
100: P33
101: P27
110: P2 NOR 0–3
111: P2 NOR 0–7
D1
Clock
W
W
0
0
External Clock Divide-by-2
0: SCLK ÷ TCLK = Crystal ÷ 2
1: SCLK = Crystal
D0
SCLK/TCLK
SCLK/TCLK Divide-by-16
0: Off
1: On
Notes:
1. For the Stop-Mode Recovery Source, either SMR or SMR2 can be selected. If SMR is used to
select the Stop-Mode Recovery Source, bits D1–D0 of SMR2 must be 0.
2. Cleared by RESET and SMR.
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
72
Stop-Mode Recovery Register 2
The Stop-Mode Recovery Register, SMR2, controls additional Port 2 clocking
functions. WRITE and reset states for bits D7–D0 are listed in Table 51.
Table 51.Stop-Mode Recovery Register 2—SMR2 0Dh/R13 Bank Fh:WRITE ONLY
Bit
D7
W
X
D6
W
X
D5
W
X
D4
W
X
D3
W
X
D2
W
X
D1
W
0
D0
W
0
R/W
Reset
Note: W = Write, X = Indeterminate.
Bit
Bit
Position Field
R/W
W
State Description
D7–D2
D1–D0
Reserved
STOP Mode
X
Reserved—must be 0
W
00
Stop-Mode Recovery Source 2*
00: POR only
01: AND P20, P21, P22, P23
10: AND P20, P21, P22, P23, P24, P25,
P26, P27
Note: For the Stop-Mode Recovery Source, either SMR or SMR2 can be selected. If SMR2 is used
to select the Stop-Mode Recovery Source, bits D4–D2 of SMR must be 0.
Watch-Dog Timer Mode Register
The Watch-Dog Timer Mode Register, WDTMR, controls Watch-Dog Timer func-
tions. WRITE and reset states for bits D7–D0 are listed in Table 52.
Table 52.Watch-Dog Timer Mode Register—WDTMR 0Fh/R15 Bank Fh: WRITE ONLY
Bit
D7
W
X
D6
W
X
D5
W
X
D4
W
0
D3
W
1
D2
W
1
D1
W
0
D0
W
1
R/W
Reset
Note: W = Write, X = Indeterminate.
Bit
Bit
Position Field
R/W State Description
D7–D5
D4
Reserved
W
W
X
0
Reserved—must be 0
X
Crystal Input/Internal RC Select for WDT
0: On-Board RC
IN
1: Crystal
Note: Not used in conjunction with SMR Source.
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
73
Bit
Bit
Position Field
R/W State Description
D3
WDT
W
W
W
1
WDT During STOP
0: WDT disabled during STOP mode
1: WDT enabled during STOP mode
D2
WDT
1
WDT During HALT
0: WDT disabled during HALT mode
1: WDT enabled during HALT mode
D1–D0
WDT Tap
01 WDT Tap Int. RC Osc. System Clock
00:
01:
10:
11:
3.5ms
7 ms
14 ms
56 ms
128 SCLK
256 SCLK
512 SCLK
2048 SCLK
Note: Not used in conjunction with SMR Source.
PS004005-1100
P R E L I M I N A R Y
Control Registers
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
74
Interrupts
Interrupt Block Diagram
Figure 24. Interrupt Block Diagram
IRQ0 IRQ2
IRQ1, 3, 4, 5
Interrupt
Edge
IRQ (D6, D7)
Select
IRQ
IMR
IPR
6
Global
Interrupt
Enable
Interrupt
Request
PRIORITY
LOGIC
Vector Select
PS004005-1100
P R E L I M I N A R Y
Interrupts
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
75
Electrical Characteristics
Absolute Maximum Ratings
Stresses greater than the Absolute Maximum Ratings listed in Table 53 may
cause permanent damage to the device. This rating is a stress rating only. Func-
tional operation of the device at any condition above those indicated in the opera-
tional sections of these specifications is not implied. Exposure to absolute
maximum rating conditions for an extended period may affect device reliability.
Table 53.Absolute Maximum Ratings
Parameter
Min
–40
Max
+105
+150
+7
Units
C
Notes
Ambient Temperature under Bias
Storage Temperature
–65
C
Voltage on any Pin with Respect to V
–0.6
–0.3
–0.6
V
1
2
SS
Voltage on V
Pin with Respect to V
+7
V
DD
SS
Voltage on X and RESET Pins with Respect to V
V
+1
V
IN
DD
SS
Total Power Dissipation
1.21
W
Maximum Allowable Current out of V
220
180
+600
+600
25
mA
mA
µA
µA
mA
mA
SS
Maximum Allowable Current into V
DD
Maximum Allowable Current into an Input Pin
–600
–600
3
4
Maximum Allowable Current into an Open-Drain Pin
Maximum Allowable Output Current Sunk by Any I/O Pin
Maximum Allowable Output Current Sourced by Any I/O Pin
25
Notes:
1. Applies to all pins except Crystal pins and where otherwise noted.
2. There is no input protection diode from pin to V
3. Excludes Crystal pins.
4. Device pin is not at an output Low state.
and current into pin is limited to 600 µA.
DD
Total power dissipation should not exceed 1.21 W for the package. Power dissipa-
tion is calculated as follows:
Total Power Dissipation = V x [I – (sum of I ),
DD
DD
OH
+ sum of [(V – V ) x I ]
OH
DD
OH
+ sum of (V x I
)
OL
OL
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
76
DC Electrical Characteristics
Standard Temperature Range
Table 54.DC Electrical Characteristics at Standard Temperature
T =
A
0°C to +70°C
2
Typical
Sym
Parameter
V
Min
Max
@25°C
Units Conditions
Notes
CC1
V
Clock Input
High Voltage
4.5V
5.5V
4.5V
5.5V
0.7 V
V
V
+0.3
1.8
V
V
V
V
Driven by
External Clock
Generator
CH
CC
CC
CC
CC
0.7 V
+0.3
2.6
1.2
2.1
Driven by
External Clock
Generator
V
Clock Input
Low Voltage
GND–0.3
GND–0.3
0.2 V
0.2 V
Driven by
External Clock
Generator
CL
CC
Driven by
CC
External Clock
Generator
V
V
Input High
Voltage
4.5V
5.5V
4.5V
5.5V
0.7 V
0.7 V
V
V
+0.3
+0.3
1.8
2.6
1.1
1.6
V
V
V
V
IH
CC
CC
CC
CC
Input Low
Voltage
GND–0.3
GND–0.3
0.2 V
IL
CC
CC
0.2 V
Notes:
1. The
V
voltage specification of 4.5V guarantees 3.3V 0.3V with typicals at
V
= 3.3V, and the V voltage
CC
CC
specification of 5.5V guarantees 5.0V 0.5V with typicals at
CC
V
= 5.0V.
CC
2. Typical voltage is
3. STANDARD Mode (not Low-EMI Mode).
V
= 5.0V and 3.3V.
CC
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at
8. Clock must be forced Low, when X is clock-driven and X
V
.
CC
is floating.
IN
OUT
9. 0ºC to 70ºC (standard temperature).
10.Autolatch (Mask Option) selected.
11.The V voltage increases as the temperature decreases and overlaps lower
V
operating region. See
CC
LV
Figure 23 on page 49
12.–40˚C to 150˚C (extended temperature).
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
77
Table 54.DC Electrical Characteristics at Standard Temperature (Continued)
T =
A
0°C to +70°C
2
Typical
Sym
Parameter
V
Min
Max
@25°C
Units Conditions
Notes
CC1
V
Output High
Voltage
(Low-EMI
Mode)
4.5V
5.0V
V
V
–0.4
3.1
V
V
I
= –0.5 mA
= –0.5 mA
OH
CC
CC
OH
OH
–0.4
4.8
I
V
V
Output High
Voltage
4.5V
5.5V
4.5V
5.0V
V
V
–0.4
–0.4
3.1
4.8
0.2
0.1
V
V
V
V
I
I
I
I
= –2.0 mA
= –2.0 mA
= 1.0 mA
= 1.0 mA
3
3
OH1
CC
OH
OH
OL
OL
CC
Output Low
Voltage
(Low-EMI
Mode)
0.6
0.4
OL
V
V
V
V
V
Output Low
Voltage
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
0.6
0.4
1.2
1.2
0.2
0.1
0.3
0.4
1.8
2.6
1.1
1.6
0.3
0.3
V
V
V
V
V
V
V
V
V
V
I
I
I
I
= +4.0 mA
= +4.0 mA
= +6 mA
3
3
3
3
4
4
4
4
4
4
OL1
OL2
RH
OL
OL
OL
OL
Output Low
Voltage
= +12 mA
Reset Input
High Voltage
0.8 V
0.8 V
V
CC
CC
CC
V
CC
Reset Input
Low Voltage
GND–0.3
GND–0.3
0.2 V
0.2 V
Rl
CC
CC
Reset Output 4.5V
Low Voltage
0.6
0.6
I
I
= +1.0 mA
= +1.0 mA
OLR
OL
5.5V
OL
Notes:
1. The
V
voltage specification of 4.5V guarantees 3.3V 0.3V with typicals at
V
= 3.3V, and the V voltage
CC
CC
specification of 5.5V guarantees 5.0V 0.5V with typicals at
CC
V
= 5.0V.
CC
2. Typical voltage is
3. STANDARD Mode (not Low-EMI Mode).
V
= 5.0V and 3.3V.
CC
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at
8. Clock must be forced Low, when X is clock-driven and X
V
.
CC
is floating.
IN
OUT
9. 0ºC to 70ºC (standard temperature).
10.Autolatch (Mask Option) selected.
11.The V voltage increases as the temperature decreases and overlaps lower
V
operating region. See
CC
LV
Figure 23 on page 49
12.–40˚C to 150˚C (extended temperature).
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
78
Table 54.DC Electrical Characteristics at Standard Temperature (Continued)
T =
A
0°C to +70°C
2
Typical
Sym
Parameter
V
Min
Max
@25°C
Units Conditions
Notes
CC1
V
Comparator
Input Offset
Voltage
4.5V
5.5V
25
25
10
mV
mV
5
5
OFFSET
10
I
I
I
I
Input
Leakage
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
–1
–1
2
2
0.004
0.004
0.004
0.004
–60
–85
7
µA
µA
µA
µA
µA
µA
V
V
V
V
= 0V, V
= 0V, V
= 0V, V
= 0V, V
IL
IN
IN
IN
IN
CC
CC
CC
CC
Output
Leakage
–1
1
OL
IR
–1
1
Reset Input
Current
–20
–20
–130
–180
20
25
15
20
Supply
Current
mA @ 16 MHz
mA @ 16 MHz
mA @ 12 MHz
mA @ 12 MHz
6
6
6
6
CC
20
5
15
Notes:
1. The
V
voltage specification of 4.5V guarantees 3.3V 0.3V with typicals at
V
= 3.3V, and the
V
voltage
CC
specification of 5.5V guarantees 5.0V 0.5V with typicals at
CC
CC
V
= 5.0V.
CC
2. Typical voltage is
3. STANDARD Mode (not Low-EMI Mode).
V
= 5.0V and 3.3V.
CC
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at
8. Clock must be forced Low, when X is clock-driven and X
V
.
CC
is floating.
IN
OUT
9. 0ºC to 70ºC (standard temperature).
10.Autolatch (Mask Option) selected.
11.The V voltage increases as the temperature decreases and overlaps lower
V
operating region. See
CC
LV
Figure 23 on page 49
12.–40˚C to 150˚C (extended temperature).
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
79
Table 54.DC Electrical Characteristics at Standard Temperature (Continued)
T =
A
0°C to +70°C
2
Typical
Sym
I
Parameter
V
Min
Max
@25°C
Units Conditions
Notes
CC1
Standby
Current
(HALT mode)
4.5V
5.5V
4.5V
4.5
2.0
mA
V
= 0V, V
6
CC1
IN
CC
CC
@ 16 MHz
8
3.7
1.5
mA
V
= 0V, V
6
6
IN
@ 16 MHz
3.4
mA Clock Divide-
by-16 @ 16
MHz
5.5V
4.5V
5.5V
4.5V
5.5V
7.0
8
2.9
2
mA Clock Divide-
by-16 @ 16
MHz
6
I
Standby
Current
(STOP
Mode)
µA
µA
µA
µA
V
= 0V, V
7,8
CC2
IN
CC
CC
CC
CC
WDT is not
Running
10
4
V
= 0V, V
7,8
IN
WDT is not
Running
500
800
310
600
V
= 0V, V
7,8,9
7,8,9
IN
WDT is
Running
V
= 0V, V
IN
WDT is
Running
Notes:
1. The
V
voltage specification of 4.5V guarantees 3.3V 0.3V with typicals at
V
= 3.3V, and the
V
voltage
CC
specification of 5.5V guarantees 5.0V 0.5V with typicals at
CC
CC
V
= 5.0V.
CC
2. Typical voltage is
3. STANDARD Mode (not Low-EMI Mode).
V
= 5.0V and 3.3V.
CC
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at
8. Clock must be forced Low, when X is clock-driven and X
V
.
CC
is floating.
IN
OUT
9. 0ºC to 70ºC (standard temperature).
10.Autolatch (Mask Option) selected.
11.The V voltage increases as the temperature decreases and overlaps lower
V
operating region. See
CC
LV
Figure 23 on page 49
12.–40˚C to 150˚C (extended temperature).
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
80
Table 54.DC Electrical Characteristics at Standard Temperature (Continued)
T =
A
0°C to +70°C
2
Typical
Sym
Parameter
V
Min
Max
@25°C
Units Conditions
Notes
CC1
V
Input
Common
Mode
4.5V
5.5V
0
V
V
–1.0V
V
V
5
5
ICR
CC
0
–1.0V
CC
Voltage
Range
I
I
Autolatch
Low Current
4.5V
5.5V
4.5V
5.5V
4.5V
0.7
1.4
8
3
5
µA 0V<V <V
10
10
ALL
IN CC
15
–5
–8
µA 0V<V <V
IN CC
Autolatch
High Current
–0.6
–1.0
–3
–6
2.8
µA 0V<V <V
10
ALH
IN CC
µA 0V<V <V
10
IN CC
V
V
Low
V
V
4 MHz max
Interrupt CLK
Freq.
11,12
LV
CC
Voltage
Protection
Voltage
5.5V
2.2
3.1
2.8
6 MHz max
Interrupt CLK
Freq.
9,11
Notes:
1. The
V
voltage specification of 4.5V guarantees 3.3V 0.3V with typicals at
V
= 3.3V, and the V voltage
CC
CC
specification of 5.5V guarantees 5.0V 0.5V with typicals at
CC
V
= 5.0V.
CC
2. Typical voltage is
3. STANDARD Mode (not Low-EMI Mode).
V
= 5.0V and 3.3V.
CC
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at
8. Clock must be forced Low, when X is clock-driven and X
V
.
CC
is floating.
IN
OUT
9. 0ºC to 70ºC (standard temperature).
10.Autolatch (Mask Option) selected.
11.The V voltage increases as the temperature decreases and overlaps lower
V
operating region. See
CC
LV
Figure 23 on page 49
12.–40˚C to 150˚C (extended temperature).
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
81
Extended Temperature Range
Table 55.DC Electrical Characteristics at Extended Temperature
T =
A
–40°C to +105°C
2
Typical
Sym
Parameter
V
Min
Max
@25°C
Units Conditions
Notes
CC1
V
Clock Input
High Voltage
4.5V
5.5V
4.5V
5.5V
0.7 V
V
V
+0.3
1.8
V
V
V
V
Driven by
External Clock
Generator
CH
CC
CC
CC
0.7 V
+0.3
2.6
1.2
2.1
Driven by
External Clock
Generator
CC
V
Clock Input
Low Voltage
GND–0.3
GND–0.3
0.2 V
Driven by
External Clock
Generator
CL
CC
CC
0.2 V
Driven by
External Clock
Generator
V
V
V
Input High
Voltage
4.5V
5.5V
4.5V
5.5V
4.5V
5.0V
0.7 V
0.7 V
V
V
+0.3
+0.3
1.8
2.6
1.1
1.6
3.1
4.8
V
V
V
V
V
V
IH
CC
CC
CC
CC
Input Low
Voltage
GND–0.3
GND–0.3
0.2 V
IL
CC
CC
0.2 V
Output High
Voltage
(Low-EMI
Mode)
V
V
–0.4
I
I
= –0.5 mA
= –0.5 mA
OH
CC
CC
OH
–0.4
OH
V
Output High
Voltage
4.5V
5.5V
V
V
–0.4
–0.4
3.1
4.8
V
V
I
I
= –2.0 mA
= –2.0 mA
3
3
OH1
CC
OH
CC
OH
Notes:
1. The
V
voltage specification of 5.5V guarantees 5.0V 0.5V with typicals at
V
= 5.0V.
CC
CC
2. Typicals are at
V
= 5.0V and 3.3V.
CC
3. STANDARD Mode (not Low EMI).
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at
V
IN
.
CC
8. Clock must be forced Low, when X is clock-driven and X
is floating.
OUT
9. 0ºC to 70ºC (standard temperature).
10. Autolatch (Mask Option) selected.
11. The V voltage increases as the temperature decreases and overlaps lower
V
operating region.
LV
CC
12. –40˚C to 150˚C (extended temperature).
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
82
Table 55.DC Electrical Characteristics at Extended Temperature (Continued)
T =
A
–40°C to +105°C
2
Typical
Sym
Parameter
V
Min
Max
0.6
@25°C
Units Conditions
Notes
CC1
V
Output Low
Voltage
(Low-EMI
Mode)
4.5V
5.0V
0.2
V
V
I
= 1.0 mA
= 1.0 mA
OL
OL
OL
0.4
0.1
I
V
V
V
V
V
V
Output Low
Voltage
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
0.6
0.4
1.2
1.2
0.2
0.1
0.3
0.4
1.8
2.6
1.1
1.6
0.3
0.3
10
V
V
I
I
I
I
= +4.0 mA
= +4.0 mA
= +6 mA
3
3
3
3
4
4
4
4
4
4
5
5
OL1
OL2
RH
OL
OL
OL
OL
Output Low
Voltage
V
V
= +12 mA
Reset Input
High Voltage
0.8 V
0.8 V
V
V
V
CC
CC
CC
V
CC
Reset Input
Low Voltage
GND–0.3
GND–0.3
0.2 V
0.2 V
V
Rl
CC
V
CC
Reset Output 4.5V
Low Voltage
0.6
0.6
25
V
I
I
= +1.0 mA
= +1.0 mA
OLR
OFFSET
OL
5.5V
V
OL
Comparator
Input Offset
Voltage
4.5V
5.5V
mV
mV
25
10
I
I
Input
Leakage
4.5V
5.5V
4.5V
5.5V
–1
–1
–1
–1
2
2
2
2
0.004
0.004
0.004
0.004
µA
µA
µA
µA
V
V
V
V
= 0V, V
= 0V, V
= 0V, V
= 0V, V
IL
IN
IN
IN
IN
CC
CC
CC
CC
Output
Leakage
OL
Notes:
1. The
V
voltage specification of 5.5V guarantees 5.0V 0.5V with typicals at
V
= 5.0V.
CC
CC
2. Typicals are at
V
= 5.0V and 3.3V.
CC
3. STANDARD Mode (not Low EMI).
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at
V
IN
.
CC
8. Clock must be forced Low, when X is clock-driven and X
is floating.
OUT
9. 0ºC to 70ºC (standard temperature).
10. Autolatch (Mask Option) selected.
11. The V voltage increases as the temperature decreases and overlaps lower
V
operating region.
CC
LV
12. –40˚C to 150˚C (extended temperature).
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
83
Table 55.DC Electrical Characteristics at Extended Temperature (Continued)
T =
A
–40°C to +105°C
2
Typical
Sym
Parameter
V
Min
–18
–18
Max
–130
–180
20
@25°C
–60
–85
7
Units Conditions
µA
Notes
CC1
I
Reset Input
Current
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
IR
µA
I
Supply
Current
mA @ 16 MHz
mA @ 16 MHz
mA @ 12 MHz
mA @ 12 MHz
6
6
6
6
6
CC
25
20
15
5
20
15
I
Standby
Current
(HALT mode)
4.5
2.0
mA
V
= 0V, V
CC1
IN
CC
CC
@ 16 MHz
5.5V
4.5V
8
3.7
1.5
mA
V
= 0V, V
6
6
IN
@ 16 MHz
3.4
mA Clock Divide-
by-16 @ 16
MHz
5.5V
7.0
2.9
mA Clock Divide-
by-16 @ 16
MHz
6
Notes:
1. The
V
voltage specification of 5.5V guarantees 5.0V 0.5V with typicals at
V
= 5.0V.
CC
CC
2. Typicals are at
V
= 5.0V and 3.3V.
CC
3. STANDARD Mode (not Low EMI).
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at
V
IN
.
CC
8. Clock must be forced Low, when X is clock-driven and X
is floating.
OUT
9. 0ºC to 70ºC (standard temperature).
10. Autolatch (Mask Option) selected.
11. The V voltage increases as the temperature decreases and overlaps lower
V
operating region.
LV
CC
12. –40˚C to 150˚C (extended temperature).
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
84
Table 55.DC Electrical Characteristics at Extended Temperature (Continued)
T =
A
–40°C to +105°C
2
Typical
Sym
Parameter
V
Min
Max
@25°C
Units Conditions
Notes
CC1
I
Standby
Current
(STOP
Mode)
4.5V
5.5V
4.5V
5.5V
8
2
µA
µA
µA
µA
V
= 0V, V
7,8
CC2
IN
CC
CC
CC
CC
WDT is not
Running
10
4
V
= 0V, V
7,8
IN
WDT is not
Running
600
310
600
V
= 0V, V
7,8,9
7,8,9
IN
WDT is
Running
1000
V
= 0V, V
IN
WDT is
Running
V
Input
Common
Mode
4.5V
5.5V
0
0
V
V
–1.5V
V
V
5
5
ICR
CC
–1.5V
CC
Voltage
Range
I
Autolatch
Low Current
4.5V
5.5V
0.7
1.4
10
20
3
5
µA 0V<V <V
10
10
ALL
IN CC
µA 0V<V <V
IN CC
Notes:
1. The
V
voltage specification of 5.5V guarantees 5.0V 0.5V with typicals at
V
= 5.0V.
CC
CC
2. Typicals are at
V
= 5.0V and 3.3V.
CC
3. STANDARD Mode (not Low EMI).
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at
V
IN
.
CC
8. Clock must be forced Low, when X is clock-driven and X
is floating.
OUT
9. 0ºC to 70ºC (standard temperature).
10. Autolatch (Mask Option) selected.
11. The V voltage increases as the temperature decreases and overlaps lower
V
operating region.
CC
LV
12. –40˚C to 150˚C (extended temperature).
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
85
Table 55.DC Electrical Characteristics at Extended Temperature (Continued)
T =
A
–40°C to +105°C
2
Typical
Sym
Parameter
V
Min
–0.6
–1.0
2.0
Max
–7
@25°C
Units Conditions
µA 0V<V <V
Notes
10
CC1
I
Autolatch
High Current
4.5V
5.5V
4.5V
–3
ALH
IN CC
–10
3.3
–6
µA 0V<V <V
10
IN CC
V
V
Low
2.8
V
4 MHz max
11,12
LV
CC
Voltage
Interrupt CLK
Freq.
Protection
Voltage
5.5V
2.8
6 MHz max
Interrupt CLK
Freq.
9,11
Notes:
1. The
V
voltage specification of 5.5V guarantees 5.0V 0.5V with typicals at
V
= 5.0V.
CC
CC
2. Typicals are at
V
= 5.0V and 3.3V.
CC
3. STANDARD Mode (not Low EMI).
4. Not applicable to devices in 28-pin packages.
5. For analog comparator, inputs when analog comparators are enabled.
6. All outputs unloaded, I/O pins floating, inputs at rail.
7. Same as note 6, except inputs at
V
IN
.
CC
8. Clock must be forced Low, when X is clock-driven and X
is floating.
OUT
9. 0ºC to 70ºC (standard temperature).
10. Autolatch (Mask Option) selected.
11. The V voltage increases as the temperature decreases and overlaps lower
V
operating region.
LV
CC
12. –40˚C to 150˚C (extended temperature).
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
86
AC Electrical Characteristics
Figure 25 illustrates the timing characteristics of the MUZE Family of parts with
respect to external input/output sources. See Tables 56 and 57 for descriptions of
the numbered timing parameters in the figure.
Figure 25. External I/O or Memory READ and WRITE Timing
R/W
Port 0, DM
Port 1
13
19
12
16
20
3
18
1
D7–D0 IN
A7–A0
2
9
AS
8
11
4
5
6
DS
(Read)
17
10
Port1
A7–A0
D7–D0 OUT
14
15
7
DS
(Write)
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
87
Standard Temperature Range
Table 56.External I/O or Memory READ and WRITE Timing—Standard Temperature
T = –0ºC to 70ºC
A
@ 12 MHz
1
No
Symbol
T A(AS)
Parameter
V
Min
35
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
CC
1
Address Valid to AS Rise
Delay
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
2
2
D
35
2
T AS(A)
AS Rise to Address Float
Delay
45
2
D
45
2
3
T AS(DR)
AS Rise to Read Data
Req’d Valid
250
250
2,3
2
D
4
T AS
AS Low Width
55
55
2
W
2
5
T AS(DS)
Address Float to DS Fall
DS (Read) Low Width
DS (WRITE) Low Width
0
D
0
6
T DSR
200
200
110
110
2,3
2,3
2,3
2,3
2,3
2,3
2
W
7
T DSW
W
8
T DSR(DR)
DS Fall to Read Data
Req’d Valid
150
150
D
9
T DR(DS)
Read Data to DS Rise Hold
Time
0
H
0
2
10
11
12
Notes:
T DS(A)
DS Rise to Address Active
Delay
45
55
30
45
45
45
2
D
2
T DS(AS)
DS Rise to AS Fall Delay
2
D
2
T R/W(AS)
R/W Valid to AS Rise Delay 4.5V
5.5V
2
D
2
1. Z86E142/E143/E144/E145/E146 only; SCLK ÷ TCLK = Crystal ÷ 2.
2. The voltage specification of 5.5V guarantees 5.0V 0.5V.
V
CC
3. Timing numbers provided are for minimum T C.
P
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
88
Table 56.External I/O or Memory READ and WRITE Timing—Standard Temperature (Continued)
T = –0ºC to 70ºC
A
@ 12 MHz
1
No
Symbol
T DS(R/W)
Parameter
V
Min
45
45
55
55
45
45
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
CC
13
DS Rise to R/W Not Valid
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
2
2
D
14
T DW(DSW)
WRITE Data Valid to DS
Fall (WRITE) Delay
2
D
2
15
T DS(DW)
DS Rise to WRITE Data
Not Valid Delay
2
D
2
16
T A(DR)
Address Valid to Read
Data Req’d Valid
310
310
2,3
2,3
2
D
17
T AS(DS)
AS Rise to DS Fall Delay
DM Valid to AS Fall Delay
DS Rise to DM Valid Delay
65
65
35
35
45
45
45
45
D
2
18
T DM(AS)
2
D
2
19
T DS(DM)
2
D
2
20
T DS(AS)
DS Valid to Address Valid
Hold Time
2
H
2
Notes:
1. Z86E142/E143/E144/E145/E146 only; SCLK ÷ TCLK = Crystal ÷ 2.
2. The voltage specification of 5.5V guarantees 5.0V 0.5V.
V
CC
3. Timing numbers provided are for minimum T C.
P
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
89
Extended Temperature Range
Table 57.External I/O or Memory READ and WRITE Timing—Extended Temperature
T = –40ºC to
A
+105ºC @ 12 MHz
1
No
Symbol
T A(AS)
Parameter
V
Min
35
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
CC
1
Address Valid to AS Rise
Delay
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
2
2
D
35
2
T AS(A)
AS Rise to Address Float
Delay
45
2
D
45
2
3
T AS(DR)
AS Rise to Read Data
Req’d Valid
250
250
2,3
2
D
4
T AS
AS Low Width
55
55
2
W
2
5
T AS(DS)
Address Float to DS Fall
DS (Read) Low Width
DS (WRITE) Low Width
0
D
0
6
T DSR
200
200
110
110
2,3
2,3
2,3
2,3
2,3
2,3
2
W
7
T DSW
W
8
T DSR(DR)
DS Fall to Read Data
Req’d Valid
150
150
D
9
T DR(DS)
Read Data to DS Rise Hold
Time
0
H
0
2
10
11
Notes:
T DS(A)
DS Rise to Address Active
Delay
45
55
30
45
2
D
2
T DS(AS)
DS Rise to AS Fall Delay
2
D
2
1. E142/E143/E144/E145/E146 only; SCLK ÷ TCLK = Crystal ÷ 2.
2. The voltage specification of 4.5V guarantees 3.3V 0.3V, and the
V
V
voltage specification of 5.5V guar-
CC
CC
antees 5.0V 0.5V.
3. Timing numbers provided are for minimum T C.
P
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
90
Table 57.External I/O or Memory READ and WRITE Timing—Extended Temperature (Continued)
T = –40ºC to
A
+105ºC @ 12 MHz
1
No
Symbol
T R/W(AS)
Parameter
V
Min
45
45
45
45
55
55
45
45
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
CC
12
R/W Valid to AS Rise Delay 4.5V
5.5V
2
2
D
13
T DS(R/W)
DS Rise to R/W Not Valid
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
2
D
2
14
T DW(DSW)
WRITE Data Valid to DS
Fall (WRITE) Delay
2
D
2
15
T DS(DW)
DS Rise to WRITE Data
Not Valid Delay
2
D
2
16
T A(DR)
Address Valid to Read
Data Req’d Valid
310
310
2,3
2,3
2
D
17
T AS(DS)
AS Rise to DS Fall Delay
DM Valid to AS Fall Delay
DS Rise to DM Valid Delay
65
65
35
35
45
45
45
45
D
2
18
T DM(AS)
2
D
2
19
T Ds(DM)
2
D
2
20
T DS(AS)
DS Valid to Address Valid
Hold Time
2
H
2
Notes:
1. E142/E143/E144/E145/E146 only; SCLK ÷ TCLK = Crystal ÷ 2.
2. The voltage specification of 4.5V guarantees 3.3V 0.3V, and the
V
V
voltage specification of 5.5V guar-
CC
CC
antees 5.0V 0.5V.
3. Timing numbers provided are for minimum T C.
P
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
91
Additional Timing
Figure 26 illustrates the timing characteristics of the MUZE Family of parts with
respect to system clock functions. See Tables 58 and 59 for descriptions of the
numbered timing parameters in the figure.
Figure 26. Additional Timing
3
1
Clock
2
2
3
7
7
TIN
4
5
6
IRQN
8
9
Clock
Setup
11
Stop
Mode
Recovery
Source
10
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
92
For the values in Table 58, SCLK ÷ TCLK = Crystal ÷ 2, within a standard temper-
ature range of 0ºC to 70ºC.
Table 58.Additional Timing at Standard Temperature
T = 0ºC to +70ºC
A
8 MHz
Max
DC
12 MHz
Min Max
DC
1
No Sym
Parameter
V
Min
250
Units Notes D1,D0
CC
1
T C
Input Clock Period
4.5V
5.5V
4.5V
5.5V
83
83
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2,3,4
2,3,4
2,3
P
250
125
125
DC
DC
DC
25
DC
DC
DC
15
250
250
2,3
2
3
T C,
Clock Input Rise & Fall 4.5V
2,3
R
T C
Times
F
5.5V
25
15
2,3
T C
Input Clock Width
4.5V
5.5V
4.5V
5.5V
125
125
62
41
41
2,3,4
2,3,4
2,3
W
125
125
100
70
62
2,3
4
5
6
7
T T L Timer Input Low Width 4.5V
100
70
2,3
W IN
5.5V
2,3
T T H Timer Input High Width 4.5V 3T C
5T C
2,3
W IN
P
P
5.5V 3T C
5T C
2,3
P
P
T T
Timer Input Period
4.5V 4T C
8T C
2,3
P IN
P
P
5.5V 4T C
8T C
2,3
P
P
T T ,
Timer Input Rise & Fall 4.5V
100
100
100
100
ns
ns
2,3
R IN
T T
Timer
F IN
5.5V
2,3
Notes:
1. The V
guarantees 5.0V 0.5V.
2. Timing reference uses 0.7 V
3. SMR: D1 = 0.
voltage specification of 4.5V guarantees 3.3V 0.3V, and the V
voltage specification of 5.5V
CC
CC
for a logic 1 and 0.2 V
CC
for a logic 0.
CC
4. The maximum frequency for the external crystal clock is 4 MHz when using LOW-EMI OSCILLATOR mode.
5. The interrupt request via Port 3 (P31–P33).
6. The interrupt request via Port 3 (P30).
7. SMR: D5 = 1, and the POR Stop-Mode Delay is on.
8. For RC and LC oscillators, and for an oscillator driven by a clock driver.
9. The D1,D0 column applies to the Watch-Dog Timer Mode Register tap selection.
10. 12 µs is the typical delay time; only applies when SMR Register bit D5 is cleared to 0
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
93
Table 58.Additional Timing at Standard Temperature (Continued)
T = 0ºC to +70ºC
A
8 MHz
Max
12 MHz
Min Max
100
70
5T C
1
No Sym
8A T IL
Parameter
V
Min
100
70
Units Notes D1,D0
CC
Interrupt Request Low 4.5V
ns
ns
2,3,5
2,3,5
2,3,6
2,3,6
2,3,5
2,3,5
7
W
Time
5.5V
8B T IL
Interrupt Request Low 4.5V 3T C
W
P
P
Time
5.5V 3T C
5T C
P
P
9
T IH
Interrupt Request Input 4.5V 3T C
5T C
P
W
P
High Time
5.5V 3T C
5T C
P
P
10
11
12
T
T
T
Stop-Mode Recovery
Width Spec
4.5V
5.5V
12
12
12
12
ns
ns
WSM
OST
WDT
7
Oscillator Startup Time 4.5V
5.5V
5T C
5T C
7,8
7,8
9
P
P
5T C
5T C
P
P
Watch-Dog Timer
Delay Timer before
time-out
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
7
3.5
14
7
ms
ms
ms
ms
ms
ms
ms
ms
0,0
0,0
0,1
0,1
1,0
1,0
1,1
1,1
9
9
9
28
14
112
56
9
9
9
9
Notes:
1. The V
guarantees 5.0V 0.5V.
2. Timing reference uses 0.7 V
3. SMR: D1 = 0.
voltage specification of 4.5V guarantees 3.3V 0.3V, and the V
voltage specification of 5.5V
CC
CC
for a logic 1 and 0.2 V
CC
for a logic 0.
CC
4. The maximum frequency for the external crystal clock is 4 MHz when using LOW-EMI OSCILLATOR mode.
5. The interrupt request via Port 3 (P31–P33).
6. The interrupt request via Port 3 (P30).
7. SMR: D5 = 1, and the POR Stop-Mode Delay is on.
8. For RC and LC oscillators, and for an oscillator driven by a clock driver.
9. The D1,D0 column applies to the Watch-Dog Timer Mode Register tap selection.
10. 12 µs is the typical delay time; only applies when SMR Register bit D5 is cleared to 0
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
94
Table 58.Additional Timing at Standard Temperature (Continued)
T = 0ºC to +70ºC
A
8 MHz
Max
12 MHz
1
No Sym
13
Parameter
V
Min
Min
Max
24
Units Notes D1,D0
CC
T
Power-On Reset Delay 4.5V
5.5V
3
ms
ms
POR
1.5
13
14
T
POR Delay Time
4.5V
5.5V
35
µs
µs
10
10
EDELAY
35
Notes:
1. The V
guarantees 5.0V 0.5V.
2. Timing reference uses 0.7 V
3. SMR: D1 = 0.
voltage specification of 4.5V guarantees 3.3V 0.3V, and the V
voltage specification of 5.5V
CC
CC
for a logic 1 and 0.2 V
CC
for a logic 0.
CC
4. The maximum frequency for the external crystal clock is 4 MHz when using LOW-EMI OSCILLATOR mode.
5. The interrupt request via Port 3 (P31–P33).
6. The interrupt request via Port 3 (P30).
7. SMR: D5 = 1, and the POR Stop-Mode Delay is on.
8. For RC and LC oscillators, and for an oscillator driven by a clock driver.
9. The D1,D0 column applies to the Watch-Dog Timer Mode Register tap selection.
10. 12 µs is the typical delay time; only applies when SMR Register bit D5 is cleared to 0
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
95
For the values in Table 59, SCLK ÷ TCLK = Crystal ÷ 2, within an extended tem-
perature range of –40ºC to 105ºC.
Table 59.Additional Timing at Extended Temperature
T = –40ºC to +105ºC
A
8 MHz
Min
12 MHz
Min Max Units Notes D1,D0
1
No Sym
Parameter
VCC
Max
DC
DC
DC
DC
25
1
T C
Input Clock Period
4.5V 250
5.5V 250
4.5V 125
5.5V 125
83
83
DC
DC
DC
DC
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2,3,4
2,3,4
2,3
P
250
250
2,3
2
3
T C,
Clock Input Rise & Fall 4.5V
2,3
R
T C
Times
F
5.5V
25
15
2,3
T C
Input Clock Width
4.5V 125
5.5V 125
41
41
2,3,4
2,3,4
2,3
W
4.5V
5.5V
62
62
125
125
100
70
2,3
4
5
6
7
T T L Timer Input Low Width 4.5V 100
2,3
W IN
5.5V
70
2,3
T T H Timer Input High Width 4.5V 3T C
5T C
2,3
W IN
P
P
5.5V 3T C
5T C
2,3
P
P
T T
Timer Input Period
4.5V 4T C
8T C
2,3
P IN
P
P
5.5V 4T C
8T C
2,3
P
P
T T ,
Timer Input Rise & Fall 4.5V
100
100
100
100
ns
ns
2,3
R IN
T T
Timer
F IN
5.5V
2,3
Notes:
1. The V
2. The timing reference uses 0.7 V
3. SMR: D1 = 0.
voltage specification of 5.5V guarantees 5.0V 0.5V.
CC
for a logic 1 and 0.2 V for a logic 0.
CC
CC
4. The maximum frequency for the external crystal clock is 4 MHz when using LOW-EMI OSCILLATOR mode.
5. The interrupt request via Port 3 (P31–P33).
6. The interrupt request via Port 3 (P30).
7. SMR: D5 = 1, and the POR Stop-Mode Delay is on.
8. For RC and LC oscillators, and for an oscillator driven by a clock driver.
9. The D1,D0 column applies to the Watch-Dog Timer Mode Register tap selection.
10. 12 µs is the typical delay time.
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
96
Table 59.Additional Timing at Extended Temperature (Continued)
T = –40ºC to +105ºC
A
8 MHz
Min Max
12 MHz
Min Max Units Notes D1,D0
1
No Sym
8A T IL
Parameter
VCC
Interrupt Request Low 4.5V 100
Time
100
70
ns
ns
2,3,5
2,3,5
2,3,6
2,3,6
2,3,5
2,3,5
7
W
5.5V
70
8B T IL
Interrupt Request Low 4.5V 3T C
5T C
P
W
P
Time
5.5V 3T C
5T C
P
P
9
T IH
Interrupt Request Input 4.5V 3T C
5T C
P
W
P
High Time
5.5V 2T C
5T C
P
P
10
11
12
T
T
T
Stop-Mode Recovery
Width Spec
4.5V
5.5V
12
12
12
12
ns
ns
WSM
OST
WDT
7
Oscillator Startup Time 4.5V
5.5V
5T C
5T C
7,8
7,8
9
P
P
5T C
5T C
P
P
Watch-Dog Timer
Delay Timer before
time-out
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
7
3.5
14
7
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
0,0
0,0
0,1
0,1
1,0
1,0
1,1
1,1
9
9
9
28
14
112
56
3
9
9
9
9
13
T
Power-On Reset Delay 4.5V
5.5V
25
14
POR
1
Notes:
1. The V
2. The timing reference uses 0.7 V
3. SMR: D1 = 0.
voltage specification of 5.5V guarantees 5.0V 0.5V.
CC
for a logic 1 and 0.2 V for a logic 0.
CC
CC
4. The maximum frequency for the external crystal clock is 4 MHz when using LOW-EMI OSCILLATOR mode.
5. The interrupt request via Port 3 (P31–P33).
6. The interrupt request via Port 3 (P30).
7. SMR: D5 = 1, and the POR Stop-Mode Delay is on.
8. For RC and LC oscillators, and for an oscillator driven by a clock driver.
9. The D1,D0 column applies to the Watch-Dog Timer Mode Register tap selection.
10. 12 µs is the typical delay time.
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
97
Table 59.Additional Timing at Extended Temperature (Continued)
T = –40ºC to +105ºC
A
8 MHz
Min Max
12 MHz
Min Max Units Notes D1,D0
1
No Sym
Parameter
VCC
14
T
POR Delay Time
4.5V
5.5V
35
35
µs
µs
10
10
EDELAY
Notes:
1. The V
2. The timing reference uses 0.7 V
3. SMR: D1 = 0.
voltage specification of 5.5V guarantees 5.0V 0.5V.
CC
for a logic 1 and 0.2 V for a logic 0.
CC
CC
4. The maximum frequency for the external crystal clock is 4 MHz when using LOW-EMI OSCILLATOR mode.
5. The interrupt request via Port 3 (P31–P33).
6. The interrupt request via Port 3 (P30).
7. SMR: D5 = 1, and the POR Stop-Mode Delay is on.
8. For RC and LC oscillators, and for an oscillator driven by a clock driver.
9. The D1,D0 column applies to the Watch-Dog Timer Mode Register tap selection.
10. 12 µs is the typical delay time.
Figure 27. Input Handshake Timing
Data In
Data In Valid
Next Data In Valid
2
1
3
DAV
(Input)
Delayed DAV
5
6
4
RDY
(Output)
Delayed RDY
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
98
Figure 28. Output Handshake Timing
Data Out
Data Out Valid
Next Data Out Valid
Delayed DAV
7
DAV
(Output)
11
9
8
10
RDY
(Input)
Delayed RDY
1
Table 60.Handshake Timing at Standard Temperature
12 MHz
Data
2
No Symbol
T DI(DAV)
Parameter
V
Min
0
Max Units
Direction
CC
1
2
3
4
5
6
7
8
Data In Setup Time
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
ns
ns
ns
ns
ns
ns
Input
S
0
Input
T DI(RDY)
Data In Hold Time
0
Input
H
0
Input
T DAV
Data Available Width
155
110
Input
W
Input
T DAVI(RDY)
DAV Fall to RDY Fall Delay 4.5V
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input
D
5.5V
DAV Out to DAV Fall Delay 4.5V
5.5V
0
Input
T DAVId(RDY)
120
80
Input
D
Input
RDY0 (DAV)
RDY Rise to DAV Fall
Delay
4.5V
5.5V
0
0
Input
D
Input
T D0(DAV)
Data Out to DAV Fall Delay 4.5V
42
42
0
Output
Output
Output
Output
D
5.5V
DAV Fall to RDY Fall Delay 4.5V
5.5V
T DAV0(RDY)
D
0
Notes:
1. The Timing Reference uses 0.7
V
for a logic 1 and 0.2
V
for a logic 0.
CC
CC
2. The
V
voltage specification of 5.5V guarantees 5.0V 0.5V.
CC
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
99
1
Table 60.Handshake Timing at Standard Temperature (Continued)
12 MHz
Data
2
No Symbol
T RDY0(DAV)
Parameter
V
Min
Max Units
Direction
CC
9
RDY Fall to DAV Rise
Delay
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
160
115
ns
ns
ns
ns
ns
ns
Output
Output
Output
Output
Output
Output
D
10 T RDY
RDY Width
110
80
W
11 T RDY0 (DAV)
RDY Rise to DAV Fall
Delay
110
80
D
D
Notes:
1. The Timing Reference uses 0.7
V
for a logic 1 and 0.2
V
for a logic 0.
CC
CC
2. The
V
voltage specification of 5.5V guarantees 5.0V 0.5V.
CC
1
Table 61.Handshake Timing at Extended Temperature
12 MHz
16 MHz
Data
Max Units Direction
2
No Symbol
Parameter
V
Min
0
Max
Min
0
CC
1
2
3
4
5
6
7
T DI(DAV)
Data In Setup Time
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
S
0
0
T DI(RDY)
Data In Hold Time
0
0
H
0
0
T DAV
Data Available Width
155
110
155
110
W
T DAVI(RDY) DAV Fall to RDY Fall
0
0
0
0
D
Delay
T DAVId(RDY) DAV Out to DAV Fall
120
80
120
80
D
Delay
RDY0 (DAV) RDY Rise to DAV Fall 4.5V
0
0
0
0
D
Delay
5.5V
T D0(DAV)
Data Out to DAV Fall
Delay
4.5V
5.5V
42
42
31
31
D
Notes:
1. The Timing Reference uses 0.7
V
for a logic 1 and 0.2
V
for a logic 0.
CC
CC
2. The
V
voltage specification of 5.5V guarantees 5.0V 0.5V.
CC
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
100
1
Table 61.Handshake Timing at Extended Temperature (Continued)
12 MHz
16 MHz
Data
Max Units Direction
2
No Symbol
Parameter
V
Min
0
Max
Min
0
CC
8
T DAV0(RDY) DAV Fall to RDY Fall
4.5V
5.5V
ns
ns
ns
ns
ns
ns
ns
ns
Output
Output
Output
Output
Output
Output
Output
Output
D
Delay
0
0
9
T RDY0(DAV) RDY Fall to DAV Rise 4.5V
160
115
160
115
D
Delay
5.5V
10 T RDY
RDY Width
4.5V
5.5V
110
80
110
80
W
11 T RDY0 (DAV RDY Rise to DAV Fall 4.5V
110
80
110
80
D
D
)
Delay
5.5V
Notes:
1. The Timing Reference uses 0.7
V
for a logic 1 and 0.2
V
for a logic 0.
CC
CC
voltage specification of 5.5V guarantees 5.0V 0.5V.
2. The
V
CC
Standard Test Conditions
The characteristics listed in following pages apply for standard test conditions as
noted. All voltages are referenced to GND. Positive current flows into the refer-
enced pin (see Figure 29.)
Figure 29. Test Load Diagram
From Output
Under Test
150 pF
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
101
Capacitance
Table 62.Capacitance*
Parameter
Min
Max
Input capacitance
Output capacitance
I/O capacitance
Note: *T = 25ºC, V
0
12 pF
12 pF
12 pF
0
0
= GND = 0V, f = 1.0 MHz, unmeasured pins to GND.
CC
A
PS004005-1100
P R E L I M I N A R Y
Electrical Characteristics
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
102
One-Time Programming
Table 63 briefly describes the MUZE Family OTP option bit selection at each bit’s
default value before programming.
Table 63.Option Bit Description*
Bit
0
Option
Unprogrammed Default Value
Disabled
EPROM Protect
RAM Protect
Autolatches
P0 Pull-Ups
P1 Pull-Ups
P2 Pull-Ups
RC Oscillator
32-kHz Oscillator
Permanent WDT
VBO
1
Disabled
2
Enabled
3
Disabled
4
Disabled
5
Disabled
6
Disabled
7
Disabled
8
Disabled
9
Enabled
10
11
12
13
14
15
Reserved
Must not be changed
Must not be changed
Must not be changed
Must not be changed
Must not be changed
Must not be changed
Reserved
Reserved
Reserved
Reserved
Reserved
Note: *Option bits are 0 when unprogrammed and are 1 when programmed. If bits are not to be
programmed, use 0.
EPROM Protect. Selecting the DISABLE EPROM PROTECT option, bit 0, allows
the software program that is in the program memory to be read using ZiLOG’s
internal factory test mode. Selecting the ENABLE EPROM PROTECT option
negates the possibility of reading the code out of the part using a tester, program-
mer, or any other standard method.
The EPROM PROTECT option bit only affects the part’s ability to read from an
external source and does not affect the operation of the part in an application.
RAM Protect. Selecting the DISABLE RAM PROTECT option, bit 1, does not
affect the RAM memory. RAM memory operates as defined in this Product Speci-
fication for all address locations. Selecting the ENABLE RAM PROTECT option,
allows protection (under software control) of a portion of the RAM’s address
space from being read or written.
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Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
103
AUTOLATCH Mode. Selecting the DISABLE AUTOLATCHES option, bit 2, dis-
ables the autolatches on the Port pins.These pins float, rather than are pulled, to
a valid CMOS level when they are inputs and not connected to an external signal.
Selecting the ENABLE AUTOLATCHES option enables the autolatches on the
Port pins and pulls the pins to a valid CMOS level when they are not connected to
an external signal.
Port 0 Pull-Ups. Selecting DISABLE PULL-UPS option, bit 3, disables the input
pull-up circuitry on all Port 0 pins. Selecting ENABLE PULL-UPS enables the
input pull-up circuitry on all Port 0 pins. This option bit does not affect any of the
other port pins on the part.
Port 1 Pull-Ups. Selecting DISABLE PULL-UPS option, bit 4, disables the input
pull-up circuitry on all Port 1 pins. Selecting ENABLE PULL-UPS enables the
input pull-up circuitry on all Port 1 pins. This option bit does not affect any of the
other port pins on the part.
Port 2 Pull-Ups. Selecting DISABLE PULL-UPS option, bit 5, disables the input
pull-up circuitry on all Port 2 pins. Selecting ENABLE PULL-UPS enables the
input pull-up circuitry on all Port 2 pins. This option bit does not affect any of the
other port pins on the part.
System Clock Source. Selecting the RC OSCILLATOR ENABLE option, bit 6, con-
figures the oscillator circuit on the microcontroller to work with an external RC cir-
cuit. Selecting the CRYSTAL/OTHER CLOCK SOURCE option configures the
oscillator circuit to work with an external crystal, ceramic resonator, or LC oscilla-
tor.
Oscillator Operational Mode. Selecting the NORMAL HIGH FREQUENCY OPER-
ATION ENABLED option, bit 7, enables the part to operate using a standard crys-
tal or resonator, but it does not operate using a 32-kHz crystal. Selecting the 32-
KHZ OPERATION ENABLED option enables the microcontroller to work with a
32-kHz crystal and an external feedback resistor—these 2 items must be supplied
between the X and X
pins. (If RC OSCILLATOR ENABLED is selected in the
IN
OUT
SYSTEM CLOCK SOURCE option, this option defaults to the NORMAL HIGH
FREQUENCY OPERATION ENABLED bit.)
WDT Mode. Selecting the WDT ENABLED BY SOFTWARE ONLY option, bit 8,
operates the Watch-Dog Timer (WDT) when turned on under software control.
Selecting the WDT ENABLED AUTOMATICALLY AFTER RESET option starts
the WDT automatically at RESET.There is no way to disable or stop this mode,
making it necessary in the code to periodically clear the WDT to prevent it from
resetting the microcontroller. If the WDT ENABLED AUTOMATICALLY AFTER
RESET option and the WDT DRIVEN BY SYSTEM CLOCK option (if offered) are
selected, the WDT never operates in STOP mode, and cannot be enabled, by any
means, to operate in STOP mode.
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One-Time Programming
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
104
VBO. Selecting the VBO option, bit 9, enables low-voltage protection circuitry. The
device resets if V goes below V when VBO is selected. If it is disabled, the
CC
LV
device does not reset if V falls below V . See Low-Voltage Protection for more
CC
LV
details.
The remainder of the OTP options, bits 10–15, are reserved by ZiLOG and must
not be changed from their default values.
PS004005-1100
P R E L I M I N A R Y
One-Time Programming
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
105
Universal Asynchronous Receiver/Transmitter
ASCI Key Features
Key features of the UART Asynchronous Serial Communications Interface (ASCI)
include:
•
•
•
•
Full-duplex operation
Programmable data format
7 or 8 data bits with optional ninth bit for multiprocessor communication
P30 and P37 are used as general-purpose I/O as long as the ASCI channels
are disabled
•
•
•
•
•
•
One or two STOP bits
Odd, even or no parity
Programmable interrupt conditions
Four level data/status FIFOs for the receiver
Receive parity, framing and overrun error detection
Break detection and generation
Transmit Data Register. Data written to the ASCI Transmit Data Register (TDR) is
transferred to the Transmit Shift Register (TSR) as soon as the TSR is empty.
Data is written while the TSR shifts the previous byte of data, thereby providing a
double buffer for the transmit data.The TDR is READ- and WRITE-accessible.
Reading from the TDR does not affect the ASCI data transmit operation currently
in progress.
Transmit Shift Register. When the Transmit Shift Register (TSR) receives data
from the ASCI Transmit Data Register, the data shifts to the TX (P37) pin. When
transmission is completed, the next byte, if available, is automatically loaded from
the TDR into the TSR.The next transmission then starts. If no data is available for
transmission, the TSR idles at a continuous High level. This register is not pro-
gram-accessible.
Receive Shift Register. When the Receive Enable (RE) bit is set in the CNTLA
register, the RX (P30) pin is monitored for a Low. One-half bit-time after a Low is
sensed at RX, the ASCI samples RX again. If RX goes back to High, the ASCI
ignores the previous Low and resumes looking for a new Low. However, if RX is
still Low, it considers RX a START bit and proceeds to clock in the data based
upon the selected baud rate. The number of data bits, parity, multiprocessor and
STOP bits are selected by the MOD2, MOD1, MOD0 and MULTIPROCESSOR
mode (MP) bits in the CNTLA and CNTLB registers.
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Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
106
After the data is received, the appropriate MP, parity and STOP bits are checked.
Data and any errors are clocked into the receive data and status FIFO during the
STOP bit if there is an empty position available. Interrupts and Receive Data Reg-
ister Full Flag also goes active during this time. If there is no space in the FIFO at
the time that the RSR attempts to transfer the received data into it, an overrun
error occurs.
Receive Data FIFO. When a complete incoming data byte is assembled in the
RSR, it is automatically transferred to the 4-byte FIFO, which serves to reduce the
incidence of overrun errors. The top (oldest) character in the FIFO (if any) is read
via the Receive Data Register (RDR).
Figure 30. Receive Data Register FIFO
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
RSR
Flags
Flags
Flags
Flags
The next incoming data byte can shift into the RSR while the FIFO is full, thus pro-
viding an additional level of buffering. However, an overrun occurs if the receive
FIFO is still full when the receiver completes assembly of that character and is
ready to transfer it to the FIFO. If this situation occurs, the overrun error bit is set
in the previous byte of the FIFO stack.
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P R E L I M I N A R Y
Universal Asynchronous Receiver/Transmitter
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
107
Figure 31. FIFO Overrun Example
Good Data Byte 1
Good Data Byte 2
Good Data Byte 3
Good Data Byte 4
Flags
Flags
Flags
Flags
Overrun Data Byte
(Lost Data)
Sets flag
The latest data byte is not transferred from the shift register to the FIFO in this
case, and is lost. When an overrun occurs, the receiver does not place any further
data in the FIFO until the most recent good byte received arrives at the top of the
FIFO and sets the Overrun latch, and software then clears the Overrun latch by a
WRITE of 0 to the EFR bit.
Figure 32. Clear FIFO Overrun Example
Good Data Byte 4
Empty
Overrun Flag
Empty
Empty
Empty
Empty
Empty
Ignored Data Bytes
PS004005-1100
P R E L I M I N A R Y
Universal Asynchronous Receiver/Transmitter
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
108
Assembly of bytes continues in the shift register, but this data is ignored until the
byte with the overrun error reaches the top of the FIFO and the status is cleared.
When a break occurs (defined as a framing error with the data equal to all zeros),
the all-zero byte, with its associated error bits, are transferred to the FIFO if it is
not full. As a result, the Break Detect bit (bit 1) is set in the ASEXT register. If the
FIFO is full, an overrun is generated, but the break, framing error and data are not
transferred to the FIFO. Any time a break is detected, the receiver does not
receive any more data until the RX pin returns to a high state.
If the channel is set in MULTIPROCESSOR mode and the MPE bit (bit 7) of the
CNTLA register is set to 1, then break, errors and data are ignored unless the MP
bit in the received character is 1. The two conditions listed above could cause the
missing of a break condition if the FIFO is full and the break occurs or if the MP bit
in the transmission is not a one with the conditions specified above.
ASCI Status FIFO/RegistersThis FIFO contains Parity Error, Framing Error, RX
Overrun, and Break status bits associated with each character in the receive data
FIFO. The status of the oldest character (if any) is read from the ASCI status reg-
ister, which also provides several other, non-FIFOed status conditions.
The outputs of the error FIFO set the inputs of the software-accessible error
latches in the status register.Writing a 0 to the EFR bit (bit 3) in CNTLA is the only
way to clear these latches. In other words, when an error bit reaches the top of the
FIFO, it sets an error latch. If the FIFO contains more data and the software reads
the next byte out of the FIFO, the error latch remains set until the software writes a
0 to the EFR bit. The error bits are cumulative, so if additional errors are in the
FIFO they set any unset error latches as they reach the top.
Baud Rate Generator (BRG)The baud rate generator features two modes. The first
provides a dual set of fixed clock divide ratios as defined in CNTLB. In the second
mode, the BRG is configured as a sixteen-bit down counter that divides the pro-
cessor clock by the value in a software accessible, sixteen-bit, time-constant reg-
ister. As a result, virtually any frequency is created by appropriately selecting the
main processor clock frequency. The BRG can also be disabled in favor of the
SCLK.
The Receiver and Transmitter subsequently divide the output of the Baud rate
Generator (or the signal from the CLK pin) by 1, 16 or 64 under the control of the
DR bit (bit 3) in the CNTLB register and the X1 bit in the ASCI Extension Control
Register (ASEXT).
ResetDuring RESET, the ASCI is forced to the following conditions:
•
•
•
•
FIFO Empty
All Error Bits Cleared (including those in the FIFO)
Receive Enable Cleared (CNTLA Bit 6 = 0)
Transmit Enable Cleared (CNTLA Bit 5 = 0)
PS004005-1100
P R E L I M I N A R Y
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Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
109
Figure 33. ASCI Interface Diagram
Internal Address/Data Bus
ASCI Transmit Data Register
TDR (Bank: Ah, Addr: 01h)
IRQ3
Interrupt Request
ASCI Transmit Shift Register
TSR*
(P37) TX
(P30) RX
ASCI Receive Data FIFO
RDR (Bank: Ah, Addr: 02h)
ASCI Receive Shift Register
RSR*
ASCI
ASCI Control Register A
CNTLA (Bank: Ah, Addr: 03h)
Control
ASCI Control Register B
CNTLB (Bank: Ah, Addr: 04h)
ASCI Status FIFO/Register
STAT (Bank: Ah, Addr: 08h)
ASCI Extension Control Reg.
ASEXT (Bank: Ah, Addr: 05h)
ASCI Time Constant High
ASTCH (Bank: Ah, Addr: 07h)
ASCI Time Constant Low
ASTCL (Bank: Ah, Add: 06h)
Baud Rate Generator
Note: *Not Programmed.
SCLK
ASCI Interrupts
The ASCI channel generates one interrupt, IRQ3, from two sources of interrupts:
a receiver and a transmitter. In addition, there are several conditions that may
cause these interrupts to trigger. Figure 64 illustrates the different conditions for
each interrupt source enabled under program control.
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Universal Asynchronous Receiver/Transmitter
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
110
Table 64.ASCI Interrupt Conditions and Sources
FIFO Full
Overrun Error
Framing Error
Parity Error
Start Bit
Receiver
Interrupt
Sources
ASCI
Interrupt
(IRQ3)
Transmitter
Interrupt
Sources
Buffer Empty
ASCI Transmit Data Register
Data written to the ASCI Transmit Data Register (TDR) is transferred to the Trans-
mit Shift Register (TSR) as soon as the TSR is empty. The TSR is not software-
accessible.The ASCI transmitter is double-buffered so data can be written to the
TDR while the TSR is shifting out the previous byte. Data can be written into and
read out of the TDR. When the TDR is read, the data transmit operation is not
affected.
READ/WRITE and reset states for bits D7–D0 of the TDR are listed in Table 65.
Table 65.Transmit Data Register—TDR 01h/R1 Bank Ah: READ/WRITE
Bit
D7
R/W
X
D6
R/W
X
D5
R/W
X
D4
R/W
X
D3
R/W
X
D2
R/W
X
D1
R/W
X
D0
R/W
X
R/W
Reset
Note: R = Read, W = Write, X = Indeterminate.
Bit/
Bit
Field
Position
R/W
State Description
Transmit Data Register
D7–D0
TDR
R/W
X
ASCI Receive Data Register
When a complete incoming data byte is assembled in the Receive Shift Register
(RSR), it is automatically transferred to the highest available location in the
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The MUZE Family of Z8 Microcontrollers
111
Receive Data FIFO. The Receive Data Register (RDR) is the highest location in
the Receive Data FIFO. The Receive Data Register Not Empty bit (RDRNE—bit
7) in the STAT register is set when one or more bytes is available from the FIFO.
The FIFO status for the character in the RDR is available in the STAT register via
bits 6, 5 and 4. STAT should be read before reading the RDR. The data in both
FIFO locations is popped when the character is read from the RDR.
READ/WRITE and reset states for bits D7–D0 of the RDR are listed in Table 66.
Table 66.Receive Data Register—RDR 02h/R2 Bank Ah: READ/WRITE
Bit
D7
R/W
X
D6
R/W
X
D5
R/W
X
D4
R/W
X
D3
R/W
X
D2
R/W
X
D1
R/W
X
D0
R/W
X
R/W
Reset
Note: R = Read, W = Write, X = Indeterminate.
Bit/
Bit
Field
Position
R/W
State Description
Receive Data Register
D7–D0
RDR
R/W
X
ASCI Control Register A
ASCI Control Register A, CNTLA, controls data transmit, receive, and clocking
functions. READ/WRITE and reset states for bits D7–D0 are listed in Table 67.
Table 67.Control Register A—CNTLA 03h/R3 Bank Ah: READ/WRITE
Bit
D7
R/W
0
D6
R/W
0
D5
R/W
0
D4
R/W
1
D3
R/W
0
D2
R/W
0
D1
R/W
0
D0
R/W
0
R/W
Reset
Note: R = Read, W = Write, X = Indeterminate.
Bit
Bit/Field Position
R/W
State Description
D7
MPE
R/W
0
Multiprocessor Enable
0: Receive all bytes
1: Filter bytes with MPB = 0
D6
RE
R/W
0
Receiver Enable
0: ASCI Receiver Disabled
(P30 = Input)
1: ASCI Receiver Enabled
(P30 = RX)
PS004005-1100
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Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
112
Bit
Bit/Field Position
R/W
State Description
D5
TE
R/W
0
Transmitter Enable
0: ASCI Transmitter Disabled
(P37 = Output)
1: ASCI Transmitter Enabled
(P37 = TX)
D4
D3
Reserved
MPBR
EFR
R/W
R
1
0
0
Reserved
Multiprocessor Bit Received
W
Error Flag Reset
0: Clear Error Latches
1: No Effect
D2–D0
MOD2–0
R
0
MOD2—Number of Data Bits
0: 7 Data Bits
1: 8 Data Bits
MOD1—Parity Enabled
0: No Parity
1: With Parity
MOD0—Number of Stop Bits
0: 1 Stop Bit
1: 2 Stop Bits
Multiprocessor Enable. The ASCI features a multiprocessor communication mode
that utilizes an extra data bit for selective communication when a number of pro-
cessors share a common serial bus. Multiprocessor data format is selected when
the MP in the corresponding register is set to 1. If MULTIPROCESSOR mode is
not selected (MP bit in CNTLB = 0), MULTIPROCESSOR ENABLE (MPE, bit 7)
exhibits no effect. If MULTIPROCESSOR mode is selected (MPE bit in
CNTLB = 1), MPE enables or disables the wake-up feature as follows. If MPE is
set to 1, only received bytes in which the multiprocessor bit (MPB) = 1 are treated
as valid data characters and loaded into the receiver FIFO with corresponding
error flags in the status FIFO. Bytes with MPB = 0 are ignored by the ASCI. If MPE
is reset to 0, all bytes are received by the ASCI, regardless of the state of the MPB
data bit.
Receiver Enable. When Receiver Enable (RE, bit 6) is set to 1, the ASCI receiver
is enabled. When RE is reset to 0, the receiver is disabled and any receive opera-
tion in progress is aborted. However, the previous contents of the receiver data
and status FIFO are not affected.
Transmitter Enable. When Transmitter Enable (TE, bit 5) is set to 1, the ASCI
transmitter is enabled. When TE is reset to 0, the transmitter is disabled and any
transmit operation in progress is aborted. However, the previous contents of the
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Universal Asynchronous Receiver/Transmitter
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The MUZE Family of Z8 Microcontrollers
113
transmitter data register and the TDRE flag (bit 1 of the STAT register) are not
affected.
Bit 4 is reserved.
Multiprocessor Bit Receive. When MULTIPROCESSOR mode is enabled (MP in
CNTLB = 1), this READ-ONLY bit, when read, contains the value of the MPB bit
for the data byte currently available at the Receive Data Register (the top of the
receiver FIFO). The Multiprocessor Bit Receive bit, MPBR, is bit 3.
Error Flag Reset. When the WRITE-ONLY Error Flag Reset (EFR), bit 3, is written
to 0, the error flags (OVRN, FE; PE in STAT and BRK in ASEXT) are cleared to 0.
This command self-resets, and as a result, writing EFR to a 1 is not required.
ASCI Data Format Mode. Bits 2–0 program the ASCI data format, as indicated in
Table 68.
Table 68.ASCI Data Format Mode Control Bits
Bit
2
Name
MOD2
MOD1
MOD0
Function
Bit = 0
Bit = 1
Number of Data Bits
Parity Enabled
Number of Stop Bits
7
No Parity
1
8
With Parity
2
1
0
If MOD1 = 1, parity is checked on received data and a parity bit is appended to the
data bits in the transmitted data. Parity Even/Odd (PEO) in CNTLB selects even
or odd parity.
The ASCI serial data format is illustrated in Figure 34.
Figure 34. ASCI Serial Data Format
7 or 8 bits Data Field
1 or 2
Stop Bit(s)
Start Bit
Parity
Bit
ASCI Control Register B
Control Register B, CNTLB, controls multiprocessor, parity, and clock sourcing
functions. READ/WRITE and reset states for bits D7–D0 are listed in Table 69.
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Table 69.Control Register B—CNTLB 04h/R4 Bank Ah: READ/WRITE
Bit
D7
R/W
0
D6
R/W
0
D5
R/W
0
D4
R/W
0
D3
R/W
0
D2
R/W
1
D1
R/W
1
D0
R/W
1
R/W
Reset
Note: R = Read, W = Write, X = Indeterminate.
Bit/
Bit
Field
Position
R/W
State Description
D7
MPBT
R/W
0
Multiprocessor Bit Transmitter
0: Transmit 0 in MPB
1: Transmit 1 in MPB
D6
MP
R/W
0
Multiprocessor Mode
0: MULTIPROCESSOR mode disabled
1: MULTIPROCESSOR mode enabled
(no parity)
D5
D4
D3
D2
D1
D0
PR
W
R/W
R/W
R
0
0
0
1
1
1
Prescale
0: BRG ÷ 10
1: BRG ÷ 30
PEO
DR
Parity Even/Odd
0: Even Parity
1: Odd Parity
Divide Ratio
0: Divide by 16
1: Divide by 64
SS2
SS1
SS0
Clock Source and Speed Bits—SS2
0: ÷1, ÷2, ÷4, ÷8
1: ÷16, ÷32, ÷64, Reserved
R
Clock Source and Speed Bits—SS1
0: ÷1, ÷2, ÷16, ÷32
1: ÷4, ÷8, ÷64, Reserved
R
Clock Source and Speed Bits—SS0
0: ÷1, ÷4, ÷16, ÷64
1: ÷2, ÷8, ÷32, Reserved
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Multiprocessor Bit Transmit. When multiprocessor format is selected (MP bit = 1),
Multiprocessor Bit Transmit (MPBT, bit 7) is used to specify the MPB data bit for
transmission. If MPBT = 1, then a 1 is transmitted in the MPB bit position. If MPBT
= 0, a 0 is transmitted.
MULTIPROCESSOR Mode. When MULTIPROCESSOR mode is set to 1, the serial
data format is configured for MULTIPROCESSOR mode (MP, bit 6), adding a bit
position whose value is specified in MPBT immediately after the specified number
of data bits and preceding the specified number of STOP bits.
Note:
The multiprocessor format does not provide parity. The serial data format
while in MP mode is illustrated in Figure 35.
Figure 35. Multiprocessor Mode Serial Data Format
7 or 8 bits Data Field
1 or 2
Stop Bit(s)
Start Bit
MPB
If MP = 0, the data format is based on MOD2–0 in CNTLA and may include parity.
BRG Prescaler. The Prescale bit specifies the baud rate generator (BRG, bit 5)
prescale factor when using the SS2–0 bits to define the ASCI baud rate (BRG
mode = 0). Writing a 0 to this bit sets the BRG Prescaler to divide by 10. Setting
this bit to a 1 sets the BRG Prescaler to divide by 30. See the Baud Rate Genera-
tion Summary for more information on setting the ASCI baud rate.
Parity Even/Odd. Parity Even/Odd (PEO, bit 4) controls the parity bit transmitted
on the serial output and the parity check on the serial input. If PEO is cleared to 0,
even parity is transmitted and checked. If PEO is set to 1, odd parity is transmitted
and checked.
Divide Ratio. The Divide Ratio bit (DR, bit 3) specifies the divider used to obtain
the baud rate from the data sampling clock when using the SS2–0 bits to define
the ASCI baud rate (BRG mode = 0). If DR is 0, then DIVIDE-BY-16 is used. If DR
is set to 1, then DIVIDE-BY-64 is used. See the Baud Rate Generation Summary
for more information on setting the ASCI baud rate.
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DR
0
Sampling Clock
Divide by 16
1
Divide by 64
Clock Source and Speed Select. When the BRG mode bit (bit 3) in the ASEXT reg-
ister is set to 0, these 3 bits, along with DR and PR in this register define the ASCI
baud rate. Bits 2, 1 and 0 specify a power-of-two divider of the SCLK as defined in
Table 70.These bits should never be set to all 1s or erratic results may occur. See
the Baud Rate Generation Summary for more information on setting the ASCI
baud rate.
Table 70.Clock Source and Speed Bits
SS2
0
SS1
0
SS0
0
Divider (DIV)
÷1
÷2
0
0
1
0
1
0
÷4
0
1
1
÷8
1
0
0
÷16
1
0
1
÷32
1
1
0
÷64
1
1
1
Reserved
ASCI Extension Control Register
Following are the bit functions for the ASCI Extension Control Register (ASEXT).
Table 71.Extension Control Register—ASEXT 05h/R5 Bank Ah: READ/WRITE
Bit
D7
R
D6
R/W
0
D5
R/W
0
D4
R/W
0
D3
R/W
0
D2
R/W
0
D1
R
D0
R/W
0
R/W
Reset
P30
0
Note: R = Read, W = Write, X = Indeterminate.
Bit/
Bit
Field
Position
R/W
R
State Description
D7
D6
D5
RX
P30 RX Data State
Reserved
Reserved
R/W
R/W
0
0
Reserved
Reserved
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D4
D3
Reserved
BRG
R/W
R/W
0
0
Reserved (must be 0)
Baud Rate Generator Mode
0: Use SS Selection
1: Use ASTH or ASTL Value
D2
D1
D0
RIS
BD
SB
R/W
R
0
0
0
RX Interrupt on Start Bit
0: No IRQ on Start Bit
1: IRQ3 on Start Bit
Break Detect
0: Valid Data Byte
1: Break Detected
R/W
Send Break
0: Normal Operation
1: Send Break
RX State. This bit provides the real-time state of the channel’s receive data input
pin (RX, bit 7), which is P30.
Reserved bits 6, 5, and 4. When read, bits 6 and 5 reflect the default value 0.When
written, these bits are ignored. Bit 4 must be set to 0 or erratic results may occur.
BRG Mode. When the Baud Rate Generator (BRG, bit 3) bit is set to 1, the ASCI’s
baud rate is set by the 16-bit programmable divider programmed in ASCI Time
Constant High (ASTH) and ASCI Time Constant Low (ASTL). If this bit is set to 0,
the baud rate is defined by the PR bit, the DR bit, and the SS2–0 bits in the
CNTLB register. In either case, the source for the baud rate generator is the
SCLK. See the Baud Rate Generation Summary for more information on setting
the ASCI baud rate.
RX Interrupt on Start. If software sets RX (bit 2) to 1, a receive interrupt is
requested (in a combinatorial fashion) when a START bit is detected on RX. Such
a receive interrupt is always followed by setting RDRNE (bit 7) in the middle of the
STOP bit. Upon receiving the interrupt service request, the RX Interrupt on Start
(RIS) bit must be set to 0, then immediately set to 1 to continue operation with a
start bit interrupt. One function of this feature is to wake the part from HALT mode
when a character arrives, so that the ASCI receives clocking to process the char-
acter. Another function is to ensure that the associated interrupt service routine is
activated in time to sense the setting of RDRNE in the status register, and to start
a timer for baud rate measurement at that time.
Break Detect. This READ-ONLY status bit (BD, bit 1)is set to 1 when a break is
detected. A break is defined as a framing error with the data bits all equal to 0.
The all-zero byte with its associated error bits are transferred to the FIFO if it is not
full. If the FIFO is full, an overrun is generated, but the break, framing error and
data are not transferred to the FIFO. Any time a break is detected, the receiver
does not receive any more data until the RX pin returns to a High state. When set,
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this bit remains set until it is cleared by writing a 0 to the EFR bit in the CNTLA
register.
Send Break. Setting the SB bit (bit 0) to a 1 forces the channel’s transmitter data
output pin, TX, to a Low for as long as it remains set. Before starting the break,
any character(s) in the TSR and in the TDR are transmitted completely. If a char-
acter is loaded into the TDR while a break is being generated, that character is
held until the break is terminated and then transmitted.
ASCI Time Constant Registers
The ASTL and ASTH registers are only used when the BRG mode bit in the
ASEXT register is set to 1. These two 8-bit registers form a 16-bit counter with a
flip-flop logic circuit (DIVIDE-BY-2) on the output so that the final BRG output is
symmetrical. The values written to these registers determine the time constant
from which the baud rate is generated.
READ/WRITE and reset states for bits D7–D0 of the ASTL and ASTH registers
are listed in Tables 72 and 73, respectively.
Table 72.Time Constant Register Low—ASTL 06h/R6 Bank Ah: READ/WRITE
Bit
D7
R/W
1
D6
R/W
1
D5
R/W
1
D4
R/W
1
D3
R/W
1
D2
R/W
1
D1
R/W
1
D0
R/W
1
R/W
Reset
Note: R = Read, W = Write, X = Indeterminate.
Bit/
Bit
Field
Position
R/W
State Description
ASCI Time Constant Low
D7–D0
ASTL
R/W
1
Table 73.Time Constant Register High—ASTH 07h/R7 Bank Ah: READ/WRITE
Bit
D7
R/W
1
D6
R/W
1
D5
R/W
1
D4
R/W
1
D3
R/W
1
D2
R/W
1
D1
R/W
1
D0
R/W
1
R/W
Reset
Note: R = Read, W = Write, X = Indeterminate.
Bit/
Bit
Field
Position
R/W
State Description
ASCI Time Constant High
D7–D0
ASTH
R/W
1
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ASCI Status Register
The ASCI Status Register, STAT, controls status functions. READ/WRITE and
reset states for bits D7–D0 are listed in Table 74.
Table 74.Status Register—STAT 08h/R8 Bank Ah: READ/WRITE
Bit
D7
R
D6
R
D5
R
D4
R
D3
R/W
0
D2
R/W
0
D1
R
D0
R/W
0
R/W
Reset
0
0
0
0
1
Note: R = Read, W = Write, X = Indeterminate.
Bit/
Bit
Field
Position
R/W
State Description
D7
D6
D5
D4
D3
RDRNE
R
0
0
0
0
0
Receive Data Register Not Empty
0: Receive FIFO Empty
1: Receive FIFO contains 1 or more bytes
OE
R
R
Overrun Error
0: Receive OK
1: Next byte is a FIFO overrun
PE
Parity Error
0: Parity OK
1: Parity Error
FE
R
Framing Error
0: Receive OK
1: Framing Error
RIE
R/W
Receive Interrupt Enable
0: No IRQ on Receive
1: IRQ3 on RDRNE↑ or Start Bit
D2
D1
Reserved
TDRE
R/W
R
0
1
Reserved
Transmit Data Register Empty
0: Transmitter Working
1: Transmit Buffer Empty
D0
TIE
R/W
0
Transmit Interrupt Enable
0: No IRQ on Transmit
1: IRQ3 on TDRE
↑
Receive Data Register Not Empty. RDRNE (RDRNE, bit 7)is set to 1 when the
receiver transfers a character from the RSR into an empty RX FIFO.
Note:
If a framing or parity error occurs, RDRNE is still set and the receive data
(which generated the error) is still loaded into the FIFO.
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When there is more than one byte in the FIFO and software reads a byte, RDRNE
is not cleared to 0. The bit is cleared when the last byte is read from the FIFO.
Overrun Error. An overrun error (OE, bit 6) occurs if the receive FIFO is still full
when the receiver completes assembly of a character and is ready to transfer it to
the FIFO. If this situation occurs, the overrun error bit associated with the previous
byte in the FIFO is set. In this case, the latest data byte is not transferred from the
shift register to the FIFO and is lost.
When an overrun occurs, the receiver does not place any further data in the FIFO
until the most recent good byte received (the byte with the associated overrun
error bit set) moves to the top of the FIFO and sets the Overrun latch, and soft-
ware then clears the Overrun latch. Assembly of bytes continues in the shift regis-
ter, but this data is ignored until the byte with the overrun error reaches the top of
the FIFO and the status is cleared. When set, the bit remains set until it is cleared
by writing a 0 to the EFR bit in the CNTLA register. The bit is also cleared during
Power-On Reset.
Parity Error. A parity error (PE, bit 5) is detected when parity generation and
checking is enabled by the MOD1 bit (bit 1) in the CNTLA register and a character
is assembled in which the parity does not match that specified by the PEO bit (bit
4) in CNTLB.
Note:
PE is FIFOed and the error bit is not actually set until the associated data
becomes available for reading in the RDR.
When set, the bit remains set until it is cleared by writing a 0 to the EFR bit (bit 3)
in the CNTLA register. The bit is cleared at Power-On Reset.
Framing Error. A framing error (FE, bit 4) is detected when the stop bit of a char-
acter is sampled as a 0 (space). Like PE, FE is FIFOed and the error bit is not
actually set until the associated data becomes available for reading in the RDR.
When set, the bit remains set until it is cleared by writing a 0 to the EFR bit (bit 3)
in the CNTLA register. The bit is cleared at Power-On Reset.
Receive Interrupt Enable. RIE, bit 3, must be set to 1 to enable ASCI receive inter-
rupt requests. The Z8 edge-triggered interrupt (IRQ3) is generated when RDRNE
(bit 7 of the STAT Register) is transitioned from 0 to 1. IRQ3 is also generated if a
start bit is detected; the RIE bit is set to 1, and bit 2 of the ASEXT register is set to
1.
Reserved Bit 2. When read, bit 2 reflects the default value 0. When written, bit 2 is
ignored.
Transmit Data Register Empty. TDRE = 1 indicates that the Transmit Data Register
(TDR) is empty and that the next data byte to be transmitted can be written into
the TDR. TDRE, bit 1, is cleared to 0 after the byte is written to TDR, until the
ASCI transfers the byte from the TDR to the Transmit Shift Register (TSR), and
then TDRE is again set to 1. TDRE is set to 1 at Power-On Reset.
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Transmit Interrupt Enable. TIE, bit 0, should be set to 1 to enable ASCI transmit
interrupt requests. An interrupt (IRQ3) is generated when TDRE (bit 1 of the STAT
register) transitions from 0 to 1. TIE is cleared to 0 at Power-On Reset.
Note:
If both TIE and RIE are set to 1, a receive interrupt is not generated on the
incoming (RDR) data. To generate a receive interrupt:
1. The user must set only RIE to 1.
2. If both TIE and RIE have been previously set to 1, ZiLOG recommends
that the EFR flag also be cleared to 0. If the EFR flag is not cleared to
0, the receive interrupt may not occur. Clear the EFR flag bit with the
following instruction:
push
srp
rp
#%1A
;save the register pointer
;switch to the ASCI control register
;bank
Loop1:ld
temp,RDR
;clean up the RDR register
tm
STAT,#10000000b ;make sure no data exists
;in the RDR FIFO
jr
nz,Loop1
and
pop
CNTLA,#11110111b :clear EFR
rp
;restore the register pointer
Baud Rate Generation Summary
The application can select between one of two baud rate generators for the ASCI.
If the BRG mode bit in the ASEXT register is set to 0, the SS2,1,0 bits, the DR bit,
and the PR bit in CNTLB are used to select the baud rate. If the BRG mode bit is
set to 1, the ASTL and ASTH registers are used to select the baud rate.
The following formulas are used to calculate the baud rate from the two baud rate
generators:
If BRG mode = 0:
Baud Rate =
SCLK
(10 + 20 x PS) x DIV x DIVIDE RATIO
Where:
1. SCLK is the system clock.
2. PS = 1 or 0 and is bit 5 of CNTLB.
3. DIV = 1, 2, 4, 8, 16, 32 or 64 as reflected by SS2–0 in CNTLB.
4. DIVIDE RATIO = 16 or 64, as defined by DR (bit 3) in CNTLB.
If BRG mode = 1:
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SCLK
(2 x (TC + 2) x DIVIDE RATIO
Baud Rate =
or
SCLK
2 x BAUD RATE x DIVIDE RATIO
TC =
– 2
Where:
1. SCLK is the system clock.
2. TC is the 16-bit value programmed in ASTL and ASTH. A minimum TC value
of 0 is valid.
3. DIVIDE RATIO = 16 or 64, as defined by DR in CNTLB.
4. BAUD RATE is the desired baud rate.
5. A maximum baud rate of 115Kbps can be obtained by using a 16-MHz
Crystal, when TC = 0 and the DIVIDE RATIO = 16.
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Table 75.Baud Rate List—BRG Mode = 0
Sampling
Example Baud Rate
(bps)
Prescaler
Rate
Baud Rate
SCLK= SCLK= SCLK=
Divide
Ratio
Divide General
DR Rate SS2 SS1 SS0 Ratio Divide Ratio
6.144 4.608 3.072
PS
MHz
38400
19200
9600
4800
2400
1200
600
MHz
MHz
19200
9600
4800
2400
1200
600
0
SCLK ÷ 10
0
16
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
÷1
÷2
÷4
÷8
SCLK ÷ 160
SCLK ÷ 320
SCLK ÷ 640
SCLK ÷ 1280
÷16 SCLK ÷ 2560
÷32 SCLK ÷ 5120
÷64 SCLK ÷ 10240
300
1
64
÷1
÷2
÷4
÷8
SCLK ÷ 640
SCLK ÷ 1280
SCLK ÷ 2560
SCLK ÷ 5120
9600
4800
2400
1200
600
4800
2400
1200
600
÷16 SCLK ÷ 10240
÷32 SCLK ÷ 20480
÷64 SCLK ÷ 40960
300
300
150
150
75
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Table 75.Baud Rate List—BRG Mode = 0 (Continued)
Sampling
Example Baud Rate
(bps)
Prescaler
Rate
Baud Rate
SCLK= SCLK= SCLK=
Divide
Ratio
Divide General
DR Rate SS2 SS1 SS0 Ratio Divide Ratio
6.144 4.608 3.072
PS
MHz
MHz
4800
2400
1200
600
300
150
75
MHz
1
SCLK ÷ 30
0
16
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
÷1
÷2
÷4
÷8
SCLK ÷ 480
SCLK ÷ 960
SCLK ÷ 1920
SCLK ÷ 3840
÷16 SCLK ÷ 7680
÷32 SCLK ÷ 15360
÷64 SCLK ÷ 30720
1
64
÷1
÷2
÷4
÷8
SCLK ÷ 1920
SCLK ÷ 3840
SCLK ÷ 7680
SCLK ÷ 15360
2400
1200
600
300
150
75
÷16 SCLK ÷ 30720
÷32 SCLK ÷ 61440
÷64 SCLK ÷
122880
37.5
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In-Circuit Serial Programming
In-Circuit Serial Programming Block Diagram
Figure 36 shows the basic functionality of the In-Circuit Serial Programming Inter-
face (ICSP). The ICSP interface receives and transmits data via the SDIO line in
conjunction with an ICSP clock on the SCK line. Please refer to the MUZE Pro-
gramming Specification for more details.
Figure 36. ICSP Block Diagram
OTP
Options
SDIO
ICSP
EPROM
SCK
The ICSP interface is a five-wire connection. The connections for the MUZE are:
. Power Supply.
V
CC
SDIO. Serial Data Input/Output (SDIO)—data input and output pin, open-drain.
SCK. Serial ICSP Clock (SCK)—data input and output clock.
ICSP_RESET. Active Low (ICSP) Reset. ICSP_RESET is an internal serial pro-
gramming reset, not a complete Z8 reset, as is the case with POR.
GND. Ground.
The recommended circuit is illustrated in Figure 37.
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Figure 37. ICSP Connectivity
VCC
Optional protection diode.
ICSP provides limited
supply current.
V
CC
1 KΩ
VCC
GND
GND
GND
GND
SCK
SDIO
SCK
SDIO
ICSP Cable
VPP/ICSP_RESET
VPP/ICSP_RESET
ICSP
Cable
Header
on
Z8
User
PCB
Note:
The diode shown in Figure 37 is an optional protection diode. ICSP
provides limited supply current.
The following operations are specific to programming in ICSP mode:
•
•
•
•
•
•
Serial Operations—Unlock
Serial Programming Option Bits—WORD Mode
Serial Programming Option Bits—BYTE Mode
Serial Operations—Reading
Data Verify
Device-Specific Options
For a complete description of these operations, please refer to the MUZE Pro-
gramming Specification.
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Packaging
Figure 38 illustrates the 20-pin DIP package for the Z86E122, Z86E123,
Z86E124, Z86E125, and Z86E126 microcontroller devices.
Figure 38. 20-Pin DIP Package Diagram
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Figure 39 illustrates the 20-pin SOIC package for the Z86E122, Z86E123,
Z86E124, Z86E125, and Z86E126 microcontroller devices.
Figure 39. 20-Pin SOIC Package Diagram
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Figure 40 illustrates the 28-pin DIP package for the Z86E132, Z86E133,
Z86E134, Z86E135, and Z86E136 microcontroller devices.
Figure 40. 28-Pin DIP Package Diagram
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Figure 41 illustrates the 28-pin SOIC package for the Z86E132, Z86E133,
Z86E134, Z86E135, and Z86E136 microcontroller devices.
Figure 41. 28-Pin SOIC Package Diagram
PS004005-1100
P R E L I M I N A R Y
Packaging
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
131
Figure 42 illustrates the 40-pin DIP package for the Z86E142, Z86E143,
Z86E144, Z86E145, and Z86E146 microcontroller devices.
Figure 42. 40-Pin DIP Package Diagram
PS004005-1100
P R E L I M I N A R Y
Packaging
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
132
Figure 43 illustrates the 44-pin PQFP package for the Z86E142, Z86E143,
Z86E144, Z86E145, and Z86E146 microcontroller devices.
Figure 43. 44-Pin PQFP Package Diagram
PS004005-1100
P R E L I M I N A R Y
Packaging
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
133
Ordering Information
Table 76.Ordering Information
Size
Pin Count
Package
DIP
Order Number*
Z86E136PZ016SC
Z86E136SZ016SC
Z86E146PZ016SC
Z86E146FZ016SC
Z86E135PZ016SC
Z86E135SZ016SC
Z86E145PZ016SC
Z86E145FZ016SC
Z86E134PZ016SC
Z86E134SZ016SC
Z86E144PZ016SC
Z86E144FZ016SC
Z86E133PZ016SC
Z86E133SZ016SC
Z86E143FZ016SC
Z86E143SZ016SC
Z86E132PZ016SC
Z86E132SZ016SC
Z86E142PZ016SC
Z86E142FZ016SC
64 KB
28
SOIC
DIP
40
44
28
PQFP
DIP
32 KB
16 KB
8 KB
SOIC
DIP
40
44
28
PQFP
DIP
SOIC
DIP
40
44
28
PQFP
DIP
SOIC
DIP
40
44
28
PQFP
DIP
4 KB
SOIC
DIP
40
44
PQFP
Note: *The Standard temperature range is 0ºC to 70ºC. For parts that operate in the Extended temperature range of
–40ºC to 105ºC, substitute the letter E for the letter S. For example, the Order Number for a 28-pin DIP operating at
64 KB in the Extended temperature range is Z86E136PZ016EC.
For fast results, contact your local ZiLOG sale office for assistance in ordering the
part(s) desired.
PS004005-1100
P R E L I M I N A R Y
Ordering Information
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
134
Part Number Description
ZiLOG part numbers consist of a number of components. For example, part num-
ber Z86E136PZ016SC is a 16-MHz 28-pin DIP that operates in the –0ºC to +70ºC
temperature range, with Plastic Standard Flow. The Z86E136PZ016SC part num-
ber corresponds to the code segments indicated in the following table.
Z
ZiLOG Prefix
Z8 Product
86
E
OTP Product
Product Number
Package
136
PZ
016
S
Speed (MHz)
Temperature
Environmental Flow
C
For fast results, contact your local ZiLOG sales office for assistance in ordering
the part required.
Precharacterization Product
The product represented by this document is newly introduced and ZiLOG has not
completed the full characterization of the product. The document states what
ZiLOG knows about this product at this time, but additional features or non-con-
formance with some aspects of the document may be found, either by ZiLOG or
its customers in the course of further application and characterization work. In
addition, ZiLOG cautions that delivery may be uncertain at times, due to start-up
yield issues.
ZiLOG, Inc.
910 East Hamilton Avenue, Suite 110
Campbell, CA 95008
Telephone (408) 558-8500
FAX 408 558-8300
Internet: www.ZiLOG.com
PS004005-1100
P R E L I M I N A R Y
Ordering Information
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
135
Document Information
Document Number Description
The Document Control Number that appears in the footer of each page of this
document contains unique identifying attributes, as indicated in the following
table:
PS
0040 Unique Document Number
05 Revision Number
1100 Month and Year Published
Product Specification
Change Log
Rev
Date
Purpose
By
01
02
03
04
05
02/00
03/00
03/00
06/00
11/00
Original issue
Corrections
K. Johnston, R. Beebe
K. Johnston, R. Beebe
K. Johnston, R. Beebe
K. Johnston, R. Beebe
K. Johnston, R. Beebe
Corrections
Corrections
Additions and Corrections
PS004005-1100
P R E L I M I N A R Y
Document Information
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
136
Customer Feedback Form
MUZE Product Specification
If you experience any problems while operating this product, or if you note any inaccura-
cies while reading this Product Specification, please copy and complete this form, then
mail or fax it to ZiLOG (see Return Information, below). We also welcome your sugges-
tions!
Customer Information
Name
Country
Phone
Fax
Company
Address
City/State/Zip
E-Mail
Product Information
Serial # or Board Fab #/Rev. #
Software Version
Document Number
Host Computer Description/Type
Return Information
ZiLOG
System Test/Customer Support
910 E. Hamilton Avenue, Suite 110, MS 4–3
Campbell, CA 95008
Fax: (408) 558-8536
Email: tools@zilog.com
Problem Description or Suggestion
Provide a complete description of the problem or your suggestion. If you are reporting a
specific problem, include all steps leading up to the occurrence of the problem. Attach
additional pages as necessary.
_______________________________________________________________________________
_______________________________________________________________________________
_______________________________________________________________________________
_______________________________________________________________________________
_______________________________________________________________________________
_______________________________________________________________________________
PS004005-1100
P R E L I M I N A R Y
Customer Feedback Form
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
137
Index
A
C
Absolute Maximum Ratings . . . . . . . . . . . .75
AC Electrical Characteristics . . . . . . . . . . . .86
Additional Timing . . . . . . . . . . . . . . . . . . . .91
Address output . . . . . . . . . . . . . . . . . . . . . .20
Address Strobe . . . . . . . . . . . . . . . .12, 16, 20
Ambient Temperature . . . . . . . . . . . . . . . . .75
AN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
AN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
ANALOG mode . . . . . . . . . . . . . . . . . . . . . .25
Architectural Overview . . . . . . . . . . . . . . . . .1
AS . . . . . . . .12, 16, 20, 22, 28, 41, 56, 87–90
ASCI Control Register A . . . . . . . . . . .25, 112
ASCI Control Register B . . . . . . . . . . . . . .115
ASCI Data Format Mode . . . . . . . . . . . . . .113
Control Bits . . . . . . . . . . . . . . . . . . . . .113
ASCI Extension Control Register . . . .65, 108
ASCI Status FIFO/Registers . . . . . . . . . . .108
ASCI Time Constant High Register . . .66–67
ASCI Time Constant Low Register . . . . . . .66
ASEXT . . . . . . . . . . . . . . . . . . . .61, 113, 116
ASEXT register . . . . .108, 116, 118, 120–121
ASTH . . . . . . . . . . . . . . . . . .61, 65, 117, 121
ASTL . . . . . . . . . . . . . . . . . . .61, 65, 117, 121
ASTL Register Bit Functions . . . . . . . .66, 118
Autolatch . . . . . . . . . . . . . . . . . .24, 27, 76, 81
High Current . . . . . . . . . . . . . . . . . .80, 85
Low Current . . . . . . . . . . . . . . . . . .79, 84
AUTOLATCH DISABLE option . . . . . . . . . .27
AUTOLATCH Mode . . . . . . . . . . . . . . . . .103
Capacitance . . . . . . . . . . . . . . . . . . . . . . . 101
Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . 59
ceramic resonator . . . . . . . . . . 3, 20, 38, 103
Change Log . . . . . . . . . . . . . . . . . . . . . . . 135
Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Clock Input . . . . . . . . . . . . . . . . . . . . . . 92, 95
High Voltage . . . . . . . . . . . . . . . . . 76, 81
Low Voltage . . . . . . . . . . . . . . . . . . 76, 81
Clock Source . . . . . . . . . . . . . . . . . . . . . . 116
for WDT . . . . . . . . . . . . . . . . . . . . . . . . 47
CMOS- compatible . . . . . . . . . . . . 20, 22, 23
CMOS level . . . . . . . . . . . . . . . . . . . . 27, 103
CNTLA . . . . . . . . . . 25, 61, 63, 105, 111, 115
register . . . . . . . . . . . . . . . . 108, 118, 120
CNTLB . . . . . . . . .61, 64, 105, 108, 112, 113,
114, 120, 121
register . . . . . . . . . . . . . . . . . . . . 108, 117
Cold or Warm Start . . . . . . . . . . . . . . . . . . 45
comparator front end . . . . . . . . . . . . . . . . . 25
Comparator Inputs and Outputs . . . . . . . . 25
Comparator Output . . . . . . . . . . . . 26, 39, 69
Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . 40
comparator reference voltage . . . . . . . . . . 25
input . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Comparator1 . . . . . . . . . . . . . . . . . . . . . . . 37
Comparator2 . . . . . . . . . . . . . . . . . . . . . . . 37
comparators, onboard . . . . . . . . . . . . . . . . 24
Control Register A . 25, 61, 63, 105, 111, 115
Control Register B . . . . . . . .61, 64, 105, 108,
112, 113, 114, 120, 121
Control Registers . . . . . . . . . . . . . . . . . . . . 50
Counter/Timer 0 . . . . . . . . . . . . . . . . . . . . . 53
Register . . . . . . . . . . . . . . . . . . . . . . . . 53
Counter/Timer 1 . . . . . . . . . . . . . . . . . . 24, 52
Register . . . . . . . . . . . . . . . . . . . . . . . . 52
Counter/Timers . . . . . . . . . . . . . . . . . . . . . 34
B
Baud Rate Generation . . . . . . . . . . .108, 121
Break detect . . . . . . . . . . . . . . . . . . .105, 117
bit . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
BRG mode . . . . . . . . . . . .115, 117–118, 121
BRG Prescaler . . . . . . . . . . . . . . . . . . . . .115
byte-programmed input buffers . . . . . . . . . .22
PS004005-1100
P R E L I M I N A R Y
Index
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
138
Crystal . . . . . . . . . . . . . . . . . . . .43, 46, 71, 72
clock . . . . . . . . . . . . . . . . . . . . . . . .47, 49
operation . . . . . . . . . . . . . . . . . . . . . . . .41
oscillation . . . . . . . . . . . . . . . . . . . . . . .39
pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Crystal 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Crystal 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Customer Feedback Form . . . . . . . . . . . .136
Customer Information . . . . . . . . . . . . . . . .136
Extended Temperature Range . . . . . . 81, 89
Extension Control Register . . . . . . . . 65, 116
External Clock Divide-by-Two . . . . . . . . . . 43
External Clock Generator . . . . . . . . . . 76, 81
external crystal oscillation . . . . . . . . . . . . . 39
External Memory Timing . . . . . . . . . . . . . . 55
external memory transfer . . . . . . . . . . . . . . 20
External Program Memory . . . . . . . 25, 31–32
external single-phase clock . . . . . . . . . . . . 20
External Timing Input . . . . . . . . . . . . . . . . . 52
D
F
D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
D1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
D2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
D4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
D5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
D6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
D7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41, 45
Data Memory . . . . . . . . .1, 20, 24, 30, 31, 34
Select . . . . . . . . . . . . . . . . . . . . . . . . . .25
Data Strobe . . . . . . . . . . . . . . . . . . .12, 16, 20
DAV1 . . . . . . . . . . . . . . . . . . . . . . . . . . .22, 55
DC Electrical Characteristics . . . . . . . . . . .76
Decimal Adjust Flag . . . . . . . . . . . . . . . . . .59
Divide Ratio . . . . . . . . . . . . . . . .115, 121, 123
DM . . . . . . . . . . . . . . . . . . .25, 31, 55, 88, 90
DMA applications . . . . . . . . . . . . . . . . .21, 22
Document Information . . . . . . . . . . . . . . . .135
Document Number Description . . . . . . . . .135
DS . . . . . . . .12, 16, 20–22, 28, 41, 56, 87–90
FE . . . . . . . . . . . . . . . . . . . . . . . . . . 113, 120
Flag Register . . . . . . . . . . . . . . . . . . . . . . . 59
floating node . . . . . . . . . . . . . . . . . . . . . . . 27
framing error . . . . . . . . . . . . . . 108, 117, 120
Full-Duplex UART . . . . . . . . . . . . . . . . . . . . 2
Functional Block Diagram . . . . . . . . . . . . . . 4
G
General-Purpose Registers . . . . . . . . . . . . 34
GND . . . . . . . . 1, 5, 8, 12, 14, 16, 18, 20, 100
GPR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
H
Half Carry Flag . . . . . . . . . . . . . . . . . . . . . 59
HALT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
HALT mode . . . . . . . . . . . . 39, 43, 47, 78, 83
handshake control . . . . . . . . . . . . . 20, 22, 23
lines . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
HANDSHAKE mode . . . . . . . . . . . . . . . . . 23
handshake signal assignment . . . . . . . . . . 23
Handshake signal direction . . . . . . . . . . . . 20
high-impedance state . . . . . . . . . . . . . 20–22
E
EFR . . . . . . . . . . . . . . . . . . . . . . . . . . .63, 113
bit . . . . . . . . . . . . . . . .107–108, 118, 120
Electrical Characteristics . . . . . . . . . . . . . . .75
EPROM Protect . . . . . . . . . . . . . . . . .32, 102
ERF . . . . . . . . . . . . . . . . . . . . . . . .1, 3, 32–33
Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Error Flag Reset . . . . . . . . . . . . .63, 112–113
Expanded Register File . . .1, 3, 32–33, 39, 60
Bank Fh . . . . . . . . . . . . . . . . . . . . . . . . .67
I
ICSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
initialization routine . . . . . . . . . . . . . . . . . . 21
input buffers . . . . . . . . . . . . . . . . . . 20, 22–23
PS004005-1100
P R E L I M I N A R Y
Index
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
139
Input Clock Period . . . . . . . . . . . . . . . . .92, 95
Input Common Mode . . . . . . . . . . . . . .79, 84
Input High Voltage . . . . . . . . . . . . . . . .76, 81
Input Leakage . . . . . . . . . . . . . . . . . . . .77, 82
Input Low Voltage . . . . . . . . . . . . . . . . .76, 81
internal clock . . . . . . . . . . . . . . . . . .34, 39, 49
output . . . . . . . . . . . . . . . . . . . . . . . . . .51
Interrupt Edge . . . . . . . . . . . . . . . . . . . . . . .57
Select . . . . . . . . . . . . . . . . . . . . . . . . . .37
Interrupt Group Priority . . . . . . . . . . . . . . . .56
interrupt inputs . . . . . . . . . . . . . . . . . . . . . .37
falling-edge . . . . . . . . . . . . . . . . . . . . . .24
Interrupt Mask Register . . . . . . . . . . . . . . . .58
Interrupt Priority Register . . . . . . . . . . . . . .56
Interrupt Request . . . . . . . . . . . . . . . . .93, 96
Register . . . . . . . . . . . . . . . . . . . . . . . . .57
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .36
ASCI . . . . . . . . . . . . . . . . . . . . . . . . . .109
edge-triggered . . . . . . . . . . . . . . . . . . . .24
external . . . . . . . . . . . . . . . . . . . . . . . . .39
Receive Shift Register . . . . . . . . . . . .106
Z8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
IRQ0 . . . . . . . . . . . . . . . . . .25, 36, 39, 57, 58
IRQ1 . . . . . . . . . . . . . . . . . .25, 36, 39, 57, 58
source . . . . . . . . . . . . . . . . . . . . . . . . . .25
IRQ2 . . . . . . . . . . . . . . . . . .25, 36, 39, 57, 58
IRQ3 . . . . . . . 25, 37, 39, 56, 58, 65, 67, 109,
117, . . . . . . . . . . . . . . . . . . . . . . . .119–121
IRQ4 . . . . . . . . . . . . . . . . . . . . . . . .34, 37, 57
IRQ5 . . . . . . . . . . . . . . . . . . . . .34, 37, 56–57
Low-EMI Port 3 . . . . . . . . . . . . . . . . . . . . . 41
M
Memory address transfers . . . . . . . . . . . . . 20
Mode Select . . . . . . . . . . . . . . . . . . . . . . . . 63
MPBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
MPE . . . . . . . . . . . . . . . . . . . . . . . . . . 63, 111
bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
multiplexed Address/Data mode . . . . . . . . 22
multiplexed ports . . . . . . . . . . . . . . . . . . . . 22
Multiprocessor Bit Receive (Read only) . 113
Multiprocessor Bit Received . . . . . . . 63, 112
Multiprocessor Bit Transmit . . . . . . . . . . . 115
Multiprocessor Bit Transmitter . . . . . . 64, 114
Multiprocessor Enable . . . . . . . . 63, 111, 112
MULTIPROCESSOR mode . . .105, 108, 112,
113, 115
N
nibble-programmed input buffers . . . . . . . . 20
O
Offset Voltage . . . . . . . . . . . . . . . . . . . 77, 82
onboard comparators . . . . . . . . . . . . . . . . 24
on-chip oscillator . . . . . . . . . . . . . . . 3, 20, 38
Oscillator Operational Mode . . . . . . . . . . 103
Oscillator Startup Time . . . . . . . . . . . . 93, 96
Output High Voltage . . . . . . . . . . . 76, 77, 81
Output Leakage . . . . . . . . . . . . . . . . . . 78, 82
Output Low Voltage . . . . . . . . . . . . . . . 77, 82
Overflow Flag . . . . . . . . . . . . . . . . . . . . . . 59
Overrun Error . . . . . . . . . . 105, 106, 108, 120
bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
L
LC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3, 38
network . . . . . . . . . . . . . . . . . . . . . . . . .20
oscillator . . . . . . . . . . . . . .39, 92, 95, 103
Low-EMI Emission . . . . . . . . . . . . . . . . . . .41
LOW-EMI mode . . . . . .22, 41, 76–77, 81–82
Low-EMI Oscillator . . . . . . . . . . . . .39–41, 69
mode . . . . . . . . . . . . . . . . . . . . .41, 92, 95
Low-EMI output buffers . . . . . . . . . .20, 22–24
Low-EMI Port 0 . . . . . . . . . . . . . . . . . . . . . .41
Low-EMI Port 1 . . . . . . . . . . . . . . . . . . . . . .41
Low-EMI Port 2 . . . . . . . . . . . . . . . . . . . . . .41
P
P3M . . . . . . . . . . . . . . . 24, 25, 28, 31, 46, 54
parallel-resonant crystal . . . . . . . . . . . . . . 20
Parity Error . . . . . . . . . . . . . . . . . . . 108, 120
Parity Even/Odd . . . . . . . . . . . . . . . 113, 115
PS004005-1100
P R E L I M I N A R Y
Index
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
140
Part Number Description . . . . . . . . . . . . . .134
PCON . . . . . . . . . . . . . . . . . . . . . . .28, 33, 39
Register . . . . . . . . . . . . . . . . . . .22, 39, 41
Register Bit . . . . . . . . . . . . . . . . . . . . . .25
PE . . . . . . . . . . . . . . . . . . . . . . . . . . .113, 120
PEO . . . . . . . . . . . . . . . . . . . . .113, 115, 120
Pin Description . . . . . . . . . . . . . . . . . . . . . . .5
Plastic Standard Flow . . . . . . . . . . . . . . . .134
POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
POR Only . . . . . . . . . . . . . . . . .43, 45, 71, 72
Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
mode register . . . . . . . . . . . . . . . . . . . .21
Open-Drain . . . . . . . . . . . . . . . . . . . . . .41
Pull-Ups . . . . . . . . . . . . . . . . . . . . . . .103
Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Open-Drain . . . . . . . . . . . . . . . . . . . . . .40
Pull-Ups . . . . . . . . . . . . . . . . . . . . . . .103
Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Mode Register . . . . . . . . . . . . . . . . . . . .54
Pull-Ups . . . . . . . . . . . . . . . . . . . . . . .103
Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Mode Register . . . . . . . . . . .24, 31, 54, 55
mode register . . . . . . . . . . . . . . . . . . . .25
Pin Assignments . . . . . . . . . . . . . . . . . .25
Port Configuration Register . . . . . . . . . .39, 69
Power Supply . . . . . .5, 6, 7, 9, 11, 13, 15, 17
power-on cycle . . . . . . . . . . . . . . . . . . . . . .42
Power-On Reset . .3, 27, 29, 38, 47, 120, 121
Delay . . . . . . . . . . . . . . . . . . . . . . . .94, 96
Precharacterization Product . . . . . . . . . . .134
Prescale bit . . . . . . . . . . . . . . . . . . . . . . . .115
prescale factor . . . . . . . . . . . . . . . . . . . . .115
prescaler . . . . . . . . . . . . . . . . . . . . . . .43, 123
Prescaler 0 Register . . . . . . . . . . . . . . . . . .53
Prescaler 1 Register . . . . . . . . . . . . . . . . . .52
Prescaler Modulo . . . . . . . . . . . . . . . . .52, 53
prescaler, 6-bit programmable . . . . . . . .3, 34
prescaler, T1 . . . . . . . . . . . . . . . . . . . . . . . .34
Problem Description or Suggestion . . . . .136
Product Information . . . . . . . . . . . . . . . . . .136
program memory . . . . . . . . . . . . . . .1, 30, 102
vector location . . . . . . . . . . . . . . . . . . . .37
external . . . . . . . . . . . . . . . . . . . . . . . . .25
programmable Watch-Dog Timers . . . . . . . .1
R
RAM Protect . . . . . . . . . . . . . . . . 32, 58, 102
RC . . . . . . . . . . . . . . . . . . . . . . . 3, 47, 92, 95
circuit, external . . . . . . . . . . . . . . . . . 103
network . . . . . . . . . . . . . . . . . . . . . . . . 20
oscillator . . . . . . . . . . . . . . . . . 38–39, 46
RC OSCILLATOR ENABLED . . . . . . . . . 103
RC Select for WDT . . . . . . . . . . . . . . . . . . 46
RDR . . . . . . . . . . . . . . . . . . . . . . . 61, 62, 111
RDRNE . . . . . . . . . . . . . . . . . . 111, 119, 120
bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
RDY1 . . . . . . . . . . . . . . . . . . . . . . . . . . 22, 55
RE . . . . . . . . . . . . . . . . . . . . . . . . 25, 63, 105
READ operation . . . . . . . . . . . . . . . . . . . . . 20
READ/WRITE signal . . . . . . . . . . . . . . . . . 20
Receive Data FIFO . . . . . . . . . . . . . . . . . 106
Receive Data Register . . . . . . . . . . . . 62, 111
Receive Data Register Not Empty . . 111, 119
Receive Shift Register . . . . . . . . . . . . . . . 105
Receiver Enable . . . . . . . . . . . . . . . . . . . 112
Receiver Interrupt Enable . . . . . . . . . . . . 120
Register File . . . . . . . . . . . . . . . . . . . . . 1, 32
Register Pointer Register . . . . . . . . . . . . . 59
RESET . . . . . . . . . . . . . . . . . . . . . . . . 27, 108
delay . . . . . . . . . . . . . . . . . 42, 45, 94, 96
Reset Input Current . . . . . . . . . . . . . . . 78, 83
Reset Input High Voltage . . . . . . . . . . . 77, 82
Reset Input Low Voltage . . . . . . . . . . . 77, 82
Reset Output Low Voltage . . . . . . . . . . 77, 82
RESET pin . . . . . . . . . . . . . . . . . . . 27, 30, 75
Return Information . . . . . . . . . . . . . . . . . . 136
RIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
ROM mode . . . . . . . . . . . . . . . 20–21, 30–31
ROM pin . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ROM selectivity . . . . . . . . . . . . . . . . . . . . . . 1
ROMless mode . . . . . . . . . . . . . . . . . . 21, 34
ROMless pin . . . . . . . . . . . . . . . . . . . . . . . 20
ROMless selectivity . . . . . . . . . . . . . . . . . . . 1
RX Interrupt on Start . . . . . . . . . . . . . . . . 117
RX State . . . . . . . . . . . . . . . . . . . . . . . . . 117
S
Schmitt-triggered input buffers . . . . . . 20, 22
PS004005-1100
P R E L I M I N A R Y
Index
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
141
SCLK . . 41, 43, 46–47, 71, 73, 87, 89, 92, 95,
108, 116–117, 121, 123
T0 output . . . . . . . . . . . . . . . . . . . . . . . . . . 34
T0 prescaler . . . . . . . . . . . . . . . . . . . . . . . . 34
T1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Count . . . . . . . . . . . . . . . . . . . . . . . . . . 51
prescaler . . . . . . . . . . . . . . . . . . . . . . . 34
TCLK . . . . . . . . . . . 41, 43, 71, 87, 89, 92, 95
TDR . . . . . . . . . . . . . . . . . . . . . . . 61, 62, 110
TDRE . . . . . . . . . . . . . . . . . . . . 113, 120, 121
TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25, 63
TIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Time Constant Register High . . . . . . 66, 118
Time Constant Register Low . . . . . . . 66, 118
Timer Input . . . . . . . . . . . . . . . . . . . . . 92, 95
Timer Mode Register . . . . . . . . . . . . . . . . . 51
SCLK/TCLK Divide-by-16 Select . . . . . . . .43
Send Break . . . . . . . . . . . . . . . . . . . . . . . .118
Sign Flag . . . . . . . . . . . . . . . . . . . . . . . . . . .59
SMR . . . . . .28, 33, 37–38, 41, 46, 70, 92, 95
SMR2 . . . . . . . . . . . . . . . . . . . .33, 37, 45, 72
Speed Select . . . . . . . . . . . . . . . . . . . . . . .116
Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Stack Pointer . . . . . . . . . . . . . . . . . . . . .34, 60
High Register . . . . . . . . . . . . . . . . . . . .60
Low Register . . . . . . . . . . . . . . . . . . . . .60
Stack Selection . . . . . . . . . . . . . . . . . . . . . .56
Standard Output . . . . . . . . . . . . . . . . . .40, 69
Standard Temperature Range . . . . . . .76, 87
Standard Test Conditions . . . . . . . . . . . . .100
Standby Current . . . . . . . . . . . .78, 79, 83, 84
STAT . . . . . . . . . . . . . . . . . . . . . . .61, 67, 119
STAT register . . . . . . .67, 111, 113, 119–121
STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Stop Delay . . . . . . . . . . . . . . . . . . . . . .46, 71
STOP mode . . 28, 39, 45-47, 71, 79, 84, 103
delay . . . . . . . . . . . . . . . . . . . . . . . .92, 95
Stop-Mode Recovery . 27, 34, 38–39, 42–43,
47, 50, 61, 68, 71
Delay Select . . . . . . . . . . . . . . . . . . . . .45
Edge Select . . . . . . . . . . . . . . . . . . . . . .45
Register . . . . . . . . . . . . . . . . . . . . . .41, 70
Register 1 . . . . . . . . . . . . . . . . . . . . . . .70
Register 2 . . . . . . . . . . . . . . . . . . . .45, 72
Source . . . . . . . . . . . . . .29, 37, 43, 45, 71
Source 2 . . . . . . . . . . . . . . . . . . . . . . . .72
Width Spec . . . . . . . . . . . . . . . . . . .93, 96
Storage Temperature . . . . . . . . . . . . . . . . .75
Supply Current . . . . . . . . . . . . . . . . . . .78, 83
system clock . . . . . . . . . . . . . .41, 43, 47, 121
option, WDT DRIVEN BY . . . . . . . . . .103
SOURCE option . . . . . . . . . . . . . . . . .103
system clocks, internal . . . . . . . . . . . . . . . .46
T
. . . . . . . . . . . . . . . . . . . . . . 25, 36, 52, 54
mode . . . . . . . . . . . . . . . . . . . . . . . 34, 51
IN
Total Power Dissipation . . . . . . . . . . . . . . . 75
. . . . . . . . . . . . . . . . . . . . . . . . . . 25, 54
T
OUT
mode . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Transmit Data Register . . . . . . . 62, 105, 110
Empty . . . . . . . . . . . . . . . . . . . . . . . . 120
Transmit Interrupt Enable . . . . . . . . . . . . 121
Transmit Shift Register . . . . . . . . . . . . . . 105
Transmitter Enable . . . . . . . . . . . . . . 63, 112
trigger input . . . . . . . . . . . . . . . . . . . . . 34, 51
two-NOP delay . . . . . . . . . . . . . . . . . . . . . 26
U
UART . . . . . . . . . . . . . . . . . . . . . 2, 37, 39, 57
onboard ASCI . . . . . . . . . . . . . . . . . . . 25
User Flags . . . . . . . . . . . . . . . . . . . . . . . . . 59
V
VBO . . . . . . . . . . . . . . . . . . . . . . . . . . . 3, 104
V
. . . . . . .1, 5–7, 9, 11, 13, 15, 17, 20, 34,
CC
47, 76–77, 87, 89, 98–99, 101, 104
Low-Voltage Protection . . . . . . . . . . . . 48
Low Voltage Protection Voltage . . 80, 85
Power-On Reset . . . . . . . . . . . . . . . . . 38
T
Verify Register . . . . . . . . . . . . . . . . . . . 33, 70
VFY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Voltage Comparator . . . . . . . . . . . . . . . . . 48
T0 Count . . . . . . . . . . . . . . . . . . . . . . . . . . .51
T0 Output . . . . . . . . . . . . . . . . . . . . . . . . . .51
PS004005-1100
P R E L I M I N A R Y
Index
Z86E12X/Z86E13X/Z86E14X
The MUZE Family of Z8 Microcontrollers
142
W
X
IN
wake-up circuitry . . . . . . . . . . . . . . . . . . . . . .1
Watch-Dog Timer . . .1, 3, 29, 72, 93, 96, 103
Mode Register . . . . . . . . . . . . . . . . .46, 72
reset . . . . . . . . . . . . . . . . . . . . . . . . . . .27
WDT Mode . . . . . . . . . . . . . . . . . . . . . . . .103
WDT Time Select . . . . . . . . . . . . . . . . . . . .47
WDT time-out . . . . . . . . . . . . . .38, 39, 46, 47
WDTMR . . . . . . . . . . . . . . . . . .28, 33, 46, 72
During HALT . . . . . . . . . . . . . . . . . . . . .47
During STOP . . . . . . . . . . . . . . . . . . . . .47
Register Accessibility . . . . . . . . . . . . . .47
Working Register Pointer . . . . . . . . . . . . . .59
WRITE operations . . . . . . . . . . . . . . . . . . . .20
X
X
. . . . . . 5, 7, 12, 15, 20, 38, 72, 75–76, 81
pin . . . . . . . . . . . . . . . . . . . . . . . . 46, 103
IN
X , external pin . . . . . . . . . . . . . . . . . . . . . 47
IN
X
X
. . . . . . . . . . 5, 7, 12, 15, 20, 38, 76, 81
pin . . . . . . . . . . . . . . . . . . . . . . . . . 103
OUT
OUT
Z
Z8 MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Zero Flag . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PS004005-1100
P R E L I M I N A R Y
Index
相关型号:
Z86E133SZ016EG
IC 8-BIT, OTPROM, MICROCONTROLLER, PDSO28, SOIC-28, MicrocontrollerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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ZILOG
Z86E134PZ016EG
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Z86E134SZ016SG
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Z86E134SZ16SC
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Z86E135PZ016EG
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Z86E136PZ016EG
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Z86E136PZ016SG
IC 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PDIP28, DIP-28, MicrocontrollerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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Z86E142FZ016EG
Microcontroller, 8-Bit, OTPROM, 16MHz, CMOS, PQFP44, QFP-44Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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ZILOG
Z86E142FZ016SG
IC 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP44, QFP-44, MicrocontrollerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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ZILOG
Z86E142FZ16EC
Microcontroller, 8-Bit, OTPROM, 16MHz, CMOS, PQFP44, PLASTIC, QFP-44Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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IXYS
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