Z8E00110PSG [IXYS]
Microcontroller, 8-Bit, OTPROM, 10MHz, CMOS, PDIP20, PLASTIC, DIP-18;
| 型号： | Z8E00110PSG |
| 厂家： | 
IXYS CORPORATION |
| 描述： | Microcontroller, 8-Bit, OTPROM, 10MHz, CMOS, PDIP20, PLASTIC, DIP-18 可编程只读存储器 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总46页 (文件大小：730K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
Z8E001
1
FEATURE-RICH Z8PLUS ONE-TIME
PROGRAMMABLE (OTP) MICROCONTROLLER
FEATURES
Ð
Includes Special Functionality: Stop-Mode Re-
covery Input, Comparator Inputs, Selectable Edge
Interrupts, and Timer Output
Part
Number
ROM
(KB)
RAM*
(Bytes)
Speed
(MHz)
Z8E001
1
64
10
¥ One Analog Comparator
Note: * General-Purpose
¥ 16-Bit Programmable Watch-Dog Timer (WDT)
¥ Software Programmable Timers Configurable as:
Microcontroller Core Features
¥ All Instructions Execute in one 1 µs Instruction Cycle
Ð
Two 8-Bit Standard Timers and One 16-Bit Stan-
dard Timer, or
with a 10 MHz Crystal
¥ 1K x 8 On-Chip OTP EPROM Memory
¥ 64 x 8 General-Purpose Registers (SRAM)
¥ Six Vectored Interrupts with Fixed Priority
¥ Operating Speed: DCÐ10 MHz
Ð
One 16-Bit Standard Timer and One 16-Bit Pulse
Width Modulator (PWM) Timer
Additional Features
¥ On-Chip Oscillator that accepts an XTAL, Ceramic Res-
onator, LC, or External Clock
¥ Six Addressing Modes: R, IR, X, D, RA, & IM
¥ Programmable Options:
Peripheral Features
Ð
EPROM Protect
¥ 13 Total Input/Output Pins
¥ One 8-Bit I/O Port (Port A)
¥ Power Reduction Modes:
Ð
Ð
HALT Mode with Peripheral Units Active
STOP Mode with all Functionality Shut Down
Ð
Ð
I/O Bit Programmable
Each Bit Programmable as Push-Pull or Open-
Drain
CMOS/Technology Features
¥ Low-Power Consumption
¥ One 5-Bit I/O Port (Port B)
I/O Bit Programmable
Ð
¥ 3.5V to 5.5V Operating Range @ 0°C to +70°C
4.5V to 5.5V Operating Range @ Ð40°C to +105°C
¥ 18-Pin DIP, SOIC, and 20-Pin SSOP Packages.
GENERAL DESCRIPTION
Allowing easy software development, debug, and prototyp-
ing, ZiLOGÕs new Z8E001 Microcontroller (MCU) offers
acost-effectiveOne-TimeProgrammable(OTP)solutionto
its single-chip Z8Plus MCU family.
For applications demanding powerful I/O capabilities, the
Z8E001Õs dedicated input and output lines are grouped into
two ports, and are configurable under software control.
Both 8-bit and 16-bit on-chip timers, with a large number
of user-selectable modes, offload the system of administer-
DS001101-Z8X0400
1
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
GENERAL DESCRIPTION (Continued)
ing real-time tasks such as counting/timing and I/O data
communications.
Power connections follow conventional descriptions be-
low:
Connection
Power
Circuit
Device
Note: All signals with an overline, Ò Ó, are active Low. For
example, B/W (WORD is active Low, only); B/W
(BYTE is active Low, only).
V
V
CC
DD
Ground
GND
V
SS
RESET
XTAL
GND
V
CC
Two 8-bit Timers
or
One 16-bit PWM
Timer
Machine
Timing
ALU
FLAG
One 16-bit
Std. Timer
OTP
Prg. Mem-
Interrupt
Control
Register
Pointer
Program
Counter
One Analog
Comparator
RAM
Register
Port A
I/O
Port B
I/O
Figure 1. Functional Block Diagram
2
P R E L I M I N A R Y
DS001101-Z8X0400
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
D7Ð0
AD9Ð0
Z8E001 MCU
AD9Ð0
ADDRESS
MUX
DATA
MUX
EPROM
D7Ð0
AD9Ð0
ADDRESS
GENERATOR
Z8E001
D7Ð0
PORT
A
ROM PROT
OPTION BIT
PGM + TEST
MODE LOGIC
PGM
ADCLR/V
PP
ADCLK
XTAL1
Figure 2. EPROM Programming Mode Block Diagram
DS001101-Z8X0400
P R E L I M I N A R Y
3
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
PIN DESCRIPTION
1
PGM
GND
GND
GND
18
ADCLK
XTAL1
NC
GND
18-Pin DIP
ADCLR/V
V
DD
PP
D7
D6
D5
D4
D0
D1
D2
D3
9
10
Figure 3. 18-Pin DIP/SOIC Pin Identification/EPROM Programming Mode
EPROM Programming Mode
Pin #
Symbol
Function
Direction
1
PGM
Prog Mode
Input
2Ð4
5
GND
Ground
ADCLR/V
Clear Clk./Prog Volt.
Input
PP
6-9
D7ÐD4
D3ÐD0
Data 7,6,5,4
Data 3,2,1,0
Power Supply
Input/Output
Input/Output
10Ð13
14
V
DD
15
16
17
18
GND
Ground
NC
No Connection
1MHz Clock
Address Clock
XTAL1
ADCLK
Input
Input
4
P R E L I M I N A R Y
DS001101-Z8X0400
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
1
PB1
PB2
PB3
PB4
RST
PA7
PA6
PA5
PA4
18
PBO
XTAL1
XTAL2
V
SS
DIP 18-Pin
V
CC
PA0
PA1
PA2
PA3
9
10
Figure 4. 18-Pin DIP/SOIC Pin Identification
Standard Mode
Pin #
Symbol
Function
Direction
1Ð4
5
PB1ÐPB4
RESET
Port B, Pins 1,2,3,4
Reset
Input/Output
Input
6-9
10Ð13
14
PA7ÐPA4
PA3ÐPA0
Port A, Pins 7,6,5,4
Port A, Pins 3,2,1,0
Power Supply
Input/Output
Input/Output
V
V
CC
SS
15
Ground
16
17
18
XTAL2
XTAL1
PB0
Crystal Osc. Clock
Crystal Osc. Clock
Port B, Pin 0
Output
Input
Input/Output
DS001101-Z8X0400
P R E L I M I N A R Y
5
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
PIN DESCRIPTION (Continued)
1
PB1
PB2
PB3
20
PBO
XTAL1
XTAL2
V
PB4
SS
RESET
NC
V
SSOP 20-Pin
CC
NC
PA7
PA6
PA5
PA4
PA0
PA1
PA2
PA3
10
11
Figure 5. 20-Pin SSOP Pin Identification
Standard Mode
Pin #
Symbol
Function
Direction
1Ð4
5
PB1ÐPB4
RESET
NC
Port B, Pins 1,2,3,4
Reset
Input/Output
Input
6
No Connection
Port A, Pins 7,6,5,4
Port A, Pins 3,2,1,0
No Connection
Power Supply
7Ð10
11Ð14
15
PA7ÐPA4
PA3ÐPA0
NC
Input/Output
Input/Output
16
V
V
CC
SS
17
Ground
18
19
20
XTAL2
XTAL1
PB0
Crystal Osc. Clock
Crystal Osc. Clock
Port B, Pin 0
Output
Input
Input/Output
6
P R E L I M I N A R Y
DS001101-Z8X0400
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
1
PGM
GND
GND
GND
20
ADCLK
XTAL1
NC
GND
ADCLR/V
V
PP
NC
D7
D6
D5
D4
DD
SSOP 20-Pin
NC
D0
D1
D2
D3
10
11
Figure 6. 20-Pin SSOP Pin Identification/EPROM Programming Mode
EPROM Programming Mode
Pin #
Symbol
Function
Direction
1
PGM
Prog Mode
Input
2Ð4
5
GND
Ground
ADCLR/V
Clear Clk./Prog Volt.
Input
PP
6
NC
No Connection
Data 7,6,5,4
7Ð10
11Ð14
15
D7ÐD4
D3ÐD0
NC
Input/Output
Input/Output
Data 3,2,1,0
No Connection
Power Supply
16
V
DD
17
18
19
20
GND
Ground
NC
No Connection
1MHz Clock
Address Clock
XTAL1
ADCLK
Input
Input
DS001101-Z8X0400
P R E L I M I N A R Y
7
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
ABSOLUTE MAXIMUM RATINGS
Parameter
Min
Max
Units
Note
Ambient Temperature under Bias
Storage Temperature
Ð40
Ð65
Ð0.6
+105
+150
+7
C
C
V
Voltage on any Pin with Respect to V
SS
1
2
Voltage on V
Pin with Respect to V
Ð0.3
Ð0.6
+7
V
V
DD
SS
Voltage on RESET Pin with Respect to V
Total Power Dissipation
V
+1
SS
DD
880
80
mW
mA
Maximum Allowable Current out of V
SS
Maximum Allowable Current into V
DD
80
mA
Maximum Allowable Current into an Input Pin
Ð600
Ð600
+600
+600
25
mA
mA
mA
mA
mA
mA
mA
mA
3
4
Maximum Allowable Current into an Open-Drain Pin
Maximum Allowable Output Current Sunk by Any I/O Pin
Maximum Allowable Output Current Sourced by Any I/O Pin
Maximum Allowable Output Current Sunk by Port A
Maximum Allowable Output Current Sourced by Port A
Maximum Allowable Output Current Sunk by Port B
Maximum Allowable Output Current Sourced by Port B
25
40
40
40
40
Notes:
1. Applies to all pins except the RESET pin and where otherwise noted.
2. There is no input protection diode from pin to V
3. Excludes XTAL pins.
.
DD
4. Device pin is not at an output Low state.
Stresses greater than those listed under Absolute Maximum
Ratingscancausepermanentdamagetothedevice.Thisrat-
ingisastressratingonly. Functionaloperationofthedevice
at any condition above those indicated in the operational
sections of these specifications is not implied. Exposure to
absolutemaximumratingconditionsforanextendedperiod
can affect device reliability. Total power dissipation should
not exceed 880 mW for the package. Power dissipation is
calculated as follows:
Total Power Dissipation = V
x [I
DD
Ð (sum of I )]
OH
DD
+ sum of [(V
Ð V ) x I
]
DD
OH
)
OH
+ sum of (V x I
0L 0L
8
P R E L I M I N A R Y
DS001101-Z8X0400
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test con-
ditionsasnoted. AllvoltagesarereferencedtoGround. Pos-
itive current flows into the referenced pin (Figure 7).
From Output
Under Test
150 pF
Figure 7. Test Load Diagram
CAPACITANCE
T = 25¡C, V = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
A
CC
Parameter
Min
Max
Input capacitance
Output capacitance
I/O capacitance
0
0
0
12 pF
12 pF
12 pF
DS001101-Z8X0400
P R E L I M I N A R Y
9
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
DC ELECTRICAL CHARACTERISTICS
Table 1. DC Electrical Characteristics
pF TA = 0¡C to +70¡C
Standard Temperatures
2
Typical
@ 25¡C Units Conditions
1
V
Sym
Parameter
Min
Max
Notes
CC
V
Clock Input High
Voltage
3.5V
5.5V
3.5V
5.5V
0.7V
V
V
+0.3
1.3
2.5
0.7
1.5
V
V
V
V
Driven by External
Clock Generator
CH
CC
CC
0.7V
+0.3
Driven by External
Clock Generator
CC
CC
V
Clock Input Low
Voltage
V
V
Ð0.3
Ð0.3
0.2V
0.2V
Driven by External
Clock Generator
CL
SS
SS
CC
CC
Driven by External
Clock Generator
V
V
V
Input High Voltage
Input Low Voltage
3.5V
5.5V
0.7V
0.7V
V
V
+0.3
+0.3
1.3
2.5
V
V
IH
CC
CC
CC
CC
3.5V
5.5V
V
V
Ð0.3
Ð0.3
0.2V
0.2V
0.7
1.5
V
V
IL
SS
SS
CC
CC
Output High Voltage 3.5V
5.5V
V
V
Ð0.4
Ð0.4
3.1
4.8
0.2
0.1
0.5
0.5
1.1
2.2
0.9
1.4
V
V
V
V
V
V
V
V
V
V
IOH = Ð2.0 mA
IOH = Ð2.0 mA
IOL = +4.0 mA
IOL = +4.0 mA
IOL = +6 mA
OH
CC
CC
V
V
V
V
V
Output Low Voltage
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
0.6
0.4
1.2
1.2
OL1
Output Low Voltage
OL2
IOL = +12 mA
Reset Input High
Voltage
0.5V
0.5V
V
RH
CC
CC
CC
CC
V
Reset Input Low
Voltage
V
V
Ð0.3
Ð0.3
0.2V
0.2V
RL
SS
SS
CC
CC
Comparator Input
Offset Voltage
3.5V
5.5V
3.5V
25.0
10.0
10.0
mV
mV
OFFSET
25.0
2.0
I
I
Input Leakage
Ð1.0
Ð1.0
Ð1.0
Ð1.0
0.064
mA VIN = 0V, V
mA VIN = 0V, V
µA VIN = 0V, V
µA VIN = 0V, V
V
IL
CC
CC
CC
CC
5.5V
3.5V
5.5V
3.5V
5.5V
2.0
2.0
2.0
0.064
0.114
0.114
Output Leakage
OL
V
Comparator Input
Common Mode
Voltage Range
V
V
Ð0.3
V
V
Ð1.0
3
3
ICR
SS
SS
CC
CC
Ð0.3
Ð1.0
V
I
Reset Input Current
3.5V
5.5V
Ð10
Ð20
Ð60
Ð180
Ð30
µA
µA
IR
Ð100
10
P R E L I M I N A R Y
DS001101-Z8X0400
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
Table 1. DC Electrical Characteristics (Continued)
pF TA = 0¡C to +70¡C
Standard Temperatures
2
Typical
1
V
Sym
Parameter
Min
Max
@ 25¡C Units Conditions
Notes
CC
I
Supply Current
3.5V
5.5V
3.5V
2.5
6.0
2.0
2.0
3.5
1.0
mA @ 10 MHz
4,5
4,5
4,5
CC
mA @ 10 MHz
I
Standby Current
Standby Current
mA HALT Mode VIN = 0V,
CC1
V
@ 10 MHz
CC
5.5V
3.5V
4.0
2.5
mA HALT Mode VIN = 0V,
@ 10 MHz
4,5
6
V
CC
I
500
150
nA STOP Mode VIN = 0V,
CC2
V
CC
Notes:
1. The V voltage specification of 3.5V guarantees 3.5V and the V voltage specification of 5.5 V guarantees 5.0 V ±0.5 V.
CC
CC
2. Typical values are measured at V = 3.3V and V = 5.0V; V = 0V = GND.
CC
CC
SS
3. For analog comparator input when analog comparator is enabled.
4. All outputs unloaded and all inputs are at V or V level.
CC
SS
5. CL1 = CL2 = 22 pF.
6. Same as note 4 except inputs at V
.
CC
DS001101-Z8X0400
P R E L I M I N A R Y
11
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
DC ELECTRICAL CHARACTERISTICS (Continued)
Table 2. DC Electrical Characteristics
T = Ð40¡C to +105¡C
A
Extended Temperatures
2
Typical
@ 25¡C Units Conditions
1
V
Sym
Parameter
Min
Max
Notes
CC
V
Clock Input High
Voltage
4.5V
5.5V
4.5V
5.5V
0.7 V
V
V
+0.3
2.5
2.5
1.5
1.5
V
V
V
V
Driven by External
Clock Generator
CH
CC
CC
0.7 V
+0.3
Driven by External
Clock Generator
CC
CC
V
Clock Input Low
Voltage
V
V
Ð0.3
Ð0.3
0.2 V
0.2 V
Driven by External
Clock Generator
CL
SS
SS
CC
CC
Driven by External
Clock Generator
V
V
V
V
V
V
V
Input High Voltage
Input Low Voltage
4.5V
5.5V
4.5V
5.5V
0.7 V
0.7 V
V
V
+0.3
+0.3
2.5
2.5
1.5
1.5
4.8
4.8
0.1
0.1
0.5
0.5
1.1
2.2
V
V
V
V
V
V
V
V
V
V
V
V
IH
CC
CC
CC
CC
V
V
Ð0.3
Ð0.3
Ð0.4
Ð0.4
0.2 V
0.2 V
IL
SS
SS
CC
CC
CC
CC
Output High Voltage 4.5V
V
V
IOH = Ð2.0 mA
IOH = Ð2.0 mA
IOL = +4.0 mA
IOL = +4.0 mA
IOL = +12 mA
IOL = +12 mA
OH
5.5V
Output Low Voltage 4.5V
5.5V
0.4
0.4
1.2
1.2
OL1
OL2
RH
Output Low Voltage 4.5V
5.5V
Reset Input High
Voltage
4.5V
5.5V
0.5V
0.5V
V
CC
CC
CC
CC
V
Comparator Input
Offset Voltage
4.5V
5.5V
4.5V
25.0
25.0
2.0
10.0
10.0
<1.0
mV
mV
OFFSET
I
Input Leakage
Ð1.0
µA VIN = 0V, V
µA VIN = 0V, V
µA VIN = 0V, V
µA VIN = 0V, V
V
IL
CC
CC
CC
CC
5.5V
4.5V
5.5V
4.5V
5.5V
Ð1.0
Ð1.0
Ð1.0
0
2.0
2.0
2.0
<1.0
<1.0
<1.0
I
Output Leakage
OL
V
Comparator Input
Common Mode
Voltage Range
V
V
Ð1.5V
3
3
ICR
CC
CC
0
Ð1.5V
V
I
Reset Input Current 4.5V
5.5V
Ð18
Ð18
Ð180
Ð180
Ð112
Ð112
mA
mA
IR
12
P R E L I M I N A R Y
DS001101-Z8X0400
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
Table 2. DC Electrical Characteristics (Continued)
T = Ð40¡C to +105¡C
A
Extended Temperatures
2
Typical
@ 25¡C Units Conditions
1
V
Sym
Parameter
Min
Max
Notes
CC
I
Supply Current
4.5V
5.5V
4.5V
7.0
7.0
2.0
4.0
4.0
1.0
mA @ 10 MHz
4,5
4,5
4,5
CC
mA @ 10 MHz
I
Standby Current
Standby Current
mA HALT Mode VIN = 0V,
CC1
V
@ 10 MHz
CC
5.5V
4.5V
5.5V
2.0
700
700
1.0
250
250
mA HALT Mode VIN = 0V,
@ 10 MHz
4,5
6
V
CC
I
nA STOP Mode VIN
= 0V,V
CC2
CC
nA STOP Mode VIN
= 0V,V
6
CC
Notes:
1. The V voltage specification of 4.5V and 5.5V guarantees 5.0V ±0.5V.
CC
2. Typical values are measured at V = 3.3V and V = 5.0V; V = 0V = GND.
CC
CC
SS
3. For analog comparator input when analog comparator is enabled.
4. All outputs unloaded and all inputs are at V or V level.
CC
SS
5. CL1 = CL2 = 22 pF.
6. Same as note 4 except inputs at V
.
CC
DS001101-Z8X0400
P R E L I M I N A R Y
13
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
AC ELECTRICAL CHARACTERISTICS
1
3
CLOCK
3
2
2
IRQ
N
4
5
Figure 8. AC Electrical Timing Diagram
Table 3. Additional Timing
T = 0¡C to +70¡C
A
T = Ð40¡C to +105¡C
A
@ 10 MHz
1
V
No
Symbol
Parameter
Min
Max
Units
Notes
CC
1
TpC
Input Clock Period
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
100
100
DC
DC
15
ns
ns
ns
ns
ns
ns
ns
ns
2
2
2
2
2
2
2
2
2
2
2
TrC,TfC
TwC
Clock Input Rise and Fall Times
Input Clock Width
15
3
50
50
4
TwIL
Int. Request Input Low Time
Int. Request Input High Time
70
70
5
TwIH
Twsm
Tost
5TpC
5TpC
12
6
STOP Mode Recovery Width
Spec.
ns
ns
12
7
Oscillator Start-Up Time
5TpC
5TpC
Notes:
1. The V voltage specification of 3.5V guarantees 3.5V. The V voltage specification of 5.5V guarantees 5.0V ±0.5V.
DD
DD
2. Timing Reference uses 0.7 V for a logic 1 and 0.2 V for a logic 0.
CC
CC
14
P R E L I M I N A R Y
DS001101-Z8X0400
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
Z8PLUS CORE
The Z8E001 is based on the ZiLOG Z8Plus Core Architec-
ture. This core is capable of addressing up to 64KBytes of
program memory and 4KBytes of RAM. Register RAM is
accessed as either 8 or 16 bit registers using a combination
of 4, 8, and 12 bit addressing modes. The architecture sup-
ports up to 15 vectored interrupts from external and internal
sources. The processor decodes 44 CISC instructions using
six addressing modes. See the Z8Plus UserÕs Manual for
more information.
RESET
This section describes the Z8E001 reset conditions, reset
timing, and register initialization procedures. Reset is gen-
erated by the Reset Pin, Watch-Dog Timer (WDT), and
Stop-Mode Recovery (SMR).
are reset to their default conditions after a reset from
the RESET pin. The control registers and ports are not reset
to their default conditions after wakeup from Stop Mode or
WDT timeout.
A system reset overrides all other operating conditions and
puts the Z8E001 into a known state. To initialize the chipÕs
internal logic, the RESET input must be held Low for at
least 30 XTAL clock cycles. The control registers and ports
During RESET, the program counter is loaded with 0020H.
I/Oportsandcontrolregistersareconfiguredtotheirdefault
reset state. Resetting the Z8E001 does not affect the con-
tents of the general-purpose registers.
RESET PIN OPERATION
The Z8E001 hardware RESET pin initializes the control
and peripheral registers, as shown in Table 4. Specific reset
values are shown by 1 or 0, while bits whose states are un-
changed or unknown from Power-Up are indicated by the
letter U.
RESET to V . A pull-up resistor on the RESET pin is ap-
proximately 500 KΩ, typical.
CC
Program execution starts 10 XTAL clock cycles after RE-
SET has returned High. The initial instruction fetch is from
location 0020H. Figure 9 indicates reset timing.
RESET must be held Low until the oscillator stabilizes, for
an additional 30 XTAL clock cycles, in order to be sure that
theinternalresetiscomplete.TheRESETpinhasaSchmitt-
Trigger input with a trip point. There is no High side pro-
tection diode. The user should place an external diode from
After a reset, the first routine executed must be one that ini-
tializes the TCTLHI control register to the required system
configuration, followed by initialization of the remaining
control registers.
Table 4. Control and Peripheral Registers
Bits
Register (HEX) Register Name
7
6
5
4
3
2
1
0
Comments
FF
Stack Pointer
0
0
U
U
U
U
U
U
Stack pointer is not affected by
RESET
FE
FD
Reserved
Register Pointer
U
U
U
U
U
U
U
U
0
0
0
*
0
*
Register pointer is not affected by
RESET
FC
Flags
U
U
Only WDT & SMR flags are affected
by RESET
FB
FA
Interrupt Mask
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
All interrupts masked by RESET
Interrupt Request
All interrupt requests cleared by
RESET
F9ÐF0
EFÐE0
Reserved
Virtual Copy
Virtual Copy of the Current Working
Register Set
DFÐD8
Reserved
DS001101-Z8X0400
P R E L I M I N A R Y
15
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
RESET PIN OPERATION (Continued)
Table 4. Control and Peripheral Registers (Continued)
Bits
Register (HEX) Register Name
7
6
5
4
3
2
1
0
Comments
D7
D6
D5
D4
D3
D2
D1
D0
Port B Special
Function
0
0
0
0
0
0
0
0
Deactivates all port special functions
after RESET
Port B Directional
Control
0
U
U
0
0
U
U
0
0
U
U
0
0
0
U
U
0
0
U
U
0
0
U
U
0
0
U
U
0
Defines all bits as inputs in PortB
after RESET
Port B Output
U
U
0
Output register not affected by
RESET
Port B Input
Current sample of the input pin
following RESET
Port A Special
Function
Deactivates all port special functions
after RESET
Port A Directional
Control
0
0
0
0
0
0
0
0
Defines all bits as inputs in PortA
after RESET
Port A Output
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
Output register not affected by
RESET
Port A Input
Current sample of the input pin
following RESET
CF
CE
CD
CC
CB
CA
C9
C8
C7
C6
C5
C4
C3
C2
C1
Reserved
Reserved
T1VAL
U
U
U
U
U
U
U
U
U
U
1
U
U
U
U
U
U
U
U
U
U
1
U
U
U
U
U
U
U
U
U
U
1
U
U
U
U
U
U
U
U
U
U
1
U
U
U
U
U
U
U
U
U
U
1
U
U
U
U
U
U
U
U
U
U
1
U
U
U
U
U
U
U
U
U
U
1
U
U
U
U
U
U
U
U
U
U
1
T0VAL
T3VAL
T2VAL
T3AR
T2AR
T1ARHI
T0ARHI
T1ARLO
T0ARLO
WDTHI
WDTLO
TCTLHI
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
WDT Enabled in HALT Mode, WDT
timeout at maximum value, STOP
Mode disabled
C0
TCTLLO
0
0
0
0
0
0
0
0
All standard timers are disabled
Note: *The SMR and WDT flags are set indicating the source of the RESET.
16
P R E L I M I N A R Y
DS001101-Z8X0400
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
Table 5. Flag Register Bit D1, D0
D1
D0
Reset Source
0
0
1
1
0
1
0
1
RESET Pin
SMR Recovery
WDT Reset
Reserved
First Machine Cycle
Clock
RESET
Hold Low For 30 XTAL
Periods (Minimum)
10 XTAL CLOCK CYCLES
First Instruction Fetch
Figure 9. Reset Timing
V
CC
V
CC
100 K½
1K½
500 K½
RESET
Z8E001
1 µF
Figure 10. Example of External Power-On Reset (POR) Circuit
DS001101-Z8X0400
P R E L I M I N A R Y
17
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
RESET PIN OPERATION (Continued)
TCTLHI
D6,D5,D4
3
WDT TAP SELECT
WDTRST
XTAL
/64
16-BIT TIMER
WDTRST
WATCHDOG TIMER
SMR LOGIC
SMR
(PB0)
SMR
RECOVERY
Figure 11. Z8E001 Reset Circuitry with WDT and SMR
18
P R E L I M I N A R Y
DS001101-Z8X0400
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
Z8E001 WATCH-DOG TIMER (WDT)
The WDT is a retriggerable one-shot 16-bit timer that resets
theZ8E001ifitreachesitsterminalcount.TheWDTisdriv-
en by the XTAL2 clock pin. To provide the longer timeout
periods required in applications, the watchdog timer is only
updatedevery64thclockcycle.WhenoperatingintheRUN
or HALT Modes, a WDT timeout reset is functionally
equivalent to an interrupt vectoring the PC to 0020H and
setting the WDT flag to a one state. Coming out of RESET,
the WDT is fully enabled with its timeout value set at the
maximum value, unless otherwise programmed during the
first instruction. Subsequent executions of the WDT in-
struction,reinitializethewatchdogtimerregisters(C2Hand
C3H), to their initial values as defined by bits D6, D5, and
D4 of the TCTLHI register. The WDT cannot be disabled
except on the first cycle after RESET, and if the device en-
ters Stop mode.
get near 0. Because the WDT timeout periods are relatively
long, a WDT reset will occur in the unlikely event that the
WDT times out on exactly the same cycle that the WDT in-
struction is executed.
The WDT and SMR flags are the only flags that are affected
by the external RESET pin. RESET clears both the WDT
and SMR flags. A WDT timeout sets the WDT flag. The
STOP instruction sets the SMR flag. This behavior enables
software to determine whether a pin RESET occurred, or
whether a WDT timeout occurred, or whether a return from
STOP Mode occurred. Reading the WDT and SMR flags
does not reset it to zero, the user must clear it via software.
Note: Failure to clear the SMR flag can result in undefined be-
havior.
The WDT instruction should be executed often enough to
provide some margin before allowing the WDT registers to
0C1
TCTLHI
D0
D7
D6
D5
D3
D2
D1
D4
RESERVED (MUST BE 0)
0 = STOP MODE ENABLED
1 = STOP MODE DISABLED*
D6 D5 D4 WDT TIMEOUT VALUE
---- ---- ---- --------------------------------
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
DISABLED
65,536 TpC
131,072 TpC
262,144 TpC
524,288 TpC
1 1,048,576 TpC
0 2,097,152 TpC
1 4,194,304 TpC*
(XTAL CLOCKS TO TIMEOUT)
1 = WDT ENABLED IN HALT MODE*
0 = WDT DISABLED IN HALT MODE
*Designates Default Value after RESET
Figure 12. Z8E001 TCTLHI Register for Control of WDT
DS001101-Z8X0400
P R E L I M I N A R Y
19
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
STOP MODE (D3). Coming out of RESET, the Z8E001
STOP Mode is disabled. If an application requires use of
STOP Mode, bit D3 must be cleared immediately upon
leaving RESET. If bit D3 is set, the STOP instruction exe-
cutes as a NOP. If bit D3 is cleared, the STOP instruction
enters Stop Mode. Whenever the Z8E001 wakes up after
having been in STOP Mode, the STOP Mode is again dis-
abled.
Note: The WDT can only be disabled via software if the first
instruction out of RESET performs this function. Logic
within the Z8E001 detects that it is in the process of ex-
ecuting the first instruction after the part leaves RESET.
During the execution of this instruction, the upper five
bits of the TCTLHI register can be written. After this
first instruction, hardware does not allow the upper five
bits of this register to be written.
Bits 2, 1 and 0. These bits are reserved and must be 0.
Table 6. WDT Time-Out
The TCTLHI bits for control of the WDT are described be-
low:
Crystal Clocks* Time-Out Using
D6 D5 D4 to Timeout
a 10 MHZ Crystal
WDT Time Select (D6, D5, D4). Bits 6, 5, and 4 determine
the time-out period. Table 6 indicates the range of timeout
values that can be obtained. The default values of D6, D5,
and D4 are all 1, thus setting the WDT to its maximum tim-
eout period when coming out of RESET.
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Disabled
Disabled
6.55 ms
0
65,536 TpC
0
131,072 TpC
262,144 TpC
524,288 TpC
1,048,576 TpC
2,097,152 TpC
4,194,304 TpC
13.11 ms
26.21 ms
52.43 ms
104.86 ms
209.72 ms
419.43 ms
0
1
WDT During HALT (D7). This bit determines whether or
not the WDT is active during HALT Mode. A 1 indicates
active during HALT. A 0 prevents the WDT from resetting
the part while halted.Coming out of reset, the WDT is en-
abled during HALT Mode.
1
1
1
Note:
*TpC=XTAL clock cycle. The default on reset is D6=D5=D4=1.
POWER-DOWN MODES
In addition to the standard RUN mode, the Z8E001 MCU sup-
ports two Power-Down modes to minimize device current con-
sumption. The two modes supported are HALT and STOP.
HALT MODE OPERATION
The HALT Mode suspends instruction execution and turns
off the internal CPU clock. The on-chip oscillator circuit
remains active so the internal clock continues to run and is
applied to the timers and interrupt logic.
The HALT Mode can be exited by servicing an interrupt
(either externally or internally) generated. Upon comple-
tion of the interrupt service routine, the user program con-
tinues from the instruction after the HALT instruction.
To enter the HALT Mode, the Z8E001 only requires a
HALT instruction. It is NOT necessary to execute a NOP
instruction immediately before the HALT instruction.
The HALT Mode can also be exited via a RESET activation
or a Watch-Dog Timer (WDT) timeout. In these cases, pro-
gram execution restarts at the reset restart address 0020H.
7F
HALT
; enter HALT Mode
20
P R E L I M I N A R Y
DS001101-Z8X0400
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
STOP MODE OPERATION
The STOP Mode provides the lowest possible device stand-
by current. This instruction turns off the on-chip oscillator
and internal system clock.
The Z8E001 provides a dedicated STOP-Mode Recovery
(SMR) circuit. In this case, a low-level applied to input pin
PB0 triggers an SMR. To use this mode, pin PB0 (I/O Port
B, bit 0) must be configured as an input before the STOP
Mode is entered. The Low level on PB0 must be held for a
ToentertheSTOPMode, theZ8E001onlyrequiresaSTOP
instruction. It is NOT necessary to execute a NOP instruc-
tion immediately before the STOP instruction.
minimum pulse width T
plus any oscillator startup
WSM
time. Program execution starts at address 20Hex after PB0
is raised back to a high level.
6F
STOP
;enter STOP Mode
Notes: Use of the PB0 input for the stop mode recovery does
The STOP Mode is exited by any one of the following re-
sets: RESET pin or a STOP-Mode Recovery source. Upon
reset generation, the processor always restarts the applica-
tion program at address 0020H, and the STOP Mode Flag
is set. Reading the STOP Mode Flag does not clear it. The
user must clear the STOP Mode Flag with software.
not initialize the control registers.
The STOP Mode current (I ) is minimized when:
CC2
•
•
•
V
is at the low end of the devices operating range.
CC
Output current sourcing is minimized.
All inputs (digital and analog) are at the Low or
High rail voltages.
Note: Failure to clear the STOP Mode Flag can result in unde-
fined behavior.
CLOCK
The Z8E001 MCU derives its timing from on-board clock
circuitry connected to pins XTAL1 and XTAL2. The clock
circuitry consists of an oscillator, a glitch filter, a divide-
by-two shaping circuit, a divide-by-four shaping circuit,
and a divide-by-eight shaping circuit. Figure 13 illustrates
the clock circuitry. The oscillatorÕs input is XTAL1 and its
output is XTAL2. The clock can be driven by a crystal, a
ceramic resonator, LC clock, or an external clock source.
Machine
Clock
Glitch
Filter
XTAL1
XTAL2
÷2
(5 cycles
per in-
struction)
Timer
Clock
÷4
÷8
WDT
Clock
Figure 13. Z8E001 Clock Circuit
DS001101-Z8X0400
P R E L I M I N A R Y
21
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
OSCILLATOR OPERATION
The Z8E001 MCU uses a Pierce oscillator with an internal
feedback resistor (Figure 14). The advantages of this circuit
are low-cost, large output signal, low-power level in the
or components except at the Z8E001 device V pin. The
SS
objective is to prevent differential system ground noise in-
jection into the oscillator (Figure 15).
crystal, stability with respect to V and temperature, and
CC
low impedances (not disturbed by stray effects).
Z8E001
V
SS
One draw back is the requirement for high gain in the am-
plifier to compensate for feedback path losses. The oscil-
lator amplifies its own noise at start-up until it settles at the
frequency that satisfies the gain/phase requirements (A x B
A
R
I
V
V
1
0
= 1; where A = V /V is the gain of the amplifier and B =
o
i
V /V is the gain of the feedback element). The total phase
i
o
shift around the loop is forced to zero (360 degrees). V
IN
XTAL1
XTAL2
C2
mustbeinphasewithitself;therefore,theamplifier/inverter
providesa180-degreephaseshift,andthefeedbackelement
is forced to provide the other 180-degree phase shift.
C1
R1 is a resistive component placed from output to input of
theamplifier. Thepurposeofthisfeedbackistobiastheam-
plifier in its linear region and provide the start-up transition.
Figure 14. Pierce Oscillator with Internal Feedback
Circuit
Capacitor C , combined with the amplifier output resis-
2
Indications of an Unreliable Design
tance, provides a small phase shift. It also provides some
attenuation of overtones.
There are two major indicators that are used in working de-
signs to determine their reliability over full lot and temper-
ature variations. They are:
Capacitor C , combined with the crystal resistance, pro-
1
vides an additional phase shift.
Start-up Time. If start-up time is excessive, or varies wide-
ly from unit to unit, there is probably a gain problem. To
fix the problem, the capacitors C1/C2 require reduction.
The amplifier gain is either not adequate at frequency, or
the crystal Rs are too large.
C and C can affect the start-up time if they increase dra-
1
2
matically in size. As C and C increase, the start-up time
1
2
increases until the oscillator reaches a point where it does
not start up any more.
It is recommended for fast and reliable oscillator start-up
(over the manufacturing process range) that the load capac-
itors be sized as low as possible without resulting in over-
tone operation.
Output Level. The signal at the amplifier output should
swing from ground to V to indicate adequate gain in the
CC
amplifier. As the oscillator starts up, the signal amplitude
grows until clipping occurs. At that point, the loop gain is
effectively reduced to unity, and constant oscillation is
achieved. A signal of less than 2.5 volts peak-to-peak is an
Layout
indication that low gain can be a problem. Either C or C
should be made smaller, or a low-resistance crystal should
be used.
1
2
Traces connecting crystal, caps, and the Z8E001 oscillator
pins should be as short and wide as possible, to reduce par-
asitic inductance and resistance. The components (caps,
crystal, resistors) should be placed as close as possible to
the oscillator pins of the Z8E001.
Circuit Board Design Rules
The following circuit board design rules are suggested:
The traces from the oscillator pins of the IC and the ground
side of the lead caps should be guarded from all other traces
¥ To prevent induced noise, the crystal and load capacitors
should be physically located as close to the Z8E001 as
possible.
(clock, V , address/data lines, system ground) to reduce
CC
cross talk and noise injection. Guarding is usually accom-
plished by keeping other traces and system ground trace
planes away from the oscillator circuit, and by placing a
¥ Signal lines should not run parallel to the clock oscillator
inputs. In particular, the crystal input circuitry and the in-
ternal system clock output should be separated as much
as possible.
Z8E001 device V ground ring around the traces/compo-
SS
nents. The ground side of the oscillator lead caps should be
connected to a single trace to the Z8E001 V (GND) pin.
SS
It should not be shared with any other system ground trace
22
P R E L I M I N A R Y
DS001101-Z8X0400
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
¥ V power lines should be separated from the clock os- ¥ Resistivity between XTAL1 or XTAL2 (and the other
CC
cillator input circuitry.
pins) should be greater than 10 MΩ.
XTAL1 17
C1
C2
Z8E001
XTAL2 16
15
V
SS
Clock Generator Circuit
Signals A B
Z8E001
(Parallel Traces
Must Be Avoided)
PB0
Signal C
X1
XTAL1
17
16
X2
VSS
VCC
Z8E001
XTAL2
Board Design Example
(Top View)
Figure 15. Circuit Board Design Rules
Dependingontheoperationfrequency, theoscillatorcanre-
Crystals and Resonators
quire additional capacitors, C1 and C2, as shown in Figure
16 and Figure 17. The capacitance values are dependent on
the manufacturerÕs crystal specifications.
Crystalsandceramicresonators(Figure16)shouldhavethe
following characteristics to ensure proper oscillation:
Crystal Cut
Mode
AT (crystal only)
Parallel, Fundamental Mode
Crystal Capacitance <7pF
Load Capacitance
10pF < CL < 220 pF,
15 typical
Resistance
100 ohms max
DS001101-Z8X0400
P R E L I M I N A R Y
23
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
OSCILLATOR OPERATION (Continued)
tal/ceramic resonator manufacturer. The R can be in-
D
creased to decrease the amount of drive from the oscillator
output to the crystal. It can also be used as an adjustment
toavoidclippingoftheoscillatorsignaltoreducenoise. The
V
SS
Z8E001
XTAL2
R canbeusedtoimprovethestart-upofthecrystal/ceramic
XTAL1
F
resonator. The Z8E001 oscillator already has an internal
shunt resistor in parallel to the crystal/ceramic resonator.
R
R
F
D
XTAL1
C2
C1
Z8E001
V
Figure 16. Crystal/Ceramic Resonator Oscillator
SS
N/C
XTAL2
Figure 18. External Clock
XTAL1
C1
Figure 16, Figure 17, and Figure 18 recommend that the
load capacitor ground trace connect directly to the V
Z8E001
L
SS
(GND) pin of the Z8E001. This requirement assures that no
system noise is injected into the Z8E001 clock. This trace
should not be shared with any other components except at
V
SS
XTAL2
the V pin of the Z8E001.
SS
C2
Note: A parallel resonant crystal or resonator data sheet speci-
fies a load capacitor value that is a series combination of
C and C , including all parasitics (PCB and holder).
Figure 17. LC Clock
1
2
In most cases, the R is 0 Ohms and R is infinite. These
D
F
specifications are determined and specified by the crys-
24
P R E L I M I N A R Y
DS001101-Z8X0400
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
LC OSCILLATOR
The Z8E001 oscillator can use a LC network to generate a
XTAL clock (Figure 17).
1/ C
If C
=
=
=
=
1/C + 1/C
1
T
2
C
2
1
The frequency stays stable over V and temperature. The
CC
oscillation frequency is determined by the equation:
1/C
2 C
1
T
1
2C
Frequency =
C
T
1
1/2
2π (LC )
T
where L is the total inductance including parasitics, and C
is the total series capacitance including parasitics.
T
A sample calculation of capacitance C and C for 5.83
MHz frequency and inductance value of 27 µH is displayed
as follows:
1
2
Simple series capacitance is calculated using the equation
at the top of the next column.
1
5.83 (10^6) =
-6
2¹ [2.7 (10 ) C ] º
T
C = 27.6 pF
T
Thus C = 55.2 pF and C = 55.2 pF.
1
2
TIMERS
For the Z8E001, 8-bit timers (T0 and T1) are available to
function as a pair of independent 8-bit standard timers, or
they can be cascaded to function as a 16-bit PWM timer.
In addition to T0 and T1, extra 8-bit timers (T2 and T3) are
provided, but they can only operate in cascade to function
as a 16-bit standard timer.
OSC/8
Enable TCTLL0 (D5)
16-bit Down Counter
IRQ5 (T23)
T3VAL
T3AR
T2AR
T2VAL
Internal Data Bus
Figure 19. Z8E001 16-Bit Standard Timer
DS001101-Z8X0400
P R E L I M I N A R Y
25
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
TIMERS (Continued)
Internal Data Bus
T1ARHI
T1ARLO
T1VAL
OSC/8
(Not used
in this mode)
8-bit
Down
Counter
IRQ2 (T1)
Enable TCTLL0 (D2-D0)
8-bit
Down
Counter
Enable TCTLL0 (D2-D0)
IRQ2 (T0)
(Not used
in this mode)
T0ARHI
T0ARLO
T0VAL
OSC/8
Internal Data Bus
Figure 20. 8-Bit Standard Timers
Internal Data Bus
T1ARHI
T1ARLO
T1VAL
High Side
PWM
Low Side
IRQ0
IRQ2
Edge Detect
Logic
T1
T0
16-bit Down Counter
TOUT
OSC/8
T0ARHI
T0ARLO
T0VAL
Internal Data Bus
Figure 21. 16-bit Standard PWM Timer
26
P R E L I M I N A R Y
DS001101-Z8X0400
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
0C0
TCTLLO
D3
D7
D6
D5
D4
D2
D1
D0
TIMER STATUS
T1 T01
---- ---- --- ------------ ------------ ---------------
D2 D1 D0
T0
0
0
0
0
1
1
1
1
0 0 DISAB. DISAB.
0 1 ENAB. DISAB.
1 0 DISAB. ENAB.
1 1 ENAB. ENAB.
0 0
0 1 ENAB.(*) DISAB.
1 0 DISAB. ENAB.(*)
1 1 ENAB.(*) ENAB.(*)
ENAB.(*)
(NOTE: (*) INDICATES AUTO-RELOAD
IS ACTIVE.)
RESERVED (MUST BE 0)
1 = T23 16-BIT TIMER ENABLED WITH
AUTO-RELOAD ACTIVE
0 = T2 AND T3 TIMERS DISABLED
RESERVED (MUST BE 0)
Note: Timer T01 is a 16-bit PWM Timer formed by cascading 8-bit timers
T1 (MSB) and T0 (LSB). T23 is a standard 16-bit timer formed
by cascading 8-bit timers T3 (MSB) and T2 (LSB).
Figure 22. TCTLLO Register
Each 8-bit timer is provided a pair of registers, which are
both readable and writable. One of the registers is defined
to contain the auto-initialization value for the timer, while
the second register contains the current value for the timer.
When a timer is enabled, the timer decrements whatever
value is currently held in its count register, and then con-
tinues decrementing until it reaches 0. At this time, an in-
terrupt is generated and the contents of the auto-initializa-
tion register optionally copy into the count value register.
If auto-initialization is not enabled, the timer stops counting
upon reaching 0, and control logic clears the appropriate
control register bit to disable the timer. This operation is re-
ferred to as Òsingle-shotÓ. If auto-initialization is enabled,
the timer continues counting from the initialization value.
Software should not attempt to use registers that are defined
as having timer functionality.
Note: Strange behavior can result if the software update oc-
curred at exactly the point that the timer was reaching 0
to trigger an interrupt and/or reload.
Similarly, if software updates the initialization value reg-
ister while the timer is active, the next time that the timer
reaches 0, it initializes using the updated value.
Note: Strange behavior could result if the initialization value
register is being written while the timer is in the process
of being initialized.
Whether initialization is done with the new or old value is
a function of the exact timing of the write operation. In all
cases, the Z8E001 prioritizes the software write above that
of a decrementer writeback; however, when hardware
clears a control register bit for a timer that is configured for
single-shot operation, the clearing of the control bit over-
rides a software write. Reading either register can be done
Software is allowed to write to any register at any time, but
care should be taken if timer registers are updated while the
timer is enabled. If software updates the count value while
the timer is in operation, the timer continues counting based
upon the software-updated value.
DS001101-Z8X0400
P R E L I M I N A R Y
27
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
TIMERS (Continued)
at any time, and will have no effect on the functionality of
the timer.
T01 times out, it alternately initializes its count value using
the LO auto-init pair, followed by the HI auto-init pair. This
functionalitycorrespondstoaPWM, wheretheT1interrupt
defines the end of the HI section of the waveform, and the
T0 interrupt marks the end of the LO portion of the PWM
waveform.
If a timer pair is defined to operate as a single 16-bit entity,
the entire 16-bit value must reach 0 before an interrupt is
generated. In this case, a single interrupt is generated, and
the interrupt corresponds to the even 8-bit timer.
To use the cascaded timers as a PWM, one must initialize
the T0 and T1 count registers to work in conjunction with
the port pin. The user should initialize the T0 and T1 count
registers to the PWM_HI auto-init value to obtain the re-
quired PWM behavior. The PWM is arbitrarily defined to
use the LO autoreload registers first, implying that it had
just timed out after beginning in the HI portion of the PWM
waveform. As such, the PWM is defined to assert the T1
interrupt after the first timeout interval.
Example: Timers T2 and T3 are cascaded to form a single 16-
bit timer, so the interrupt for the combined timer is
defined to be that of timer T2 rather than T3. When
a timer pair is specified to act as a single 16-bit
timer, the even timer registers in the pair (timer T0
or T2) is defined to hold the timerÕs least significant
byte. In contrast, the odd timer in the pair holds the
timerÕs most significant byte.
After the auto-initialization has been completed, decre-
menting occurs for the number of counts defined by the
PWM_LO registers. When decrementing again reaches 0,
the T0 interrupt is asserted; and auto-init using the
PWM_HI registers occurs. Decrementing occurs for the
number of counts defined by the PWM_HI registers until
reaching 0. From there, the T1 interrupt is asserted, and the
cycle begins again.
In parallel with the posting of the interrupt request, the in-
terrupting timerÕs count value is initialized by copying the
contents of the auto-initialization value register to the count
value register. It should be noted that any time that a timer
pair is defined to act as a single 16-bit timer, that the auto-
reload function is performed automatically. All 16-bit tim-
ers continue counting while their interrupt requests are ac-
tive, and each operates in a free-running manner.
The internal timers can be used to trigger external events
by toggling the PB1 output when generating an interrupt.
This functionality can only be achieved in conjunction with
the port unit defining the appropriate pin as an output signal
withthetimeroutputspecialfunctionenabled. Inthismode,
the appropriate port output is toggled when the timer count
reaches 0, and continues toggling each time that the timer
times out.
If interrupts are disabled for a long period of time, it is pos-
sible for the timer to decrement to 0 again before its initial
interrupt has been responded to. This condition is termed a
degenerate case, and hardware is not required to detect it.
When the timer control register is written, all timers that are
enabled by the write begins counting using the value that
is held in the count register. In this case, an auto-initializa-
tion is not performed. All timers can receive an internal
clock source only. Each timer that is enabled is updated ev-
ery 8th XTAL clock cycle.
T
Mode
OUT
The PortB special function register PTBSFR (0D7H) (Fig-
ure 23) is used in conjunction with the Port B directional
control register PTBDIR (0D6) (Figure 24) to configure
If T0 and T1 are defined to work independently, then each
works as an 8-bit timer with a single auto-initialization reg-
ister (T0ARLO for T0, and T1ARLO for T1). Each timer
asserts its predefined interrupt when it times out, optionally
performing the auto-initialization function. If T0 and T1 are
cascaded to form a single 16-bit timer, then the single 16-
bit timer is capable of performing as a Pulse-Width Mod-
ulator(PWM). ThistimerisreferredtoasT01todistinguish
it as having special functionality that is not available when
T0 and T1 act independently.
PB1 for T
operation for timer0. In order for T
to
OUT
OUT
function, PB1 must be defined as an output line by setting
PTBDIR bit 1 to 1. Configured in this way, PB1 has the ca-
pability of being a clock output for timer0, toggling the PB1
output pin on each timer0 timeout.
At end-of-count, the interrupt request line IRQ0, clocks a
toggle flip-flop. The output of this flip-flop drives the T
OUT
line,PB1.Inallcases,whentimer0reachesitsend-of-count,
toggles to its opposite state (Figure 25). If, for ex-
T
OUT
ample, timer0 is in Continuous Counting Mode, T
has
OUT
When T01 is enabled, it can use a pair of 16-bit auto-ini-
tialization registers. In this mode, one 16-bit auto-initial-
ization value is composed of the concatenation of T1ARLO
and T0ARLO. The second auto-initialization value is com-
posed of the concatenation of T1ARHI and T0ARHI. When
a 50 percent duty cycle output. This duty cycle can easily
be controlled by varying the initial values after each end-
of-count.
28
P R E L I M I N A R Y
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Z8E001
Z8Plus OTP Microcontroller
ZiLOG
0D7
PTBSFR
D3
D7
D5
D4
D2
D1
D0
D6
1 = ENABLE BIT 0 AS SMR INPUT
0 = NO SPECIAL FUNCTIONALITY
1 = ENABLE BIT 1 AS TIMER0 OUTPUT
0 = NO SPECIAL FUNCTIONALITY
1 = ENABLE BIT 2 AS INT1 INPUT
0 = NO SPECIAL FUNCTIONALITY
D4 D3 COMPAR. INTERRUPTS
--- --- -------------- -------------------
0
0
1
1
0 DISABLED DISABLED
1 ENABLED DISABLED
0 DISABLED ENABLED
1 ENABLED ENABLED
BIT 3: COMP. REF. INPUT
BIT 4: COMP. SIGNAL INPUT/
INT0/INT2
RESERVED (MUST BE 0)
Figure 23. PortB Special Function Register (T Operation)
out
0D6
PTBDIR
D7
D6
D5
D4
D3
D2
D1
D0
1 = BIT N SET AS OUTPUT
0 = BIT N SET AS INPUT
RESERVED (MUST BE 0)
Figure 24. Port B Directional Control Register
IRQ0
÷2
PB1
(T0
T
OUT
End-of-Count)
Figure 25. Timer T0 Output Through T
OUT
DS001101-Z8X0400
P R E L I M I N A R Y
29
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
RESET CONDITIONS
After a hardware RESET, the timers are disabled. See Table
4 for timer control, value, and auto-initialization register
status after RESET.
I/O PORTS
Table 7. Z8E001 I/O Ports Registers
The Z8E001 has 13 lines dedicated to input and output.
These lines are grouped into two ports known as Port A and
Port B. Port A is an 8-bit port, bit programmable as either
inputs or outputs. Port B can be programmed to provide
standard input/output or the following special functions:
timer0 output, comparator input, SMR input, and external
interrupt inputs.
Register
Address
Identifier
PTBSFR
Port B Special Function
Port B Directional Control
Port B Output Value
Port B Input Value
OD7H
0D6H
0D5H
0D4H
0D3H
0D2H
0D1H
0D0H
PTBDIR
PTBOUT
PTBIN
Port A Special Function
Port A Directional Control
Port A Output Value
PTASFR
PTADIR
PTAOUT
PTAIN
All ports have push-pull CMOS outputs. In addition, the
outputs of Port A on a bit-wise basis can be configured for
open-drain operation.The ports operate on a bit-wise basis.
As such, the register values for/at a given bit position only
affect the bit in question.
Port A Input Value
Each port is defined by a set of four control registers. See
Figure 27.
Input and Output Value Registers
Each port has an Output Value Register and a pF Input Val-
ue Register. For port bits configured as an input by means
of the Directional Control Register, the Input Value Reg-
ister for that bit position contains the current synchronized
input value.
Directional Control and Special Function
Registers
Each port on the Z8E001 has a dedicated Directional Con-
trol Register that determines (on a bit-wise basis) whether
a given port bit operates as either an input or an output.
For port bits configured as an output by means of the Di-
rectionalControlRegister, thevalueheldinthecorrespond-
ing bit of the Output Value Register is driven directly onto
the output pin. The opposite register bit for a given pin (the
output register bit for an input pin and the input register bit
for an output pin) holds their previous value. These bits are
not changed and donÕt have any effect on the hardware.
Each port on the Z8E001 has a Special Function Register
that, in conjunction with the Directional Control Register,
implements (on a bit-wise basis), any special functionality
that can be defined for each particular port bit.
READ/WRITE OPERATIONS
The control for each port is done on a bit-wise basis. All
bits are capable of operating as inputs or outputs, depending
upon the setting of the portÕs Directional Control Register.
If configured as an input, each bit is provided a Schmitt-
trigger. The output of the Schmitt-trigger is latched twice
to perform a synchronization function, and the output of the
synchronizer is fed to the port input register, which can be
read by software.
thatbitpositioncontainsthecurrentsynchronizedinputval-
ue. Thus, writestothatbitpositionisoverwrittenonthenext
clock cycle with the newly sampled input data. However,
if the particular port bit is programmed as an output, the in-
put register for that bit retains the software-updated value.
The port bits that are programmed as outputs do not sample
the value being driven out.
Any bit in either port can be defined as an output by setting
the appropriate bit in the directional control register. If such
is the case, the value held in the appropriate bit of the port
output register is driven directly onto the output pin.
A write to a port input register has the effect of updating
the contents of the input register, but subsequent reads do
not necessarily return the same value that was written. If the
bit in question is defined as an input, the input register for
30
P R E L I M I N A R Y
DS001101-Z8X0400
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
others; however, care should be taken when updating the
directional control and special function registers.
Note: The preceding result does not necessarily reflect the ac-
tual output value. If an external error is holding an output
pin either High or Low against the output driver, the soft-
ware read returns the required value, not the actual state
caused by the contention. When a bit is defined as an out-
put, the Schmitt-trigger on the input is disabled to save
power.
When updating a Directional Control Register, the Special
FunctionRegistershouldfirstbedisabled. Ifthisprecaution
is not taken, spurious events could take place as a result of
the change in port I/O status. This precaution is especially
important when defining changes in Port B, as the spurious
event referred to above could be one or more interrupts.
Clearing of the SFR register should be the first step in con-
figuring the port, while setting the SFR register should be
the final step in the port configuration process. To ensure
deterministic behavior, the SFR register should not be writ-
ten until the pins are being driven appropriately, and all ini-
tialization has been completed.
Updates to the output register takes effect based upon the
timing of the internal instruction pipeline, but is referenced
to the rising edge of the clock. The output register can be
read at any time, and returns the current output value that
is held. No restrictions are placed on the timing of reads
and/or writes to any of the port registers with respect to the
PORT A
Port A is a general-purpose port. Figure 26 features a block
diagram of Port A. Each of its lines can be independently
programmed as input or output via the Port A Directional
Control Register (PTADIR at 0D2H) as seen in Figure 27.
A bit set to a 1 in PTADIR configures the corresponding
bit in Port A as an output, while a bit cleared to 0 configures
the corresponding bit in Port A as an input.
Register 0D2H
PTADIR Register
D7 D6 D5 D4 D3 D2 D1 D0
1 = Output
0 = Input
The input buffers are Schmitt-triggered. Bits programmed
as outputs can be individually programmed as either push-
pull or open drain by setting the corresponding bit in the
Special Function Register (PTASFR, Figure 27).
Figure 26. Port A Directional Control Register
PTASFR.bitN
N = 0...7
PTADIR.bitN
N = 0...7
PA0ÐPA7
PIN
PTAOUT.bitN
N = 0...7
PTAIN.bitN
N = 0...7
Figure 27. Port A Configuration with Open-Drain Capability and Schmitt-Trigger
DS001101-Z8X0400
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Z8Plus OTP Microcontroller
ZiLOG
PORT A REGISTER DIAGRAMS
Register 0D0H
PTAIN
D3
D7
D6
D5
D4
D2
D1
D0
PORT A BIT N CURRENT INPUT
VALUE
(only updated for pins in
input mode)
Figure 28. Port A Input Value Register
Register 0D1H
PTAOUT
D7
D6
D5
D4
D3
D2
D1
D0
PORT A BIT N CURRENT
OUTPUT VALUE
Figure 29. Port A Output Value Register
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P R E L I M I N A R Y
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Z8Plus OTP Microcontroller
ZiLOG
Register 0D2H
PTADIR
D3
D7
D6
D5
D4
D2
D1
D0
1 = BIT N SET AS AN OUTPUT
0 = BIT N SET AS AN INPUT
Figure 30. Port A Directional Control Register
Register 0D3H
PTASFR
D7
D6
D5
D4
D3
D2
D1
D0
1 = BIT N IN OPEN-DRAIN MODE
0 = BIT N IN PUSH-PULL MODE
Figure 31. Port A Special Function Register
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Z8E001
Z8Plus OTP Microcontroller
ZiLOG
PORT B
Port B Description
Table 8. Port B Special Functions
Input Special Output Special
PortBisa5-bit(bidirectional),CMOS-compatibleI/Oport.
These five I/O lines can be configured under software con-
trol to be an input or output, independently. Input buffers
are Schmitt-triggered. See Figure 33 through Figure 36 for
diagrams of all five Port B pins.
Port Pin Function
Function
PB0
Stop Mode Recovery
None
Input
None
IRQ3
In addition to standard input/output capability on all five
pins of Port B, each pin provides special functionality as
shown in the following table:
PB1
PB2
PB3
Timer0 Output
None
Comparator Reference None
Input
SpecialfunctionalityisinvokedviathePortBSpecialFunc-
tionRegister. SeeFigure32forthearrangementandcontrol
conventions of this register.
PB4
Comparator Signal
Input/IRQ1/IRQ4
None
Register 0D7H
PTBSFR
D7
D6
D5
D4
D3
D2
D1
D0
1 = ENABLE PB0 AS SMR INPUT
0 = NO SPECIAL FUNCTIONALITY
1 = ENABLE PB1 AS TIMER0 OUTPUT
0 = NO SPECIAL FUNCTIONALITY
1 = ENABLE PB2 AS IRQ3 INPUT
0 = NO SPECIAL FUNCTIONALITY
1 = Analog Comparator on PB3 & PB4
0 = Digital Inputs on PB3 & PB4
1 = PB4 Interrupts Enabled
0 = PB4 Interrupts Disabled
RESERVED (MUST BE 0)
Figure 32. Port B Special Function Register
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P R E L I M I N A R Y
DS001101-Z8X0400
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
PORT BÑPIN 0 CONFIGURATION
PTBDIR.bit0
PTBIN.bit0
SMR
RESET
PTBSFR.bit0
SMR Flag
PTBDIR.bit0
PB0
PIN
PTBOUT.bit0
Figure 33. Port B Pin 0 Diagram
DS001101-Z8X0400
P R E L I M I N A R Y
35
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
PORT BÑPIN 1 CONFIGURATION
PTBDIR.bit1
PTBIN.bit1
PTBDIR.bit1
PB1
PIN
PTBOUT.bit1
M
U
TIMER0
X
Output
PTBSFR.bit1
Figure 34. Port B Pin 1 Diagram
36
P R E L I M I N A R Y
DS001101-Z8X0400
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
PORT BÑPIN 2 CONFIGURATION
PTBDIR.bit2
PTBIN.bit2
IRQ3
EDGE DETECT LOGIC
PTBSFR.bit2
PTBDIR.bit2
PB2
PIN
PTBOUT.bit2
Figure 35. Port B Pin 2 Diagram
DS001101-Z8X0400
P R E L I M I N A R Y
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Z8E001
Z8Plus OTP Microcontroller
ZiLOG
PORT BÑPINS 3 AND 4 CONFIGURATION
PTBDIR.bit4
PTBIN.bit4
M
U
X
IRQ1
EDGE DETECT LOGIC
IRQ4
PTBSFR.bit4
AN IN
REF
+
-
PTBSFR.bit3
PTBDIR.bit3
PTBIN.bit3
PTBDIR.bit3
PB3
PIN
PTBOUT.bit3
PTBDIR.bit4
PB4
PIN
PTBOUT.bit4
Figure 36. Port B Pins 3 and 4 Diagram
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P R E L I M I N A R Y
DS001101-Z8X0400
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
PORT B CONTROL REGISTERS
Register 0D4H
PTBIN
D3
D7
D6
D5
D4
D2
D1
D0
PORT B BIT N CURRENT INPUT
VALUE
(only updated for pins in
input mode)
RESERVED (MUST BE 0)
Figure 37. Port B Input Value Register
Register 0D5H
PTBOUT
D7
D6
D5
D4
D3
D2
D1
D0
PORT B BIT N CURRENT
OUTPUT VALUE
RESERVED (MUST BE 0)
Figure 38. Port B Output Value Register
Register 0D6H
PTBDIR
D7
D6
D5
D4
D3
D2
D1
D0
1 = BIT N SET AS OUTPUT
0 = BIT N SET AS INPUT
RESERVED (MUST BE 0)
Figure 39. Port B Directional Control Register
DS001101-Z8X0400
P R E L I M I N A R Y
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Z8E001
Z8Plus OTP Microcontroller
ZiLOG
PORT B CONTROL REGISTERS (Continued)
Register 0D7H
PTBSFR
D6
D7
D5
D4
D3
D0
D2
D1
1 = ENABLE PB0 AS SMR INPUT
0 = NO SPECIAL FUNCTIONALITY
1 = ENABLE PB1 AS TIMER0 OUTPUT
0 = NO SPECIAL FUNCTIONALITY
1 = ENABLE PB2 AS IRQ3 INPUT
0 = NO SPECIAL FUNCTIONALITY
1 = Analog Comparator on PB3 & PB4
0 = Digital Inputs on PB3 & PB4
1 = PB4 Interrupts Enabled
0 = PB4 Interrupts Disabled
RESERVED (MUST BE 0)
Figure 40. Port B Special Function Register
40
P R E L I M I N A R Y
DS001101-Z8X0400
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
I/O PORT RESET CONDITIONS
Full Reset
overwrites the previously held data with the current sample
of the input pins.
Port A and Port B output value registers are not affected by
RESET.
On RESET, the Port A and Port B special function registers
is cleared to all zeros, which deactivates all port special
functions.
On RESET, the Port A and Port B directional control reg-
isters is cleared to all zeros, which defines all pins in both
ports as inputs.
Note: The SMR and WDT timeout events are NOT full device
resets. The port control registers are not affected by ei-
ther of these events.
On RESET, the directional control registers redefine all
pinsasinputs,andthePortAandPortBinputvalueregisters
ANALOG COMPARATOR
The Z8E001 includes one on-chip analog comparator. Pin
PB4 has a comparator front end. The comparator reference
voltage is on pin PB3.
When the analog comparator function is enabled, bit 4 of
theinputregisterisdefinedasholdingthesynchronizedout-
put of the comparator, while bit 3 retains a synchronized
sample of the reference input.
Comparator Description
If the interrupts for PB4 are enabled when the comparator
special function is selected, the output of the comparator
generates interrupts.
The on-chip comparator can process an analog signal on
PB4 with reference to the voltage on PB3. The analog func-
tion is enabled by programming the Port B Special Function
Register bits 3 and 4.
COMPARATOR OPERATION
V
The comparator output reflects the relationship between the
analog input to the reference input. If the voltage on the an-
alog input is higher than the voltage on the reference input,
then the comparator output is at a High state. If the voltage
ontheanaloginputislowerthanthevoltageonthereference
input, then the analog output will be at a Low state.
OFFSET
The absolute value of the voltage between the positive input
and the reference input required to make the comparator
output voltage switch is the input offset voltage (V
).
OFFSET
I
IO
For the CMOS voltage comparator input, the input offset
Comparator Definitions
current (I ) is the leakage current of the CMOS input gate.
IO
V
ICR
HALT Mode
Theusablevoltagerangeforthepositiveinputandreference
input is called the common mode voltage range (V ).
The analog comparator is functional during HALT Mode.
If the interrupts are enabled, an interrupt generated by the
comparator will cause a return from HALT Mode.
ICR
Note: The comparator is not guaranteed to work if the input is
outside of the V
range.
ICR
STOP Mode
The analog comparator is disabled during STOP Mode. The
comparatorispowereddowntopreventitfromdrawingany
current.
DS001101-Z8X0400
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Z8E001
Z8Plus OTP Microcontroller
ZiLOG
INPUT PROTECTION
All I/O pins on the Z8E001 have diode input protection.
However, on the Z8E001, the RESET pin has only the input
There is a diode from the I/O pad to V and V (Figure
protection diode from pad to V (Figure 42).
CC
SS
SS
41).
V
PIN
CC
RESET
V
SS
PIN
Figure 42. RESET Pin Input Protection
The high-side input protection diode was removed on this
pin to allow the application of high voltage during the OTP
programming mode.
For better noise immunity in applications that are exposed
V
SS
to system EMI, a clamping diode to V from this pin can
CC
berequiredtoprevententeringtheOTPprogrammingmode
or to prevent high voltage from damaging this pin.
Figure 41. I/O Pin Diode Input Protection
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DS001101-Z8X0400
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
PACKAGE INFORMATION
Figure 43. 18-Pin DIP Package Diagram
Figure 44. 18-Pin SOIC Package Diagram
DS001101-Z8X0400
P R E L I M I N A R Y
43
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
PACKAGE INFORMATION (Continued)
Figure 45. 20-Pin SSOP Package Diagram
44
P R E L I M I N A R Y
DS001101-Z8X0400
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
ORDERING INFORMATION
Standard Temperature
18-Pin DIP
Z8E00110SSC
18-Pin SOIC
20-Pin SSOP
Z8E00110HSC
Z8E00110PSC
Extended Temperature
18-Pin DIP
18-Pin SOIC
20-Pin SSOP
Z8E00110PEC
Z8E00110SEC
Z8E00110HEC
For fast results, contact your local ZiLOG sales office for
assistance in ordering the part(s) required.
Codes
Preferred Package
Longer Lead Time
P = Plastic DIP
S = SOIC
H = SSOP
Preferred Temperature S = 0¡C to +70¡C
E = Ð40¡C to +105¡C
Speed
10 = 10 MHz
Environmental
C = Plastic Standard
Example:
Z 8E001 10 P S C
is a Z86E001, 10 MHz, DIP, 0¡ to +70¡C, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
ZiLOG Prefix
DS001101-Z8X0400
P R E L I M I N A R Y
45
Z8E001
Z8Plus OTP Microcontroller
ZiLOG
Pre-Characterization Product:
The product represented by this document is newly introduced
and ZiLOG has not completed the full characterization of the
product. The document states what ZiLOG knows about this
product at this time, but additional features or non-conformance
with some aspects of the document may be found, either by
ZiLOG or its customers in the course of further application and
characterization work. In addition, ZiLOG cautions that delivery
may be uncertain at times, due to start-up yield issues.
Development Projects:
Customer is cautioned that while reasonable efforts will be
employed to meet performance objectives and milestone dates,
development is subject to unanticipated problems and delays.
No production release is authorized or committed until the
Customer and ZiLOG have agreed upon a Product Specification
for this project.
Low Margin:
Customer is advised that this product does not meet ZiLOG's
internal guardbanded test policies for the specification requested
and is supplied on an exception basis. Customer is cautioned that
delivery may be uncertain and that, in addition to all other
limitations on ZiLOG liability stated on the front and back of the
acknowledgement, ZiLOG makes no claim as to quality and
reliability under the document. The product remains subject to
standard warranty for replacement due to defects in materials
and workmanship.
©1999 by ZiLOG, Inc. All rights reserved. Information in this
publication concerning the devices, applications, or technology
described is intended to suggest possible uses and may be
superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY
FOR OR PROVIDE A REPRESENTATION OF ACCURACY
OF THE INFORMATION, DEVICES, OR TECHNOLOGY
DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES
NOT ASSUME LIABILITY FOR INTELLECTUAL
PROPERTY INFRINGEMENT RELATED IN ANY
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Internet: http://www.zilog.com
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P R E L I M I N A R Y
DS001101-Z8X0400
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