C0805C102K1GALTU_技术文档

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Commercial “L” Series, SnPb Termination, C0G Dielectric

10 – 250 VDC (Commercial Grade)

Overview

KEMET’s Commercial “L” Series with Tin/Lead Termination

KEMET’s C0G dielectric features a 125°C maximum

surface mount capacitors in C0G dielectric are designed to operating temperature and is considered “stable.”

meet the needs of critical applications where tin/lead end

metallization is required. KEMET’s tin/lead electroplating

process is designed to meet a 5% minimum lead content

and address concerns for a more robust and reliable

lead containing termination system. As the bulk of the

electronics industry moves towards RoHS compliance,

KEMET continues to provide tin/lead terminated products

for military, aerospace and industrial applications and will

ensure customers have a stable and long-term source of

supply.

The Electronics Components, Assemblies & Materials

Association (EIA) characterizes C0G dielectric as a Class I

material. Components of this classiﬁcation are temperature

compensating and are suited for resonant circuit

applications or those where Q and stability of capacitance

characteristics are required. C0G exhibits no change in

capacitance with respect to time and voltage and boasts a

negligible change in capacitance with reference to ambient

temperature. Capacitance change is limited to ±30 ppm/ºC

from −55°C to +125°C.

Beneﬁts

• −55°C to +125°C operating temperature range

• Reliable and robust termination system

• EIA 0402, 0603, 0805, 1206, 1210, 1808, 1812, 1825,

2220, and 2225 case sizes

• DC voltage ratings of 10 V, 16 V, 25 V, 50 V, 100 V, 200 V

and 250 V

• Capacitance offerings ranging from 0.5 pF up to 0.47 μF

• Available capacitance tolerances of ±0.10 pF, ±0.25 pF, ±0.5

pF, ±1%, ±2%, ±5%, ±10%, and ±20%

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Ordering Information

C

1206

C

104

J

3

G

A

L

TU

Case Size Speciﬁcation/

Capacitance

Code (pF)

Capacitance Rated Voltage

Failure Rate/ Termination

Packaging/

Grade (C-Spec)

Ceramic

Dielectric

G = C0G

(L" x W")

Series

Tolerance¹

(VDC)

Design

Finish²

0402

0603

0805

1206

1210

1808

1812

1825

2220

2225

C = Standard

Two signiﬁcant

digits +

number of zeros.

Use 9 for 1.0 – 9.9 pF

Use 8 for 0.5 – .99 pF

ex. 2.2 pF = 229

ex. 0.5 pF = 508

B = ±0.10 pF

C = ±0.25 pF

D = ±0.5 pF

F = ±1%

G = ±2%

J = ±5%

8 = 10

4 = 16

3 = 25

5 = 50

1 = 100

2 = 200

A = 250

A = N/A

L = SnPb

(5% Pb

See

“Packaging

C-Spec

Ordering

Options

Table” below

minimum)

K = ±10%

M = ±20%

¹Additional capacitance tolerance offerings may be available. Contact KEMET for details.

²Additional termination ﬁnish options may be available. Contact KEMET for details

One world. One KEMET

C1019_C0G_SnPb_SMD • 8/11/2016

1

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Commercial “L” Series, SnPb Termination, C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Packaging C-Spec Ordering Options Table

Packaging/Grade

Packaging Type¹

Ordering Code (C-Spec)

Bulk Bag/Unmarked

7" Reel/Unmarked

Not required (Blank)

TU

7411 (EIA 0603 and smaller case sizes)

7210 (EIA 0805 and larger case sizes)

7081

13" Reel/Unmarked

7" Reel/Unmarked/2 mm pitch²

13" Reel/Unmarked/2 mm pitch²

7082

¹Default packaging is “Bulk Bag”. An ordering code C-Spec is not required for “Bulk Bag” packaging.

¹The terms “Marked” and “Unmarked” pertain to laser marking option of capacitors. All packaging options labeled as “Unmarked” will contain

capacitors that have not been laser marked. The option to laser mark is not available on these devices. For more information see “Capacitor Marking”.

²The 2 mm pitch option allows for double the packaging quantity of capacitors on a given reel size. This option is limited to EIA 0603 (1608 metric) case

size devices. For more information regarding 2 mm pitch option see “Tape & Reel Packaging Information”.

Beneﬁts cont'd

• No piezoelectric noise

• Extremely low ESR and ESL

• High thermal stability

• No capacitance change with respect to applied rated DC

voltage

• No capacitance decay with time

• High ripple current capability

• Non-polar device, minimizing installation concerns

• Preferred capacitance solution at line frequencies and into • SnPb plated termination ﬁnish (5% Pb minimum)

the MHz range • Flexible termination option available upon request

• Negligible capacitance change with respect to temperature • Available for other surface mount products, additional

from −55°C to +125°C

dielectrics and higher voltage ratings upon request

Applications

Typical applications include military, aerospace and other high reliability applications.

C1019_C0G_SnPb_SMD • 8/11/2016

2

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Commercial “L” Series, SnPb Termination, C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Dimensions – Millimeters (Inches)

L

ꢁ

T

ꢀ

S

EIA Size

Code

Metric Size

Code

L

W

Width

T

B

Mounting

Technique

Separation

Minimum

Length

Thickness

Bandwidth

1.00 (0.040)

±0.05 (0.002)

1.60 (0.063)

±0.15 (0.006)

2.00 (0.079)

±0.20 (0.008)

3.20 (0.126)

±0.20 (0.008)

3.20 (0.126)

±0.20 (0.008)

4.70 (0.185)

±0.50 (0.020)

4.50 (0.177)

±0.30 (0.012)

4.50 (0.177)

±0.30 (0.012)

5.70 (0.224)

±0.40 (0.016)

5.60 (0.220)

±0.40 (0.016)

0.50 (0.020)

±0.05 (0.002)

0.80 (0.032)

±0.15 (0.006)

1.25 (0.049)

±0.20 (0.008)

1.60 (0.063)

±0.20 (0.008)

2.50 (0.098)

±0.20 (0.008)

2.00 (0.079)

±0.20 (0.008)

3.20 (0.126)

±0.30 (0.012)

6.40 (0.252)

±0.40 (0.016)

5.00 (0.197)

±0.40 (0.016)

6.40 (0.248)

±0.40 (0.016)

0.30 (0.012)

±0.10 (0.004)

0.35 (0.014)

±0.15 (0.006)

0.50 (0.02)

±0.25 (0.010)

0.50 (0.02)

Solder Reﬂow

0402

0603

0805

1206

1210

1808

1812

1825

2220

2225

1005

1608

2012

3216

3225

4520

4532

4564

5650

5664

0.30 (0.012)

0.70 (0.028)

0.75 (0.030)

Only

Solder Wave or

Solder Reﬂow

±0.25 (0.010)

0.50 (0.02)

±0.25 (0.010)

0.60 (0.024)

±0.35 (0.014)

0.60 (0.024)

±0.35 (0.014)

0.60 (0.024)

±0.35 (0.014)

0.60 (0.024)

±0.35 (0.014)

0.60 (0.024)

±0.35 (0.014)

See Table 2 for

Thickness

N/A

Solder Reﬂow

Only

Qualiﬁcation/Certiﬁcation

Commercial Grade products are subject to internal qualiﬁcation. Details regarding test methods and conditions are

referenced in Table 4, Performance & Reliability.

Environmental Compliance

These devices do not meet RoHS criteria due to the concentration of Lead (Pb) in the termination ﬁnish.

C1019_C0G_SnPb_SMD • 8/11/2016

3

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Commercial “L” Series, SnPb Termination, C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Electrical Parameters/Characteristics

Item

Parameters/Characteristics

Operating Temperature Range

−55°C to +125°C

±30 ppm/ºC

0%

Capacitance Change with Reference to

+25°C and 0 VDC Applied (TCC)

Aging Rate (Maximum % Capacitance Loss/Decade Hour)

¹Dielectric Withstanding Voltage (DWV)

250% of rated voltage

(5±1 seconds and charge/discharge not exceeding 50 mA)

²Dissipation Factor (DF) Maximum Limit at 25ºC

0.1%

1,000 megohm microfarads or 100 GΩ

(Rated voltage applied for 120±5 seconds at 25°C)

³Insulation Resistance (IR) Limit at 25°C

¹DWV is the voltage a capacitor can withstand (survive) for a short period of time. It exceeds the nominal and continuous working voltage of the

capacitor.

²Capacitance and dissipation factor (DF) measured under the following conditions:

1 MHz ±100 kHz and 1.0 Vrms ±0.2 V if capacitance ≤ 1,000 pF

1 kHz ±50 Hz and 1.0 Vrms ±0.2 V if capacitance > 1,000 pF

³To obtain IR limit, divide MΩ-µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits.

Capacitance and Dissipation Factor (DF) measured under the following conditions:

Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 and Agilent E4980 have a feature known

as Automatic Level Control (ALC). The ALC feature should be switched to "ON."

Post Environmental Limits

High Temperature Life, Biased Humidity, Moisture Resistance

Rated DC

Voltage

Capacitance Dissipation Factor Capacitance

Insulation

Dielectric

C0G

Value

(Maximum %)

Shift

Resistance

10% of Initial

Limit

All

0.5

0.3% or ±0.25 pF

C1019_C0G_SnPb_SMD • 8/11/2016

4

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Commercial “L” Series, SnPb Termination, C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Table 1A – Capacitance Range/Selection Waterfall (0402 – 1206 Case Sizes)

Case Size/

Series

C0402C

C0603C

C0805C

C1206C

Cap

Code

Cap

Voltage Code

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

Rated Voltage (VDC)

Capacitance

Tolerance

Product Availability and Chip Thickness Codes – See Table 2 for Chip Thickness Dimensions

0.50 & 0.75 pF 508 & 758 B C D

109 –

BB BB BB BB

CF CF CF CF CF CF CF DN DN DN DN DN DN DN

1.0 – 9.1 pF*

B C D

BB BB BB BB

CF CF CF CF CF CF CF DN DN DN DN DN DN DN EB EB EB EB EB EB EB

919*

100 –

200*

220

10 – 20 pF*

22 pF

F

G

J

K M BB BB BB BB

CF CF CF CF CF CF CF DN DN DN DN DN DN DN EB EB EB EB EB EB EB

240 –

910*

101

24 – 91 pF*

100 pF

F

G

J

K M BB BB BB BB BB BB BB CF CF CF CF CF CF CF DN DN DN DN DN DN DN EB EB EB EB EB EB EB

110 – 180 pF* 111 – 181*

201 –

200 – 270 pF

271*

F

G

J

K M BB BB BB BB BB BB BB CF CF CF CF CF CF CF DN DN DN DN DN DN DN EB EB EB EB EB EB EB

300 pF

330 pF

360 pF

390 pF

430 pF

470 pF

301

331

361

391

431

471

511

561

621

681

751

821

911

102

112

122

132

152

162

182

F

G

J

K M BB BB BB BB BB BD BD CF CF CF CF CF CF CF DN DN DN DN DN DN DN EB EB EB EB EB EB EB

K M BB BB BB BB BB

K M BB BB BB BB

CF CF CF CF CF CF CF DN DN DN DN DN DN DN EB EB EB EB EB EB EB

CF CF CF CF CF CF CF DN DN DN DN DN DP DP EB EB EB EB EB EB EB

CF CF CF CF CF CF CF DN DN DN DN DN DN DN EB EB EB EB EB EB EB

CF CF CF CF CF CF CF DN DN DN DN DN DP DP EB EB EB EB EB EB EB

CF CF CF CF CF CH CH DN DN DN DN DN DN DN EB EB EB EB EB EB EB

CF CF CF CF CF CH CH DP DP DP DP DP DN DN EB EB EB EB EC EC EC

CF CF CF CF CF CH CH DP DP DP DP DP DN DN EB EB EB EB ED EC EC

CF CF CF CF CF CH CH DP DP DP DP DP DN DN EB EB EB EB ED ED ED

510 pF

560 pF

620 pF

680 pF

750 pF

820 pF

910 pF

1,000 pF

1,100 pF

1,200 pF

1,300 pF

1,500 pF

1,600 pF

1,800 pF

K M BB BB BB BB

K M BB BB BB

Rated Voltage (VDC)

Voltage Code

Cap

Code

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

Cap

Case Size/Series

C0402C

C0603C

C0805C

C1206C

*Capacitance range Includes E24 decade values only. (i.e., 10, 11, 12, 13, 15, 16, 18, 20, 22, 24, 27, 30, 33, 36, 39, 43, 47, 51, 56, 62, 68, 75, 82, and 91)

KEMET reserves the right to substitute product with an improved temperature characteristic, tighter capacitance tolerance and/or higher voltage

capability within the same form factor (conﬁguration and dimensions).

These products are protected under US Patents 7,172,985 and 7,670,981, other patents pending, and any foreign counterparts.

C1019_C0G_SnPb_SMD • 8/11/2016

5

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Commercial “L” Series, SnPb Termination, C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Table 1A – Capacitance Range/Selection Waterfall (0402 – 1206 Case Sizes) cont'd

Case Size/

Series

C0402C

C0603C

C0805C

C1206C

Cap

Code

Cap

Voltage Code

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

Rated Voltage (VDC)

Capacitance

Tolerance

Product Availability and Chip Thickness Codes – See Table 2 for Chip Thickness Dimensions

2,000 pF

2,200 pF

2,400 pF

2,700 pF

3,000 pF

3,300 pF

3,600 pF

3,900 pF

4,300 pF

4,700 pF

5,100 pF

5,600 pF

6,200 pF

6,800 pF

7,500 pF

8,200 pF

9,100 pF

10,000 pF

12,000 pF

15,000 pF

18,000 pF

22,000 pF

27,000 pF

33,000 pF

39,000 pF

47,000 pF

56,000 pF

68,000 pF

82,000 pF

0.10 µF

202

222

242

272

302

332

362

392

432

472

512

562

622

682

752

822

912

103

123

153

183

223

273

333

393

473

563

683

823

104

683

823

104

F

G

J

K M BB BB BB

K M

CF CF CF CF CF CH CH DN DN DN DN DN DN DN EB EB EB EB ED ED ED

CF CF CF CF CF CH CH DN DN DN DN DN DN DN EB EB EB EB EE EE EE

CF CF CF CF CF

CF CF CF CF

CF CF CF

DN DN DN DN DN DN DN EB EB EB EB EC EC EC

DP DP DP DP DN DN DN EC EC EC EC EC EB EB

DP DP DP DP DN DN DN EC EC EC EC EE EB EB

DP DP DP DP DN DP DP EC EC EC EC EE EB EB

DE DE DE DE DN DP DP EC EC EC EC EF EB EB

DE DE DE DE DN DP DP EC EC EC EC EC EB EB

DE DE DE DE DN DP DP ED ED ED ED ED EB EB

DN DN DN DN DN DP DP ED ED ED ED ED EB EB

DN DN DN DN DN DG DG EB EB EB EB EB EB EB

DN DN DN DN DN DG DG EC EC EC EC EB EC EC

CF CF CF

DN DN DN DN DN

DN DN DN DN DP

DN DN DN DN DE

DN DN DN DP DG

DN DN DN DP

DP DP DP DF

DF DF DF

DG DG DG

EC EC EC EC EB EC EC

ED ED ED ED EB EC EC

EB EB EB EB EB ED ED

EB EB EB EB EB EF EF

EB EB EB EB EB EH EH

EB EB EB EB EC EH EH

EB EB EB EB EE

EC EC EC EE EH

ED ED ED EF

EF EF EF EH

EH EH EH EH

EH EH EH

EF EF EF EH

EH EH EH EH

EH EH EH

68,000 pF

82,000 pF

0.10 µF

Rated Voltage (VDC)

Voltage Code

Cap

Code

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

Cap

Case Size/Series

C0402C

C0603C

C0805C

C1206C

*Capacitance range Includes E24 decade values only. (i.e., 10, 11, 12, 13, 15, 16, 18, 20, 22, 24, 27, 30, 33, 36, 39, 43, 47, 51, 56, 62, 68, 75, 82, and 91)

KEMET reserves the right to substitute product with an improved temperature characteristic, tighter capacitance tolerance and/or higher voltage

capability within the same form factor (conﬁguration and dimensions).

These products are protected under US Patents 7,172,985 and 7,670,981, other patents pending, and any foreign counterparts.

C1019_C0G_SnPb_SMD • 8/11/2016

6

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Commercial “L” Series, SnPb Termination, C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Table 1B – Capacitance Range/Selection Waterfall (1210 – 2225 Case Sizes)

Case Size/

C1210C

C1808C

C1812C

C1825C

C2220C

C2225C

Series

Cap

Code

Voltage Code

8

4

3

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

Cap

Rated Voltage (VDC)

Capacitance

Tolerance

Product Availability and Chip Thickness Codes

See Table 2 for Chip Thickness Dimensions

1.0 – 9.1 pF* 109 – 919*

10 – 91 pF* 100 – 910*

100 – 300 pF* 101 – 301*

330 – 430 pF* 331 – 431*

470 – 910 pF* 471 – 911*

B

C

D

FB FB FB FB FB FB FB

K M FB FB FB FB FB FB FB

F

G

J

K M FB FB FB FB FB FB FB LF LF LF LF

K M FB FB FB FB FB FB FB LF LF LF LF GB GB GB GB

K M FB FB FB FB FB FC FC LF LF LF LF GB GB GB GB

K M FB FB FB FB FB FE FE LF LF LF LF GB GB GB GB

K M FB FB FB FB FC FE FE LF LF LF LF GB GB GB GB

K M FB FB FB FB FC FG FG LF LF LF LF GB GB GB GB

K M FB FB FB FB FC FC FC LF LF LF LF

K M FB FB FB FB FC FC FC LF LF LF LF GB GB GB GB

K M FB FB FB FB FC FF FF LF LF

K M FB FB FB FB FF FF FF LF LF

1,000 pF

1,100 pF

1,200 pF

1,300 pF

1,500 pF

1,600 pF

1,800 pF

2,000 pF

2,200 pF

2,400 pF

2,700 pF

3,000 pF

3,300 pF

3,600 pF

3,900 pF

4,300 pF

4,700 pF

5,100 pF

5,600 pF

6,200 pF

6,800 pF

7,500 pF

8,200 pF

9,100 pF

10,000 pF

12,000 pF

15,000 pF

18,000 pF

22,000 pF

27,000 pF

33,000 pF

39,000 pF

47,000 pF

56,000 pF

68,000 pF

82,000 pF

0.10 µF

102

112

122

132

152

162

182

202

222

242

272

302

332

362

392

432

472

512

562

622

682

752

822

912

103

123

153

183

223

273

333

393

473

563

683

823

104

124

154

184

224

274

334

394

474

GB GB GB GB

GB GB GB GB HB HB HB HB

GB GB GD GD HB HB HB HB

GB GB GH GH HB HB HB HB

K

M FB FB FB FB FF FF FF LF LF

K M FF FF FF FF FG FG FG LF LF

K M FB FB FB FB FG FG FG

K M FB FB FB FB FG FB FB

K M FC FC FC FC FC FB FB

K M FE FE FE FE FE FB FB

K M FF FF FF FF FF FB FB

K M FG FG FG FG FB FB FB

K M FG FG FG FG FB FC FC

K M FB FB FB FB FB FC FC

K M FB FB FB FB FB FF FF

K M FB FB FB FB FB FG FG

K M FB FB FB FB FB FH FH

K M FB FB FB FB FE FH FH

K M FB FB FB FB FE FJ FJ

K M FB FB FB FB FF

K M FB FB FB FC FG

K M FC FC FC FF FH

K M FE FE FE FG FM

K M FG FG FG FH

KE KE KE KE

KE KE

GB GB GJ GJ HB HB HB HB JE JE JB

GB GH GB GB HB HB HB HB JE JE JB

GB GH GB GB HB HB HE HE JE JE JB

GB GG GB GB HB HB HE HE JE JE JB

GB GB GB GB HB HB

GB GB GB GB HB HE

GB GB GB GB HB HG

GB GB GB GB

GB GB GD GD

GB GB GK GK

GB GB GM GM

GB GD GM GM

GB GH

JE JE JB

JE JB JB

JB JB JB

JB JB JD

JB JB JG

JB JD JG

JB JD JL

JB JF

KE KE

KE

0.12 µF

0.15 µF

0.18 µF

0.22 µF

K M FH FH FH FM

K M FJ FJ FJ

K M FK FK FK

K M

GD GN

GH

GK

0.27 µF

0.33 µF

0.39 µF

0.47 µF

JD JG

JG

Rated Voltage (VDC)

Voltage Code

8

4

3

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

Cap

Cap Code

Case Size/Series

C1210C

C1808C

C1812C

C1825C

C2220C

C2225C

*Capacitance range Includes E24 decade values only. (i.e., 10, 11, 12, 13, 15, 16, 18, 20, 22, 24, 27, 30, 33, 36, 39, 43, 47, 51, 56, 62, 68, 75, 82, and 91)

KEMET reserves the right to substitute product with an improved temperature characteristic, tighter capacitance tolerance and/or higher voltage

capability within the same form factor (conﬁguration and dimensions).

These products are protected under US Patents 7,172,985 and 7,670,981, other patents pending, and any foreign counterparts.

C1019_C0G_SnPb_SMD • 8/11/2016

7

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Commercial “L” Series, SnPb Termination, C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Table 2A – Chip Thickness/Tape & Reel Packaging Quantities

Paper Quantity¹

Plastic Quantity

Thickness Case Thickness ±

Code

Size¹Range (mm)

7" Reel

13" Reel

7" Reel

13" Reel

BB

BD

CF

CH

DN

DP

DE

DF

DG

EB

EC

ED

EE

EF

0402

0603

0805

1206

1210

1706

1808

1812

1825

2220

2225

0.50 ± 0.05

0.55 ± 0.05

0.80 ± 0.07

0.85 ± 0.07

0.78 ± 0.10

0.90 ± 0.10

1.00 ± 0.10

1.10 ± 0.10

1.25 ± 0.15

0.78 ± 0.10

0.90 ± 0.10

1.00 ± 0.10

1.10 ± 0.10

1.20 ± 0.15

1.60 ± 0.20

0.78 ± 0.10

0.90 ± 0.10

1.00 ± 0.10

1.10 ± 0.10

1.25 ± 0.15

1.55 ± 0.15

1.70 ± 0.20

1.85 ± 0.20

2.10 ± 0.20

1.00 ± 0.15

1.00 ± 0.10

1.25 ± 0.15

1.40 ± 0.15

1.55 ± 0.10

1.60 ± 0.20

1.70 ± 0.15

1.70 ± 0.20

2.00 ± 0.20

1.10 ± 0.15

1.40 ± 0.15

1.60 ± 0.20

1.00 ± 0.15

1.30 ± 0.15

1.40 ± 0.15

1.50 ± 0.15

1.70 ± 0.15

2.00 ± 0.20

1.40 ± 0.15

10,000

4,000

0

4,000

0

50,000

15,000

10,000

15,000

0

2,500

4,000

2,500

2,000

4,000

2,500

2,000

4,000

2,500

1,000

500

10,000

8,000

10,000

8,000

10,000

4,000

2,000

4,000

2,000

4,000

0

10,000

0

EH

FB

FC

FE

FF

0

FG

FH

FM

FJ

FK

NC

LF

GB

GD

GH

GG

GK

GJ

GN

GM

HB

HE

HG

JB

JD

JE

1,000

500

JF

JG

JL

0

KE

1,000

7" Reel

13" Reel

7" Reel

13" Reel

Thickness

Code

Case

Size¹

Thickness ±

Range (mm)

Paper Quantity¹

Plastic Quantity

Package quantity based on ﬁnished chip thickness speciﬁcations.

¹If ordering using the 2 mm Tape and Reel pitch option, the packaging quantity outlined in the table above will be doubled. This option is limited to EIA

0603 (1608 metric) case size devices. For more information regarding 2 mm pitch option see “Tape & Reel Packaging Information”.

C1019_C0G_SnPb_SMD • 8/11/2016

8

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Commercial “L” Series, SnPb Termination, C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Table 2B – Bulk Packaging Quantities

Loose Packaging

Packaging Type

Bulk Bag (default)

Packaging C-Spec¹

N/A²

Case Size

Packaging Quantities (pieces/unit packaging)

EIA (in)

Metric (mm)

Minimum

Maximum

0402

0603

0805

1206

1210

1808

1812

1825

2220

2225

1005

1608

2012

3216

3225

4520

4532

4564

5650

5664

50,000

1

20,000

¹The "Packaging C-Spec" is a 4 to 8 digit code which identiﬁes the packaging type and/or product grade. When ordering, the proper code must be

included in the 15th through 22nd character positions of the ordering code. See "Ordering Information" section of this document for further details.

Commercial Grade product ordered without a packaging C-Spec will default to our standard "Bulk Bag" packaging. Contact KEMET if you require a bulk

bag packaging option for Automotive Grade products.

²A packaging C-Spec (see note 1 above) is not required for "Bulk Bag" packaging (excluding Anti-Static Bulk Bag and Automotive Grade products). The

15th through 22nd character positions of the ordering code should be left blank. All product ordered without a packaging C-Spec will default to our

standard "Bulk Bag" packaging.

C1019_C0G_SnPb_SMD • 8/11/2016

9

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Commercial “L” Series, SnPb Termination, C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Table 3 – Chip Capacitor Land Pattern Design Recommendations per IPC–7351

Density Level A:

Maximum (Most)

Land Protrusion (mm)

Density Level B:

Median (Nominal)

Land Protrusion (mm)

Density Level C:

Minimum (Least)

Land Protrusion (mm)

EIA

Size

Code

Metric

Size

Code

C

Y

X

V1

V2

C

Y

X

V1

V2

C

Y

X

V1

V2

0402

0603

0805

1206

1210

1210¹

1808

1812

1825

2220

2225

1005

1608

2012

3216

3225

4520

4532

4564

5650

5664

0.50

0.72

2.20

1.20

0.45

0.62

1.90

1.00

0.40

0.52

1.60

0.80

0.90

1.00

1.60

1.50

2.30

2.15

2.75

2.70

1.15

1.35

1.60

1.75

1.60

1.70

1.10

1.55

1.90

2.80

2.90

2.30

3.60

6.90

5.50

6.90

4.00

4.40

5.60

5.65

5.60

7.40

6.90

8.20

8.10

2.10

2.60

2.90

3.80

3.90

3.30

4.60

7.90

6.50

7.90

0.80

0.90

1.50

1.40

2.20

2.05

2.65

2.60

0.95

1.15

1.40

1.55

1.40

1.50

1.00

1.45

1.80

2.70

2.80

2.20

3.50

6.80

5.40

6.80

3.10

3.50

4.70

6.50

6.00

7.30

7.20

1.50

2.00

2.30

3.20

3.30

2.70

4.00

7.30

5.90

7.30

0.60

0.75

1.40

1.30

2.10

1.95

2.55

2.50

0.75

0.95

1.20

1.35

1.20

1.30

0.90

1.35

1.70

2.60

2.70

2.10

3.40

6.70

5.30

6.70

2.40

2.80

4.00

5.80

5.30

6.60

6.50

1.20

1.70

2.00

2.90

3.00

2.40

3.70

7.00

5.60

7.00

¹Only for capacitance values ≥ 22 µF

Density Level A: For low-density product applications. Recommended for wave solder applications and provides a wider process window for reﬂow

solder processes. KEMET only recommends wave soldering of EIA 0603, 0805 and 1206 case sizes.

Density Level B: For products with a moderate level of component density. Provides a robust solder attachment condition for reﬂow solder processes.

Density Level C: For high component density product applications. Before adapting the minimum land pattern variations the user should perform

qualiﬁcation testing based on the conditions outlined in IPC Standard 7351 (IPC–7351).

Image below based on Density Level B for an EIA 1210 case size.

V1

ꢀ

V2

ꢁ

C

Grid Placement Courtyard

C1019_C0G_SnPb_SMD • 8/11/2016 10

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Commercial “L” Series, SnPb Termination, C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Soldering Process

Recommended Soldering Technique:

• Solder wave or solder reﬂow for EIA case sizes 0603, 0805 and 1206

• All other EIA case sizes are limited to solder reﬂow only

Recommended Reﬂow Soldering Proﬁle:

KEMET’s families of surface mount multilayer ceramic capacitors (SMD MLCCs) are compatible with wave (single or dual),

convection, IR or vapor phase reﬂow techniques. Preheating of these components is recommended to avoid extreme thermal

stress. KEMET’s recommended proﬁle conditions for convection and IR reﬂow reﬂect the proﬁle conditions of the IPC/

J-STD-020 standard for moisture sensitivity testing. These devices can safely withstand a maximum of three reﬂow passes

at these conditions.

Termination Finish

T_P

T_L

t_P

Proﬁle Feature

Maꢀimum ꢁamp ꢂp ꢁate ꢃ ꢄꢅCꢆsec

Maꢀimum ꢁamp Doꢇn ꢁate ꢃ ꢈꢅCꢆsec

SnPb

100% Matte Sn

t_L

Preheat/Soak

Temperature Minimum (T_Smin

)

100°C

150°C

200°C

T_smaꢀ

T_smin

Temperature Maximum (T_Smax

Time (t_S) from T_Sminto T_Smax

)

60 – 120 seconds

3°C/second

60 – 120 seconds

3°C/second

t_s

Ramp-Up Rate (T_Lto T_P)

maximum

25

Liquidous Temperature (T_L)

Time Above Liquidous (t_L)

Peak Temperature (T_P)

183°C

60 – 150 seconds

235°C

217°C

60 – 150 seconds

260°C

25ꢅC to Peaꢉ

Time

Time Within 5°C of Maximum

Peak Temperature (t_P)

20 seconds

maximum

30 seconds

maximum

6°C/second

maximum

6°C/second

maximum

Ramp-Down Rate (T_Pto T_L)

Time 25°C to Peak

Temperature

6 minutes

maximum

8 minutes

maximum

Note 1: All temperatures refer to the center of the package, measured on the

capacitor body surface that is facing up during assembly reﬂow.

C1019_C0G_SnPb_SMD • 8/11/2016 11

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Commercial “L” Series, SnPb Termination, C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Table 4 – Performance & Reliability: Test Methods and Conditions

Stress

Reference

Test or Inspection Method

Terminal Strength

JIS–C–6429

Appendix 1, Note: Force of 1.8 kg for 60 seconds.

Appendix 2, Note: Standard termination system – 2.0 mm (minimum) for all except 3 mm

for C0G. Flexible termination system – 3.0 mm (minimum).

Board Flex

JIS–C–6429

Magniﬁcation 50 X. Conditions:

a) Method B, 4 hours at 155°C, dry heat at 235°C

b) Method B at 215°C category 3

Solderability

J–STD–002

c) Method D, category 3 at 260°C

1,000 Cycles (−55°C to +125°C). Measurement at 24 hours +/− 4 hours after test

conclusion.

Load Humidity: 1,000 hours 85°C/85% RH and rated voltage. Add 100 K ohm resistor.

Measurement at 24 hours +/− 4 hours after test conclusion.

Low Volt Humidity: 1,000 hours 85°C/85% RH and 1.5 V. Add 100 K ohm resistor.

Measurement at 24 hours +/− 4 hours after test conclusion.

t = 24 hours/cycle. Steps 7a and 7b not required.

Measurement at 24 hours +/− 4 hours after test conclusion.

−55°C/+125°C. Note: Number of cycles required – 300, maximum transfer time – 20

seconds, dwell time – 15 minutes. Air – Air.

Temperature Cycling

Biased Humidity

JESD22 Method JA–104

MIL–STD–202 Method

103

MIL–STD–202 Method

Moisture Resistance

Thermal Shock

106

MIL–STD–202 Method

107

MIL–STD–202 Method

108

/EIA–198

MIL–STD–202 Method

108

High Temperature Life

Storage Life

1,000 hours at 125°C (85°C for X5R, Z5U and Y5V) with 2 X rated voltage applied.

150°C, 0 VDC for 1,000 hours.

5 g's for 20 min., 12 cycles each of 3 orientations. Note: Use 8" X 5" PCB 0.031" thick 7

secure points on one long side and 2 secure points at corners of opposite sides. Parts

mounted within 2" from any secure point. Test from 10 – 2,000 Hz

MIL–STD–202 Method

204

Vibration

MIL–STD–202 Method

Mechanical Shock

Figure 1 of Method 213, Condition F.

213

MIL–STD–202 Method

215

Resistance to Solvents

Add aqueous wash chemical, OKEM Clean or equivalent.

Storage and Handling

Ceramic chip capacitors should be stored in normal working environments. While the chips themselves are quite robust in

other environments, solderability will be degraded by exposure to high temperatures, high humidity, corrosive atmospheres,

and long term storage. In addition, packaging materials will be degraded by high temperature–reels may soften or warp

and tape peel force may increase. KEMET recommends that maximum storage temperature not exceed 40ºC and maximum

storage humidity not exceed 70% relative humidity. Temperature ﬂuctuations should be minimized to avoid condensation on

the parts and atmospheres should be free of chlorine and sulfur bearing compounds. For optimized solderability chip stock

should be used promptly, preferably within 1.5 years of receipt.

C1019_C0G_SnPb_SMD • 8/11/2016 12

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Commercial “L” Series, SnPb Termination, C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Construction

Detailed Cross Section

Dielectric Material

(Caꢄrꢅ_ꢆ)

ꢀarrier Layer

(ꢁi)

Dielectric

Material (Caꢄrꢅ_ꢆ)

ꢃnd Terminationꢊ

ꢃꢋternal ꢃlectrode

(Cu)

Termination ꢇinish

(SnPb ꢈ 5ꢉ Pb min)

ꢂnner ꢃlectrodes

(ꢁi)

ꢃnd Terminationꢊ

ꢃꢋternal ꢃlectrode

(Cu)

ꢀarrier Layer

(ꢁi)

Termination ꢇinish

(SnPb ꢈ 5ꢉ Pb min)

ꢂnner ꢃlectrodes

(ꢁi)

Capacitor Marking (Optional):

Laser marking option is not available on:

• C0G, Ultra Stable X8R and Y5V dielectric devices

• EIA 0402 case size devices

• EIA 0603 case size devices with Flexible Termination option.

• KPS Commercial and Automotive grade stacked devices.

These capacitors are supplied unmarked only.

C1019_C0G_SnPb_SMD • 8/11/2016 13

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Commercial “L” Series, SnPb Termination, C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Tape & Reel Packaging Information

KEMET offers multilayer ceramic chip capacitors packaged in 8, 12 and 16 mm tape on 7" and 13" reels in accordance with

EIA Standard 481. This packaging system is compatible with all tape-fed automatic pick and place systems. See Table 2 for

details on reeling quantities for commercial chips.

ꢓar Code Label

ꢆntiꢇStatic ꢈeel

®

ꢉmbossed Plasticꢊ or

Punched Paper Carrierꢃ

Chip and ꢏPS ꢐrientation in Pocꢎet

(eꢍcept 1ꢀ25 Commercial, and 1ꢀ25 and 2225 Military)

KEMET

Sprocꢎet ꢔoles

ꢉmbossment or Punched Caꢋity

ꢀ mm, 12 mm

or 1ꢁ mm Carrier Tape

ꢆntiꢇStatic Coꢋer Tape

(ꢃ10 mm (ꢃ00ꢌꢄ) Maꢍimum Thicꢎness)

1ꢂꢀ mm (ꢂꢃ00ꢄ)

or

ꢅꢅ0 mm (1ꢅꢃ00ꢄ)

ꢊꢉꢑꢆ 01005, 0201, 0ꢌ02 and 0ꢁ0ꢅ case siꢒes aꢋailable on punched paper carrier onlyꢃ

Table 5 – Carrier Tape Conﬁguration, Embossed Plastic & Punched Paper (mm)

New 2 mm Pitch Reel Options*

Embossed Plastic Punched Paper

Tape

Packaging

Ordering Code

(C-Spec)

C-3190

7" Reel 13" Reel 7" Reel 13" Reel

EIA Case Size Size

(W)*

Packaging Type/Options

Pitch (P₁)* Pitch (P₁)*

01005 – 0402

0603

8

2

2/4

4

Automotive grade 7" reel unmarked

Automotive grade 13" reel unmarked

Commercial grade 7" reel unmarked

Commercial grade 13" reel unmarked

C-3191

2/4

4

C-7081

0805

8

4

C-7082

1206 – 1210

1805 – 1808

≥ 1812

8

4

* 2 mm pitch reel only available for 0603 EIA case size.

2 mm pitch reel for 0805 EIA case size under development.

12

16

8

4

8

Beneﬁts of Changing from 4 mm to 2 mm Pitching Spacing

• Lower placement costs

• Double the parts on each reel results in fewer reel

changes and increased efﬁciency

• Fewer reels result in lower packaging, shipping and

storage costs, reducing waste

KPS 1210

8

KPS 1812 & 2220

Array 0508 & 0612

12

4

12

4

*Refer to Figures 1 & 2 for W and P₁carrier tape reference locations.

*Refer to Tables 6 & 7 for tolerance speciﬁcations.

C1019_C0G_SnPb_SMD • 8/11/2016 14

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Commercial “L” Series, SnPb Termination, C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Figure 1 – Embossed (Plastic) Carrier Tape Dimensions

T

P 2

ꢌ10 pitches cumulatiꢂe

tolerance on tape ꢍ 0ꢎ2 mmꢏ

2

ꢈ

1

Po

ꢇDo

ꢃo

ꢀ

ꢅo

ꢁ

ꢈ

2

ꢄ

1

ꢄo

S

1

P

1

T

1

ꢈmbossment

ꢀor caꢂity siꢉe,

see ꢊote 1 Table ꢋ

Center Lines of Caꢂity

ꢇD

1

Coꢂer Tape

is for tape feeder reference only,

includinꢆ draft concentric about ꢄ

ꢄ

1

o

.

User Direction of Unreeling

Table 6 – Embossed (Plastic) Carrier Tape Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

D₁Minimum

Note 1

1.0

(0.039)

R Reference S₁Minimum

T

T₁

Tape Size

8 mm

D₀

E₁

P₀

P₂

Note 2

Note 3

Maximum Maximum

25.0

(0.984)

1.5 +0.10/-0.0

(0.059 +0.004/-

0.0)

1.75 ±0.10

4.0 ±0.10

2.0 ±0.05

0.600

(0.024)

0.100

(0.004)

12 mm

16 mm

(0.069 ±0.004) (0.157 ±0.004) (0.079 ±0.002)

(0.024)

1.5

(0.059)

30

(1.181)

Variable Dimensions — Millimeters (Inches)

B₁Maximum

Note 4

E₂

T₂

W

Tape Size

8 mm

Pitch

F

P₁

A₀,B₀& K₀

Minimum

6.25

(0.246)

Maximum Maximum

2.5

(0.098)

4.35

(0.171)

3.5 ±0.05

(0.138 ±0.002) (0.157 ±0.004)

4.0 ±0.10

8.3

(0.327)

Single (4 mm)

Single (4 mm) &

Double (8 mm)

8.2

10.25

5.5 ±0.05

8.0 ±0.10

4.6

12.3

12 mm

16 mm

Note 5

(0.323)

(0.404)

(0.217 ±0.002) (0.315 ±0.004)

(0.181)

(0.484)

12.1

(0.476)

14.25

(0.561)

7.5 ±0.05 12.0 ±0.10

(0.138 ±0.002) (0.157 ±0.004)

4.6

(0.181)

16.3

(0.642)

Triple (12 mm)

1. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment. Dimensions of embossment

location and hole location shall be applied independent of each other.

2. The tape with or without components shall pass around R without damage (see Figure 6).

3. If S₁< 1.0 mm, there may not be enough area for cover tape to be properly applied (see EIA Standard 481 paragraph 4.3 section b).

4. B₁dimension is a reference dimension for tape feeder clearance only.

5. The cavity deﬁned by A₀, B₀and K₀shall surround the component with sufﬁcient clearance that:

(a) the component does not protrude above the top surface of the carrier tape.

(b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.

(c) rotation of the component is limited to 20° maximum for 8 and 12 mm tapes and 10° maximum for 16 mm tapes (see Figure 3).

(d) lateral movement of the component is restricted to 0.5 mm maximum for 8 and 12 mm wide tape and to 1.0 mm maximum for 16 mm tape (see

Figure 4).

(e) for KPS Series product, A₀and B₀are measured on a plane 0.3 mm above the bottom of the pocket.

(f) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.

C1019_C0G_SnPb_SMD • 8/11/2016 15

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Commercial “L” Series, SnPb Termination, C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Figure 2 – Punched (Paper) Carrier Tape Dimensions

T

ꢊ10 pitches cumulatiꢀe

ꢂ¹

Po

ꢁDo

tolerance on tape ꢋ 0ꢌ2 mmꢍ

ꢅ⁰

ꢃ

ꢄ

ꢂ²

ꢆ⁰

ꢆottom Coꢀer Tape

P¹

G

Caꢀity Siꢇe,

See

T¹

Center Lines of Caꢀity

Top Coꢀer Tape

ꢈote 1, Table ꢉ

ꢆottom Coꢀer Tape

User Direction of Unreeling

Table 7 – Punched (Paper) Carrier Tape Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

R Reference

Note 2

Tape Size

8 mm

D₀

E₁

P₀

P₂

T₁Maximum

G Minimum

0.10

1.5 +0.10 -0.0

(0.059 +0.004 -0.0)

1.75 ±0.10

(0.069 ±0.004)

4.0 ±0.10

(0.157 ±0.004)

2.0 ±0.05

(0.079 ±0.002)

0.75

(0.030)

25

(0.984)

(0.004)

Maximum

Variable Dimensions — Millimeters (Inches)

Tape Size

8 mm

Pitch

E2 Minimum

F

P₁

T Maximum

W Maximum

A₀B₀

2.0 ±0.05

(0.079 ±0.002)

4.0 ±0.10

(0.157 ±0.004)

8.3

(0.327)

8.3

(0.327)

Half (2 mm)

Single (4 mm)

6.25

(0.246)

3.5 ±0.05

(0.138 ±0.002)

1.1

(0.098)

Note 1

8 mm

1. The cavity deﬁned by A₀, B₀and T shall surround the component with sufﬁcient clearance that:

a) the component does not protrude beyond either surface of the carrier tape.

b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.

c) rotation of the component is limited to 20° maximum (see Figure 3).

d) lateral movement of the component is restricted to 0.5 mm maximum (see Figure 4).

e) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.

2. The tape with or without components shall pass around R without damage (see Figure 6).

C1019_C0G_SnPb_SMD • 8/11/2016 16

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Commercial “L” Series, SnPb Termination, C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Packaging Information Performance Notes

1. Cover Tape Break Force: 1.0 Kg minimum.

2. Cover Tape Peel Strength: The total peel strength of the cover tape from the carrier tape shall be:

Tape Width

8 mm

Peel Strength

0.1 to 1.0 Newton (10 to 100 gf)

0.1 to 1.3 Newton (10 to 130 gf)

12 and 16 mm

The direction of the pull shall be opposite the direction of the carrier tape travel. The pull angle of the carrier tape shall be

165° to 180° from the plane of the carrier tape. During peeling, the carrier and/or cover tape shall be pulled at a velocity of

300 ±10 mm/minute.

3. Labeling: Bar code labeling (standard or custom) shall be on the side of the reel opposite the sprocket holes. Refer to EIA

Standards 556 and 624.

Figure 3 – Maximum Component Rotation

°

T

Maximum Component Rotation

Top View

Maximum Component Rotation

Side View

Typical Pocꢅet Centerline

Tape

Maximum

°

T

s

Width (mm) Rotation (

)

ꢂ,12

1ꢃ – 200

20

10

ꢁo

Tape

Maximum

°

S

Width (mm) Rotation (

)

ꢂ,12

1ꢃ – 5ꢃ

ꢄ2 – 200

20

10

5

Typical Component Centerline

ꢀo

Figure 4 – Maximum Lateral Movement

Figure 5 – Bending Radius

ꢃmbossed

Carrier

Punched

Carrier

ꢂ mm ꢃ 12 mm Tape

1ꢄ mm Tape

0ꢀ5 mm maꢁimum

1ꢀ0 mm maꢁimum

ꢀ

ꢁendinꢂ

ꢀadius

ꢀ

C1019_C0G_SnPb_SMD • 8/11/2016 17

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Commercial “L” Series, SnPb Termination, C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Figure 6 – Reel Dimensions

ꢂull ꢃadius,

ꢍꢎ (ꢈncludes

flanꢏe distortion

at outer edꢏe)

ꢀccess ꢅole at

Slot Location

(ꢆ ꢇ0 mm minimum)

See ꢁote

ꢍ2 (Measured at hub)

D

(See ꢁote)

ꢀ

ꢁ

C

(ꢀrbor hole

ꢍ1 (Measured at hub)

diameter)

ꢈf present,

tape slot in core

for tape startꢉ

2ꢊ5 mm minimum ꢋidth ꢌ

10ꢊ0 mm minimum depth

ꢄ

(see ꢁote)

ꢁoteꢉ Driꢐe spoꢑes optionalꢒ if used, dimensions ꢄ and D shall applyꢊ

Table 8 – Reel Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

Tape Size

8 mm

A

B Minimum

C

D Minimum

178 ±0.20

(7.008 ±0.008)

or

1.5

(0.059)

13.0 +0.5/-0.2

(0.521 +0.02/-0.008)

20.2

(0.795)

12 mm

16 mm

330 ±0.20

(13.000 ±0.008)

Variable Dimensions — Millimeters (Inches)

Tape Size

8 mm

N Minimum

W₁

W₂Maximum

W₃

8.4 +1.5/-0.0

(0.331 +0.059/-0.0)

14.4

(0.567)

50

(1.969)

12.4 +2.0/-0.0

18.4

Shall accommodate tape

width without interference

12 mm

16 mm

(0.488 +0.078/-0.0)

(0.724)

16.4 +2.0/-0.0

(0.646 +0.078/-0.0)

22.4

(0.882)

C1019_C0G_SnPb_SMD • 8/11/2016 18

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Commercial “L” Series, SnPb Termination, C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Figure 7 – Tape Leader & Trailer Dimensions

ꢄmbossed Carrier

Carrier Tape

Punched Carrier

ꢉ mm ꢊ 12 mm only

ꢁound Sprocꢂet ꢃoles

START

END

Top Coꢈer Tape

ꢄlonꢅated Sprocꢂet ꢃoles

(ꢆ2 mm tape and ꢇider)

100 mm

Minimum Leader

ꢋ00 mm Minimum

Trailer

Components

1ꢀ0 mm Minimum

Top Coꢈer Tape

Figure 8 – Maximum Camber

ꢅlonꢄated sprocꢁet holes

(ꢆ2 mm ꢇ ꢈider tapes)

Carrier Tape

ꢀound Sprocꢁet ꢂoles

1 mm Maꢃimum, either direction

Straiꢄht ꢅdꢄe

250 mm

C1019_C0G_SnPb_SMD • 8/11/2016 19

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

Commercial “L” Series, SnPb Termination, C0G Dielectric, 10 – 250 VDC (Commercial Grade)

KEMET Electronic Corporation Sales Ofﬁces

For a complete list of our global sales ofﬁces, please visit www.kemet.com/sales.

Disclaimer

All product speciﬁcations, statements, information and data (collectively, the “Information”) in this datasheet are subject to change. The customer is responsible for

checking and verifying the extent to which the Information contained in this publication is applicable to an order at the time the order is placed.

All Information given herein is believed to be accurate and reliable, but it is presented without guarantee, warranty, or responsibility of any kind, expressed or implied.

Statements of suitability for certain applications are based on KEMET Electronics Corporation’s (“KEMET”) knowledge of typical operating conditions for such

applications, but are not intended to constitute – and KEMET speciﬁcally disclaims – any warranty concerning suitability for a speciﬁc customer application or use.

The Information is intended for use only by customers who have the requisite experience and capability to determine the correct products for their application. Any

technical advice inferred from this Information or otherwise provided by KEMET with reference to the use of KEMET’s products is given gratis, and KEMET assumes no

obligation or liability for the advice given or results obtained.

Although KEMET designs and manufactures its products to the most stringent quality and safety standards, given the current state of the art, isolated component

failures may still occur. Accordingly, customer applications which require a high degree of reliability or safety should employ suitable designs or other safeguards

(such as installation of protective circuitry or redundancies) in order to ensure that the failure of an electrical component does not result in a risk of personal injury or

property damage.

Although all product–related warnings, cautions and notes must be observed, the customer should not assume that all safety measures are indicted or that other

measures may not be required.

KEMET is a registered trademark of KEMET Electronics Corporation.

C1019_C0G_SnPb_SMD • 8/11/2016 20


型号：	C0805C102K1GALTU
厂家：	KEMET CORPORATION
描述：	Ceramic Capacitor, Multilayer, Ceramic, 100V, C0G, -/+30ppm/Cel TC, 0.001uF, 0805 电容器
文件：	总20页 (文件大小：1317K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

C0805C102K1GALTU [KEMET]

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