C1825C104D3GACTU_技术文档

SurfaceꢀMountꢀMultilayerꢀCeramicꢀChipꢀCapacitorsꢀ(SMDꢀMLCCs)

C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Overview

KEMET’sꢀC0Gꢀdielectricꢀfeaturesꢀaꢀ125°Cꢀmaximumꢀoperatingꢀ

temperatureꢀandꢀisꢀconsideredꢀ“stable.”ꢀTheꢀElectronicsꢀ

Components, Assemblies & Materials Association (EIA)

andꢀstabilityꢀofꢀcapacitanceꢀcharacteristicsꢀareꢀrequired.ꢀC0Gꢀ

exhibitsꢀnoꢀchangeꢀinꢀcapacitanceꢀwithꢀrespectꢀtoꢀtimeꢀandꢀ

voltageꢀandꢀboastsꢀaꢀnegligibleꢀchangeꢀinꢀcapacitanceꢀwithꢀ

characterizesꢀC0GꢀdielectricꢀasꢀaꢀClassꢀIꢀmaterial.ꢀComponentsꢀ referenceꢀtoꢀambientꢀtemperature.ꢀCapacitanceꢀchangeꢀisꢀ

ofꢀthisꢀclassiﬁcationꢀareꢀtemperatureꢀcompensatingꢀandꢀareꢀ

suitedꢀforꢀresonantꢀcircuitꢀapplicationsꢀorꢀthoseꢀwhereꢀQꢀ

limitedꢀtoꢀ±30ꢀppm/ºCꢀfromꢀ−55°Cꢀtoꢀ+125°C.ꢀ

Beneﬁts

•ꢀ −55°Cꢀtoꢀ+125°Cꢀoperatingꢀtemperatureꢀrange

• Lead (Pb)-Free, RoHS, and REACH compliant

• EIA 0201, 0402, 0603, 0805, 1206, 1210, 1808, 1812, 1825,

2220, and 2225 case sizes

•ꢀ DCꢀvoltageꢀratingsꢀofꢀ10ꢀV,ꢀ16ꢀV,ꢀ25ꢀV,ꢀ50ꢀV,ꢀ100ꢀV,ꢀ200ꢀVꢀandꢀ250ꢀV

•ꢀ Capacitanceꢀofferingsꢀrangingꢀfromꢀ0.5ꢀpFꢀupꢀtoꢀ0.47ꢀμFꢀ

•ꢀ Availableꢀcapacitanceꢀtolerancesꢀofꢀ±0.10ꢀpF,ꢀ±0.25ꢀpF,ꢀ±0.5ꢀ

pF,ꢀ±1%,ꢀ±2%,ꢀ±5%,ꢀ±10%,ꢀandꢀ±20%ꢀꢀ

• No piezoelectric noise

• Extremely low ESR and ESL

•ꢀ Highꢀthermalꢀstability

•ꢀ Highꢀrippleꢀcurrentꢀcapability

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Ordering Information

C

1206

C

104

J

3

G

A

C

TU

Case Size Speciﬁcation/

(L" x W")

Capacitance

Code (pF)

Capacitance RatedꢀVoltageꢀ

FailureꢀRate/

Design

Packaging/Gradeꢀ

Ceramic

Dielectric

G = C0G

TerminationꢀFinish³

Series¹

Tolerance²

(VDC)

(C-Spec)

0201

0402

0603

0805

1206

1210

1808

1812

1825

2220

2225

C = Standard

Twoꢀsigniﬁcantꢀ

digitsꢀ+

numberꢀofꢀzeros.

Useꢀ9ꢀforꢀ1.0ꢀ–ꢀ9.9ꢀpF Fꢀ=ꢀ±1%

Useꢀ8ꢀforꢀ0.5ꢀ–ꢀ.99ꢀpF Gꢀ=ꢀ±2%

e.g.,ꢀ2.2ꢀpFꢀ=ꢀ229

e.g.,ꢀ0.5ꢀpFꢀ=ꢀ508

Bꢀ=ꢀ±0.10ꢀpF

8 = 10

A = N/A

Cꢀ=ꢀ100%ꢀMatteꢀ Seeꢀ“Packagingꢀ

Cꢀ=ꢀ±0.25ꢀpF 4 = 16

Sn

C-Spec

Orderingꢀ

OptionsꢀTable”ꢀ

below

Dꢀ=ꢀ±0.5ꢀpF

3 = 25

5 = 50

1 = 100

2 = 200

A = 250

Jꢀ=ꢀ±5%

Kꢀ=ꢀ±10%

Mꢀ=ꢀ±20%

¹Flexible termination option is available. Please see FT-CAP product bulletin C1062_C0G_FT-CAP_SMD

²Additional capacitance tolerance offerings may be available. Contact KEMET for details.

³Additional termination ﬁnish options may be available. Contact KEMET for details.

One world. One KEMET

C1003_C0G • 3/30/2016

1

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Packaging C-Spec Ordering Options Table

Packaging/Grade

Packaging Type¹

Ordering Code (C-Spec)

BulkꢀBagꢀ/ꢀUnmarked

7"ꢀReelꢀ/ꢀUnmarked

Notꢀrequiredꢀ(Blank)

TU

7411ꢀ(EIAꢀ0603ꢀandꢀsmallerꢀcaseꢀsizes)

7210ꢀ(EIAꢀ0805ꢀandꢀlargerꢀcaseꢀsizes)

13" Reel / Unmarked

7"ꢀReelꢀ/ꢀUnmarkedꢀ/ꢀ2ꢀmmꢀpitch²

13"ꢀReelꢀ/ꢀUnmarkedꢀ/ꢀ2ꢀmmꢀpitch²

7081

7082

¹Default packaging is “Bulk Bag”. An ordering code C-Spec is not required for “Bulk Bag” packaging.

¹The terms “Marked” and “Unmarked” pertain to laser marking option of capacitors. All packaging options labeled as “Unmarked” will contain capacitors that have

not been laser marked. The option to laser mark is not available on these devices. For more information see “Capacitor Marking”.

²The 2 mm pitch option allows for double the packaging quantity of capacitors on a given reel size. This option is limited to EIA 0603 (1608 metric) case size

devices. For more information regarding 2 mm pitch option see “Tape & Reel Packaging Information”.

Beneﬁts cont'd

•ꢀ PreferredꢀcapacitanceꢀsolutionꢀatꢀlineꢀfrequenciesꢀandꢀintoꢀtheꢀMHzꢀrange

•ꢀ NoꢀcapacitanceꢀchangeꢀwithꢀrespectꢀtoꢀappliedꢀratedꢀDCꢀvoltage

•ꢀ Negligibleꢀcapacitanceꢀchangeꢀwithꢀrespectꢀtoꢀtemperatureꢀfromꢀ−55°Cꢀtoꢀ+125°C

•ꢀ Noꢀcapacitanceꢀdecayꢀwithꢀtime

•ꢀ Non-polarꢀdevice,ꢀminimizingꢀinstallationꢀconcerns

•ꢀ 100%ꢀpureꢀmatteꢀtin-platedꢀterminationꢀﬁnishꢀallowingꢀforꢀexcellentꢀsolderability

•ꢀ SnPbꢀplatedꢀterminationꢀﬁnishꢀoptionꢀavailableꢀuponꢀrequestꢀ(5%ꢀPbꢀminimum)

Applications

Typicalꢀapplicationsꢀincludeꢀcriticalꢀtiming,ꢀtuning,ꢀcircuitsꢀrequiringꢀlowꢀloss,ꢀcircuitsꢀwithꢀpulse,ꢀhighꢀcurrent,ꢀdecoupling,ꢀbypass,ꢀ

ﬁltering,ꢀtransientꢀvoltageꢀsuppression,ꢀblockingꢀandꢀenergyꢀstorage.

Qualiﬁcation/Certiﬁcation

CommercialꢀGradeꢀproductsꢀareꢀsubjectꢀtoꢀinternalꢀqualiﬁcation.ꢀDetailsꢀregardingꢀtestꢀmethodsꢀandꢀconditionsꢀareꢀreferencedꢀinꢀ

Tableꢀ4,ꢀPerformanceꢀandꢀReliability.

Environmental Compliance

Leadꢀ(Pb)-Free,ꢀRoHS,ꢀandꢀREACHꢀcompliantꢀwithoutꢀexemptions.

C1003_C0G • 3/30/2016

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Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Dimensions – Millimeters (Inches)

L

W

T

B

S

EIA

Size

Code

Metric

Size

Code

S

L

W

Width

T

B

Mounting

Technique

Separation

Minimum

Length

Thickness

Bandwidth

0201

0402

0603

0805

1206

1210

1808

1812

1825

2220

2225

0603

1005

1608

2012

3216

3225

4520

4532

4564

5650

5664

0.60ꢀ(.024)ꢀ±ꢀ0.03ꢀ(.001) 0.30ꢀ(.012)ꢀ±ꢀ0.03ꢀ(.001)

1.00ꢀ(.040)ꢀ±ꢀ0.05ꢀ(.002) 0.50ꢀ(.020)ꢀ±ꢀ0.05ꢀ(.002)

1.60ꢀ(.063)ꢀ±ꢀ0.15ꢀ(.006) 0.80ꢀ(.032)ꢀ±ꢀ0.15ꢀ(.006)

2.00ꢀ(.079)ꢀ±ꢀ0.20ꢀ(.008) 1.25ꢀ(.049)ꢀ±ꢀ0.20ꢀ(.008)

3.20ꢀ(.126)ꢀ±ꢀ0.20ꢀ(.008) 1.60ꢀ(.063)ꢀ±ꢀ0.20ꢀ(.008)

3.20ꢀ(.126)ꢀ±ꢀ0.20ꢀ(.008) 2.50ꢀ(.098)ꢀ±ꢀ0.20ꢀ(.008)

4.70ꢀ(.185)ꢀ±ꢀ0.50ꢀ(.020) 2.00ꢀ(.079)ꢀ±ꢀ0.20ꢀ(.008)

4.50ꢀ(.177)ꢀ±ꢀ0.30ꢀ(.012) 3.20ꢀ(.126)ꢀ±ꢀ0.30ꢀ(.012)

4.50ꢀ(.177)ꢀ±ꢀ0.30ꢀ(.012) 6.40ꢀ(.252)ꢀ±ꢀ0.40ꢀ(.016)

5.70ꢀ(.224)ꢀ±ꢀ0.40ꢀ(.016) 5.00ꢀ(.197)ꢀ±ꢀ0.40ꢀ(.016)

5.60ꢀ(.220)ꢀ±ꢀ0.40ꢀ(.016) 6.40ꢀ(.248)ꢀ±ꢀ0.40ꢀ(.016)

0.15ꢀ(.006)ꢀ±ꢀ0.05ꢀ(.002)

0.30ꢀ(.012)ꢀ±ꢀ0.10ꢀ(.004)

0.35ꢀ(.014)ꢀ±ꢀ0.15ꢀ(.006)

0.50ꢀ(0.02)ꢀ±ꢀ0.25ꢀ(.010)

0.60ꢀ(.024)ꢀ±ꢀ0.35ꢀ(.014)

N/A

SolderꢀReﬂowꢀOnly

0.30 (.012)

0.70ꢀ(.028)

0.75ꢀ(.030)

Solder Wave or

SolderꢀReﬂow

SeeꢀTableꢀ2ꢀforꢀ

Thickness

N/A

SolderꢀReﬂowꢀOnly

C1003_C0G • 3/30/2016

3

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Electrical Parameters/Characteristics

Item

Parameters/Characteristics

OperatingꢀTemperatureꢀRange

−55°Cꢀtoꢀ+125°Cꢀꢀ

±30ꢀppm/ºCꢀ

0%

CapacitanceꢀChangeꢀwithꢀReferenceꢀtoꢀ+25°Cꢀandꢀ0ꢀVDCꢀAppliedꢀ(TCC)

AgingꢀRateꢀ(Maximumꢀ%ꢀCapacitanceꢀLoss/DecadeꢀHour)

250%ꢀofꢀratedꢀvoltage

(5ꢀ±1ꢀsecondsꢀandꢀcharge/dischargeꢀnotꢀexceedingꢀ50ꢀmA)

¹DielectricꢀWithstandingꢀVoltageꢀ(DWV)

²DissipationꢀFactorꢀ(DF)ꢀMaximumꢀLimitꢀ@ꢀ25ºC

0.1%

1,000ꢀmegohmꢀmicrofaradsꢀorꢀ100ꢀGΩ

(Ratedꢀvoltageꢀappliedꢀforꢀ120ꢀ±5ꢀsecondsꢀ@ꢀ25°C)

³InsulationꢀResistanceꢀ(IR)ꢀLimitꢀ@ꢀ25°C

¹DWV is the voltage a capacitor can withstand (survive) for a short period of time. It exceeds the nominal and continuous working voltage of the capacitor.

²Capacitance and dissipation factor (DF) measured under the following conditions:

1 MHz ±100 kHz and 1.0 Vrms ±0.2 V if capacitance ≤ 1,000 pF

1 kHz ±50 Hz and 1.0 Vrms ±0.2 V if capacitance > 1,000 pF

³To obtain IR limit, divide MΩ-µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits.

Capacitance and Dissipation Factor (DF) measured under the following conditions:

Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 and Agilent E4980 have a feature known as

Automatic Level Control (ALC). The ALC feature should be switched to "ON."

Post Environmental Limits

High Temperature Life, Biased Humidity, Moisture Resistance

Rated DC

Voltage

Capacitance

Dissipation Factor

(Maximumꢀ%)ꢀ

Capacitance

Insulationꢀ

Resistance

Dielectric

C0G

Value

Shiftꢀ

All

0.5

0.3%ꢀorꢀ±0.25ꢀpFꢀ 10%ꢀofꢀInitialꢀLimit

C1003_C0G • 3/30/2016

4

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Table 1A – Capacitance Range/Selection Waterfall (0201 – 1206 Case Sizes)

Case Size/

Series

C0201C

C0402C

C0603C

C0805C

C1206C

Cap

Code

Voltage Code

8

4

3

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

Cap

Rated Voltage (VDC)

Capacitance

Tolerance

Product Availability and Chip Thickness Codes

See Table 2 for Chip Thickness Dimensions

0.50ꢀ&ꢀ0.75ꢀpF

0.75ꢀpF

1.0ꢀ–ꢀ9.1ꢀpF*

1.1 pF

1.2 pF

1.3 pF

1.5 pF

1.6 pF

1.8 pF

2.0 pF

2.2 pF

2.4 pF

2.7ꢀpF

3.0 pF

3.3 pF

3.6 pF

3.9 pF

4.3 pF

4.7ꢀpF

5.1 pF

5.6 pF

6.2 pF

6.8 pF

7.5ꢀpF

8.2 pF

9.1 pF

10 pF

508ꢀ&ꢀ758

758

109ꢀ–ꢀ919*

119

B

C D

BB BB BB BB

CF CF CF CF CF CF CF DN DN DN DN DN DN DN

B

CF CF CF CF CF CF CF DN DN DN DN DN DN DN EB EB EB EB EB EB EB

CF CF CF CF CF CF CF DM DM DM DM DN DN DN EB EB EB EB EB EB EB

CF CF CF CF CF CF CF DN DN DN DN DN DN DN EB EB EB EB EB EB EB

129

139

159

169

189

209

229

249

279

309

339

369

399

439

479

519

569

629

689

759

829

919

100

110

120

130

150

160

180

200

220

240

270

300

330

360

390

430

470

F

G

J

K M AB¹ AB¹ AB¹ BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB BB BB BB CF CF CF CF CF CF CF DN DN DN DN DN DN DN EB EB EB EB EB EB EB

11 pF

12 pF

13 pF

15 pF

16 pF

18 pF

20 pF

22 pF

24 pF

27ꢀpF

30 pF

33 pF

36 pF

39 pF

43 pF

47ꢀpF

51 pF

56 pF

62 pF

68 pF

75ꢀpF

82 pF

91 pF

100 pF

510

560

620

680

750

820

910

101

Rated Voltage (VDC)

Voltage Code

Cap

Code

8

4

3

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

Cap

Case Size/Series C0201C

C0402C

C0603C

C0805C

C1206C

*Capacitance range Includes E24 decade values only. (i.e., 10, 11, 12, 13, 15, 16, 18, 20, 22, 24, 27, 30, 33, 36, 39, 43, 47, 51, 56, 62, 68, 75, 82 and 91).

xx¹ Available only in D, J, K,M tolerance

xx² Available only in J, K, M tolerance.

These products are protected under US Patents 7,172,985 & 7,670,981, other patents pending, and any foreign counterparts.

C1003_C0G • 3/30/2016

5

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Table 1A – Capacitance Range/Selection Waterfall (0201 – 1206 Case Sizes) cont'd

Case Size/

Series

C0201C

C0402C

C0603C

C0805C

C1206C

Cap

Code

Voltage Code

8

4

3

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

Cap

Rated Voltage (VDC)

Capacitance

Tolerance

Product Availability and Chip Thickness Codes

See Table 2 for Chip Thickness Dimensions

110ꢀ–ꢀ180ꢀpF*

200ꢀ–ꢀ270ꢀpF*

300 pF

330 pF

360 pF

390 pF

430 pF

470ꢀpF

510 pF

560 pF

620 pF

680 pF

750ꢀpF

820 pF

910 pF

1,000 pF

1,100 pF

1,200 pF

1,300 pF

1,500 pF

1,600 pF

1,800 pF

2,000 pF

2,200 pF

2,400 pF

2,700ꢀpF

3,000 pF

3,300 pF

3,600 pF

3,900 pF

4,300 pF

4,700ꢀpF

5,100 pF

5,600 pF

6,200 pF

6,800 pF

7,500ꢀpF

8,200 pF

9,100 pF

10,000 pF

12,000 pF

15,000 pF

18,000 pF

22,000 pF

27,000ꢀpF

33,000 pF

39,000 pF

47,000ꢀpF

56,000 pF

68,000 pF

82,000 pF

0.10 µF

111ꢀ–ꢀ181*

201ꢀ–ꢀ271*

301

331

361

391

431

471

F

G

J

K M

BB BB BB BB BB BB BB CF CF CF CF CF CF CF DN DN DN DN DN DN DN EB EB EB EB EB EB EB

BB BB BB BB BB BD BD CF CF CF CF CF CF CF DN DN DN DN DN DN DN EB EB EB EB EB EB EB

BB BB BB BB BB

BB BB BB BB

BB BB BB

CF CF CF CF CF CF CF DN DN DN DN DN DN DN EB EB EB EB EB EB EB

CF CF CF CF CF CF CF DN DN DN DN DN DP DP EB EB EB EB EB EB EB

CF CF CF CF CF CF CF DN DN DN DN DN DN DN EB EB EB EB EB EB EB

CF CF CF CF CF CF CF DN DN DN DN DP DP DP EB EB EB EB EB EB EB

CF CF CF CF CF CH CH DN DN DN DN DN DN DN EB EB EB EB EB EB EB

CF CF CF CF CF CH CH DP DP DP DP DP DN DN EB EB EB EB EC EC EC

CF CF CF CF CF CH CH DP DP DP DP DP DN DN EB EB EB EB ED EC EC

CF CF CF CF CF CH CH DP DP DP DP DP DN DN EB EB EB EB ED ED ED

CF CF CF CF CF CH CH DN DN DN DN DN DN DN EB EB EB EB ED ED ED

CF CF CF CF CF CH CH DN DN DN DN DN DN DN EB EB EB EB EE EE EE

511

561

621

681

751

821

911

102

112

122

132

152

162

182

202

222

242

272

302

332

362

392

432

472

512

562

622

682

752

822

912

103

123

153

183

223

273

333

393

473

563

683

823

104

CF CF CF CF CF

CF CF CF CF

CF CF CF

DN DN DN DN DN DN DN EB EB EB EB EC EC EC

DP DP DP DP DN DN DN EC EC EC EC EC EB EB

DP DP DP DP DN DN DN EC EC EC EC EE EB EB

DP DP DP DP DN DP DP EC EC EC EC EE EB EB

DE DE DE DE DN DP DP EC EC EC EC EF EB EB

DE DE DE DE DN DP DP EC EC EC EC EC EB EB

DE DE DE DE DN DP DP ED ED ED ED ED EB EB

DN DN DN DN DN DP DP ED ED ED ED ED EB EB

DN DN DN DN DN DG DG EB EB EB EB EB EB EB

DN DN DN DN DN DG DG EC EC EC EC EB EC EC

CF CF CF

DN DN DN DN DN

DN DN DN DN DP

DN DN DN DN DE

DN DN DN DP DG

DN DN DN DP

DP DP DP DF

DF DF DF

EC EC EC EC EB EC EC

ED ED ED ED EB EC EC

EB EB EB EB EB ED ED

EB EB EB EB EB EF EF

EB EB EB EB EB EH EH

EB EB EB EB EC EH EH

EB EB EB EB EE

DG DG DG

EB EB EB EB EE

DG DG DG

EC EC EC EE EH

DG DG DG

EC EC EC EE EH

ED ED ED EF

EF EF EF EH

EH EH EH EH

EH EH EH

Rated Voltage (VDC)

Voltage Code

Cap

Code

8

4

3

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

Cap

Case Size/Series C0201C

C0402C

C0603C

C0805C

C1206C

*Capacitance range Includes E24 decade values only. (i.e., 10, 11, 12, 13, 15, 16, 18, 20, 22, 24, 27, 30, 33, 36, 39, 43, 47, 51, 56, 62, 68, 75, 82 and 91).

xx¹ Available only in D, J, K,M tolerance

xx² Available only in J, K, M tolerance.

These products are protected under US Patents 7,172,985 & 7,670,981, other patents pending, and any foreign counterparts.

C1003_C0G • 3/30/2016

6

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Table 1B – Capacitance Range/Selection Waterfall (1210 – 2225 Case Sizes)

Case Size/

Series

C1210C

C1808C

C1812C

C1825C

C2220C

C2225C

Cap

Code

Voltage Code

8

4

3

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

Cap

Rated Voltage (VDC)

Capacitance

Tolerance

B C D

Product Availability and Chip Thickness Codes

See Table 2 for Chip Thickness Dimensions

1.0ꢀ–ꢀ9.1ꢀpF*

10ꢀ–ꢀ91ꢀpF*

100ꢀ–ꢀ300ꢀpF*

330ꢀ–ꢀ430ꢀpF*

470ꢀ–ꢀ910ꢀpF*

1,000 pF

1,100 pF

109ꢀ–ꢀ919*

100ꢀ–ꢀ910*

101ꢀ–ꢀ301*

331ꢀ–ꢀ431*

471ꢀ–ꢀ911*

102

112

122

132

152

162

182

202

222

242

272

302

332

362

392

432

472

512

562

622

682

752

822

912

103

123

153

183

223

FB FB FB FB FB FB FB

F G J K M FB FB FB FB FB FB FB

F G J K M FB FB FB FB FB FB FB LF LF LF LF

F G J K M FB FB FB FB FB FB FB LF LF LF LF GB GB GB GB

F G J K M FB FB FB FB FB FC FC LF LF LF LF GB GB GB GB

F G J K M FB FB FB FB FB FE FE LF LF LF LF GB GB GB GB

F G J K M FB FB FB FB FC FE FE LF LF LF LF GB GB GB GB

F G J K M FB FB FB FB FC FG FG LF LF LF LF GB GB GB GB

F G J K M FB FB FB FB FC FC FC LF LF LF LF

1,200 pF

1,300 pF

1,500 pF

1,600 pF

1,800 pF

2,000 pF

2,200 pF

2,400 pF

2,700ꢀpF

3,000 pF

3,300 pF

3,600 pF

3,900 pF

4,300 pF

4,700ꢀpF

5,100 pF

5,600 pF

6,200 pF

6,800 pF

7,500ꢀpF

8,200 pF

9,100 pF

10,000 pF

12,000 pF

15,000 pF

18,000 pF

22,000 pF

27,000ꢀpF

33,000 pF

39,000 pF

47,000ꢀpF

56,000 pF

68,000 pF

82,000 pF

0.10 µF

F G J K M FB FB FB FB FC FC FC LF LF LF LF GB GB GB GB

F G J K M FB FB FB FB FC FF FF LF LF

F G J K M FB FB FB FB FF FF FF LF LF

F G J K M FF FF FF FF FG FG FG LF LF

F G J K M FB FB FB FB FG FG FG

F G J K M FB FB FB FB FG FB FB

F G J K M FC FC FC FC FC FB FB

F G J K M FE FE FE FE FE FB FB

F G J K M FF FF FF FF FF FB FB

F G J K M FG FG FG FG FB FB FB

F G J K M FG FG FG FG FB FC FC

F G J K M FB FB FB FB FB FC FC

F G J K M FB FB FB FB FB FF FF

F G J K M FB FB FB FB FB FG FG

F G J K M FB FB FB FB FB FH FH

F G J K M FB FB FB FB FE FH FH

F G J K M FB FB FB FB FE FJ FJ

F G J K M FB FB FB FB FF

GB GB GB GB

GB GB GB GB HB HB HB HB

GB GB GD GD HB HB HB HB

GB GB GH GH HB HB HB HB

KE KE KE KE

KE KE

GB GB GJ GJ HB HB HB HB JE JE JB

GB GH GB GB HB HB HB HB JE JE JB

GB GH GB GB HB HB HE HE JE JE JB

GB GG GB GB HB HB HE HE JE JE JB

GB GB GB GB HB HB

GB GB GB GB HB HE

GB GB GB GB HB HG

GB GB GB GB

GB GB GD GD

GB GB GK GK

GB GB GM GM

GB GD GM GM

GB GH

JE JE JB

JE JB JB

JB JB JB

JB JB JD

JB JB JG

JB JD JG

JB JD JL

JB JF

KE KE

KE

273

333

393

473

563

683

823

104

124

154

184

224

F G J K M FB FB FB FC FG

F G J K M FC FC FC FF FH

F G J K M FE FE FE FG FM

F G J K M FG FG FG FH

F G J K M FH FH FH FM

F G J K M FJ FJ FJ

F G J K M FK FK FK

F G J K M

0.12 µF

0.15 µF

0.18 µF

0.22 µF

GD GN

GH

GK

0.27ꢀµF

274

0.33 µF

334

F G J K M

JD JG

0.39 µF

394

F G J K M

JG

0.47ꢀµF

474

F G J K M

JG

Rated Voltage (VDC)

Cap

Code

Voltage Code

8

4

3

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

Cap

Case Size/

Series

C1210C

C1808C

C1812C

C1825C

C2220C

C2225C

*Capacitance range Includes E24 decade values only. (i.e., 10, 11, 12, 13, 15, 16, 18, 20, 22, 24, 27, 30, 33, 36, 39, 43, 47, 51, 56, 62, 68, 75, 82 and 91).

These products are protected under US Patents 7,172,985 & 7,670,981, other patents pending, and any foreign counterparts.

C1003_C0G • 3/30/2016

7

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Table 2A – Chip Thickness/Tape & Reel Packaging Quantities

Paper Quantity¹

7" Reel 13" Reel

Plastic Quantity

7" Reel 13" Reel

Thickness Case Thickness ±

Code

Size¹

Range (mm)

AB

BB

BD

CF

CH

DM

DN

DP

DE

DF

DG

EB

EC

ED

EE

EF

EH

FB

FC

FE

FF

FG

FH

FM

FJ

FK

NC

LF

GB

GD

GH

GG

GK

GJ

GN

GM

HB

HE

HG

JB

0201

0402

0603

0805

1206

1210

1706

1808

1812

1825

2220

2225

0.30ꢀ±ꢀ0.03

0.50ꢀ±ꢀ0.05

0.55ꢀ±ꢀ0.05

0.80ꢀ±ꢀ0.07

0.85ꢀ±ꢀ0.07

0.70ꢀ±ꢀ0.20

0.78ꢀ±ꢀ0.10

0.90ꢀ±ꢀ0.10

1.00ꢀ±ꢀ0.10

1.10ꢀ±ꢀ0.10

1.25ꢀ±ꢀ0.15

0.78ꢀ±ꢀ0.10

0.90ꢀ±ꢀ0.10

1.00ꢀ±ꢀ0.10

1.10ꢀ±ꢀ0.10

1.20ꢀ±ꢀ0.15

1.60ꢀ±ꢀ0.20

0.78ꢀ±ꢀ0.10

0.90ꢀ±ꢀ0.10

1.00ꢀ±ꢀ0.10

1.10ꢀ±ꢀ0.10

1.25ꢀ±ꢀ0.15

1.55ꢀ±ꢀ0.15

1.70ꢀ±ꢀ0.20

1.85ꢀ±ꢀ0.20

2.10ꢀ±ꢀ0.20

1.00ꢀ±ꢀ0.15

1.00ꢀ±ꢀ0.10

1.25ꢀ±ꢀ0.15

1.40ꢀ±ꢀ0.15

1.55ꢀ±ꢀ0.10

1.60ꢀ±ꢀ0.20

1.70ꢀ±ꢀ0.15

1.70ꢀ±ꢀ0.20

2.00ꢀ±ꢀ0.20

1.10ꢀ±ꢀ0.15

1.40ꢀ±ꢀ0.15

1.60ꢀ±ꢀ0.20

1.00ꢀ±ꢀ0.15

1.30ꢀ±ꢀ0.15

1.40ꢀ±ꢀ0.15

1.50ꢀ±ꢀ0.15

1.70ꢀ±ꢀ0.15

2.00ꢀ±ꢀ0.20

1.40ꢀ±ꢀ0.15

15,000

10,000

0

50,000

10,000

4,000

50,000

15,000

0

4,000

10,000

15,000

0

4,000

15,000

0

2,500

4,000

2,500

2,000

4,000

2,500

2,000

4,000

2,500

1,000

500

10,000

8,000

10,000

8,000

10,000

4,000

2,000

4,000

2,000

4,000

0

10,000

0

1,000

500

JD

JE

JF

JG

JL

KE

0

1,000

7" Reel

13" Reel

7" Reel

13" Reel

Thickness

Code

Case

Size¹

Thickness ±

Range (mm)

Paper Quantity¹

Plastic Quantity

Package quantity based on ﬁnished chip thickness speciﬁcations.

¹If ordering using the 2 mm Tape and Reel pitch option, the packaging quantity outlined in the table above will be doubled. This option is limited to EIA 0603 (1608 metric)

case size devices. For more information regarding 2 mm pitch option see “Tape & Reel Packaging Information”.

C1003_C0G • 3/30/2016

8

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Table 2B – Bulk Packaging Quantities

Loose Packaging

Packaging Type

BulkꢀBagꢀ(default)

PackagingꢀC-Spec¹

N/A²

Case Size

Packaging Quantities (pieces/unit packaging)

EIA (in)

Metric (mm)

Minimum

Maximum

0402

0603

0805

1206

1210

1808

1812

1825

2220

2225

1005

1608

2012

3216

3225

4520

4532

4564

5650

5664

50,000

1

20,000

¹The "Packaging C-Spec" is a 4 to 8 digit code which identiﬁes the packaging type and/or product grade. When ordering, the proper code must be included in the 15th

through 22nd character positions of the ordering code. See "Ordering Information" section of this document for further details. Commercial Grade product ordered without

a packaging C-Spec will default to our standard "Bulk Bag" packaging. Contact KEMET if you require a bulk bag packaging option for Automotive Grade products.

²A packaging C-Spec (see note 1 above) is not required for "Bulk Bag" packaging (excluding Anti-Static Bulk Bag and Automotive Grade products). The 15th through

22nd character positions of the ordering code should be left blank. All product ordered without a packaging C-Spec will default to out standard "Bulk Bag" packaging.

C1003_C0G • 3/30/2016

9

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Table 3 – Chip Capacitor Land Pattern Design Recommendations per IPC–7351

Density Level A:

Maximum (Most)

Land Protrusion (mm)

Density Level B:

Median (Nominal)

Land Protrusion (mm)

Density Level C:

Minimum (Least)

Land Protrusion (mm)

EIA

Size

Code

Metric

Size

Code

C

Y

X

V1

V2

C

Y

X

V1

V2

C

Y

X

V1

V2

0201

0402

0603

0805

1206

1210

1210¹

1808

1812

1825

2220

2225

0603

1005

1608

2012

3216

3225

4520

4532

4564

5650

5664

0.38

0.56

0.52

1.80

1.00

0.33

0.46

0.42

1.50

0.80

0.28

0.36

0.32

1.20

0.60

0.50

0.90

1.00

1.60

1.50

2.30

2.15

2.75

2.70

0.72

1.15

1.35

1.60

1.75

1.60

1.70

0.72

1.10

1.55

1.90

2.80

2.90

2.30

3.60

6.90

5.50

6.90

2.20

4.00

4.40

5.60

5.65

5.60

7.40

6.90

8.20

8.10

1.20

2.10

2.60

2.90

3.80

3.90

3.30

4.60

7.90

6.50

7.90

0.45

0.80

0.90

1.50

1.40

2.20

2.05

2.65

2.60

0.62

0.95

1.15

1.40

1.55

1.40

1.50

0.62

1.00

1.45

1.80

2.70

2.80

2.20

3.50

6.80

5.40

6.80

1.90

3.10

3.50

4.70

6.50

6.00

7.30

7.20

1.00

1.50

2.00

2.30

3.20

3.30

2.70

4.00

7.30

5.90

7.30

0.40

0.60

0.75

1.40

1.30

2.10

1.95

2.55

2.50

0.52

0.75

0.95

1.20

1.35

1.20

1.30

0.52

0.90

1.35

1.70

2.60

2.70

2.10

3.40

6.70

5.30

6.70

1.60

2.40

2.80

4.00

5.80

5.30

6.60

6.50

0.80

1.20

1.70

2.00

2.90

3.00

2.40

3.70

7.00

5.60

7.00

¹Only for capacitance values ≥ 22 µF

Density Level A: For low-density product applications. Recommended for wave solder applications and provides a wider process window for reﬂow solder

processes. KEMET only recommends wave soldering of EIA 0603, 0805 and 1206 case sizes.

Density Level B: For products with a moderate level of component density. Provides a robust solder attachment condition for reﬂow solder processes.

Density Level C: For high component density product applications. Before adapting the minimum land pattern variations the user should perform qualiﬁcation

testing based on the conditions outlined in IPC Standard 7351 (IPC–7351).

Image below based on Density Level B for an EIA 1210 case size.

V1

Y

V2

X

C

Grid Placement Courtyard

C1003_C0G • 3/30/2016 10

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Soldering Process

Recommended Soldering Technique:

ꢀ •ꢀSolderꢀwaveꢀorꢀsolderꢀreﬂowꢀforꢀEIAꢀcaseꢀsizesꢀ0603,ꢀ0805ꢀandꢀ1206

ꢀ •ꢀAllꢀotherꢀEIAꢀcaseꢀsizesꢀareꢀlimitedꢀtoꢀsolderꢀreﬂowꢀonly

Recommended Reﬂow Soldering Proﬁle:

KEMET’sꢀfamiliesꢀofꢀsurfaceꢀmountꢀmultilayerꢀceramicꢀcapacitorsꢀ(SMDꢀMLCCs)ꢀareꢀcompatibleꢀwithꢀwaveꢀ(singleꢀorꢀdual),ꢀconvection,ꢀ

IRꢀorꢀvaporꢀphaseꢀreﬂowꢀtechniques.ꢀPreheatingꢀofꢀtheseꢀcomponentsꢀisꢀrecommendedꢀtoꢀavoidꢀextremeꢀthermalꢀstress.ꢀKEMET’sꢀ

recommendedꢀproﬁleꢀconditionsꢀforꢀconvectionꢀandꢀIRꢀreﬂowꢀreﬂectꢀtheꢀproﬁleꢀconditionsꢀofꢀtheꢀIPC/J-STD-020ꢀstandardꢀforꢀmoistureꢀ

sensitivityꢀtesting.ꢀTheseꢀdevicesꢀcanꢀsafelyꢀwithstandꢀaꢀmaximumꢀofꢀthreeꢀreﬂowꢀpassesꢀatꢀtheseꢀconditions.

T_P

T_L

Termination Finish

t_P

Maximum Ramp Up Rate = 3°C/sec

Maximum Ramp Down Rate = 6°C/sec

Proﬁle Feature

SnPb

100%ꢀMatteꢀSn

t_L

Preheat/Soak

T_smax

T_smin

TemperatureꢀMinimumꢀ(T_Smin

TemperatureꢀMaximumꢀ(T_Smax

Time (t_S)ꢀfromꢀT_Sminto T_Smax

)

100°C

150°C

200°C

)

t_S

60ꢀ–ꢀ120ꢀseconds

Ramp-Up Rate (T_Lto T_P)

LiquidousꢀTemperatureꢀ(T_L)

TimeꢀAboveꢀLiquidousꢀ(t_L)

PeakꢀTemperatureꢀ(T_P)

3°C/secondꢀmaximum 3°C/secondꢀmaximum

25

183°C

60ꢀ–ꢀ150ꢀseconds

235°C

217°C

60ꢀ–ꢀ150ꢀseconds

260°C

25° C to Peak

Time

TimeꢀWithinꢀ5°CꢀofꢀMaximumꢀ

20ꢀsecondsꢀmaximum 30ꢀsecondsꢀmaximum

PeakꢀTemperatureꢀ(t_P)

Ramp-Down Rate (T_Pto T_L) 6°C/secondꢀmaximum 6°C/secondꢀmaximum

Timeꢀ25°CꢀtoꢀPeakꢀ

6ꢀminutesꢀmaximum

8ꢀminutesꢀmaximum

Temperature

Note 1: All temperatures refer to the center of the package, measured on the

capacitor body surface that is facing up during assembly reﬂow.

C1003_C0G • 3/30/2016 11

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Table 4 – Performance & Reliability: Test Methods and Conditions

Stress

Reference

Test or Inspection Method

TerminalꢀStrength

JIS–C–6429

Appendixꢀ1,ꢀNote:ꢀForceꢀofꢀ1.8ꢀkgꢀforꢀ60ꢀseconds.

Appendixꢀ2,ꢀNote:ꢀStandardꢀterminationꢀsystemꢀ–ꢀ2.0ꢀmmꢀ(minimum)ꢀforꢀallꢀexceptꢀ3ꢀmmꢀforꢀC0G.ꢀ

Flexibleꢀterminationꢀsystemꢀ–ꢀ3.0ꢀmmꢀ(minimum).

Board Flex

JIS–C–6429

Magniﬁcationꢀ50ꢀX.ꢀConditions:

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀa)ꢀMethodꢀB,ꢀ4ꢀhoursꢀ@ꢀ155°C,ꢀdryꢀheatꢀ@ꢀ235°C

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀb)ꢀMethodꢀBꢀ@ꢀ215°Cꢀcategoryꢀ3

Solderability

J–STD–002

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀc)ꢀMethodꢀD,ꢀcategoryꢀ3ꢀ@ꢀ260°C

TemperatureꢀCycling

BiasedꢀHumidity

JESD22ꢀMethodꢀJA–104

MIL–STD–202ꢀMethodꢀ103

1,000ꢀCyclesꢀ(−55°Cꢀtoꢀ+125°C).ꢀMeasurementꢀatꢀ24ꢀhoursꢀ+/-ꢀ4ꢀhoursꢀafterꢀtestꢀconclusion.

LoadꢀHumidity:ꢀ1,000ꢀhoursꢀ85°C/85%ꢀRHꢀandꢀratedꢀvoltage.ꢀAddꢀ100ꢀKꢀohmꢀresistor.ꢀMeasurementꢀ

atꢀ24ꢀhoursꢀ+/-ꢀ4ꢀhoursꢀafterꢀtestꢀconclusion.

LowꢀVoltꢀHumidity:ꢀ1,000ꢀhoursꢀ85°C/85%ꢀRHꢀandꢀ1.5ꢀV.ꢀAddꢀ100ꢀKꢀohmꢀresistor.ꢀ

Measurementꢀatꢀ24ꢀhoursꢀ+/-ꢀ4ꢀhoursꢀafterꢀtestꢀconclusion.

tꢀ=ꢀ24ꢀhours/cycle.ꢀStepsꢀ7aꢀandꢀ7bꢀnotꢀrequired.ꢀ

MoistureꢀResistance

ThermalꢀShock

MIL–STD–202ꢀMethodꢀ106

MIL–STD–202ꢀMethodꢀ107

Measurementꢀatꢀ24ꢀhoursꢀ+/-ꢀ4ꢀhoursꢀafterꢀtestꢀconclusion.

−55°C/+125°C.ꢀNote:ꢀNumberꢀofꢀcyclesꢀrequiredꢀ–ꢀ300,ꢀmaximumꢀtransferꢀtimeꢀ–ꢀ20ꢀseconds,ꢀdwellꢀ

timeꢀ–ꢀ15ꢀminutes.ꢀAirꢀ–ꢀAir.

MIL–STD–202ꢀMethodꢀ108

/EIA–198

HighꢀTemperatureꢀLife

StorageꢀLife

1,000ꢀhoursꢀatꢀ125°Cꢀ(85°CꢀforꢀX5R,ꢀZ5UꢀandꢀY5V)ꢀwithꢀ2ꢀXꢀratedꢀvoltageꢀapplied.

MIL–STD–202ꢀMethodꢀ108 150°C,ꢀ0ꢀVDCꢀforꢀ1,000ꢀhours.

5ꢀg'sꢀforꢀ20ꢀmin.,ꢀ12ꢀcyclesꢀeachꢀofꢀ3ꢀorientations.ꢀNote:ꢀUseꢀ8"ꢀXꢀ5"ꢀPCBꢀ0.031"ꢀthickꢀ7ꢀsecureꢀ

MIL–STD–202ꢀMethodꢀ204 pointsꢀonꢀoneꢀlongꢀsideꢀandꢀ2ꢀsecureꢀpointsꢀatꢀcornersꢀofꢀoppositeꢀsides.ꢀPartsꢀmountedꢀwithinꢀ2"ꢀ

fromꢀanyꢀsecureꢀpoint.ꢀTestꢀfromꢀ10ꢀ–ꢀ2,000ꢀHz

Vibration

MechanicalꢀShock

MIL–STD–202ꢀMethodꢀ213 Figureꢀ1ꢀofꢀMethodꢀ213,ꢀConditionꢀF.

Resistance to Solvents MIL–STD–202ꢀMethodꢀ215 Addꢀaqueousꢀwashꢀchemical,ꢀOKEMꢀCleanꢀorꢀequivalent.

Storage and Handling

Ceramicꢀchipꢀcapacitorsꢀshouldꢀbeꢀstoredꢀinꢀnormalꢀworkingꢀenvironments.ꢀWhileꢀtheꢀchipsꢀthemselvesꢀareꢀquiteꢀrobustꢀinꢀotherꢀ

environments,ꢀsolderabilityꢀwillꢀbeꢀdegradedꢀbyꢀexposureꢀtoꢀhighꢀtemperatures,ꢀhighꢀhumidity,ꢀcorrosiveꢀatmospheres,ꢀandꢀlongꢀtermꢀ

storage.ꢀInꢀaddition,ꢀpackagingꢀmaterialsꢀwillꢀbeꢀdegradedꢀbyꢀhighꢀtemperature–ꢀreelsꢀmayꢀsoftenꢀorꢀwarpꢀandꢀtapeꢀpeelꢀforceꢀmayꢀ

increase.ꢀKEMETꢀrecommendsꢀthatꢀmaximumꢀstorageꢀtemperatureꢀnotꢀexceedꢀ40ºCꢀandꢀmaximumꢀstorageꢀhumidityꢀnotꢀexceedꢀ70%ꢀ

relativeꢀhumidity.ꢀTemperatureꢀﬂuctuationsꢀshouldꢀbeꢀminimizedꢀtoꢀavoidꢀcondensationꢀonꢀtheꢀpartsꢀandꢀatmospheresꢀshouldꢀbeꢀfreeꢀofꢀ

chlorineꢀandꢀsulfurꢀbearingꢀcompounds.ꢀForꢀoptimizedꢀsolderabilityꢀchipꢀstockꢀshouldꢀbeꢀusedꢀpromptly,ꢀpreferablyꢀwithinꢀ1.5ꢀyearsꢀofꢀ

receipt.

C1003_C0G • 3/30/2016 12

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Construction

Detailed Cross Section

Dielectric Material

(CaZrO₃)

Barrier Layer

(Ni)

Dielectric Material

(CaZrO₃)

End Termination/

External Electrode

(Cu)

Termination Finish

(100% Matte Sn)

Inner Electrodes

(Ni)

End Termination/

External Electrode

(Cu)

Barrier Layer

(Ni)

Termination Finish

(100% Matte Sn)

Inner Electrodes

(Ni)

Capacitor Marking (Optional):

Laserꢀmarkingꢀoptionꢀisꢀnotꢀavailableꢀon:

•ꢀ C0G,ꢀUltraꢀStableꢀX8RꢀandꢀY5Vꢀdielectricꢀdevicesꢀ

• EIA 0402 case size devices

•ꢀ EIAꢀ0603ꢀcaseꢀsizeꢀdevicesꢀwithꢀFlexibleꢀTerminationꢀoption.

•ꢀ KPSꢀCommercialꢀandꢀAutomotiveꢀgradeꢀstackedꢀdevices.

Theseꢀcapacitorsꢀareꢀsuppliedꢀunmarkedꢀonly.

C1003_C0G • 3/30/2016 13

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Tape & Reel Packaging Information

KEMETꢀoffersꢀmultilayerꢀceramicꢀchipꢀcapacitorsꢀpackagedꢀinꢀ8,ꢀ12ꢀandꢀ16ꢀmmꢀtapeꢀonꢀ7"ꢀandꢀ13"ꢀreelsꢀinꢀaccordanceꢀwithꢀEIAꢀ

Standardꢀ481.ꢀThisꢀpackagingꢀsystemꢀisꢀcompatibleꢀwithꢀallꢀtape-fedꢀautomaticꢀpickꢀandꢀplaceꢀsystems.ꢀSeeꢀTableꢀ2ꢀforꢀdetailsꢀonꢀ

reelingꢀquantitiesꢀforꢀcommercialꢀchips.

Bar Code Label

Anti-Static Reel

®

Embossed Plastic* or

Punched Paper Carrier.

Chip and KPS Orientation in Pocket

(except 1825 Commercial, and 1825 and 2225 Military)

KEMET

Sprocket Holes

Embossment or Punched Cavity

8 mm, 12 mm

or 16 mm Carrier Tape

Anti-Static Cover Tape

(.10 mm (.004") Maximum Thickness)

178 mm (7.00")

or

330 mm (13.00")

*EIA 01005, 0201, 0402 and 0603 case sizes available on punched paper carrier only.

Table 5 – Carrier Tape Conﬁguration, Embossed Plastic & Punched Paper (mm)

New 2 mm Pitch Reel Options*

Embossed Plastic Punched Paper

Tape

Packaging

Ordering Code

(C-Spec)

C-3190

7"ꢀReel

13" Reel

7"ꢀReel

13" Reel

EIA Case Size Size

(W)*

Packaging Type/Options

Pitchꢀ(P₁)*

01005ꢀ–ꢀ0402

0603

8

2

2/4

4

2

2/4

4

Automotiveꢀgradeꢀ7"ꢀreelꢀunmarked

Automotiveꢀgradeꢀ13"ꢀreelꢀunmarked

Commercialꢀgradeꢀ7"ꢀreelꢀunmarked

Commercialꢀgradeꢀ13"ꢀreelꢀunmarked

C-3191

C-7081

0805

8

4

C-7082

1206ꢀ–ꢀ1210

1805ꢀ–ꢀ1808

≥ꢀ1812

8

4

* 2 mm pitch reel only available for 0603 EIA case size.

2 mm pitch reel for 0805 EIA case size under development.

12

16

8

4

8

Beneﬁts of Changing from 4 mm to 2 mm Pitching Spacing

• Lower placement costs

•ꢀ Doubleꢀtheꢀpartsꢀonꢀeachꢀreelꢀresultsꢀinꢀfewerꢀreelꢀ

changesꢀandꢀincreasedꢀef ꢀciency

•ꢀ Fewerꢀreelsꢀresultꢀinꢀlowerꢀpackaging,ꢀshippingꢀandꢀ

storageꢀcosts,ꢀreducingꢀwaste

KPS 1210

8

KPS 1812 & 2220

Array 0508 & 0612

12

4

12

4

*Refer to Figures 1 & 2 for W and P₁carrier tape reference locations.

*Refer to Tables 6 & 7 for tolerance speciﬁcations.

C1003_C0G • 3/30/2016 14

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Figure 1 – Embossed (Plastic) Carrier Tape Dimensions

T

P2

[10 pitches cumulative

tolerance on tape ± 0.2 mm]

2

E

1

Po

ØDo

Ao

F

Ko

W

E

2

B

1

Bo

S

1

P

1

T

1

Embossment

For cavity size,

see Note 1 Table 4

Center Lines of Cavity

ØD

1

Cover Tape

is for tape feeder reference only,

including draft concentric about B

B

1

o

.

User Direction of Unreeling

Table 6 – Embossed (Plastic) Carrier Tape Dimensions

Metricꢀwillꢀgovern

Constant Dimensions — Millimeters (Inches)

D₁ꢀMinimum

Note 1

1.0

(0.039)

RꢀReference S₁ꢀMinimum

T

T₁

Tape Size

8 mm

D₀

E₁

P₀

P₂

Note 2

Note 3

Maximum

25.0

(0.984)

1.5ꢀ+0.10/-0.0ꢀ

(0.059ꢀ+0.004/-0.0)

1.75ꢀ±0.10ꢀ

4.0ꢀ±0.10ꢀ

2.0ꢀ±0.05

0.600

(0.024)

0.600

(0.024)

0.100

(0.004)

12 mm

16 mm

(0.069ꢀ±0.004) (0.157ꢀ±0.004) (0.079ꢀ±0.002)

1.5

(0.059)

30

(1.181)

Variable Dimensions — Millimeters (Inches)

B₁ꢀMaximum

Note 4

4.35

(0.171)

E₂

T₂

W

Tape Size

8 mm

Pitchꢀ

F

P₁

A₀,B₀& K₀

Minimum

6.25

(0.246)

Maximum

2.5

(0.098)

Maximum

8.3

(0.327)

3.5ꢀ±0.05ꢀ

(0.138ꢀ±0.002) (0.157ꢀ±0.004)

4.0ꢀ±0.10

Singleꢀ(4ꢀmm)

Singleꢀ(4ꢀmm)ꢀ&ꢀ

Doubleꢀ(8ꢀmm)

8.2

10.25

5.5ꢀ±0.05ꢀ

8.0ꢀ±0.10

4.6

12.3

12 mm

16 mm

Note 5

(0.323)

(0.404)

(0.217ꢀ±0.002) (0.315ꢀ±0.004)

(0.181)

(0.484)

12.1

(0.476)

14.25

(0.561)

7.5ꢀ±0.05 12.0ꢀ±0.10

(0.138ꢀ±0.002)ꢀ (0.157ꢀ±0.004)ꢀ

4.6

(0.181)

16.3

(0.642)

Triple (12 mm)

1. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment. Dimensions of embossment location and

hole location shall be applied independent of each other.

2. The tape with or without components shall pass around R without damage (see Figure 6).

3. If S₁< 1.0 mm, there may not be enough area for cover tape to be properly applied (see EIA Standard 481 paragraph 4.3 section b).

4. B₁dimension is a reference dimension for tape feeder clearance only.

5. The cavity deﬁned by A₀, B₀and K₀shall surround the component with sufﬁcient clearance that:

(a) the component does not protrude above the top surface of the carrier tape.

(b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.

(c) rotation of the component is limited to 20° maximum for 8 and 12 mm tapes and 10° maximum for 16 mm tapes (see Figure 3).

(d) lateral movement of the component is restricted to 0.5 mm maximum for 8 and 12 mm wide tape and to 1.0 mm maximum for 16 mm tape (see Figure 4).

(e) for KPS Series product, A₀and B₀are measured on a plane 0.3 mm above the bottom of the pocket.

(f) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.

C1003_C0G • 3/30/2016 15

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Figure 2 – Punched (Paper) Carrier Tape Dimensions

T

P2

[10 pitches cumulative

tolerance on tape ± 0.2 mm]

E

1

Po

ØDo

0

A

F

W

2

E

0

B

Bottom Cover Tape

P

1

G

Cavity Size,

See

1

T

1

T

Top Cover Tape

Center Lines of Cavity

Note 1, Table 7

Bottom Cover Tape

User Direction of Unreeling

Table 7 – Punched (Paper) Carrier Tape Dimensions

Metricꢀwillꢀgovern

Constant Dimensions — Millimeters (Inches)

RꢀReference

Tape Size

8 mm

D₀

E₁

P₀

P₂

T₁Maximum

GꢀMinimum

Note 2

0.10

1.5ꢀ+0.10ꢀ-0.0ꢀ

(0.059ꢀ+0.004ꢀ-0.0)

1.75ꢀ±0.10ꢀ

(0.069ꢀ±0.004)

4.0ꢀ±0.10ꢀ

(0.157ꢀ±0.004)

2.0ꢀ±0.05ꢀ

(0.079ꢀ±0.002)

0.75ꢀ

(0.030)

25

(0.984)

(0.004)

Maximum

Variable Dimensions — Millimeters (Inches)

Tape Size

8 mm

Pitch

E2ꢀMinimum

F

P₁

TꢀMaximum

WꢀMaximum

A₀B₀

2.0ꢀ±0.05ꢀ

(0.079ꢀ±0.002)

ꢀ4.0ꢀ±0.10ꢀ

8.3

Halfꢀ(2ꢀmm)

Singleꢀ(4ꢀmm)

(0.327)ꢀ

8.3

6.25

(0.246)

3.5ꢀ±0.05ꢀ

(0.138ꢀ±0.002)

1.1

(0.098)

Note 1

8 mm

(0.157ꢀ±0.004)

(0.327)

1. The cavity deﬁned by A₀, B₀and T shall surround the component with sufﬁcient clearance that:

a) the component does not protrude beyond either surface of the carrier tape.

b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.

c) rotation of the component is limited to 20° maximum (see Figure 3).

d) lateral movement of the component is restricted to 0.5 mm maximum (see Figure 4).

e) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.

2. The tape with or without components shall pass around R without damage (see Figure 6).

C1003_C0G • 3/30/2016 16

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Packaging Information Performance Notes

1. Cover Tape Break Force:ꢀ1.0ꢀKgꢀminimum.

2. Cover Tape Peel Strength: Theꢀtotalꢀpeelꢀstrengthꢀofꢀtheꢀcoverꢀtapeꢀfromꢀtheꢀcarrierꢀtapeꢀshallꢀbe:ꢀ

Tape Width

8 mm

Peel Strength

0.1ꢀtoꢀ1.0ꢀNewtonꢀ(10ꢀtoꢀ100ꢀgf)

0.1ꢀtoꢀ1.3ꢀNewtonꢀ(10ꢀtoꢀ130ꢀgf)

12 and 16 mm

Theꢀdirectionꢀofꢀtheꢀpullꢀshallꢀbeꢀoppositeꢀtheꢀdirectionꢀofꢀtheꢀcarrierꢀtapeꢀtravel.ꢀTheꢀpullꢀangleꢀofꢀtheꢀcarrierꢀtapeꢀshallꢀbeꢀ165°ꢀtoꢀ180°ꢀ

fromꢀtheꢀplaneꢀofꢀtheꢀcarrierꢀtape.ꢀDuringꢀpeeling,ꢀtheꢀcarrierꢀand/orꢀcoverꢀtapeꢀshallꢀbeꢀpulledꢀatꢀaꢀvelocityꢀofꢀ300ꢀ±10ꢀmm/minute.

3. Labeling:ꢀBarꢀcodeꢀlabelingꢀ(standardꢀorꢀcustom)ꢀshallꢀbeꢀonꢀtheꢀsideꢀofꢀtheꢀreelꢀoppositeꢀtheꢀsprocketꢀholes.ꢀRefer to EIA

Standards 556 and 624.

Figure 3 – Maximum Component Rotation

°

T

Maximum Component Rotation

Top View

Maximum Component Rotation

Side View

Typical Pocket Centerline

Tape

Maximum

°

T

s

Width (mm) Rotation (

)

8,12

16 – 200

20

10

Bo

Tape

Maximum

°

S

Width (mm) Rotation (

)

8,12

16 – 56

72 – 200

20

10

5

Typical Component Centerline

Ao

Figure 5 – Bending Radius

Figure 4 – Maximum Lateral Movement

Embossed

Carrier

Punched

Carrier

8 mm & 12 mm Tape

16 mm Tape

0.5 mm maximum

1.0 mm maximum

R

Bending

Radius

R

C1003_C0G • 3/30/2016 17

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Figure 6 – Reel Dimensions

Full Radius,

See Note

W3 (Includes

flange distortion

at outer edge)

Access Hole at

Slot Location

(Ø 40 mm minimum)

W

2 (Measured at hub)

D

(See Note)

A

N

C

(Arbor hole

W

1 (Measured at hub)

diameter)

If present,

tape slot in core

for tape start:

2.5 mm minimum width x

10.0 mm minimum depth

B

(see Note)

Note: Drive spokes optional; if used, dimensions B and D shall apply.

Table 8 – Reel Dimensions

Metricꢀwillꢀgovern

Constant Dimensions — Millimeters (Inches)

Tape Size

8 mm

A

BꢀMinimum

C

DꢀMinimum

178ꢀ±0.20ꢀ

(7.008ꢀ±0.008)ꢀ

or

330ꢀ±0.20

(13.000ꢀ±0.008)

1.5

(0.059)

13.0ꢀ+0.5/-0.2ꢀ

(0.521ꢀ+0.02/-0.008)

20.2

(0.795)

12 mm

16 mm

Variable Dimensions — Millimeters (Inches)

Tape Size

8 mm

NꢀMinimum

W₁

W₂ꢀMaximum

W₃

8.4ꢀ+1.5/-0.0

(0.331ꢀ+0.059/-0.0)

14.4

(0.567)

50

(1.969)

12.4ꢀ+2.0/-0.0

18.4

Shallꢀaccommodateꢀtapeꢀwidthꢀ

withoutꢀinterference

12 mm

16 mm

(0.488ꢀ+0.078/-0.0)ꢀꢀ

(0.724)

16.4ꢀ+2.0/-0.0

(0.646ꢀ+0.078/-0.0)

22.4

(0.882)

C1003_C0G • 3/30/2016 18

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Figure 7 – Tape Leader & Trailer Dimensions

Embossed Carrier

Carrier Tape

Round Sprocket Holes

Punched Carrier

8 mm & 12 mm only

START

END

Top Cover Tape

Elongated Sprocket Holes

(32 mm tape and wider)

100 mm

Minimum Leader

400 mm Minimum

Trailer

160 mm Minimum

Components

Top Cover Tape

Figure 8 – Maximum Camber

Elongated sprocket holes

(32 mm & wider tapes)

Carrier Tape

Round Sprocket Holes

1 mm Maximum, either direction

Straight Edge

250 mm

C1003_C0G • 3/30/2016 19

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 250 VDC (Commercial Grade)

KEMET Corporation

World Headquarters

Europe

Asia

Southern Europe

Sasso Marconi, Italy

Tel: 39-051-939111

Northeast Asia

HongꢀKong

Tel: 852-2305-1168

2835 KEMET Way

Simpsonville, SC 29681

Skopje,ꢀMacedonia

Tel: 389-2-55-14-623

Shenzhen,ꢀChina

Tel:ꢀ86-755-2518-1306

MailingꢀAddress:

P.O. Box 5928

Greenville, SC 29606

Beijing,ꢀChina

Central Europe

Landsberg,ꢀGermanyꢀꢀ

Tel: 49-8191-3350800

Tel:ꢀ86-10-5877-1075

www.kemet.com

Tel: 864-963-6300

Fax: 864-963-6521

Shanghai,ꢀChina

Tel:ꢀ86-21-6447-0707

Kamen, Germany

Tel:ꢀ49-2307-438110

Corporate Ofﬁces

FortꢀLauderdale,ꢀFL

Tel:ꢀ954-766-2800

Seoul,ꢀSouthꢀKorea

Tel: 82-2-6294-0550

Northern Europe

Wyboston,ꢀUnitedꢀKingdomꢀ

Tel:ꢀ44-1480-273082ꢀ

Taipei, Taiwan

Tel:ꢀ886-2-27528585

North America

Northeast

Wilmington,ꢀMA

Tel:ꢀ978-658-1663ꢀ

Espoo, Finland

Tel: 358-9-5406-5000

Southeast Asia

Singapore

Tel:ꢀ65-6701-8033

Southeast

Lake Mary, FL

Tel:ꢀ407-855-8886

Penang,ꢀMalaysia

Tel: 60-4-6430200

Central

Novi, MI

Tel: 248-994-1030

Bangalore,ꢀIndia

Tel:ꢀ91-806-53-76817

Irving,ꢀTX

Tel:ꢀ972-915-6041

West

Milpitas, CA

Tel: 408-433-9950

Mexico

Guadalajara,ꢀJaliscoꢀ

Tel: 52-33-3123-2141

Note: KEMET reserves the right to modify minor details of internal and external construction at any time in the interest of product improvement. KEMET does not

assume any responsibility for infringement that might result from the use of KEMET Capacitors in potential circuit designs. KEMET is a registered trademark of

KEMET Electronics Corporation.

C1003_C0G • 3/30/2016 20

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Disclaimer

Allꢀproductꢀspeci ꢀcations,ꢀstatements,ꢀinformationꢀandꢀdataꢀ(collectively,ꢀtheꢀ“Information”)ꢀinꢀthisꢀdatasheetꢀareꢀsubjectꢀtoꢀchange.ꢀTheꢀcustomerꢀisꢀresponsibleꢀforꢀcheckingꢀandꢀ

verifyingꢀtheꢀextentꢀtoꢀwhichꢀtheꢀInformationꢀcontainedꢀinꢀthisꢀpublicationꢀisꢀapplicableꢀtoꢀanꢀorderꢀatꢀtheꢀtimeꢀtheꢀorderꢀisꢀplaced.

AllꢀInformationꢀgivenꢀhereinꢀisꢀbelievedꢀtoꢀbeꢀaccurateꢀandꢀreliable,ꢀbutꢀitꢀisꢀpresentedꢀwithoutꢀguarantee,ꢀwarranty,ꢀorꢀresponsibilityꢀofꢀanyꢀkind,ꢀexpressedꢀorꢀimplied.

StatementsꢀofꢀsuitabilityꢀforꢀcertainꢀapplicationsꢀareꢀbasedꢀonꢀKEMETꢀElectronicsꢀCorporation’sꢀ(“KEMET”)ꢀknowledgeꢀofꢀtypicalꢀoperatingꢀconditionsꢀforꢀsuchꢀapplications,ꢀbutꢀareꢀ

notꢀintendedꢀtoꢀconstituteꢀ–ꢀandꢀKEMETꢀspeci ꢀcallyꢀdisclaimsꢀ–ꢀanyꢀwarrantyꢀconcerningꢀsuitabilityꢀforꢀaꢀspeci ꢀcꢀcustomerꢀapplicationꢀorꢀuse.ꢀTheꢀInformationꢀisꢀintendedꢀforꢀuseꢀonlyꢀ

byꢀcustomersꢀwhoꢀhaveꢀtheꢀrequisiteꢀexperienceꢀandꢀcapabilityꢀtoꢀdetermineꢀtheꢀcorrectꢀproductsꢀforꢀtheirꢀapplication.ꢀAnyꢀtechnicalꢀadviceꢀinferredꢀfromꢀthisꢀInformationꢀorꢀotherwiseꢀ

providedꢀbyꢀKEMETꢀwithꢀreferenceꢀtoꢀtheꢀuseꢀofꢀKEMET’sꢀproductsꢀisꢀgivenꢀgratis,ꢀandꢀKEMETꢀassumesꢀnoꢀobligationꢀorꢀliabilityꢀforꢀtheꢀadviceꢀgivenꢀorꢀresultsꢀobtained.

AlthoughꢀKEMETꢀdesignsꢀandꢀmanufacturesꢀitsꢀproductsꢀtoꢀtheꢀmostꢀstringentꢀqualityꢀandꢀsafetyꢀstandards,ꢀgivenꢀtheꢀcurrentꢀstateꢀofꢀtheꢀart,ꢀisolatedꢀcomponentꢀfailuresꢀmayꢀstillꢀ

occur.ꢀAccordingly,ꢀcustomerꢀapplicationsꢀwhichꢀrequireꢀaꢀhighꢀdegreeꢀofꢀreliabilityꢀorꢀsafetyꢀshouldꢀemployꢀsuitableꢀdesignsꢀorꢀotherꢀsafeguardsꢀ(suchꢀasꢀinstallationꢀofꢀprotectiveꢀ

circuitryꢀorꢀredundancies)ꢀinꢀorderꢀtoꢀensureꢀthatꢀtheꢀfailureꢀofꢀanꢀelectricalꢀcomponentꢀdoesꢀnotꢀresultꢀinꢀaꢀriskꢀofꢀpersonalꢀinjuryꢀorꢀpropertyꢀdamage.

Althoughꢀallꢀproduct–relatedꢀwarnings,ꢀcautionsꢀandꢀnotesꢀmustꢀbeꢀobserved,ꢀtheꢀcustomerꢀshouldꢀnotꢀassumeꢀthatꢀallꢀsafetyꢀmeasuresꢀareꢀindictedꢀorꢀthatꢀotherꢀmeasuresꢀmayꢀnotꢀ

beꢀrequired.

C1003_C0G • 3/30/2016 21


型号：	C1825C104D3GACTU
厂家：	KEMET CORPORATION
描述：	C0G Dielectric, 10 - 250 VDC (Commercial Grade)
文件：	总21页 (文件大小：1432K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

C1825C104D3GACTU [KEMET]

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