KK74ACT175D [KODENSHI]

Quad D Flip-Flop with Common Clock and Reset High-Speed Silicon-Gate CMOS; 四D触发器与普通时钟和复位高速硅栅CMOS


型号：	KK74ACT175D
厂家：	KODENSHI KOREA CORP.
描述：	Quad D Flip-Flop with Common Clock and Reset High-Speed Silicon-Gate CMOS 四D触发器与普通时钟和复位高速硅栅CMOS 触发器栅时钟
文件：	总6页 (文件大小：332K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TECHNICAL DATA

KK74ACT175

Quad D Flip-Flop with

Common Clock and Reset

High-Speed Silicon-Gate CMOS

The KK74ACT175 is identical in pinout to the LS/ALS175,

HC/HCT175. The KK74ACT175 may be used as a level converter for

interfacing TTL or NMOS outputs to High Speed CMOS inputs.

This device consists of four D flip-flops with common Reset and

Clock inputs, and separate D inputs. Reset (active-low) is asynchronous

and occurs when a low level is applied to the Reset input. Information at a

D input is transferred to the corresponding Q output on the next positive-

going edge of the Clock input.

ORDERING INFORMATION

KK74ACT175N Plastic

KK74ACT175D SOIC

T_A= -40° to 85° C for all packages

•

TTL/NMOS Compatible Input Levels

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 4.5 to 5.5 V

Low Input Current: 1.0 µA; 0.1 µA @ 25°C

Outputs Source/Sink 24 mA

PIN ASSIGNMENT

LOGIC DIAGRAM

FUNCTION TABLE

Inputs

Clock

Outputs

Reset

PIN 16=V_CC

PIN 8 = GND

no change

X = Don’t care

KK74ACT175

MAXIMUM RATINGS^*

Symbol

Parameter

Value

-0.5 to +7.0

-0.5 to V_CC+0.5

±20

Unit

V_CC

V_IN

V_OUT

I_IN

DC Supply Voltage (Referenced to GND)

DC Input Voltage (Referenced to GND)

DC Output Voltage (Referenced to GND)

DC Input Current, per Pin

I_OUT

I_CC

DC Output Sink/Source Current, per Pin

DC Supply Current, V_CCand GND Pins

±50

P_D

Power Dissipation in Still Air, Plastic DIP+

SOIC Package+

750

500

Tstg

T_L

Storage Temperature

-65 to +150

260

°C

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

^*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol

V_CC

Parameter

DC Supply Voltage (Referenced to GND)

DC Input Voltage, Output Voltage (Referenced to GND)

Junction Temperature (PDIP)

Min

4.5

Max

Unit

5.5

V_CC

140

+85

-24

V_IN, V_OUT

T_J

°C

T_A

Operating Temperature, All Package Types

Output Current - High

-40

°C

I_OH

ns/V

I_OL

Output Current - Low

t_r, t_f

Input Rise and Fall Time ^*

(except Schmitt Inputs)

V_CC=4.5 V

V_CC=5.5 V

8.0

^*V_INfrom 0.8 V to 2.0 V

This device contains protection circuitry to guard against damage due to high static voltages or electric fields.

However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this

high-impedance circuit. For proper operation, V_INand V_OUTshould be constrained to the range GND≤(V_INor

_OUT)≤V_CC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V_CC). Unused

outputs must be left open.

KK74ACT175

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

V_CC

Guaranteed Limits

Symbol

V_IH

Parameter

Test Conditions

V_OUT=0.1 V or V_CC-0.1 V

I_OUT≤ -50 µA

Unit

25 °C

-40°C to

85°C

Minimum High-

Level Input Voltage

4.5

5.5

2.0

V_IL

Maximum Low -

Level Input Voltage

4.5

5.5

0.8

V_OH

Minimum High-

Level Output Voltage

4.5

5.5

4.4

5.4

4.4

5.4

^*V_IN=V_IHor V_IL

I_OH=-24 mA

4.5

5.5

3.86

4.86

3.76

4.76

V_OL

Maximum Low-

Level Output Voltage

4.5

5.5

0.1

I_OUT≤ 50 µA

^*V_IN=V_IHor V_IL

I_OL=24 mA

4.5

5.5

0.36

0.44

I_IN

∆I_CCT

I_OLD

I_OHD

I_CC

Maximum Input

Leakage Current

V_IN=V_CCor GND

V_IN=V_CC- 2.1 V

5.5

±0.1

±1.0

1.5

µA

Additional Max.

I_CC/Input

+Minimum Dynamic V_OLD=1.65 V Max

Output Current

+Minimum Dynamic V_OHD=3.85 V Min

Output Current

-75

Maximum Quiescent

Supply Current

(per Package)

V_IN=V_CCor GND

8.0

^*All outputs loaded; thresholds on input associated with output under test.

+Maximum test duration 2.0 ms, one output loaded at a time.

KK74ACT175

AC ELECTRICAL CHARACTERISTICS (V_CC=5.0 V ± 10%, C_L=50pF,Input t_r=t_f=3.0 ns)

Guaranteed Limits

25 °C -40°C to 85°C

Symbol

Parameter

Unit

Min Max

175

Min

145

1.5

Max

f_max

t_PLH

t_PHL

Maximum Clock Frequency (Figure 1)

MHz

Propagation Delay, Clock to Q or Q (Figure 1)

2.0

10.0

11.0

9.5

11.0

12.0

10.5

1.5

t_PHL, t_PLHPropagation Delay, Reset to Q or Q (Figure 2)

1.5

C_IN

Maximum Input Capacitance

4.5

Typical @25°C,V_CC=5.0 V

C_PD

Power Dissipation Capacitance

TIMING REQUIREMENTS(V_CC=5.0 V ± 10%, C_L=50pF,Input t_r=t_f=3.0 ns)

Guaranteed Limits

25 °C -40°C to 85°C

Symbol

Parameter

Unit

t_su(H) Minimum Setup Time, Data to Clock (Figure 3)

(L)

2.0

2.5

2.0

2.5

t_h

t_w

Minimum Hold Time, Clock to Data (Figure 3)

Minimum Pulse Width, Reset (Figure 2)

Minimum Pulse Width, Clock (Figure 1)

1.0

3.0

1.0

4.0

3.5

t_w

t_rec

Minimum Recovery Time, Reset to Clock

(Figure 2)

KK74ACT175

Figure 1. Switching Waveforms

Figure 2. Switching Waveforms

Figure 3. Switching Waveforms

EXPANDED LOGIC DIAGRAM

KK74ACT175

N SUFFIX PLASTIC DIP

(MS - 001BB)

Dimension, mm

Symbol

MIN

18.67

6.1

MAX

19.69

7.11

5.33

0.36

1.14

0.56

1.78

2.54

7.62

SEATING

PLANE

-T-

2.92

7.62

0.2

3.81

8.26

0.36

0.25 (0.010) M

NOTES:

1. Dimensions “A”, “B” do not include mold flash or protrusions.

Maximum mold flash or protrusions 0.25 mm (0.010) per side.

0.38

D SUFFIX SOIC

(MS - 012AC)

Dimension, mm

Symbol

MIN

9.8

MAX

3.8

1.35

0.33

0.4

1.75

0.51

1.27

R x 45

1.27

5.72

-T-

SEATING

PLANE

0.25 (0.010) M T C

0.1

0.19

5.8

0.25

6.2

NOTES:

1. Dimensions A and B do not include mold flash or protrusion.

2. Maximum mold flash or protrusion 0.15 mm (0.006) per side

0.25

0.5

for A; for B 0.25 mm (0.010) per side.

‑

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