KK74HC164AN [KODENSHI]
8-Bit Serial-Input/Parallel-Output Shift Register High-Performance Silicon-Gate CMOS; 8位串行输入/并行输出移位寄存器高性能硅栅CMOS型号: | KK74HC164AN |
厂家: | KODENSHI KOREA CORP. |
描述: | 8-Bit Serial-Input/Parallel-Output Shift Register High-Performance Silicon-Gate CMOS |
文件: | 总6页 (文件大小:383K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TECHNICAL DATA
KK74HC164А
8-Bit Serial-Input/Parallel-Output
Shift Register
High-Performance Silicon-Gate CMOS
The KK74HC164A is identical in pinout to the LS/ALS164. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The KK74HC164A is an 8-bit, serial-input to parallel-output shift
register. Two serial data inputs, A1 and A2, are provided so that one input
may be used as a data enable. Data is entered on each rising edge of the
clock. The active-low asynchronous Reset overrides theClock and Serial
Data inputs.
ORDERING INFORMATION
KK74HC164АN Plastic
KK74HC164АD SOIC
TA = -55° to 125° C for all packages
•
•
•
•
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Outputs
RESET CLOCK
A1 A2
X X
QA QB…QH
L
H
H
X
L
L… L
X X
no change
PIN 14 =VCC
PIN 7 = GND
H D
D
QAn…QGn
H
D H
D
QAn…QGn
D = data input
X = don’t care
QAn - QGn = data shifted from the previous stage on a
rising edge at the clock input.
1
KK74HC164А
MAXIMUM RATINGS*
Symbol
Parameter
Value
-0.5 to +7.0
-1.5 to VCC +1.5
-0.5 to VCC +0.5
±20
Unit
V
VCC
VIN
VOUT
IIN
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
V
V
mA
mA
mA
mW
IOUT
ICC
DC Output Current, per Pin
±25
DC Supply Current, VCC and GND Pins
±50
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg
TL
Storage Temperature
-65 to +150
260
°C
°C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
2.0
0
Max
Unit
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
VCC
VIN, VOUT
TA
V
-55
+125
°C
ns
tr, tf
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
V
OUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
KK74HC164А
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol
VIH
Parameter
Test Conditions
Unit
V
25 °C
to
≤85
°C
≤125
°C
-55°C
Minimum High-
Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢≤ 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
VIL
Maximum Low -
Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH
Minimum High-
Level Output Voltage
VIN= VIH or VIL
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN= VIH or VIL
⎢IOUT⎢ ≤ 4.0 mA
⎢IOUT⎢ ≤ 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL
Maximum Low-
Level Output Voltage
VIN=VIH or VIL
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN=VIH or VIL
⎢IOUT⎢ ≤ 4.0 mA
⎢IOUT⎢ ≤ 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
6.0
±0.1
±1.0
±1.0
µA
µA
ICC
Maximum Quiescent VIN=VCC or GND
Supply Current
(per Package)
6.0
8.0
80
160
I
OUT=0µA
3
KK74HC164А
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC
V
Guaranteed Limit
Symbol
fmax
Parameter
Unit
MHz
ns
25 °C
to
≤85°C ≤125°C
-55°C
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
tPLH, tPHL Maximum Propagation Delay,Clock to Q (Figures 2.0
175
35
220
44
265
53
1 and 4)
4.5
6.0
30
37
45
tPHL
Maximum Propagation Delay,Reset to Q
(Figures 2 and 4)
2.0
4.5
6.0
205
41
35
255
51
43
310
62
53
ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
CIN
tSU
Maximum Input Capacitance
-
10
10
10
pF
ns
Minimum Setup Time,A1 or A2 to Clock
(Figure 3)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
th
trec
tw
Minimum Hold Time, Clock to A1 or A2
(Figure 3)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
ns
ns
ns
ns
Minimum Recovery Time, Reset Inactive to
Clock (Figure 2)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
Minimum Pulse Width, Reset (Figure 2)
Minimum Pulse Width, Clock (Figure 1)
Maximum Input Rise and Fall Times (Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
tw
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
tr, tf
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
Power Dissipation Capacitance (Per Package)
Typical @25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption:
140
pF
PD=CPDVCC2f+ICCVCC
4
KK74HC164А
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit
TIMING DIAGRAM
EXPANDED LOGIC DIAGRAM
5
KK74HC164А
N SUFFIX PLASTIC DIP
(MS - 001AA)
A
Dimension, mm
Symbol
MIN
18.67
6.1
MAX
19.69
7.11
8
7
14
1
B
A
B
C
D
F
5.33
0.36
1.14
0.56
F
L
1.78
C
2.54
7.62
G
H
J
-T-
SEATING
PLANE
N
0
°
10
°
M
J
G
K
H
D
2.92
7.62
0.2
3.81
8.26
0.36
K
L
M
N
0.25 (0.010) M
T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
0.38
D SUFFIX SOIC
(MS - 012AB)
Dimension, mm
A
14
8
Symbol
MIN
8.55
3.8
MAX
8.75
4
A
B
C
D
F
H
B
P
1.35
0.33
0.4
1.75
0.51
1.27
1
7
G
R x 45
C
1.27
5.27
G
H
J
-T-
SEATING
PLANE
K
M
D
J
F
0°
8°
0.25 (0.010) M
T
M
C
0.1
0.25
0.25
6.2
K
M
P
NOTES:
0.19
5.8
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
0.25
0.5
R
for A; for B 0.25 mm (0.010) per side.
‑
6
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