KK74HC175AN [KODENSHI]

Quad D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS; 四D触发器与普通时钟和复位高性能硅栅CMOS


型号：	KK74HC175AN
厂家：	KODENSHI KOREA CORP.
描述：	Quad D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS 四D触发器与普通时钟和复位高性能硅栅CMOS 触发器锁存器栅时钟
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TECHNICAL DATA

KK74HC175A

Quad D Flip-Flop with

Common Clock and Reset

High-Performance Silicon-Gate CMOS

The KK74HC175A is identical in pinout to the LS/ALS175. The

device inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LS/ALSTTL outputs.

This device consists of four D flip-flops with common Reset and

Clock inputs, and separate D inputs. Reset (active-low) is asynchronous

and occurs when a low level is applied to the Reset input. Information at a

D input is transferred to the corresponding Q output on the next positive-

going edge of the Clock input.

ORDERING INFORMATION

KK74HC175AN Plastic

KK74HC175AD SOIC

T_A= -55° to 125° C for all packages

•

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 2.0 to 6.0 V

Low Input Current: 1.0 µA

High Noise Immunity Characteristic of CMOS Devices

PIN ASSIGNMENT

LOGIC DIAGRAM

FUNCTION TABLE

Inputs

Clock

Outputs

Reset

PIN 16=V_CC

PIN 8 = GND

no change

X = Don’t care

KK74HC175A

MAXIMUM RATINGS^*

Symbol

Parameter

Value

-0.5 to +7.0

-1.5 to V_CC+1.5

-0.5 to V_CC+0.5

±20

Unit

V_CC

V_IN

V_OUT

I_IN

DC Supply Voltage (Referenced to GND)

DC Input Voltage (Referenced to GND)

DC Output Voltage (Referenced to GND)

DC Input Current, per Pin

I_OUT

I_CC

DC Output Current, per Pin

±25

DC Supply Current, V_CCand GND Pins

±50

P_D

Power Dissipation in Still Air, Plastic DIP+

SOIC Package+

750

500

Tstg

T_L

Storage Temperature

-65 to +150

260

°C

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

^*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol

V_CC

Parameter

Min

2.0

Max

Unit

DC Supply Voltage (Referenced to GND)

DC Input Voltage, Output Voltage (Referenced to GND)

Operating Temperature, All Package Types

6.0

V_CC

V_IN, V_OUT

T_A

-55

+125

°C

t_r, t_f

Input Rise and Fall Time (Figure 1)

V_CC=2.0 V

V_CC=4.5 V

V_CC=6.0 V

1000

500

400

This device contains protection circuitry to guard against damage due to high static voltages or electric fields.

However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this

high-impedance circuit. For proper operation, V_INand V_OUTshould be constrained to the range GND≤(V_INor

_OUT)≤V_CC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V_CC). Unused

outputs must be left open.

KK74HC175A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

V_CC

Guaranteed Limit

Symbol

V_IH

Parameter

Test Conditions

Unit

25 °C

≤85 ≤125

°C

-55°C

Minimum High-

Level Input Voltage

V_OUT=0.1 V or V_CC-0.1 V

⎢I_OUT⎢≤ 20 µA

2.0

4.5

6.0

1.5

3.15

4.2

1.5

3.15

4.2

1.5

3.15

4.2

V_IL

Maximum Low -

Level Input Voltage

V_OUT=0.1 V or V_CC-0.1 V

⎢I_OUT⎢ ≤ 20 µA

2.0

4.5

6.0

0.3

0.9

1.2

0.3

0.9

1.2

0.3

0.9

1.2

V_OH

Minimum High-

Level Output Voltage

V_IN=V_IHor V_IL

⎢I_OUT⎢ ≤ 20 µA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V_IN=V_IHor V_IL

⎢I_OUT⎢ ≤ 4.0 mA

⎢I_OUT⎢ ≤ 5.2 mA

4.5

6.0

3.98

5.48

3.84

5.34

3.7

5.2

V_OL

Maximum Low-

Level Output Voltage

V_IN= V_ILor V_IH

⎢I_OUT⎢ ≤ 20 µA

2.0

4.5

6.0

0.1

V_IN= V_ILor V_IH

⎢I_OUT⎢ ≤ 4.0 mA

⎢I_OUT⎢ ≤ 5.2 mA

4.5

6.0

0.26

0.33

0.4

I_IN

Maximum Input

Leakage Current

V_IN=V_CCor GND

6.0

±0.1

±1.0 ±1.0

µA

I_CC

Maximum Quiescent V_IN=V_CCor GND

Supply Current

(per Package)

6.0

8.0

80 160

_OUT=0µA

KK74HC175A

AC ELECTRICAL CHARACTERISTICS (C_L=50pF,Input t_r=t_f=6.0 ns)

V_CC

Guaranteed Limit

Symbol

f_max

Parameter

Unit

MHz

25 °C

≤85°C ≤125°C

-55°C

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

2.0

4.5

6.0

4.8

4.0

t_PLH, t_PHLMaximum Propagation Delay, Clock to Q or Q

(Figures 1 and 4)

2.0

4.5

6.0

150

190

225

t_PHL,t_PLHMaximum Propagation Delay , Reset to Q or Q

(Figures 2 and 4)

2.0

4.5

6.0

125

155

190

t_TLH, t_THLMaximum Output Transition Time, Any Output

(Figures 1 and 4)

2.0

4.5

6.0

110

C_IN

Maximum Input Capacitance

Power Dissipation Capacitance (Per Flip-Flop)

Typical @25°C,V_CC=5.0 V

C_PD

Used to determine the no-load dynamic power

consumption: P_D=C_PDV_CC²f+I_CCV_CC

TIMING REQUIREMENTS (C_L=50pF,Input t_r=t_f=6.0 ns)

V_CC

Guaranteed Limit

Symbol

t_SU

Parameter

Unit

25 °C to

-55°C

≤85°C

≤125°C

Minimum Setup Time, Data to

Clock (Figure 3)

2.0

4.5

6.0

100

125

150

t_h

t_rec

t_w

Minimum Hold Time, Clock

to Data (Figure 3)

2.0

4.5

6.0

Minimum Recovery Time,

Reset Inactive to Clock

(Figure 2)

2.0

4.5

6.0

100

125

150

Minimum Pulse Width, Clock

(Figure 1)

2.0

4.5

6.0

100

120

t_w

Minimum Pulse Width, Reset

(Figure 2)

2.0

4.5

6.0

100

120

t_r,t_f

Maximum Input Rise and Fall

Times (Figure 1)

2.0

4.5

6.0

1000

500

400

1000

500

400

1000

500

400

KK74HC175A

Figure 1. Switching Waveforms

Figure 2. Switching Waveforms

Figure 3. Switching Waveforms

Figure 4. Test Circuit

EXPANDED LOGIC DIAGRAM

KK74HC175A

N SUFFIX PLASTIC DIP

(MS - 001BB)

Dimension, mm

Symbol

MIN

18.67

6.1

MAX

19.69

7.11

5.33

0.36

1.14

0.56

1.78

2.54

7.62

SEATING

PLANE

-T-

2.92

7.62

0.2

3.81

8.26

0.36

0.25 (0.010) M

NOTES:

1. Dimensions “A”, “B” do not include mold flash or protrusions.

Maximum mold flash or protrusions 0.25 mm (0.010) per side.

0.38

D SUFFIX SOIC

(MS - 012AC)

Dimension, mm

Symbol

MIN

9.8

MAX

3.8

1.35

0.33

0.4

1.75

0.51

1.27

R x 45

1.27

5.72

-T-

SEATING

PLANE

0.25 (0.010) M T C

0.1

0.19

5.8

0.25

6.2

NOTES:

1. Dimensions A and B do not include mold flash or protrusion.

2. Maximum mold flash or protrusion 0.15 mm (0.006) per side

0.25

0.5

for A; for B 0.25 mm (0.010) per side.

‑

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