KK74HC534ADW [KODENSHI]

FF/Latch;
KK74HC534ADW
型号: KK74HC534ADW
厂家: KODENSHI KOREA CORP.    KODENSHI KOREA CORP.
描述:

FF/Latch

触发器
文件: 总6页 (文件大小:314K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
TECHNICAL DATA  
KK74HC534A  
Octal 3-State  
Inverting D Flip-Flop  
High-Performance Silicon-Gate CMOS  
The KK74HC534A is identical in pinout to the LS/ALS534. The  
device inputs are compatible with standard CMOS outputs; with pullup  
resistors, they are compatible with LS/ALSTTL outputs.  
Data meeting the setup time is clocked, in inverted form, to the  
outputs with the rising edge of the Clock. The Output Enable input does  
not affect the states of the flip-flops, but when Output Enable is high, the  
outputs are forced to the high impedance state. Thus, data may be stored  
even when the outputs are not enabled.  
ORDERING INFORMATION  
KK74HC534AN Plastic  
KK74HC534ADW SOIC  
TA = -55° to 125° C for all packages  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 µA  
High Noise Immunity Characteristic of CMOS Devices  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
FUNCTION TABLE  
Inputs  
Clock  
Output  
Q
PIN 20=VCC  
PIN 10 = GND  
Output  
Enable  
D
L
L
L
H
L
L
H
L,H,  
X
no  
change  
H
X
X
Z
X = don’t care  
Z = high impedance  
1
KK74HC534A  
MAXIMUM RATINGS*  
Symbol  
Parameter  
Value  
-0.5 to +7.0  
-1.5 to VCC +1.5  
-0.5 to VCC +0.5  
±20  
Unit  
V
VCC  
VIN  
VOUT  
IIN  
DC Supply Voltage (Referenced to GND)  
DC Input Voltage (Referenced to GND)  
DC Output Voltage (Referenced to GND)  
DC Input Current, per Pin  
V
V
mA  
mA  
mA  
mW  
IOUT  
ICC  
DC Output Current, per Pin  
±35  
DC Supply Current, VCC and GND Pins  
±75  
PD  
Power Dissipation in Still Air, Plastic DIP+  
SOIC Package+  
750  
500  
Tstg  
TL  
Storage Temperature  
-65 to +150  
260  
°C  
°C  
Lead Temperature, 1 mm from Case for 10 Seconds  
(Plastic DIP or SOIC Package)  
*Maximum Ratings are those values beyond which damage to the device may occur.  
Functional operation should be restricted to the Recommended Operating Conditions.  
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C  
SOIC Package: : - 7 mW/°C from 65° to 125°C  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
VCC  
Parameter  
Min  
2.0  
0
Max  
Unit  
V
DC Supply Voltage (Referenced to GND)  
DC Input Voltage, Output Voltage (Referenced to GND)  
Operating Temperature, All Package Types  
6.0  
VCC  
VIN, VOUT  
TA  
V
-55  
+125  
°C  
ns  
tr, tf  
Input Rise and Fall Time (Figure 1)  
VCC =2.0 V  
VCC =4.5 V  
VCC =6.0 V  
0
0
0
1000  
500  
400  
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.  
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this  
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or  
V
OUT)VCC.  
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused  
outputs must be left open.  
2
KK74HC534A  
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)  
VCC  
V
Guaranteed Limit  
Symbol  
VIH  
Parameter  
Test Conditions  
Unit  
V
25 °C  
to  
85 125  
°C  
°C  
-55°C  
Minimum High-  
Level Input Voltage  
VOUT=0.1 V or VCC-0.1 V  
IOUT⎢≤ 20 µA  
2.0  
4.5  
6.0  
1.5  
3.15  
4.2  
1.5  
3.15  
4.2  
1.5  
3.15  
4.2  
VIL  
Maximum Low -  
Level Input Voltage  
VOUT=0.1 V or VCC-0.1 V  
IOUT⎢ ≤ 20 µA  
2.0  
4.5  
6.0  
0.5  
1.35  
1.8  
0.5  
1.35  
1.8  
0.5  
1.35  
1.8  
V
VOH  
Minimum High-  
Level Output Voltage  
VIN=VIH or VIL  
IOUT⎢ ≤ 20 µA  
2.0  
4.5  
6.0  
1.9  
4.4  
5.9  
1.9  
4.4  
5.9  
1.9  
4.4  
5.9  
V
VIN=VIH or VIL  
IOUT⎢ ≤ 6.0 mA  
IOUT⎢ ≤ 7.8 mA  
4.5  
6.0  
3.98  
5.48  
3.84  
5.34  
3.7  
5.2  
VOL  
Maximum Low-  
Level Output Voltage  
VIN= VIL or VIH  
IOUT⎢ ≤ 20 µA  
2.0  
4.5  
6.0  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
V
VIN= VIL or VIH  
IOUT⎢ ≤ 6.0 mA  
IOUT⎢ ≤7.8 mA  
4.5  
6.0  
0.26  
0.26  
0.33  
0.33  
0.4  
0.4  
IIN  
Maximum Input  
Leakage Current  
VIN=VCC or GND  
6.0  
6.0  
±0.1  
±0.5  
±1.0 ±1.0  
µA  
µA  
IOZ  
Maximum Three  
State Leakage  
Current  
Output in High-Impedance  
State  
VIN =VIH or VIL  
VOUT= VCC or GND  
±5.0  
±10  
ICC  
Maximum Quiescent VIN=VCC or GND  
6.0  
4.0  
40  
160  
µA  
Supply Current  
(per Package)  
I
OUT=0µA  
3
KK74HC534A  
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns)  
VCC  
V
Guaranteed Limit  
Symbol  
fmax  
Parameter  
Unit  
MHz  
ns  
25 °C  
to  
85°C 125°C  
-55°C  
Maximum Clock Frequency (50% Duty Cycle)  
(Figures 1 and 4)  
2.0  
4.5  
6.0  
6.0  
30  
35  
5.0  
24  
28  
4.0  
20  
24  
tPLH, tPHL Maximum Propagation Delay, Clock to Q  
(Figures 1 and 4)  
2.0  
4.5  
6.0  
125  
25  
155  
31  
190  
38  
21  
26  
32  
tPLZ, tPHZ Maximum Propagation Delay, Output Enable to  
Q (Figures 2 and 5)  
2.0  
4.5  
6.0  
150  
30  
26  
190  
38  
33  
225  
45  
38  
ns  
tPZH, tPZL Maximum Propagation Delay, Output Enable to  
Q (Figures 2 and 5)  
2.0  
4.5  
6.0  
150  
30  
26  
190  
38  
33  
225  
45  
38  
ns  
tTLH, tTHL Maximum Output Transition Time, Any Output  
(Figures 1 and 4)  
2.0  
4.5  
6.0  
75  
15  
13  
95  
19  
16  
110  
22  
19  
ns  
CIN  
Maximum Input Capacitance  
-
-
10  
15  
10  
15  
10  
15  
pF  
pF  
COUT  
Maximum Three-State Output Capacitance  
(Output in High-Impedance State)  
Power Dissipation Capacitance (Per Flip-Flop)  
Typical @25°C,VCC=5.0 V  
CPD  
Used to determine the no-load dynamic power  
consumption:  
34  
pF  
PD=CPDVCC2f+ICCVCC  
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)  
VCC  
Guaranteed Limit  
Symbol  
tSU  
Parameter  
V
Unit  
25 °C to  
-55°C  
85°C  
125°C  
Minimum Setup Time, Data to  
Clock (Figure 3)  
2.0  
4.5  
6.0  
50  
10  
9
65  
13  
11  
75  
15  
13  
ns  
ns  
ns  
ns  
th  
Minimum Hold Time, Clock  
to Data (Figure 3)  
2.0  
4.5  
6.0  
5
5
5
5
5
5
5
5
5
tw  
Minimum Pulse Width, Clock  
(Figure 1)  
2.0  
4.5  
6.0  
60  
12  
10  
75  
15  
13  
90  
18  
15  
tr, tf  
Maximum Input Rise and Fall  
Times (Figure 1)  
2.0  
4.5  
6.0  
1000  
500  
400  
1000  
500  
400  
1000  
500  
400  
4
KK74HC534A  
Figure 1. Switching Waveforms  
Figure 2. Switching Waveforms  
Figure 3. Switching Waveforms  
Figure 4. Test Circuit  
Figure 5. Test Circuit  
EXPANDED LOGIC DIAGRAM  
5
KK74HC534A  
N SUFFIX PLASTIC DIP  
(MS - 001AD)  
A
Dimension, mm  
11  
10  
20  
1
Symbol MIN  
MAX  
26.92  
7.11  
B
24.89  
6.1  
A
B
C
D
F
5.33  
0.36  
1.14  
0.56  
F
L
1.78  
2.54  
7.62  
G
H
J
C
SEATING  
PLANE  
-T-  
K
N
0
10  
°
°
M
J
G
H
D
2.92  
7.62  
0.2  
3.81  
8.26  
0.36  
K
L
M
N
0.25 (0.010) M  
T
NOTES:  
1. Dimensions “A”, “B” do not include mold flash or protrusions.  
Maximum mold flash or protrusions 0.25 mm (0.010) per side.  
0.38  
D SUFFIX SOIC  
(MS - 013AC)  
A
20  
11  
Dimension, mm  
Symbol MIN  
MAX  
13  
H
B
P
12.6  
7.4  
A
B
C
D
F
7.6  
2.35  
0.33  
0.4  
2.65  
0.51  
1.27  
1
10  
G
R x 45  
C
-T-  
SEATING  
PLANE  
1.27  
9.53  
G
H
J
K
M
D
J
F
M
0.25 (0.010) M T C  
0
°
8
°
NOTES:  
0.1  
0.23  
10  
0.3  
0.32  
10.65  
0.75  
K
M
P
1. Dimensions A and B do not include mold flash or protrusion.  
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side  
for A; for B 0.25 mm (0.010) per side.  
0.25  
R
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