SD6830P-XXX(20DIP) [KODENSHI]
IC,MICROCONTROLLER,4-BIT,CMOS,DIP,20PIN,PLASTIC;
| 型号： | SD6830P-XXX(20DIP) |
| 厂家： | 
KODENSHI KOREA CORP. |
| 描述： | IC,MICROCONTROLLER,4-BIT,CMOS,DIP,20PIN,PLASTIC 微控制器 光电二极管 |
| 文件： | 总34页 (文件大小：396K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SD6830
Semiconductor
4BIT MICROCONTROLLER
1. Description
SD6830 is a remote control transmitter, consists of the optimized 4-bit CPU with ROM and
RAM. It contains power-on reset, watchdog timer and carrier frequency generator. The
SD6830 provide a various carrier frequency for encoding output of key matrix and has
built-in transistor to drive infrared LED. The SD6830 is supported with a software
development tool, which allows code development in a PC environment. It allows the user
to simulate the SD6830 on an instruction level.
2. Features
• Number of basic instructions ------------------------------------- 45
• Instruction cycle time (one word instruction)
At Fsys=480KHz ---------------------------------------- 16.67uS
At Fsys=455kHz ---------------------------------------- 17.58uS
• Memory size
ROM --------------------------------------------------- 1024 x 8 Bits
RAM ------------------------------------------------------ 32 x 4 Bits
• Input ports (D0 ~ D3, E0 ~ E3 : with pull-up resistor)
• Output ports (C, G, K, F0 ~ F7)
• Carrier frequency generator
Fsys/12 (1/2 duty), Fsys/12 (1/3 duty), Fsys/12 (1/4 duty),
Fsys/8 (1/2 duty), Fsys/8 (1/4 duty), Fsys/11 (4/11 duty), No carrier
• Watchdog Timer
• Built-in power on reset
• Single power supply ------------------------------------------------ 1.8V ~ 3.6V
• Power dissipation (stop mode , VDD = 3V) ----------------------- Less than 3uW
• Package ------------------------------------------------------------- 20/24 DIP, 20/24 SOP
• Low-power system applications such as an infrared remote controller
• MASK OPTION
1. Divide ratio of the oscillator frequency
2. Whether connected infrared LED driver or not
* Descriptions of this spec sheet assume that the SD6830 include driver for infrared LED.
3. Ordering Information
Type NO.
Marking
Package Code
DIP20
SD6830P-option
SD6830-option
SD6830P-option
SD6830-option
SD6830P-option
SD6830-option
SD6830P-option
SD6830-option
SOP20
DIP24
SOP24
KSI-W002-000
1
SD6830
4. Block Diagram
VSS
1
VDD
24
3
Port
C
Z
OSCIN
2
Watchdog
Timer
OSC
Carrier
Frequency
Generator
23
22
C/REM
TEST
OSCOUT
3
Test
Control
H
L
Reset
Control
4
3
RAM
4
4
4
Port
K
K
21
Port
G
4
4
B
4
G
A
4
4
ALU
D0
D1
5
6
7
8
20
19
18
17
16
15
14
13
F0
F1
Port
D
4
D2
D3
CY
STACK
10
F2
F3
F4
Port
F
10
PC
ROM
F5
F6
F7
E0
9
8
Port
E
E1 10
4
Instruction
Decoder
SF
E2
11
12
E3
OSC
Start/Stop
Control
4
4
Key Input
Detector
Figure 4-1 Block Diagram of the SD6830
KSI-W002-000
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SD6830
5. PIN Assignment and Description
5.1 PIN Assignment for 24PINS( DIP24, SOP24)
1
24
23
22
21
20
19
18
17
16
15
14
13
VSS
VDD
C/REM
TEST
K
2
OSCIN
3
OSCOUT
4
G
5
D0
F0
6
D1
F1
7
D2
F2
SD6830
8
D3
F3
9
E0
F4
10
E1
F5
11
E2
F6
12
E3
F7
OUTLINE 24 PIN
Figure 5-1. Pin Assignment of 24 Pins
5.2 PIN Description for 24 PINS
Symbol
VDD
Pin No.
I /O
-
Functions
I/O Type
24
Power Supply
Ground
VSS
1
-
TEST
OSCin
OSCout
C/REM
D0 - D3
E0 - E3
F0 - F7
G
22
2
INPUT
INPUT
Input for test ( Normally connected to VSS )
Input for oscillating
3
OUTPUT
OUTPUT
INPUT
Output for oscillating
23
1-Bit output for remote transmission
B
5 ~ 8
9 ~ 12
20 ~ 13
4
4-Bit input for key sense ( with pull-up resistor )
4-Bit input for key sense ( with pull-up resistor )
1-Bit individual output for key scan
1-Bit output
A
A
C
D
D
INPUT
OUTPUT
OUTPUT
OUTPUT
K
21
1-Bit output
KSI-W002-000
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SD6830
5.3 PIN Assignment for 20PINS( DIP20, SOP20)
1
2
20
VSS
OSCIN
OSCOUT
D0
VDD
19
18
17
16
15
14
13
12
11
C/REM
TEST
K
3
4
SD6830
5
D1
F0
6
D2
F1
7
D3
F2
8
E0
F3
9
E1
F4
10
F6
F5
OUTLINE 20 PIN
Figure 5-3. Pin Assignment of 20Pin
5.4 PIN Description for 20 PINS
Symbol
Pin No.
I /O
Functions
I/O Type
VDD
20
-
Power Supply
Ground
VSS
1
-
TEST
OSCin
OSCout
C/REM
D0 - D3
E0 – E1
F0 – F6
K
18
2
INPUT
INPUT
Input for test ( Normally connected to VSS )
Input for oscillating
3
OUTPUT
OUTPUT
INPUT
Output for oscillating
19
1-Bit output for remote transmission
4-Bit input for key scan ( with pull-up resistor )
2-Bit input for key scan ( with pull-up resistor )
1-Bit individual output for key scan
1-Bit output
B
A
A
C
D
4 ~ 7
8 ~ 9
16 ~ 10
17
INPUT
OUTPUT
OUTPUT
KSI-W002-000
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SD6830
5.5 I/O CIRCUIT SCHEMATICS
TYPE A
TYPE B
VDD
VDD
30ΚΩ∼150ΚΩ
PIN
PIN
DATA
CARRIER
CLOCK
PIN
DATA
VSS
VSS
TYPE C
TYPE D
VDD
VDD
PIN
PIN
DATA
STOP
DATA
VSS
VSS
Note : If STOP mode is specified, the TYPE C output becomes “L” state and the TYPE B output becomes floating
state, the TYPE D output maintains previous state
Figure 5-5. I/O Circuit Schematics
KSI-W002-000
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SD6830
6. Basic Function Block
6.1 Program Counter (PC)
Program counter is used to indicate the address of the next instruction to be executed.
The 10-bit program counter consists of two registers, PCH(4-bit) and PCL(6-bit).
This is a polynomial counter.
6.2 Program Memory (ROM)
Program memory is used to store user-specified program. This consists of a 1024 x 8-bit.
It is organized in 16 pages and each page is 64 bytes long. For page-in addressing, all
instructions excluding JMPL and CALL can be executed by page. In order to execute jump
or call in page, JMP or CAL is suitable. For page-to-page addressing, JMPL or CALL must be
used.
PROGRAM COUNTER
PCH (4-BIT)
PCL (6-BIT)
PAGE 0
000h
0
1
2
3
PAGE 15
60
61
62
63
3
RESET
ADDRESS
63
PROGRAM MEMORY
KSI-W002-000
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SD6830
6.3 Data Memory (RAM)
Data memory is used to store various type of processing data. This consists of a 32-nibble,
which is organized into two files of 16 nibbles each. RAM addressing is indirectly
implemented by a two registers; H, L. It’s upper 1-bit register (H) selects one of two files
and its lower 4-bit register (L) selects one of 16 nibbles in the selected file.
REG H (1-bit)
REG L ( 4-bit )
FILE 0
F0
F1
F2
F3
F4
F5
F6
F7
FILE 1
0
1
2
3
1
2
3
Lower
3-bit
4
PORT
F
12
13
14
15
13
14
15
DATA MEMORY
Figure 6-2. Data Memory Map
6.4 Stack Register (SK)
Stack register is used to store return address and provide a particularly mechanism for
transferring control between programs. Two level hardware push/pop stacks are
manipulated by CAL, CALL, and RET instructions. CAL/CALL instructions push the current
program counter value, incremented by “1”, into stack level 1. Stack level 1 is
automatically pushed to level 2.
If more than two subsequent CAL/CALL are executed, only the most recent two return
addresses are stored. RET instruction load the contents of stack level 1 into the program
counter while stack level 2 gets copied into level 1. If more than two subsequent RET are
executed, the stack will be filled with the address previously stored in level 2.
KSI-W002-000
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SD6830
6.5 Arithmetic and Logic Unit (ALU)
This unit is used to perform arithmetic and logical operations such as addition,
comparison, and bit manipulation.
6.6 Carry Flag (CY)
The carry flag contains the carry generated by the arithmetic and logical unit immediately
after an operation. The set carry (SETB CY) and clear carry (CLRB CY) instructions allow
direct access for setting and clearing this flag.
6.7 Skip Flag (SF)
The skip flag is a 1-bit register, which enables programs to conditionally skip an instruction.
All instructions are executed when this flag is “0”. But if SF is “1”, the program executes
NOP instruction and resets SF to “0”. Then program execution proceeds.
The following instructions affect the skip flag
Instructions
Set conditions of SF
ADD n
INC L
If carry occurs
(L) = 0
Arithmetic
IF0 @HL.b
IF0 CY
IFEQU @HL
M[HL].b = 0
(CY) = 0
(A) = M[HL].b
Compare
IFEQU n
(A) = n
STA @HL+
XCH @HL+
(L) = 0
(L) = 0
Data Transfer
The instructions, which doesn’t affect the skip flag but have a skip condition, are as follows.
Instructions
Skip conditions
If it is continuous, skip next same
instruction.
If it is continuous, skip next same
Data
Transfer
LDA n
LDL n
instruction.
If SETB H or CLRB H are continuous,
skip next
SETB H or CLRB H instruction.
Bit
SETB H
CLRB H
Manipulate
KSI-W002-000
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SD6830
6.8 Registers
Register A
Register A, called the accumulator, plays a central role, is used to store an input or an
output operand (result) in the execution of most instructions. It consists of 4-bit.
Register B
Register B is used to store a temporary data in CPU. It consists of 4-bit.
Register H
Register H is used to indicate an address of the data memory in conjunction with register L.
It consists of 1-bit, which is related with the bit 0 of accumulator
Register L
Register L is used to indicate an address of the data memory in conjunction with register H,
Also lower 3-bit can be used to indicate the bit position of the port F. It consists of 4-bit
Register Z
Register Z is used to select a carrier frequency. The carrier frequency must be selected
before Port C data write operation. It consists of 3-bit.
Register Z
Carrier frequency
Bit 2
Bit 1
Bit 0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FSYS/12, 1/2 duty
FSYS/12, 1/3 duty
FSYS/12, 1/4 duty
FSYS/8, 1/2 duty
FSYS/8, 1/4 duty
FSYS/11, 4/11 duty
No carrier
No carrier
KSI-W002-000
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SD6830
6.9 I /O Ports
Port C/REM
Port C/REM is a 1-bit output port, which is related with the bit 3 of accumulator, with CMOS
N-channel open drain, which have large current sink capability, for I.R.LED drive.
This output can be configured as carrier frequency by programming the register Z and port
C data. This pin is put into the high-impedance state in stop mode.
Port D
Port D is a 4-bit input port with pull-up resistor. Forcing any input pins to “L” state, system
reset occurs and it starts to operate from the reset address.
Port E
Port E is a 4-bit input port with pull-up resistor. Forcing any input pins to “L” state, system
reset occurs and it starts to operate from the reset address.
Port F
Port F is an 8-bit output port with N-channel open drain. Each output which specified by the
lower 3-bit of register L can be set and reset individually. All F pins are put into the low
state in stop mode.
Port G
Port G is a 1-bit output port with N-channel open drain. When stop mode is specified, this
pin still remains in the previous state. Set this pin to appropriate state before entering
stop mode for visible LED or key scan application.
Port K
Port K is a 1-bit output port with N-channel open drain. When stop mode is specified, this
pin still remains in the previous state. Set this pin to appropriate state before entering stop
mode for visible LED or key scan application.
KSI-W002-000
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SD6830
6.10 Carrier frequency generator
One of seven carrier frequencies can be selected and transmitted through the C/REM pin by
programming the register Z and port C.
Fosc/12 (1/2
Fosc/12 (1/3
Fosc/12 (1/4
Fosc/8 (1/2 duty )
Fosc/8 (1/4 duty )
Fosc/11 (4/11 duty )
V dd ( No carrier )
duty )
duty )
duty )
C/REM
7×1
MUX
V SS
3
Port C
DATA
Register Z output
Fsys
Port C DATA
C/REM OUTPUT
(Fsys/12, 1/2 duty)
C/REM OUTPUT
(Fsys/12, 1/3 duty)
C/REM OUTPUT
(Fsys/12, 1/4 duty)
C/REM OUTPUT
(Fsys/8, 1/2 duty)
C/REM OUTPUT
(Fsys/8, 1/4 duty)
C/REM OUTPUT
(Fsys/11, 4/11
duty)
C/REM OUTPUT
(No carrier)
Figure 6-3 PORT C/REM and Carrier Output
KSI-W002-000
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SD6830
6.11 Watchdog timer (WDT)
The watchdog timer provides the means to return to a reset condition when a system
malfunction occurs and the program enters an infinite loop caused by noise or any
abnormal state.
Also this timer have a function of oscillation stabilization timer. This is a 13-bit counter,
counts the clock which is divided twelve (FSYS/12). In the stop mode the oscillation circuit
stops but when a key input is detected (Port D, Port E) oscillation starts. When 12288 clock
cycles have been counted, the program will be executed from reset address (000H). If the
port C data register’s value does not change from “L” to “H” before the timer counts 98304
clock cycles, a device reset condition is generated.
The oscillator stabilization time : 12/FSYS * 210 = 1/FSYS * 12288 = 27mS (@455KHz)
The time-out period
: 12/FSYS * 213 = 1/FSYS * 98304 = 216mS (@455KHz)
WatchdogTimer (13-bit)
OPSTART
Operating Start
ToReset Logic
OVERFLOW
Fsys/12
CLK
RESET
Power-on Reset Active
Stop Mode Active
PORT CData : Low toHigh Transition
Normal
mode
Stop
mode
Normal
mode
OSCOUT
PC
27mS(Min.)
WDT
counting value
98304
Watchdog Timer
Overflow
PORT C Data
Low toHigh
PORTCData
Low to High
STOP
Instruction
12288
0
Time
Figure 6-4. Function of Watchdog Timer
KSI-W002-000
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SD6830
6.12 Power-on reset
The SD6830 incorporates an on-chip power-on reset circuitry which provides internal chip
reset for most power-up situations. The power-on reset circuit and the watchdog timer are
closely related. On power-up the power-on reset circuit is active and watchdog timer is
reset. After the reset time, which is in proportion to the rate of rise of VDD, watchdog timer
begins counting. After the oscillator stabilization time, which is typically 27mS in
FSYS=455KHz, program execution proceeds from reset address (000H).
VDD PIN
SD6830
VDD
VDD
7pF
1.8V
Internal
/POR
Internal /POR
0.3VDD
2Mohm
0
VSS
RESET TIME
Figure 6-5. Built-in Power-on Reset
6.13 Stop mode
The SD6830 support the stop mode to reduce power consumption. This mode is entered
when the STOP instruction is executed during key inputs are not active. Activating any key
inputs (Port D, Port E) the device is awakened from stop mode and restarts to operate from
reset address. When the device is released from stop mode, following module’s data must
set to appropriate value in reset routine: PORT G and PORT K.
In stop mode, the oscillator is stopped and the each port state is as follows.
Port C/REM become inactive state. (“floating” for including I.R.LED driver, “L” otherwise)
Port F become “L” state (“floating” after the reset release)
Port G and Port K retain previous state.
KSI-W002-000
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SD6830
VDD
SD6830
Key input
( PORT D or
PORTE )
4
4
PORT D
PORT E
STOP instruction
Internal
/STOP
Stop
mode
Normal
mode
Stop
mode
STOP
STOP
instruction
OSCOUT
RESET
internal /POR
WDT overflow
27mS(Min.)
Figure 6-6. Rest structure and Release Timing for STOP Mode to Normal Mode
6.14 OSC Divide Option
The OSC divide option provides a maximum 1MHz system clock (FSYS). FOSC which is
generated in oscillation circuit is divided eight or non-divide to produce FSYS.
This dividing ratio will be selected by mask option.
FOSC : Oscillator clock,
FSYS : System clock (FOSC or FOSC/8)
MASK OPTION
OSC IN
DIVIDE-8
F
OSC
FSYS
OSC
OSC OUT
Figure 6-7 OSC Divide Option
7. Electrical Specifications
7.1 Absolute maximum ratings
Symbols
VDD
Parameters
Supply Voltage
Conditions
Ratings
-0.3 ~ 6.0
Units
V
Ta=25℃
VI
Input Voltage
-0.3 ~ VDD + 0.3
-0.3 ~ VDD + 0.3
-20 ~ 85
V
VO
Output Voltage
V
℃
TOPR
TSTG
Operating temperature
Storage Temperature
-
-
℃
-40 ~ 125
KSI-W002-000
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SD6830
7.2 Recommended operating conditions
(VDD = 3V ± 10%, Ta=-20 ~ 70℃, unless otherwise noted)
Symbols
VDD
Parameters
Min.
1.8
Typ.
Max.
3.6
Units
Supply Voltage
V
-V
V
"H" input Voltage, all input pins
except OSCIN
VIH1
0.7VDD
VDD-0.3
0
VDD
VDD
0
VDD
VIH2
"H" input Voltage, OSCIN
VDD
"L" input Voltage, all input pins
except OSCIN
VIL1
0.3 VDD
0.3
V
VIL2
"L" input Voltage, OSCIN
Non-divide
0
0
V
250
2
1000
6
KHz
MHz
option
Oscillating
FOSC
frequency
Divide-8 option
7.3 Electrical characteristics
(VDD = 3V ± 10%, Ta= 25℃, unless otherwise noted)
Symbols
Parameters
Test Conditions
Min. Typ. Max. Units
250KHz≤ FOSC≤ 3.9MHz
3.9MHz≤ FOSC≤ 6.0MHz
1.8
2.2
3.0
3.0
3.6
3.6
V
V
VDD
Supply Voltage
IOH
"H" output current
"L" output current
VO = 2.0V, Port C
VO = 0.4V, Port C
-6
-9
3
-14
4.5
mA
mA
IOL0
1.5
IOL1
IOL2
IOL3
ILIH1
ILIH2
VO = 0.4V, Port C
VO = 0.4V, Port F
VO = 0.4V, Port G/K
VI = VDD, Port D/E
VI = VDD, OSCIN
180
0.5
1.5
-
210
1.0
3.0
-
240
2.0
4.5
3
mA
mA
mA
㎂
"L" output current
"H" input leakage current
㎂
-
3
10
㎂
㎂
ILIL
"L" input leakage current
"H"output leakage current
VI = VSS, OSCIN
-0.6
-
-3
-
-10
1
ILOH
VO = VDD, Port C/F/G/K
KΩ
RPULL-UP
Pull-up resistance of input Port VI = 0V, VDD=3V
30
70
150
IDD
IDDS
FSYS
Supply current at normal mode
Supply current at stop mode
Clock frequency
0.5
1.0
1.0
mA
㎂
250
250
2
1000 KHz
1000 KHz
Non-divide option
Oscillator frequency
FOSC
Divide-8 option
6
MHz
KSI-W002-000
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SD6830
8. Packing Outlines and Dimensions
24 SOP-300
0.4160(10.566)
0.3980(10.109)
BASE PLANE
SEATING PLANE
0.0118(0.300)
0.2980(7.569)
0.2920(7.417)
0.0040(0.102)
0.0125(0.318)
0.0091(0.231)
0.1040(2.642)
0.0940(2.388)
UNIT : INCH (MM)
20 SOP-300
0.4160(10.566)
0.3980(10.109)
BASE PLANE
SEATING PLANE
0.0118(0.300)
0.2980(7.569)
0.2920(7.417)
0.0040(0.102)
0.0125(0.318)
0.0091(0.231)
0.1040(2.642)
0.0940(2.388)
UNIT : INCH (MM)
KSI-W002-000
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SD6830
24 DIP-300
0.140(3.556)
0.120(3.048)
0.035(0.889)
0.020(0.508)
0.145(3.683)
0.135(3.429)
0.180(4.572)
0.155(3.937)
UNIT : INCH (MM)
20 DIP-300
0.140(3.556)
0.120(3.048)
0.035(0.889)
0.020(0.508)
0.145(3.683)
0.135(3.429)
0.180(4.572)
0.155(3.937)
UNIT : INCH (MM)
KSI-W002-000
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SD6830
9. Instructions
9.1 Symbol Description
SYMBOL
DESCRIPTIONS
A , B , L
4 Bit Register
H
1-Bit Register
3-Bit Register
Z
PCH
The Higher 4-Bit of the Program Counter
The Lower 6-Bit of the Program Counter
10-Bit Program Counter ( Consisting of the PCH and PCL )
10-Bit Stack Register
PCL
PC
SK
CY
1-Bit Carry Flag
SF
1-Bit Skip Flag
C, G, K
1-Bit Port
D, E
4-Bit Port
F
8-Bit Port
←
Direction of Data Flow
M[(HL)] or @HL
The Contents of Data Memory Addressed by Reg HL
M[(HL)].b or @HL.b The Specified Bit’s Content of Data Memory Addressed by Reg HL
@HL+
addr
n
As a result of execution, increment L by one
Address
immediate data
KSI-W002-000
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SD6830
9.2 Opcode Map
1000b~ 1100b~
1011b 1111b
MSB
0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b
LSB
0h
1h
2h
3h
4h
5h
6h
7h
8h~Bh Ch~Fh
ADDC
@HL
XCH
@HL+
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
0h
NOP
LDA
H
XCH
@HL
1h STOP
2h
CALL
addr
LDA
E
INC
L
STA
LDA
@HL
3h
H
RRC
LDZ
n
LDA
D
CLRB
H
4h
LDA
B
SETB
H
5h
IF0
@HL.b
JMPL
addr
LDA
L
6h
7h
NOT
LDL
n
ADD
n
LDA
n
JMP
addr
CAL
addr
CLRB
STA
@HL+
8h
CY
SETB
STA
@HL
9h
CY
CLRB
@HL.b
CLRB
Ah
F
SETB
Bh
F
STA
IF0
CY
CLRB
G
Ch
C
SETB
G
Dh
RET
SETB
@HL.b
IFEQU
STA
B
CLRB
K
Eh
n
IFEQU
Fh
STA
L
SETB
K
@HL
KSI-W002-000
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SD6830
9.3 Instruction Descriptions
ADD n
Binary code
Syntax
: 0110xxxx
: [<label>] ADD n
Operation
Flags
: (A) ← (A) + n, n=0~15 ( n must be decimal number )
: CY: Unaffected. SF: Set to one if carry occurs, cleared otherwise.
Words/Cycles : 1/1
Description
the accumulate.
Example
: Adds an immediate data to the accumulator and stores the result in
: ADD 8
JMP 035
JMP 05F
;
Add 8 to A.
;
Jump to 035 if 0≤ A≤ 7
Jump to 05F if 8≤A≤15
;
ADDC @HL
Binary code
Syntax
00010000
: [<label>] ADDC @HL
Operation
Flags
: (A) ← (A) + M[(HL)] + (CY), (CY) ← Carry
: CY: Set on carry-out of (A) + M[(HL)] + (CY)
SF: Unaffected
Words/Cycles : 1/1
Description
: Adds the contents of the accumulator, the contents of data memory
addressed by registers H and L, and the carry bit. It stores the result in
the accumulator and the carry flag.
Example
: CLRB
LDA
CY ; Clear CY to zero
5
; Load 5 to A
; Clear H to zero
; Load 6 to L
CLRB
LDL
H
6
ADDC @HL ; Add the content of A, M[(06)], and the content of CY
CAL addr
Binary code : 11xxxxxx
Syntax
: [<label>] CAL addr
Operation
: (SK1) ← (SK0), (SK0) ← (PC) + 1, (PCL) ← addr, addr = 000 ~ 03F
( addr must be hexadecimal number )
Flags
: CY: Unaffected
SF: Unaffected
Words/Cycles : 1/1
Description
: Calls a subroutine located at the indicated address and pushes the current
contents of the program counter to the top of stack. The indicated address
must be within the current page.
Example
: CAL 100 : Call subroutine located at the 100. The 100 must be logical
address and within the current page.
KSI-W002-000
20
SD6830
CALL addr
Binary code : 010100xx
xxxxxxxx
Syntax
:
[<label>] CALL addr
Operation
: (SK1) ← (SK0), (SK0) ← (PC) + 1, (PC) ← addr, addr = 000 ~ 3FF
( addr must be hexadecimal number )
Flags
: CY: Unaffected
SF: Unaffected
Words/Cycles : 2/2
Description
: Calls a subroutine located at the indicated address and pushes the
current contents of the program counter to the top of stack. The
indicated address can be anywhere in the full 1Kbyte memory space.
: CALL 2FF ; Call subroutine located at the 2FF.
The 2FF must be logical address.
Example
CLRB @HL.b
Binary code : 010110xx
Syntax
Operation
Flags
: [<label>] CLRB @HL.b
: M[(HL)].b ← 0
: CY: Unaffected
SF: Unaffected
Words/Cycles : 1/1
Description : Clears the specified bit of data memory addressed by registers H and L
to zero.
Example
: CLRB H
LDL 10
; Clear H to 0
; Load 10 to L. The 10 must be decimal number.
CLRB @HL.0 ; Clear the bit 0 of M[(0A)] to 0.
CLRB CY
Binary code : 00001000
Syntax
Operation
Flags
: [<label>] CLRB CY
: (CY) ← 0
: CY: Set to zero
SF: Unaffected
Words/Cycles: 1/1
Description : Clears the carry flag to zero.
Example
:
CLRB CY ; Clear CY to zero
KSI-W002-000
21
SD6830
CLRB F
Binary code
Syntax
:
:
:
:
:
00001010
[<label>] CLRB F
F.(L) ← 0
Operation
Flags
CY: Unaffected
1/1
SF: Unaffected
Words/Cycles
Description
L to zero.
Example
: Clears the specified bit of port F addressed by the lower 3-bit of register
: LDL 13 ; Load 13 to L
CLRB
F
: Clears the bit 5 of F to zero
CLRB G
Binary code
Syntax
: 00101100
: [<label>] CLRB G
: G.(L) ← 0
Operation
Flags
: CY: Unaffected
SF: Unaffected
Words/Cycles
Description
Example
:
1/1
: Clears the port G to zero.
:
CLRB
G
; Clear G to zero
CLRB H
Binary code
Syntax
:
:
:
:
00100100
[<label>] CLRB H
(H) ← 0
Operation
Flags
CY: Unaffected
SF: Unaffected
1/1
Words/Cycles
Description
:
: Clears the contents of register H to zero. Skip this instruction if it or
SETB H was used just before.
: IFEQU 1
Example
CLRB H
SETB H
; Clear H to zero and skip continuous SETB H/CLRB H, if (A)≠ 1
; Sets H to one and skip continuous SETB H/CLRB H, if (A)=1
KSI-W002-000
22
SD6830
CLRB K
Binary code : 00101110
Syntax
Operation
Flags
: [<label>] CLRB K
: (K) ← 0
: CY: Unaffected
SF: Unaffected
Words/Cycles : 1/1
Description
Example
: Clears the port K to zero.
: CLRB K ; Clear K to zero.
IF0 @HL.b
Binary code
Syntax
: 000001xx
: [<label>] IF0 @HL.b
: M[(HL)b] = 0
Operation
Flags
: CY: Unaffected
SF: Set to one if equal, cleared otherwise
: 1/1
Words/Cycles
Description
and L with zero.
Example
: Compares the specified bit of data memory addressed by registers H
: SETB H
LDL
;
Set H to one
Load 4 to L
4
;
IF0 @HL.3 ; Compare the bit 3 of M[(14)] with zero
JMP 020 ; Jump to 020 if not equal
JMP 030 ; Jump to 030 if equal
IF0 CY
Binary code
Syntax
:
00011100
:
:
:
[<label>] IF0 CY
Operation
Flags
(CY) = 0
CY : Unaffected
SF : Set to one if equal, cleared otherwise
: 1/1
Words/Cycles
Description
Example
:
Compares the carry flag with zero.
IF0 CY ; Compare the content of CY to zero
JMP 030 ; Jump to 030 if not equal
JMP 040 ; Jump to 040 if equal
:
KSI-W002-000
23
SD6830
IFEQU @HL
Binary code
Syntax
:
:
:
:
00001111
[<label>] IFEQU @HL
Operation
Flags
(A) = M[(HL)]
CY : Unaffected
SF : Set to one if equal, cleared otherwise
1/1
Words/Cycles
Description
:
:
Compares the contents of accumulator with the contents of data
memory addressed by registers H and L.
Example
:
LDA 14
; Load 14 to A, and 14 must be decimal number
; Sets H to one
SETB
LDL
H
4
; Loads 4 to L
IFEQU @HL ; Compares 14 with M[(14)]
JMP 050 ; Jump to 050 if not equal
JMP 060 ; Jump to 060 if equal
IFEQU n
Binary code
Syntax
:
:
:
:
00001110
0111xxxx
[<label>] IFEQU n
Operation
Flags
(A) = n, n = 0 ~15 ( n must be decimal number )
CY: Unaffected
SF: Set to one if equal, cleared otherwise
2/2
Words/Cycles
Description
Example
:
: Compares the contents of accumulator with an immediate data.
:
IFEQU 15 ; Compare the contents of accumulator with 15
JMP 070 ; Jump to 070 if not equal
JMP 080 ; Jump to 080 if equal
INC L
Binary code
Syntax
:
:
:
:
00100010
[<label>] INC L
(L) ← (L) + 1
Operation
Flags
CY : Unaffect
SF:As a result of execution, set to one if the contents
of register L are zero, cleared otherwise.
Words/Cycles
Description
Example
:
:
1/1
The contents of register L are incremented by one.
LDL 14 ; Load 14 to L
:
INC
INC
L
L
; The contents of L are incremented by one
; The contents of L are incremented by one
JMP 090 ; It is skipped because the contents of L is “0”
JMP 0A0 ; Jump to 0A0
KSI-W002-000
24
SD6830
JMP addr
Binary code : 10xxxxxx
Syntax
Operation
Flags
: [<label>] JMP addr
: (PCL) ← addr, addr = 00 ~ 3F ( addr must be hexadecimal number )
: CY : Unaffected
SF : Unaffected
Words/Cycles
Description
: 1/1
: Jumps unconditionally to the indicated address. The indicated address
must be within the current page.
Example
: JMP 2EF ; Jump unconditionally to the 2EF. The 2EF address must be
within the current page.
JMPL addr
Binary code : 010101xx
xxxxxxxx
Syntax
Operation
Flags
: [<label>] JMPL addr
: (PC) ← addr, addr = 000 ~ 3FF (addr must be hexadecimal number. )
: CY : Unaffected
SF : Unaffected
Words/Cycles : 2/2
Description
: Jumps unconditionally to the indicated address. The indicated address
can be anywhere in the full 1K-byte memory space.
: JMPL 100 ; Jump unconditionally to 100
Example
LDA @HL
Binary code : 00100011
Syntax
Operation
Flags
: [<label>] LDA @HL
: (A) ← M[(HL)]
: CY : Unaffected
SF : Unaffected
Words/Cycles : 1/1
Description
: Loads the contents of memory addressed by registers H and L into the
accumulator.
: SETB
Example
H
;
Set H to 1
LDL
LDA
0
;
Load 0 to L
@HL ;
Load M[(10)] into A
KSI-W002-000
25
SD6830
LDA n
Binary code : 0111xxxx
Syntax
Operation
Flags
: [<label>] LDA n
: (A) ← n, n=0~15 ( n must be decimal number. )
: CY : Unaffected
SF : Unaffected
Words/Cycles : 1/1
Description : Loads an immediate data into the accumulator. Skip this instruction if it
was used just before.
Example
: STA
LDA
B
15 ; Load 15 into A.
LDA
4
7
; It is skipped because this instruction was used just before
; It is skipped because this instruction was used just before
LDA
JMP 0B0 ; Jump to 0B0
LDA B
Binary code : 00010101
Syntax
Operation
Flags
: [<label>] LDA B
: (A) ← (B)
: CY : Unaffected
SF : Unaffected
Words/Cycles : 1/1
Description : Loads the contents of register B into the accumulator.
Example
:
LDA
B
; Load the contents of B into A
LDA D
Binary code : 00010100
Syntax
Operation
Flags
: [<label>] LDA D
: (A) ← (D)
: CY : Unaffected
SF : Unaffected
Words/Cycles : 1/1
Description : Loads the contents of port D into the accumulator.
Example
: LDA
D
; Load the contents of D into A
KSI-W002-000
26
SD6830
LDA E
Binary code
Syntax
: 00010010
: [<label>] LDA E
: (A) ← (E)
Operation
Flags
: CY : Unaffected
SF : Unaffected
Words/Cycles : 1/1.
Description
Example
: Loads the contents of port E into the accumulator
: LDA E ; Load the contents of E into A
LDA H
Binary code
Syntax
: 00010001
: [<label>] LDA H
: (A) ← (H)
: CY : Unaffected
SF : Unaffected
: 1/1
Operation
Flags
Words/Cycles
Description
Example
: Loads the contents of register H into the bit 0 of accumulator.
: LDA H ; Load the content of H into the bit 0 of A
LDA L
Binary code : 00010110
Syntax
Operation
Flags
:
[<label>] LDA L
: (A) ← (L)
: CY : Unaffected
SF : Unaffected
Words/Cycles : 1/1
Description : Loads the contents of register L into the accumulator.
Example
: LDA
L
; Load the contents of L into A
KSI-W002-000
27
SD6830
LDL n
Binary code : 0100xxxx
Syntax
Operation
Flags
: [<label>] LDL n
: (A) ← n, n = 0 ~ 15 ( n must be decimal number )
: CY : Unaffected
SF : Unaffected
Words/Cycles : 1/1
Description : Loads an immediate data to the register L. Skip this instruction if it was
used just before.
Example
: LDA
LDL
3
8
4
; Load 8 to L
LDL
; It is skipped because this instruction was used just before
JMP 0C0 ; Jump to 0C0
LDZ n
Binary code
Syntax
:
:
:
00110xxx
[<label>] LDZ n
Operation
Flags
(A) ← n, n = 0 ~ 7 ( n must be decimal number )
:
CY : Unaffected
SF : Unaffected
Words/Cycles
Description
Example
:
:
1/1
Load an immediate data into the register Z.
:
LDZ
0
; Load 0 into Z. The 0 must be decimal number
NOP
Binary code
Syntax
:
00000000
:
:
:
[<label>] NOP
(PC) ← (PC) + 1
CY : Unaffected
SF : Unaffected
1/1
Operation
Flags
Words/Cycles
Description
Example
:
:
No operation.
NOP ; No operation
:
KSI-W002-000
28
SD6830
NOT
Binary code
Syntax
:
:
:
:
00010111
[<label>] NOT
(A) ← /(A)
Operation
Flags
CY : Unaffected
SF : Unaffected
Words/Cycles : 1/1
Description
Example
:
The contents of accumulator are 1’s complemented.
LDA 7
:
NOT
; 1’s complement 7, then leaves 8 in A
RET
Binary code : 00011101
Syntax
Operation
Flags
: [<label>] RET
: (PC) ← (SK0), (SK0) ← (SK1)
: CY: Unaffected
SF: Unaffected
Words/Cycles : 1/1
Description
Example
: Returns from the subroutine to main routine.
: RET ; Returns from the subroutine to main routine
RRC
Binary code : 00010011
Syntax
Operation
Flags
: [<label>] RRC
: (A.b) ← (A.b+1) (A.3) ← (CY) (CY) ← (A.0)
: CY : Set to bit 0 of the accumulator
SF : Unaffected
Words/Cycles : 1/1
Description
: Shifts the contents of accumulator 1-bit to the right through the carry.
The carry bit content shifts into the bit 3 of accumulator, and the bit 0 of
accumulator is shifted into the carry bit.
Example
: SETB CY ; Set CY to one.
LDA
RRC
5
; Load 5 to A
; CY becomes zero, and the contents of A is 11
KSI-W002-000
29
SD6830
SETB @HL.b
Binary code
Syntax
: 010111xx
: [<label>] SETB @HL.b
: M[(HL)].b ← 1
: CY : Unaffected
SF : Unaffected
Operation
Flags
Words/Cycles : 1/1
Description
Example
: Sets the specified bit of memory addressed by registers H and L to one.
: CLRB H
LDL
; Clear H to zero
; Load 5 to L
5
SETB @HL.2 ; Set the bit 2 of M[(05)] to one
SETB CY
Binary code
Syntax
:
:
:
:
00001001
[<label>] SETB CY
Operation
Flags
(CY) ← 1
CY : Set to one
SF : Unaffected
Words/Cycles
Description
Example
:
:
1/1
Sets the contents of carry flag to one.
SETB CY ; Sets the content of CY to one
:
SETB F
Binary code
Syntax
:
:
:
:
00001011
[<label>] SETB F
Operation
Flags
F.(L) ← 1
CY : Unaffected
SF : Unaffected
Words/Cycles
Description
Example
:
:
1/1
Sets the specified bit of the port F addressed by register L to one.
:
LDL 4
; Loads 4 to L
SETB F ; Sets the bit 4 of F to one
KSI-W002-000
30
SD6830
SETB G
Binary code
Syntax
:
:
:
:
00101101
[<label>] SETB G
(G) ← 1
Operation
Flags
CY : Unaffected
SF : Unaffected
1/1
Words/Cycles
Description
Example
:
:
Sets the port G to one.
SETB G ; Sets the port G to one
:
SETB H
Binary code
Syntax
:
:
:
:
00100101
[<label>] SETB H
(H) ← 1
Operation
Flags
CY : Unaffected
SF : Unaffected
1/1
Words/Cycles
Description
:
:
Sets the contents of register H to one. Skip this instruction if it or SETB
H was used just before.
Example
:
IFEQU 1
SETB H ; Sets H to one and skip continuous CLRB H/SETB H, if (A)≠ 1
CLRB H ; Clear H to zero and skip continuous CLRB H/SETB H, if (A)=1
SETB K
Binary code
Syntax
:
:
:
:
00101111
[<label>] SETB K
(K) ← 1
Operation
Flags
CY : Unaffected
SF : Unaffected
1/1
Words/Cycles
Description
Example
:
:
Sets the port K to one.
SETB K ; Sets the port K to one
:
KSI-W002-000
31
SD6830
STA @HL
Binary code
Syntax
:
:
:
:
00101001
[<label>] STA @HL
M[(HL)] ← (A)
CY : Unaffected
SF : Unaffected
1/1
Operation
Flags
Words/Cycles
Description
:
:
Stores the contents of accumulator in memory addressed by registers
H and L.
Example
:
LDL
0
; Load 0 to L
; Set H to one
SETB
H
STA @HL ; Stores the contents of A in M[(10)]
STA @HL+
Binary code
Syntax
:
:
:
:
00101000
[<label>] STA @HL+
Operation
Flags
M[(HL)] ← (A), (L) ← (L) + 1
CY : Unaffected
SF : Unaffected
Words/Cycles
Description
:
:
1/1
Stores the contents of accumulator in memory addressed by registers
H and L. And then the contents of register L are incremented by one.
Example
:
LDL
15
H
; Load 15 to L
; Set H to one
SETB
STA @HL+ ; Stores the contents of A in M[(1F)]. L becomes “0”
JMP 035
JMP 045
; It is skipped because L is “0”
; Jump to 045
STA B
Binary code
Syntax
:
:
:
:
00011110
[<label>] STA B
(B) ← (A)
Operation
Flags
CY : Unaffected
SF : Unaffected
1/1
Words/Cycles
Description
Example
:
:
Stores the contents of accumulator in the register B.
:
STA
B
; Stores the contents of A in B
KSI-W002-000
32
SD6830
STA C
Binary code
Syntax
:
:
:
:
00001100
[<label>] STA C
Operation
Flags
(C) ← (A)3
CY : Unaffected
SF : Unaffected
Words/Cycles
Description
Example
:
:
1/1
Stores the bit 3 of accumulator in the port C.
STA C ; Stores the bit 3 of A in C
:
STA H
Binary code
Syntax
:
:
:
:
00000011
[<label>] STA H
Operation
Flags
(H) ← (A)0
CY : Unaffected
SF : Unaffected
Words/Cycles
Description
Example
:
:
1/1
Stores the bit 0 of accumulator in the register H.
:
STA
H
; Store the bit 0 of A in H
STA L
Binary code
Syntax
:
:
:
:
00011111
[<label>] STA L
Operation
Flags
(L) ← (A)
CY : Unaffected
SF : Unaffected
Words/Cycles
Description
Example
:
:
1/1
Stores the contents of accumulator in the register L.
STA L ; Stores the contents of A in L
:
KSI-W002-000
33
SD6830
STOP
Binary code
Syntax
:
:
:
:
:
00000001
[<label>] STOP
Operation
Flags
Stop the oscillation of the oscillator, and reset PORT F to zero
CY : Unaffected SF : Unaffected
Words/Cycles
Description
Example
1/1
:
:
Stops the oscillation of the oscillator.
STOP
XCH @HL
Binary code
Syntax
:
:
:
:
:
:
00100001
[<label>] XCH @HL
(A) ↔ M[(H,L)]
CY : Unaffected SF : Unaffected
1/1
Operation
Flags
Words/Cycles
Description
Exchanges the accumulator with the contents of the data memory
addressed by registers H and L without going through an
intermediate location
: LDL Load 3 to L
SETB ; Set H to one
.
Example
3
;
H
XCH @HL ; Exchanges the contents of A with M[(13)] without
going through an intermediate location
XCH @HL+
Binary code
Syntax
:
:
:
:
00100000
[<label>] XCH @HL+
Operation
Flags
(A) ↔ M[(H,L)], (L) ← (L) + 1
CY : Unaffected
SF: As a result of execution, set to one if the contents of register L are
zero, cleared otherwise
Words/Cycles
Description
:
:
1/1
Exchanges the accumulator with the contents of the data memory
addressed by registers H and L without going through an intermediate
location. As a result of execution, the contents of register L are
incremented by one.
Example
:
SETB
LDL
H
;
15
; Load 15 into L
CH @HL+
; Exchanges A with M[(1F)] without going through an
intermediate location. As a result of execution, the
contents of L are “0”
JMP
JMP
055
065
; It is skipped because L is “0”
; Jump to 065
KSI-W002-000
34
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