MC145407P [LANSDALE]
5 Volt Only Driver/Receiver RS232 EIA-232-E and CCITT V.28; 5伏只有驱动器/接收器RS232 EIA- 232 -E和CCITT V.28
| 型号： | MC145407P |
| 厂家： | 
LANSDALE SEMICONDUCTOR INC. |
| 描述： | 5 Volt Only Driver/Receiver RS232 EIA-232-E and CCITT V.28 |
| 文件： | 总8页 (文件大小：678K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ML145407
5 Volt Only Driver/Receiver
RS232 EIA–232–E and CCITT V.28
Legacy Device: Motorola MC145407
The ML145407 is a silicon–gate CMOS IC that combines three
drivers and three receivers to fulfill the electrical specifications of
RS232 EIA–232–E and CCITT V.28 while operating from a single + 5
V power supply. A voltage doubler and inverter convert the + 5V to
10 V. This is accomplished through an on–board 20 kHz oscillator
and four inexpensive external electrolytic capacitors. The three drivers
and three receivers of the ML145407 are virtually identical to those of
the ML145406. Therefore, for applications requiring more than three
drivers and/or three receivers, an ML145406 can be powered from an
ML145407, since the ML145407 charge pumps have been designed to
guarantee 5 V at the output of up to six drivers. Thus, the
ML145407 provides a high–performance, low–power, stand–alone
solution or, with the ML145406, a + 5 V only, high–performance
two–chip solution.
P DIP 20 = RP
PLASTIC DIP
CASE 738
20
1
SOG 20 = -6P
SOG PACKAGE
CASE 751D
20
1
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
P DIP 20
SOG 20
MOTOROLA
LANSDALE
MC145407P
ML145407RP
MC145407DW ML145407-6P
This device offers the following performance features:
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
• Operating Temperature Range = T –40° to +85°C
A
Drivers
7.5 V Output Swing
•
• 300Ω Power–Off Impedance
• Output Current Limiting
PIN ASSIGNMENT
1
20
• TTL and CMOS Compatible Inputs
• Slew Rate Range Limited from 4 V/µs to 30 V/µs
C2+
C1+
2
19
GND
V
CC
Receivers
• + 25 V Input Range
• 3 to 7 kΩ Input Impedance
• 0.8 V Hysteresis for Enhanced Noise Immunity
3
4
18
17
C2–
C1–
V
V
DD
SS
Charge Pumps
5
6
7
16
15
14
R
R
Rx1
Tx1
Rx2
Tx2
Rx3
DO1
DI1
• + 5 V to 10 V Dual Charge Pump Architecture
• Supply Outputs Capable of Driving Three On–Chip Drivers and
Three Drivers on the ML145406 Simultaneously
• Requires Four Inexpensive Electrolytic Capacitors
• On–Chip 20 kHz Oscillator
D
D
D
DO2
DI2
8
13
12
11
9
R
DO3
10
Tx3
DI3
D = DRIVER
R = RECEIVER
Page 1 of 8
www.lansdale.com
Issue A
ML145407
LANSDALE Semiconductor, Inc.
FUNCTION DIAGRAM
CHARGE PUMPS
OSC
GND
V
CC
+
C4
VOLTAGE
DOUBLER
VOLTAGE
INVERTER
C3
+
V
C1
C2
SS
V
DD
+
+
C1 – C1 +
C2 + C2 –
RECEIVER
DRIVER
V
DD
V
DD
V
DD
V
*
CC
15 kΩ
V
CC
Rx
+
–
DO
300
Ω
+
–
DI
LEVEL
SHIFT
Tx
5.4 k
1.4 V
V
SS
1.0 V
1.8 V
V
* Proctection circuit
SS
Page 2 of 8
www.lansdale.com
Issue A
ML145407
LANSDALE Semiconductor, Inc.
MAXIMUM RATINGS (Voltage polarities referenced to GND)
This device contains protection circuitry to
Rating
DC Supply Voltages
Symbol
Value
Unit
V
protect the inputs against damage due to high
static voltages or electric fields; however, it is
advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high imped-
ance circuit. For proper operation, it is recom-
mendedthatthevoltagesattheDIandDOpins
V
CC
– 0.5 to + 6.0
Input Voltage Range
V
IR
V
Rx1 – Rx3 Inputs
DI1 – DI3 Inputs
V
– 15 to V
+ 15
+ 0.5)
SS
– 0.5 to (V
DD
CC
DC Current per Pin
Power Dissipation
I
100
1
mA
W
be constrained to the range GND
V
V
DI CC
P
D
and GND ≤ V . Also, the voltage at
V
DO
CC
the Rx pin should be constrained to (V
Operating Temperature Range
Storage Temperature Range
T
A
– 40 to + 85
°C
°C
SS
+ 15 V), and Tx
– 15 V) ≤ V
Rx1 – Rx3
(V
DD
T
stg
– 85 to + 150
should be constrained to V
V
Tx1 – Tx3
SS
V
DD
.
Unused inputs must always be tied to
appropriate logic voltage level (e.g., GND or
V
CC
for DI, and GND for Rx).
DC ELECTRICAL CHARACTERISTICS (All polarities referenced to GND = 0 V; C1, C2, C3, C4 = 10 µF; T = – 40 to + 85°C)
A
Parameter
Symbol
Min
4.5
—
Typ
5
Max
5.5
Unit
V
DC Supply Voltage
V
CC
Quiescent Supply Current
(Outputs unloaded, inputs low)
I
1.2
3.0
mA
CC
Output Voltage
I
I
= 0 mA
= 5 mA
= 10 mA
V
8.5
7.5
6
10
9.5
9
11
—
—
V
load
load
DD
I
I
load
I
I
= 0 mA
= 5 mA
= 10 mA
V
– 8.5
– 7.5
– 6
– 10
– 9.2
– 8.6
–11
—
—
load
load
SS
load
RECEIVER ELECTRICAL SPECIFICATIONS
= + 5 V 10%; C1, C2, C3, C4 = 10 µF; T = – 40 to + 85°C)
(Voltage polarities referenced to GND = 0 V; V
CC
A
Characteristic
Symbol
Min
Typ
Max
Unit
Input Turn–on Threshold
= V
Rx1 – Rx3
Rx1 – Rx3
V
1.35
1.8
2.35
V
on
V
DO1 – DO3
OL
Input Turn–off Threshold
= V
V
off
0.75
1.0
1.25
V
V
DO1 – DO3
OH
Input Threshold Hysteresis (V – V
)
Rx1 – Rx3
Rx1 – Rx3
DO1 – DO3
V
0.6
3.0
0.8
5.4
—
V
kΩ
V
on off
hys
Input Resistance
R
7.0
in
High–Level Output Voltage
V
OH
V
= – 3 V to – 25 V
= – 20 µA
= – 1 mA
Rx1 – Rx3
I
I
V
V
– 0.1
—
4.3
—
—
OH
OH
CC
CC
– 0.7
Low–Level Output Voltage
= + 3 V to + 25 V
DO1 – DO3
V
OL
V
V
Rx1 – Rx3
I
I
= + 20 µA
= + 1.6 mA
—
—
0.01
0.5
0.1
0.7
OL
OL
Page 3 of 8
www.lansdale.com
Issue A
ML145407
LANSDALE Semiconductor, Inc.
DRIVER ELECTRICAL SPECIFICATIONS
(Voltage polarities referenced to GND = 0 V: V
= +5 V 10%; C1, C2, C3, C4 = 10 µF; T = –40 to +85°C)
A
CC
Characteristic
Symbol
Min
Typ
Max
Unit
Digital Input Voltage
Logic 0
Logic 1
DI1 – DI3
DI1 – DI3
V
V
—
2.0
—
—
0.8
—
IL
V
IH
Input Current
GND ≤ V
DI1 – DI3
I
in
—
—
1.0
µA
V
≤ V
CC
Output High Voltage
= Logic 0, R = 3.0 kΩ
Tx1 – Tx3
Tx1 – Tx6*
V
OH
6
5
7.5
6.5
—
—
V
DI1 – DI3
Output Low Voltage
= Logic 1, R = 3.0 kΩ
L
Tx1 – Tx3
Tx1 – Tx6*
V
OL
– 6
– 5
– 7.5
– 6.5
—
—
V
V
DI1 – DI3
L
Off Source Impedance (Figure 1)
Tx1 – Tx3
Tx1 – Tx3
Tx1 – Tx3 shorted to GND**
Tx1 – Tx3 shorted to 15 V***
Z
300
—
—
Ω
off
Output Short–Circuit Current
I
mA
SC
V
CC
= + 5.5 V
—
—
—
—
60
100
*Specifications for an ML145407 powering an ML145406 with three additional drivers/receivers.
**Specificationis for one Tx output pin to be shorted at a time. Should all three driver outputs be shorted simultaneously, device power dissipation
limits could be exceeded.
***This condition could exceed package limitations.
SWITCHING CHARACTERISTICS (V
CC
= + 5 V 10%; C1, C2, C3, C4 = 10 µF; T = – 40 to + 85°C; See Figures 2 and 3)
A
Characteristic
Symbol
Min
Typ
Max
Unit
Drivers
Propagation Delay Time
Low–to–High
Tx1 – Tx3
t
µs
PLH
R
= 3 kΩ, C = 50 pF or 2500 pF
—
—
0.5
0.5
1
1
L
L
High–to–Low
= 3 kΩ, C = 50 pF or 2500 pF
t
PHL
SR
R
L
L
Output Slew Rate
Minimum Load: R = 7 kΩ, C = 0 pF
Tx1 – Tx3
V/µs
µs
—
9.0
—
30
—
L
L
Maximum Load: R = 3 kΩ, C = 2500 pF
4.0
L
L
Receivers (C = 50 pF)
L
Propagation Delay Time
Low–to–High
DO1 – DO3
t
t
—
—
—
—
—
—
1
PLH
High–to–Low
Output Rise Time
Output Fall Time
1
PHL
DO1 – DO3
DO1 – DO3
t
r
250
40
400
100
ns
ns
t
f
Page 4 of 8
www.lansdale.com
Issue A
ML145407
LANSDALE Semiconductor, Inc.
PIN DESCRIPTIONS
17
V
19
V
CC
V
CC
DD
Digital Power Supply (Pin 19)
15
13
11
6
DI1
Tx1
The digital supply pin, which is connected to the logic pow-
er supply. This pin should have a 0.33 µF capacitor to ground.
8
DI2
Tx2
V
GND
in = 2 V
Ground (Pin 2)
Ground return pin is typically connected to the signal ground
pin of the EIA–232–E connector (Pin 7) as well as to the logic
power supply ground.
10
DI3
Tx3
V
4
V
V
DD
SS GND
2
in
I
R
=
out
Positive Power Supply (Pin 17)
This is the positive output of the on–chip voltage doubler and
the positive power supply input of the driver/receiver sections of
the device. This pin requires an external storage capacitor to fil-
ter the 50% duty cycle voltage generated by the charge pump.
Figure 1. Power–Off Source Resistance
V
SS
Negative Power Supply (Pin 4)
This is the negative output of the on–chip voltage
doubler/inverter and the negative power supply input of the
driver/receiver sections of the device. This pin requires an
external storage capacitor to filter the 50% duty cycle voltage
generated by the charge pump.
DRIVERS
3 V
0 V
DI1 – DI3
50%
t
t
C2+, C2–, C1–, C1+
Voltage Doubler and Inverter (Pins 1, 3, 18, 20)
f
r
V
OH
90%
Tx1 – Tx3
These are the connections to the internal voltage doubler and
inverter, which generate the VDD and VSS voltages.
10%
t
V
OL
t
PLH
PHL
Rx1, Rx2, Rx3
Receive Data Input (Pins 5, 7, 9)
RECEIVERS
These are the EIA–232–E receive signal inputs. A voltage
between + 3 and + 25 V is decoded as a space and causes the
corresponding DO pin to swing to ground (0 V). A voltage
between – 3 and – 25 V is decoded as a mark, and causes the
DO pin to swing up to VCC.
+ 3 V
0 V
Rx1 – Rx3
50%
t
t
PLH
PHL
V
OH
90%
DO1, DO2, DO3
50%
10%
DO1 – DO3
Data Output (Pins 16, 14, 12)
V
OL
These are the receiver digital output pins, which swing from
t
t
r
f
V
to GND. Each output pin is capable of driving one
CC
LSTTL input load.
Figure 2. Switching Characteristics
DI1, DI2, DI3
Data Input (Pins 15, 13, 11)
These are the high impedance digital input pins to the driv-
ers. Input voltage levels on these pins must be between V
and GND.
CC
DRIVERS
3 V
3 V
Tx1 – Tx3
Tx1, Tx2, Tx3
Transmit Data Output (Pins 6, 8, 10)
– 3 V
SLH
– 3 V
t
t
SHL
These are the EIA–232–E transmit signal output pins,which
swing toward V and V . A logic 1 at a DI input causes the
– 3 V – (3 V)
3 V – ( – 3 V)
DD SS
SLEW RATE (SR) =
OR
corresponding Tx output to swing toward V . A logic 0 caus-
t
t
SS
SLH
SHL
es the output to swing toward V . The actual levels and slew
DD
rate achieved will depend on the output loading (RL\\CL).
Figure 3. Slew Rate Characterization
Page 5 of 8
www.lansdale.com
Issue A
ML145407
LANSDALE Semiconductor, Inc.
ESD CONSIDERATIONS
10 µF charge pump caps to illustrate its capability in driving a
companion ML145406 or ML145403. If there is no require-
ment to support a second interface device and/or the charge
pump is not being used to power any other components, the
ML145407 is capable of complying with EIA–232–E and V.28
with smaller value charge pump caps.Table 1 summarizes driv-
er performance with both 2.2 µF and1.0µF charge pump caps.
ESD protection on IC devices that have their pins accessible
to the outside world is essential. High static voltages applied to
the pins when someone touches them either directly or indi-
rectly can cause damage to gate oxides and transistor junctions
by coupling a portion of the energy from the I/O pin to the
power supply busses of the IC. This coupling will usually
occur through the internal ESD protection diodes. The key to
protecting the IC is to shunt as much of the energy to ground
as possible before it enters the IC. Figure 7 shows a technique
which will clamp the ESD voltage at approximately + 15 V
using the MMBZ15VDLT1. Any residual voltage which
appears on the supply pins is shunted to ground through the
0.1 µF capacitors.
Table 1. Typical Performance
Parameter
@ 25°C
2.2 µF
7.3
1.0 µF
7.2
Tx V
Tx V
Tx V
Tx V
OH
OH
OL
OL
@ 85°C
@ 25°C
@ 85°C
7.2
7.1
– 6.5
– 6.4
OPERATION WITH SMALLER VALUE CHARGE
PUMP CAPS
– 6.1
– 6.0
Tx Slew Rate @ 25°C
Tx Slew Rate @ 85°C
8.0 V/µs
7.0 V/µs
8.0 V/µs
7.0 V/µs
The ML145407 is characterized in the electrical tables using
+ 5 V
0.1 µF
0.1
X
µF
0.1 µF
1.0 µF
17
+
19
6
20
1
9
3
V
TLA
DSI
V
DD
V
CC
in
C1 –
DD
C2 –
C
RTLA
DSI
3.579
MHz
R
1.0 µF
1.0 µF
DSI
DTMF
INPUT
1
8
3
X
C2 +
DI1
C1 +
Tx1
out
17
15
20 kΩ
15
16
13
0.1 µF
TxA
RxA2
CD
6
5
11
5
DO1
DI2
8
2
TxD
RxD
R
600
Tx
10 µF
ML145442
OR
ML145443
10 kΩ
EIA–232–E
DB–25
CONNECTOR
10 kΩ
Rx1
16
+
ML145407
RxA1
TIP
14
2
8
7
9
SQT
LB
Tx2
Rx2
600:600
3
7
*
10 kΩ
RING
18
10
DI3
ExI
FB
V
DD
C
FB
10 kΩ
0.1
µ
F
Rx3
13
7
0.1 µF
MODE
CDA
19
4
V
BYPASS
DD
V
AG
CDT
V
GND
V
SS
SS
C
4
2
CDA
0.1
µ
F
12
0.1
C
µF
CDT
1.0 µF
0.1 µF
V
BYPASS
SS
* Line protection circuit
Figure 4. 5 V, 300 Baud Modem with EIA–232–E Interface
Page 6 of 8
www.lansdale.com
Issue A
ML145407
LANSDALE Semiconductor, Inc.
+ 5 V
1
2
3
4
16
15
1
2
20
10
µF
V
V
CC
C1+
DD
C2+
GND
C2–
19
18
10
µF
V
Rx1
Tx1
Rx2
DO1
DI1
10 µF
CC
14
13
12
11
10
9
3
4
5
6
7
C1–
17
16
15
14
13
12
11
V
V
DO2
SS
DD
ML145406
5
6
7
8
Tx2
Rx3
Tx3
ML145407
Rx1
Tx1
Rx2
Tx2
Rx3
DI2
DO1
DI1
DO3
DI3
DO2
8
9
V
GND
SS
DI2
DO3
DI3
10 µF
10
Tx3
Figure 5. ML145406/ML145407 5 V Only Solution for up to Six EIA–232–E Drivers and Receivers
+ 5 V
+ 10 V
C2
C2+
GND
C2–
C1+
1
20
19
18
17
16
15
14
13
12
11
0.1
0.1
µ
µ
F
F
V
CC
2
C1–
3
V
V
DD
SS
4
C4
5
6
7
8
9
10
Figure 6. Two Supply Configuration (ML145407 Generates V
Only)
SS
+ 5 V
MMBZ15VDLT
× 6
C2
C4
C1
C2+
GND
C2–
C1+
1
20
19
18
17
16
15
14
13
12
11
0.1
µ
µ
F
F
V
CC
2
C1–
3
V
V
C3
SS
DD
4
Rx1
Tx1
Rx2
Tx2
Rx3
Tx3
DO1
DI1
0.1
5
6
DO2
DI2
TO
7
CONNECTOR
8
DO3
DI3
9
10
Figure 7. ESD Protection Scheme
Page 7 of 8
www.lansdale.com
Issue A
ML145407
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
P DIP 20 = RP
(ML145407RP)
PLASTIC DIP
CASE 738–03
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
20
1
11
10
B
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
E
F
G
J
K
L
M
N
1.010
1.070
0.260
0.180
0.022
25.66
6.10
3.81
0.39
1.27 BSC
1.27
2.54 BSC
0.21
2.80
27.17
6.60
4.57
0.55
0.240
0.150
0.015
0.050 BSC
0.050
0.100 BSC
0.008
0.110
-T-
K
SEATING
M
PLANE
0.070
1.77
E
N
0.015
0.140
0.38
3.55
G
F
J 20 PL
0.300 BSC
15
0.040
7.62 BSC
15
0.51 1.01
D 20 PL
M
M
0.25 (0.010)
T
B
0°
°
0°
°
0.020
M
M
0.25 (0.010)
T
A
SOG 20 = -6P
(ML145407-6P)
SOG PACKAGE
CASE 751D–04
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
10X P
–B–
M
M
0.010 (0.25)
B
1
10
20X D
DIM
A
B
C
D
MIN
12.65
7.40
2.35
0.35
0.50
MAX
12.95
7.60
2.65
0.49
0.90
MIN
0.499
0.292
0.093
0.014
0.020
MAX
0.510
0.299
0.104
0.019
0.035
J
M
S
S
0.010 (0.25)
T
A
B
F
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
R X 45
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
C
SEATING
PLANE
–T–
M
18X G
K
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabil-
ity, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the cus-
tomer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Page 8 of 8
www.lansdale.com
Issue A
相关型号：
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