ML12011EP [LANSDALE]
MECL PLL Components Dual Modulus Prescaler; MECL PLL元件双模预分频器
| 型号： | ML12011EP |
| 厂家： | 
LANSDALE SEMICONDUCTOR INC. |
| 描述： | MECL PLL Components Dual Modulus Prescaler |
| 文件： | 总14页 (文件大小：1231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ML12009
ML12011
MECL PLL Components Dual
Modulus Prescaler
Legacy Device: Motorola MC12009, MC12011
These devices are two–modulus prescalers which will divide by
5 and 6, 8 and 9, respectively. A MECL–to–MTTL translator is
provided to interface directly with the Motorola MC12014
Counter Control Logic. In addition, there is a buffered clock input
and MECL bias voltage source.
16
1
SO 16 = -5P
PLASTIC PACKAGE
CASE 751B
• ML12009 480 MHz (÷5/6), ML12011 550 MHz (÷8/9)
• MECL to MTTL Translator on Chip
• MECL and MTTL Enable Inputs
• 5.0 or –5.2 V Operation*
• Buffered Clock Input — Series Input RC Typ, 20 Ω and 4.0 pF
• VBB Reference Voltage
16
1
P DIP 16 = EP
PLASTIC PACKAGE
CASE 648
• 310 mW (Typ)
CROSS REFERENCE/ORDERING INFORMATION
* When using a 5.0 V supply, apply 5.0 V to Pin 1 (V
),
CCO
PACKAGE
MOTOROLA
LANSDALE
Pin 6 (MTTL V ), Pin 16 (V ), and ground Pin 8
CC CC
P DIP 16
SOIC 16
P DIP 16
SO 16W
MC12009P
MC12009D
MC12011P
MC12011D
ML12009EP
ML12009-5P
ML12011EP
ML12011-5P
(V ). When using –5.2 V supply, ground Pin 1 (V
),
Pin 6 (MTTL V ), and Pin 16 (V ) and apply –5.2 V to
EE CCO
CC
CC
Pin 8 (V ). If the translator is not required, Pin 6 may be
EE
left open to conserve DC power drain.
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
MAXIMUM RATINGS
Characteristic
(Ratings above which device life may be impaired)
Power Supply Voltage
Symbol
Rating
Unit
PIN CONNECTIONS
V
EE
–8.0
Vdc
Vdc
(V = 0)
CC
Input Voltage
(V = 0)
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Clock
CCO
Q
V
in
0 to V
EE
CC
Q
( – )
V
BB
Output Source Current
Continuous
Surge
I
O
mAdc
E1 MECL
E2 MECL
E3 MECL
50
100
( + )
MTTL V
CC
Storage Temperature Range
T
stg
–65 to 175
°C
E4 MECL
E5 MECL
MTTL Output
(Recommended Maximum Ratings above which performance may be
degraded)
V
EE
(Top View)
Operating Temperature Range
ML12009, ML12011
T
A
–30 to 85
°C
DC Fan–Out (Note 1)
(Gates and Flip–Flops)
n
70
—
NOTES: 1. AC fan–out is limited by desired system performance.
Page 1 of 14
www.lansdale.com
Issue A
ML12009, ML12011
LANSDALE Semiconductor, Inc.
Figure 1. Logic Diagrams
ML12009
MTTL E5
9
D
C
Q1
Q1
D
C
Q2
D
C
MECL
to
Q3
Q3
MTTL E4 10
MECL E3 11
MECL E2 12
MECL E1 13
MTTL
Translator
Recommended Circuitry
For ac coupled Inputs.
V
BB
7
14
15
3
2
5
+
4
–
MTTL
Out
0.1 µF
1000 pF
Clock Input
1.0 k
Q3
Q3
ML12011
MTTL E5
9
Q4
D
C
Q1
D
Q2
D
C
Q3
MECL
to
Toggle
MTTL E4 10
MECL E3 11
MECL E2 12
MECL E1 13
Flip
MTTL
Flop
Translator
C
C
Q4
Recommended Circuitry
For ac coupled Inputs.
V
BB
7
14
15
3
2
5
+
4
–
MTTL
Out
1.0 k
0.1
µF
1000 pF
Clock Input
Q4 Q4
Figure 2. Typical Frequency Synthesizer Application
Phase Detector
MC4044/ML4044
Voltage–Controlled
Oscillator MC1648/ML1648
f
f
Low–Pass Filter
ref
out
Modulus Enable Line
ML12009
ML12011
ML12013
Counter Control Logic
MC12014
Zero Detect Line
f
out
N
Programmable
A Programmable
Counter MC4016/ML4016
p
Counter MC4016/ML4016
Counter Reset Line
Page 2 of 14
www.lansdale.com
Issue A
ML12009, ML12011
LANSDALE Semiconductor, Inc.
Figure 2b Generic block diagram showing prescaler connection to
PLL Device
Prescaler
PLL
Fout
Fin
ML145146
ML12009/11
ML145158
ML145159
MC in
MC
VCO
Loop Filter
Figure 2b shows a generic block diagram of connecting a prescaler to a PLL device that supports
dual modulus controls. Applicataion not AN535 describes using a two–modulus prescaler
technique. By using prescaler higher frequencies can be achieved than by a single CMOS PLL
device.
Page 3 of 14
www.lansdale.com
Issue A
ML12009, ML12011
LANSDALE Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS (Supply Voltage = –5.2 V, unless otherwise noted.)
Test Limits
Pin
Under
Test
–30°C
25°C
85°C
Characteristic
Symbol
Unit
mAdc
mAdc
µAdc
Min
Max
Min
Max
Min
Max
I
8
6
–88
–80
–80
Power Supply Drain Current
CC1
I
5.2
5.2
5.2
CC2
inH1
Input Current
I
15
11
12
13
375
375
375
375
250
250
250
250
250
250
250
250
I
4
5
1.7
1.7
6.0
6.0
2.0
2.0
6.0
6.0
2.0
2.0
6.4
6.4
mAdc
inH2
I
I
5
0.7
3.0
1.0
3.0
1.0
3.6
inH3
9
10
100
100
100
100
100
100
µAdc
µAdc
inH4
Leakage Current
I
15
11
12
13
–10
–10
–10
–10
–10
–10
–10
–10
–10
–10
–10
–10
inL1
I
9
10
–1.6
–1.6
–1.6
–1.6
–1.6
–1.6
mAdc
inL2
Reference Voltage
V
14
–1.360
–1.160
Vdc
Vdc
BB
Logic ‘1’ Output Voltage
V
OH1
2
3
–1.100
–1.100
–0.890
–0.890
–1.000
–1.000
–0.810
–0.810
–0.930
–0.930
–0.700
–0.700
(Note 1)
V
OH2
7
–2.8
–2.6
–2.4
Logic ‘0’ Output Voltage
V
2
3
–1.990
–1.990
–1.675
–1.675
–1.950
–1.950
–1.650
–1.650
–1.925
–1.925
–1.615
–1.615
Vdc
OL1
(Note 1)
V
OL2
7
–4.26
–4.40
–4.48
Logic ‘1’ Threshold Voltage
Logic ‘0’ Threshold Voltage
Short Circuit Current
V
2
3
–1.120
–1.120
–1.020
–1.020
–0.950
–0.950
Vdc
Vdc
OHA
(Note 2)
V
2
3
–1.655
–1.655
–1.630
–1.630
–1.595
–1.595
OLA
(Note 3)
I
7
–65
–20
–65
–20
–65
–20
mAdc
OS
NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and
ground voltages must be maintained between tests. The clock input is the waveform shown.
2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock
input is the waveform shown.
Clock Input
V
IHmax
ILmin
V
3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock
input is the waveform shown.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50 Ω resistor to –2.0 V. Test procedures are shown for only one gate. The other gates are tested in the same
manner.
Page 4 of 14
www.lansdale.com
Issue A
ML12009, ML12011
LANSDALE Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS (continued) (Supply Voltage = –5.2 V, unless otherwise noted.)
TEST VOLTAGE/CURRENT VALUES
Volts
@ Test Temperature
V
V
ILmin
V
V
V
IH
V
ILH
IHmax
IHAmin
ILAmax
–30°C
25°C
85°C
–0.890
–0.810
–0.700
–1.990
–1.950
–1.925
–1.205
–1.105
–1.035
–1.500
–1.475
–1.440
–2.8
–2.8
–2.8
–4.7
–4.7
–4.7
Pin
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
Under
Characteristic
Symbol
Test
Gnd
1,16
6
V
V
ILmin
V
V
V
IH
V
IL
IHmax
IHAmin
ILAmax
Power Supply Drain Current
I
I
8
6
CC1
CC2
inH1
4
5
Input Current
I
15
11
12
13
15
11
12
13
1,16
1,16
1,16
1,16
I
4
5
5
5
4
4
6
6
inH2
I
I
5
4
5
6
inH3
9
10
9
10
1,16
1,16
inH4
Leakage Current
I
15
11
12
13
1,16
1,16
1,16
1,16
inL1
I
9
10
9
10
1,16
1,16
inL2
Reference Voltage
V
BB
14
1,16
Logic ‘1’ Output Voltage
V
2
3
11,12,13
11,12,13
9,10
9,10
1,16
1,16
OH1
(Note 1)
V
7
5
4
4
6
OH2
Logic ‘0’ Output Voltage
V
2
3
11,12,13
11,12,13
9,10
9,10
1,16
1,16
OL1
(Note 1)
V
7
5
6
OL2
Logic ‘1’ Threshold Voltage
Logic ‘0’ Threshold Voltage
Short Circuit Current
V
2
3
11,12,13
11,12,13
1,16
1,16
OHA
(Note 2)
V
2
3
11,12,13
11,12,13
1,16
1,16
OLA
(Note 3)
I
7
5
4
7
6
OS
NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and
ground voltages must be maintained between tests. The clock input is the waveform shown.
2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock
input is the waveform shown.
Clock Input
V
V
IHmax
ILmin
3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock
input is the waveform shown.
Page 5 of 14
www.lansdale.com
Issue A
ML12009, ML12011
LANSDALE Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS (continued) (Supply Voltage = –5.2 V, unless otherwise noted.)
TEST VOLTAGE/CURRENT VALUES
Volts mA
@ Test Temperature
V
IHT
V
ILT
V
EE
I
L
I
I
OH
OL
–30°C
25°C
85°C
–3.2
–3.2
–3.2
–4.4
–4.4
–4.4
–5.2
–5.2
–5.2
–0.25
–0.25
–0.25
16
–0.40
–0.40
–0.40
16
16
Pin
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
Under
Characteristic
Symbol
Test
Gnd
1,16
6
V
IHT
V
ILT
V
EE
I
L
I
I
OH
OL
Power Supply Drain Current
I
I
8
6
8
CC1
CC2
inH1
8
Input Current
I
15
11
12
13
8
8
8
8
1,16
1,16
1,16
1,16
9,10
9,10
9,10
I
4
5
8
8
6
6
inH2
I
I
5
8
6
inH3
9
10
8
8
1,16
1,16
inH4
Leakage Current
I
15
11
12
13
8,15
8,11
8,12
8,13
1,16
1,16
1,16
1,16
inL1
I
9
10
8
8
1,16
1,16
inL2
Reference Voltage
V
BB
14
8
14
1,16
Logic ‘1’ Output Voltage
V
2
3
8
8
1,16
1,16
OH1
(Note 1)
V
OH2
7
8
7
6
Logic ‘0’ Output Voltage
V
2
3
8
8
1,16
1,16
OL1
(Note 1)
V
OL2
7
8
7
6
Logic ‘1’ Threshold Voltage
Logic ‘0’ Threshold Voltage
Short Circuit Current
V
2
3
9,10
9,10
8
8
1,16
1,16
OHA
(Note 2)
V
2
3
9,10
9,10
8
8
1,16
1,16
OLA
(Note 2)
I
7
8
6
OS
NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and
ground voltages must be maintained between tests. The clock input is the waveform shown.
2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock
input is the waveform shown.
Clock Input
V
V
IHmax
ILmin
3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock
input is the waveform shown.
Page 6 of 14
www.lansdale.com
Issue A
ML12009, ML12011
LANSDALE Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS (Supply Voltage = 5.0 V, unless otherwise noted.)
Test Limits
Pin
Under
Test
–30°C
25°C
85°C
Characteristic
Symbol
Unit
mAdc
mAdc
µAdc
Min
Max
Min
Max
Min
Max
I
8
6
–88
–80
–80
Power Supply Drain Current
CC1
I
5.2
5.2
5.2
CC2
inH1
Input Current
I
15
11
12
13
375
375
375
375
250
250
250
250
250
250
250
250
I
4
5
1.7
1.7
6.0
6.0
2.0
2.0
6.0
6.0
2.0
2.0
6.4
6.4
mAdc
inH2
I
I
5
0.7
3.0
1.0
3.0
1.0
3.6
inH3
9
10
100
100
100
100
100
100
µAdc
µAdc
inH4
Leakage Current
I
15
11
12
13
–10
–10
–10
–10
–10
–10
–10
–10
–10
–10
–10
–10
inL1
I
9
10
–1.6
–1.6
–1.6
–1.6
–1.6
–1.6
mAdc
inL2
Reference Voltage
V
14
3.67
3.87
Vdc
Vdc
BB
Logic ‘1’ Output Voltage
V
OH1
2
3
3.900
3.900
4.110
4.110
4.000
4.000
4.190
4.190
4.070
4.070
4.300
4.300
(Note 1)
V
OH2
7
2.4
2.6
2.8
Logic ‘0’ Output Voltage
V
2
3
3.070
3.070
3.385
3.385
3.110
3.110
3.410
3.410
3.135
3.135
3.445
3.445
Vdc
OL1
(Note 1)
V
OL2
7
0.94
0.80
0.72
Logic ‘1’ Threshold Voltage
Logic ‘0’ Threshold Voltage
Short Circuit Current
V
2
3
3.880
3.880
3.980
3.980
4.050
4.050
Vdc
Vdc
OHA
(Note 2)
V
2
3
3.405
3.405
3.430
3.430
3.465
3.465
OLA
(Note 3)
I
7
–65
–20
–65
–20
–65
–20
mAdc
OS
NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and
ground voltages must be maintained between tests. The clock input is the waveform shown.
2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock
input is the waveform shown.
Clock Input
V
IHmax
ILmin
V
3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock
input is the waveform shown.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50 Ω resistor to –2.0 V. Test procedures are shown for only one gate. The other gates are tested in the same
manner.
Page 7 of 14
www.lansdale.com
Issue A
ML12009, ML12011
LANSDALE Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS (continued) (Supply Voltage = 5.0 V, unless otherwise noted.)
TEST VOLTAGE/CURRENT VALUES
Volts
@ Test Temperature
V
V
ILmin
V
V
V
IH
V
ILH
IHmax
IHAmin
ILAmax
–30°C
25°C
85°C
4.110
4.190
4.300
3.070
3.110
3.135
3.795
3.895
3.965
3.500
2.4
2.4
2.4
0.5
0.5
0.5
3.525
3.560
Pin
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
Under
(V
)
EE
Characteristic
Symbol
Test
Gnd
V
V
ILmin
V
V
V
IH
V
IL
IHmax
IHAmin
ILAmax
Power Supply Drain Current
I
I
8
6
8
8
CC1
CC2
inH1
4
5
Input Current
I
15
11
12
13
15
11
12
13
8
8
8
8
I
4
5
5
5
4
4
8
8
inH2
I
I
5
4
5
8
inH3
9
10
9
10
8
8
inH4
Leakage Current
I
15
11
12
13
8,15
8,11
8,12
8,13
inL1
I
9
10
9
10
8
8
inL2
Reference Voltage
V
BB
14
8
Logic ‘1’ Output Voltage
V
2
3
11,12,13
11,12,13
9,10
9,10
8
8
OH1
(Note 1)
V
7
5
4
4
8
OH2
Logic ‘0’ Output Voltage
V
2
3
11,12,13
11,12,13
9,10
9,10
8
8
OL1
(Note 1)
V
7
5
8
OL2
Logic ‘1’ Threshold Voltage
Logic ‘0’ Threshold Voltage
Short Circuit Current
V
2
3
11,12,13
11,12,13
8
8
OHA
(Note 2)
V
2
3
11,12,13
11,12,13
8
8
OLA
(Note 3)
I
7
5
4
7
8
OS
NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and
ground voltages must be maintained between tests. The clock input is the waveform shown.
2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock
input is the waveform shown.
Clock Input
V
V
IHmax
ILmin
3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock
input is the waveform shown.
Page 8 of 14
www.lansdale.com
Issue A
ML12009, ML12011
LANSDALE Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS (continued) (Supply Voltage = 5.0 V, unless otherwise noted.)
TEST VOLTAGE/CURRENT VALUES
Volts mA
@ Test Temperature
V
IHT
V
ILT
V
CC
I
L
I
I
OH
OL
–30°C
25°C
85°C
2.0
2.0
2.0
0.8
0.8
0.8
5.0
5.0
5.0
–0.25
–0.25
–0.25
16
–0.40
–0.40
–0.40
16
16
Pin
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
V
Under
(V
)
EE
Characteristic
Symbol
Test
Gnd
V
IHT
V
ILT
I
L
I
I
CC
OL
OH
Power Supply Drain Current
I
I
8
6
1,16
8
8
CC1
CC2
inH1
6
Input Current
I
15
11
12
13
1,16
1,16
1,16
1,16
8
8
8
8
9,10
9,10
9,10
I
4
5
6
6
8
8
inH2
I
I
5
6
8
inH3
9
10
1,16
1,16
8
8
inH4
Leakage Current
I
15
11
12
13
1,16
1,16
1,16
1,16
8,15
8,11
8,12
8,13
inL1
I
9
10
1,16
1,16
8
8
inL2
Reference Voltage
V
BB
14
1,16
14
8
Logic ‘1’ Output Voltage
V
2
3
1,16
1,16
8
8
OH1
(Note 1)
V
OH2
7
6
7
8
Logic ‘0’ Output Voltage
V
2
3
1,16
1,16
8
8
OL1
(Note 1)
V
OL2
7
6
7
8
Logic ‘1’ Threshold Voltage
Logic ‘0’ Threshold Voltage
Short Circuit Current
V
2
3
9,10
9,10
1,16
1,16
8
8
OHA
(Note 2)
V
2
3
9,10
9,10
1,16
1,16
8
8
OLA
(Note 3)
I
7
6
8
OS
NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and
ground voltages must be maintained between tests. The clock input is the waveform shown.
2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock
input is the waveform shown.
Clock Input
V
V
IHmax
ILmin
3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock
input is the waveform shown.
Page 9 of 14
www.lansdale.com
Issue A
ML12009, ML12011
LANSDALE Semiconductor, Inc.
SWITCHING CHARACTERISTICS
ML12509, ML12511, ML12513
TEST VOLTAGES/WAVEFORMS APPLIED TO PINS LISTED BELOW:
Pin
Under
Test
–30°C
25°C
85°C
Pulse
Gen.1
Pulse
Gen.2
Pulse
Gen.3
V
V
V
V
V
CC
+2.0
IHmin
ILmin
F
EE
Characteristic
Symbol
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
–3.0 V
–3.0 V
Propagation Delay
(See Figures 3 and 5)
t
2
2
7
7
—
—
—
—
—
—
—
—
8.1
7.5
8.4
6.5
—
—
—
—
—
—
—
—
8.1
7.5
8.1
6.5
—
—
—
—
—
—
—
—
8.9
8 2
8.9
7.1
ns
15
15
A
—
—
—
—
—
—
—
—
—
—
—
—
11,12,13
11,12,13
—
9,10
9,10
—
8
8
8
8
1,6,16
1,6,16
1,6,16
1,6,16
15+ 2+
15+ 2–
5+ 7+
5– 7–
t
t
t
A
—
—
Setup Time
(See Figures 4 and 5)
t
11
9
5.0
5.0
—
—
—
—
5.0
5.0
—
—
—
—
5.0
5.0
—
—
—
—
ns
ns
15
15
*
—
—
*
—
—
*
9,10
*
8
8
1,6,16
1,6,16
setup1
setup2
t
11,12,13
Release Time
(See Figures 4 and 5)
t
t
11
9
5.0
5.0
—
—
—
—
5.0
5.0
—
—
—
—
5.0
5.0
—
—
—
—
ns
ns
15
15
*
—
—
*
—
—
*
9.10
*
8
8
1,6,16
1,6,16
rel1
rel2
11,12,13
Toggle Frequency
(See Figure 6)
ML12509 : 5/6
ML12511 : 8/9
f
2
MHz
max
440
500
—
—
—
—
480
550
—
—
—
—
440
500
—
—
—
—
—
—
—
—
—
—
11
11
—
—
—
—
8
8
16
16
*Test inputs sequentially, with Pulse Generator 2 or 3 as indicated connected to input under test, and the voltage indicated applied to the other input(s) of the same type ( i.e., MECL or MTTL).
–30°C
1.03
25°C
1.115
0.200
85°C
1.20
V
Vdc
Vdc
IHmin
V
0.175
0.235
ILmin
Figure 3. AC Voltage Waveforms
Pulse
Generator
1
V
V
80%
IHmin
50%
20%
ILmin
t + +
Q (Pin 2)
Q (Pin 3)
50%
50%
t+ –
+ In
50%
t + +
t – –
MTTL
Out
–1.5 V
Figure 4. Setup and Release Time Waveforms
V
V
IHmin
IHmin
80%
Pulse
Pulse
Generator
1
80%
20%
50%
t
50
%
Generator
20%
V
V
V
V
ILmin
IHmin
ILmin
IHmin
rel1
t
1
setup1
80%
50%
80%
Pulse
Pulse
Generator
2
50%
rel2
20%
V
0 V
20%
10%
Generator
V
ILmin
ILmin
t
t
setup2
2
Pulse
Generator
3
0 V
90%
90%
10%
Pulse
Generator
3
V
V
EE
EE
+1.5 V
–1.5 V
Q (Pin 2)
Q (Pin 2)
Divide by 5 — ML12509
Divide by 8 — ML12511
Divide by 6 — ML12509
Divide by 9 — ML12511
Page 10 of 14
www.lansdale.com
Issue A
ML12009, ML12011
LANSDALE Semiconductor, Inc.
Figure 5. AC Test Circuit
V
V
(Scope Channel B)
in
out
V
= 2.0 V
CC
V
out
0.1 µF
25
µF
1
6
16
50
Pulse
Generator
#1
100
V
in
13
E1
E2
E3
E4
E5
C
2
3
Q
Q
12
11
10
9
50
Pulse
Generator
#2
V
out
100
V
in
15
14
5
V
BB
950
50
1950
+
MECL
to
MTTL
Trans–
lator
Pulse
Generator
#3
7
4
–
8
0.1 µF
C
T
V
in
(Scope Channel A)
V
= –3.0 V
EE
MC10109 or equiv.
A
50
All Pulse Generators are EH 137 or equiv.
Pulse Generators 1 and 2:
PRF = 10 MHz
PW = 50% Duty Cycle
t + = t – = 2.0 0.2 ns
V
= –3.0 V
EE
All resistors are +1%.
All input and output cables to the scope are equal lengths of 50 Ω coaxial cable.
The 1950 Ω resistor at Pin 7 and the scope termination impedance constitute a 40 :1 attenuator probe.
Pulse Generator 3:
PRF = 2.0 MHz
PW = 50% Duty Cycle
t + = t – = 5.0 0.5 ns
C
= 15 pF = total parasitic capacitance which includes probe, wiring, and load capacitance.
T
Unused output connected to a 50 Ω resistor to ground.
Page 11 of 14
www.lansdale.com
Issue A
ML12009, ML12011
LANSDALE Semiconductor, Inc.
Figure 6. Maximum Frequency Test Circuit
V
V
= 2.0 V
out
CC
to
Scope
0.1
µ
F
5.0
2
µF
1
16
13
E1
V
in
12
11
Q
Q
V
E2
E3
(To Scope)
EE
10
9
E4
E5
3
0.1 µF
15
C
1.0 k
14
V
BB
0.1
µF
8
0.1
µF
V
= –3.0 V
EE
Unused output connected to a 50 Ω resistor to ground
DIVIDE BY 6
800 mV
Clock
Input
850 mV typ
3 Cycles
3 Cycles
Q (Pin 2)
DIVIDE BY 9
800 mV
Clock
Input
850 mV typ
5 Cycles
4 Cycles
Q (Pin 2)
Page 12 of 14
www.lansdale.com
Issue A
ML12009, ML12011
LANSDALE Semiconductor, Inc.
Figure 7. State Diagram
DIVIDE BY 5/6 (ML12009/ML12509)
Q1
1
0
0
0
Q2
1
1
0
0
Q3
1
1
1
0
111
011
100
001
000
010
101
Enable = 0
Enable = 1
1
1
0
1
0
0
110
Enable = 1
DIVIDE BY 8/9 (ML12011)
0101
0010
0110
1000
1100
0111
1010
1111
Q1
Q2
1
1
0
0
1
1
0
0
Q3
1
1
1
0
0
1
1
0
Q4
1
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
1110
0000
0001
Enable = 0
Enable = 1
1
0
0
1101
1001
0011
Enable = 1
1011
0100
APPLICATIONS INFORMATION
The primary application of these devices is as a
high–speed variable modulus prescaler in the divide by N
section of a phase–locked loop synthesizer used as the local
oscillator of two–way radios.
Proper VHF termination techniques should be followed
when the clock is separated from the prescaler by any
appreciable distance.
In their basic form, these devices will divide by 5/6 or 8/9.
Division by 5, or 8 occurs when any one or all of the five gate
inputs E1 through E5 are high. Division by 6, or 9 occurs
when all inputs E1 through E5 are low. (Unconnected MTTL
inputs are normally high, unconnected MECL inputs are
normally low). With the addition of extra parts, many different
division configurations may be obtained.
Page 13 of 14
www.lansdale.com
Issue A
ML12009, ML12011
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
SO 16 = -5P
PLASTIC PACKAGE
(ML12009-5P, ML12011-5P)
CASE 751B–05
(SO–16)
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ISSUE J
16
1
9
8
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
0.386
0.150
0.054
0.014
0.016
R X 45
K
B
C
D
C
F
G
J
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
5.80
0.25
0.25
0.25
7
6.20
0.50
0.008
0.004
0
0.229
0.010
0.009
0.009
7
0.244
0.019
J
M
K
D
16 PL
M
P
M
S
S
0.25 (0.010)
T
B
A
R
P DIP 16 = EP
PLASTIC PACKAGE
(ML12009EP, ML12011EP)
CASE 648–08
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ISSUE R
16
1
9
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
8
INCHES
MILLIMETERS
F
DIM
A
B
C
D
F
G
H
J
K
L
M
S
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
C
L
0.740
0.250
0.145
0.015
0.040
S
SEATING
–T–
PLANE
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
K
M
H
J
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
G
0.110
0.295
0
2.80
7.50
0
D 16 PL
0.25 (0.010)
M
M
T
A
0.020
0.040
0.51
1.01
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili-
ty, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Page 14 of 14
www.lansdale.com
Issue A
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