ML145146RP [LANSDALE]
4-Bit Data Bus Input PLL Frequency Synthesizer; 4位数据总线输入锁相环频率合成器
| 型号： | ML145146RP |
| 厂家： | 
LANSDALE SEMICONDUCTOR INC. |
| 描述： | 4-Bit Data Bus Input PLL Frequency Synthesizer |
| 文件： | 总12页 (文件大小：3648K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ML145146
4–Bit Data Bus Input PLL
Frequency Synthesizer
INTERFACES WITH DUAL–MODULUS PRESCALERS
Legacy Device: Motorola MC145146-2
The ML145146 is programmed by a 4–bit input, with
strobe and address lines. The device features consist of a
reference oscillator, 12–bit programmable reference
divider, digital phase detector, 10–bit programmable
divide–by–N counter, 7–bit divide–by–A counter, and the
necessary latch circuitry for accepting the 4–bit input data.
P DIP 20 = RP
PLASTIC DIP
CASE 738
20
1
SOG 20 W = -6P
SOG PACKAGE
CASE 751D
20
• Operating Temperature Range: T – 40 to +85°C
A
• Low Power Consumption Through the Use of
CMOS Technology
• 3.0 to 9.0 V Supply Range
• Programmable Reference Divider for Values Between
3 and 4095
• Dual–Modulus 4–Bit Data Bus Programming
• ÷ N Range = 3 to 1023, ÷ A Range= 0 to 127
• “Linearized” Digital Phase Detector Enhances
Transfer Function Linearity
1
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 20
SOG 20W
MC145146P2
ML145146RP
MC145146DW2 ML145146-6P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
• Two Error Signal Options:
PIN ASSIGNMENT
Single–Ended (Three–State)
Double–Ended
D1
D0
1
2
20
19
D2
D3
f
3
4
18
17
f
R
in
V
φ
R
SS
BLOCK DIAGRAM
PD
V
5
6
16
15
φ
V
out
f
DD
V
f
12–BIT
L5
÷R COUNTER
OSC
in
R
OSC
in
7
14
13
12
11
MC
LD
ST
A2
OSC
out
OSC
8
out
L6
L7
LOCK
DETECT
LD
PD
A0
9
D0
D1
D2
D3
A2
A1
A0
A1
10
PHASE
DETECTOR A
out
LATCH
CONTROL
CIRCUITRY
LATCHES
f
V
ST
φ
V
PHASE
L2
L3
L4
L0
L1
DETECTOR B
φ
R
f
in
10–BIT
÷
N COUNTER
7–BIT
÷
A COUNTER
MODULUS CONTROL (MC)
CONTROL LOGIC
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PIN DESCRIPTIONS
LD
Lock Detector (Pin 13)
INPUT PINS
D0 - D3
High level when loop is locked (f , f of same phase and
R V
frequency). Pulses low when loop is out of lock.
Data Inputs (Pins 2, 1, 20, 19)
MC
Information at these inputs is transferred to the internal
latches when the ST input is in the high state. D3 (Pin 19) is
the most significant bit.
Modulus Control (Pin 14)
Signal generated by the on–chip control logic circuitry for
controlling an external dual–modulus prescaler. The modulus
control level is low at beginning of a count cycle and remains
low until the ÷A counter has counted down from its pro-
grammed value. At this time, modulus control goes high and
remains high until the ÷N counter has counted the rest of the
way down from its programmed value (N – A additional count-
er since both ÷N and ÷A are counting down during the first
portion of the cycle). Modulus control is then set back low, the
counters preset to their respective programmed values, and the
above sequence repeated. This provides for a total programma-
f
in
Frequency Input (Pin 3)
Input to ÷N portion of synthesizer f is typically derived
in
from loop VCO and is AC coupled into Pin 3. For larger
amplitude signals (standard CMOS – logic levels) DC coupling
may be used.
OSC /OSC
in
out
Reference Oscillator Input/Output (Pins 7 and 8)
ble divide value (N ) = N • P ÷ A where P and P ÷ 1 represent
T
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be con-
the dual–modulus prescaler divide values respectively for high
and low modulus control levels. N the number programmed
into the ÷N counter and A the number programmed into the
÷A counter.
nected from OSC to ground and OSC
in
to ground. OSC
in
out
may also serve as input for an externally–generated reference
f
V
signal. This signal is typically AC coupled to OSC , but for
in
÷N Counter Output (Pin 15)
larger amplitude signals (standard CMOS–logic levels) DC
coupling may also be used. In the external reference mode, no
This pin is the output of the ÷N counter that is internallly
connected to the phase detector input. With this output avail-
able, the ÷N counter can be used independently.
connection is required to OSC
.
out
A0 - A2
Address Inputs (Pins 9, 10, 11)
φ , φ
V R
Phase Detector Outpiuts (Pins 16 adn 17)
A0, A1 and A2 are used to define which latch receives the
information on the data input lines. The addresses refer to the
following latches.
These phase detector outputs can be combined externally for
a loop error signal. A single–ended output is also available for
this purpose (see PD ).
out
If frequency f is greater than f or if the phase of f is
V
R
V
A2 A1 A0 Selected
Function
÷ A Bits
D0 D1 D2 D3
leading, then error information is provided by φ pulsing low
V
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Latch 0
Latch 1
Latch 2
Latch 3
Latch 4
Latch 5
Latch 6
Latch 7
0
4
0
4
8
0
4
8
1
5
1
5
9
1
5
9
2
6
3
—
3
φ remains essentially high.
R
÷ A Bits
If the frequency f is less than f or if the phase of f is
V
R
V
÷ N Bits
2
lagging, then error information is provided by φ pulsing low
R
φ remains essentially high.
÷ N Bits
5
7
V
If the frequency of f = f and both are in phase, then both
V
R
÷ N Bits
—
2
—
3
φ and φ remain high except for a small minimum time peri-
V
R
Reference Bits
Reference Bits
Reference Bits
od when both pulse low in phase.
6
7
f
10 11
R
÷R Counter Output (Pin 18)
ST
Strobe Transfer (Pin 12)
This is the output of the ÷ R counter that is internally con-
nected to the phase detector input. With this output available,
the ÷ R counter can be used independently.
The rising edge of strobe transfers data into the addressed
latch. The falling edge of strobe latches data into the latch.
This pin should normally be held low to avoid loading latches
with invalid data.
POWER SUPPLY PINS
V
SS
OUTPUT PINS
Ground (Pin 4)
Circuit Ground
PDout
Single–ended Phase Detector Output (Pin 5)
V
DD
Positive Power Supply (Pin 6)
Three–state output of phase detector for use as loop error
signal.
The positive supply voltage may range from 3.0 to 9.0 V
with respect to V .
SS
Frequency f >f or f Leading: Negative Pulses
V R
V
V
Frequency f <f or f Lagging: Negative Pulses
V R
Frequency f =f and Phase Coincidence: High–Impedance
V R
State
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DESIGN CONSIDERATIONS
The oscillator can be “trimmed” on–frequency by making a
portion or all of C1 variable. The crystal and associated com-
CRYSTAL OSCILLATOR CONSIDERATIONS
ponents must be located as close as possible to the OSC and
in
OSC
pins to minimize distortion, stray capacitance, stray
The following options may be considered to provide a refer-
ence frequency to Motorola’s CMOS frequency synthesizers.
The most desirable is discussed first.
out
inductance, and startup stabilization time. In some cases, stray
capacitance should be added to the value for C and C
.
in out
Power is dissipated in the effective series resistance of the
Use of a Hybrid Crystal Oscillator
crystal, R . In Figure 10 The drive level specified by the crys-
e
Commercially available temperature–compensated crystal
oscillators (TCXOs) or crystal–controlled data clock oscilla-
tors provide very stable reference frequencies. An oscillator
capable of sinking and sourcing 50 µA at CMOS logic levels
tal manufacturer is the maximum stress that a crystal can with-
stand without damaging or excessive shift in frequency. R1 in
Figure 8 limits the drive level. The use of R1 may not be nec-
essary in some cases (i.e. R1 = 0 ohms).
may be direct or DC coupled to OSC . In general, the highest
To verify that the maximum DC supply voltage does not
overdrive the crystal, monitor the output frequency as a func-
in
frequency capability is obtained utilizing a direct coupled
square wave having a rail–to–rail (V
swing. If the oscillator does not have CMOS logic levels on the
to V ) voltage
tion of voltage at OSC . (care should be taken to minimize
DD
SS
out
loading.) the frequency should increase very slightly as the dc
supply voltage is increased. An overdriven crystal will decrease
in frequency or become unstable with an increase in supply
voltage. The operating supply voltage must be reduced or R1
must be increased in value if the overdrive condition exists.
The user should note that the oscillator start–up time is propor-
tional to the value of R1.
outputs, capacitive or AC coupling of OSC may be used.
in
OSC , an unbuffered output, should be left floating.
out
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the eem
Electronic Engineers Master Catalog, the Gold Book, or simi-
lar publications.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have developed
expertise in CMOS oscillator design with crystals. Discussions
with such manufacturers can prove very helpful. See Table 1.
Design an Off–Chip Reference
The user may design and off–chip crystal oscillator using
ICs specifically developed for crystal oscillator applications,
such as the ML12061 MECL device. The reference signal from
the MECL device is AC coupled to OSC . For large ampli-
in
tude signals (standard CMOS logic levels), DC coupling is
used. OSC , an unbuffered output, should be left floating. In
out
general, the highest frequency capability is obtained with a
direct–coupled square wave having rail–to–rail voltage swing.
Use of the On–Chip Oscillator Circuitry
The on–chip amplifier (a digital inverter) along with an
appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at the
desired operating frequency, should be connected as shown in
Figure 8.
For V
= 5.0 V, the crystal should be specified for a load-
DD
ing capacitance. C , which does not exceed 32 pF for frequen-
L
cies to approximately 8.0 MHz, 20 pF for frequencies in the
area of 8.0 to 15 MHz, and 10 pF for higher frequencies. These
are guidelines that provide a reasonable compromise between
IC capacitance, drive capability, swamping variations stray in
IC input/output capacitance, and realistic C values. The shunt
L
load capacitance, C , presented across the crystal can be esti-
mated to be:
L
where
C
C
= 5.0pF (See Figure 9)
in
= 6.0pF (See Figure 9)
out
C = 1.0pF (See Figure 9)
C = the crystal’s holder capacitance (See Figure 10)
C1 and C2 = external capacitors (See Figure 8)
a
O
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RECOMMENDED READING
Technical Note TN–24 Statek Corp.
Technical Note TN–7 Statek Corp.
N is the number programmed into the ÷N counter, A is the
number programmed into the ÷A counter, P and P ÷ 1 are the
two selectable divide ratios available in the dual–modulus
E. Hafner, “The Piezoelectric Crystal Unit – Definitions and
Method of Measurement”, Proc. iEEE, Vol 57, No 2 Feb, 1969
D. Kemper, L. Rosine, “Quartz Crystals for Frequency
Control”, Electro–Tecchnology, June 1969
P.J. Ottowitz, “AGuide to Crystal Selection”, Electronic
Design, May 1966
prescalers. To have a range of N values in sequence, the ÷A
T
counter is programmed from zero through P ÷ 1 for a particu-
lar value N in the ÷N counter. N is then incremented to the N
÷ 1, and the ÷A is sequenced from 0 through P ÷ 1 again.
There are minimum and maximum values that can be
achieved for N . These values are a function of P and the size
DUAL–MODULUS PRESCALING
T
of the ÷N and ÷A counters. The constraint N ≥ A always
The technique of dual–modulus prescaling is well estab-
lished as a method of acheiving high performance frequency
synthesizer operation at high frequencies. Basically, the
approach allows relatively low–frequency programmable coun-
ters to be used as high–frequency programmable counters with
speed capability of several hundred MHz. This is possible
without the sacrifice in system resolution and performance that
results if a fixed (single–modulus) divider is used for the
prescaler.
In dual–modulus prescaling, the lower speed counters must
be uniquely configured. Special control logic is necessary to
select the divide value P or P ÷ 1 in the prescaler for the
required amount of time (see modullus control definition).
Lansdale’s dual–modulus frequency synthesizers contain this
feature and can be used with a variety of dual–modulus
prescalers to allow speed, complexity and cost to be tailored to
the system requirements. Prescalers having P, P ÷ 1 divide val-
ues in the range of ÷3/÷4 to ÷128/÷129 can be controlled by
most Lansdale frequency synthesizers.
applies. If A
= P – 1, then N
≥ P – 1. Then NTmin =
max
min
(P – 1) P + A or (P – 1)P since A is free to assume the value of 0.
÷ N • P + A
N
Tmax
max max
To maximize system frequency capability, the dual–modulus
prescaler output must go from low to high after each group of
P or P – 1 input cycles. The prescaler should divide by P when
its modulus control line is high and by P – 1 when the modulus
control is low.
For the maximum frequency into the prescaler (f
max),
VCO
the value used for P must be large enough such that:
1. f max divided by P may not exceed the frequency
VCO
capability of f (input to the ÷N and ÷A counters).
in
2. The period of f
divided by P must be greater than the
VCO
sum of the times:
a. Propagation delay through the dual modulus
prescaler.
b. Prescaler setup or release time relative to its modulus
control signal.
c. Propagation time from f to the modulus control
in
Several dual–modulus prescaler approaches suitable for use
with the ML145146 are:
output for the frequency synthesizer device.
A sometimes useful simplification in the programming code
can be achieved by choosing the values for P of 8, 16, 32, or
64. For these cases, the desired value of N results when N
T
T
ML12009
ML12011
ML12013
ML12015
ML12016
ML12017
ML12018
ML12032
÷5/÷6
÷8/÷9
÷10/÷11
÷32/÷33
÷40/÷41
440 MHz
500 MHz
500 MHz
225 MHz
225 MHz
225 MHz
520 MHz
1.1 GHz
in binary is used as the program code to the ÷N and ÷A coun-
ters treated in the following manner:
a
1. Assume the ÷A counter contains “a” bits where 2 ≥P.
2. Always program all higher order ÷A counter bits
above “a” to 0
÷64/÷65
÷128/÷129
÷64/65 or ÷128/129
3. Assume the ÷N counter and the ÷A counter (with all
the higher order bits above “a” ignored) combined
into a single binary counter of n + a bits in length (n =
number of divider stages in the ÷N counter). The
MSB of this “hypothetical” counter is to correspond to
the MSB of ÷N and the LSB is to correspond to the
DESIGN GUIDELINES
The system total divide value. N
by the application. i.e.,
(N ) will be dictated
T
total
LSB of ÷A. The system divide value, N , now results
T
when the value of N in binary is used to program
the “new” n + a bit counter.
T
By using the two devices, several dual–modulus values are
achievable (shown in Figure 11).
Page 9 of 12
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ML145146
LANSDALE Semiconductor, Inc.
APPLICATION
MC
The features of the ML145146 permit bus operation with a
dedicated wire needed only for the strobe input. In a micro-
processor–controlled system this strobe input is accessed
when the phase lock loop is addressed. The remaining data
and address inputs will directly interface to the microproces-
sor’s data and address buses.
The device architecture allows the user to establish any
integer reference divide value between 3 and 4095. The wide
selection of ÷R values permits a high degree of flexibility in
choosing the reference oscillator frequency. As a result the
reference oscillator can frequently be chosen to serve multi-
ple system functions such as a second local oscillator in a
receiver design or a microprocessor system clock. Typical
applications that take advantage of these ML145146 features
including the dual modulus capability are shown in Figures
12, 13 and 14.
DEVICE A
DEVICE
DEVICE B
B
ML12009
÷20/÷21
ML12011
÷32/÷33
ML12013
÷40/÷41
DEVICE A
MC10131
MC10138
MC10154
÷50/÷51
÷80/÷81
÷100/÷101
÷80/÷81
÷40/÷41
OR
÷64/÷65
OR
÷128/÷129
÷80/÷81
NOTE: ML12009, ML12011 and ML12013 are pin equivalent.
ML12015, ML12016 and ML12017 are pin equivalent.
Figure 11. Dual Modulus Values
Page 10 of 12
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ML145146
LANSDALE Semiconductor, Inc.
CHOICE OF
REF. OSC.
FREQUENCY
(ON–CHIP OSC.
OPTIONAL)
FOR USE WITH EXTERNAL
PHASE DETECTOR (OPTIONAL)
}
LOCK DETECT
SIGNAL
RECEIVER LO.
443.325
(25 kHz STEPS)
443.950 MHz
8
18
15
13
LD
f
f
OSC
R
V
out
5
PD
7
6
4
out
TRANSMITTER
OSC
in
LOOP
MODULATION
AND 15.7 MHz
OFFSET
17
16
φ
R
VCO
FILTER
TRANSMITTER SIGNAL
459.025 – 459.650 MHz
(25 kHz STEPS)
ML145146
}
φ
V
V
CHOICE OF DETECTOR
ERROR SIGNALS
DD
MOD
CONTROL
14
3
V
SS
D3 D2 D1 D0 A2 A1 A0
f
in
ST
19
20
1
2
11
10
9
12
ML12034 PRESCALER
CHIP
SELECT TO
TO SHARED CONTROLLER BUS
CONTROLLER
NOTES:
1. Reciever I.F = 10.7 MHz, low side injection.
2. Duplex operation with 5 MHz receive/transmit separation.
3. f = 25 kHz, + R chosen to correspond with desired reference oscillator frequency.
R
4. N
= 17,733 to 17,758 = N • P + A; N = 227, A = 5 to 30 for P = 64.
total
Figure 13. Synthesizer for UHF Mobil Radio Telephone Channels Demonstrates Use of the ML145146 in
Microprocessor/Microcomputer Controlled Systems Operating to Several Hundred MHz
RECEIVER
2ND, L.O.
33,300 MHZ
CHOICE OF
REF. OSC.
FREQUENCY
(ON–CHIP OSC.
OPTIONAL)
FOR USE WITH EXTERNAL
PHASE DETECTOR (OPTIONAL)
}
X3
LOCK DETECT
SIGNAL
RECEIVER FIRST L.O.
825.030 844.980 MHZ
(30 KHz STEPS)
5
LD
8
f
f
V
OSC
R
out
PD
7
6
4
out
OSC
in
LOOP
FILTER
17
16
14
3
φ
X4
R
VCO
ML145146
}
TRANSMITTER
MODULATION
φ
V
V
X4
DD
CHOICE OF DETECTOR
ERROR SIGNALS
MOD
CONTROL
V
TRANSMITTER SIGNAL
825.030 844.880 MHz
(30 kHz STEPS)
SS
D3 D2 D1 D0 A2 A1 A0
f
in
ST
19
20
1
2
11
10
9
12
MC10131
DUAL F/F
ML12011
÷8/÷9 PRESCALER
CHIP
SELECT TO
CONTROLLER
TO SHARED CONTROLLER BUS
+32/+32 DUAL MODULUS PRESCALER
NOTES:
1. Receiver 1st I.F. = 45 MHz, low side injection; Receiver 2nd I.F. = 11.7 MHz, low side injection.
2. Duplex operation with 45 MHz receive/transmit separation.
3. f = 7.5 kHz, + R = 1480.
R
4. N
total
= N • 32 + A = 27,501 to 28,166: N = 859 to 880; A = 0 to 31.
5. Only one implementation is shown. Various other configurations and dual–modulus prescaling values to ÷128/÷129 are possible.
Figure 14. 666 Channel, Computer Controlled, Mobile Radio Telephone Synthesizer for
800 MHz Cellular Radio Systems
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ML145146
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
SOG = -6P
(MC145146-6P)
CASE 751D-04
-A-
NOTES:
20
11
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982
2. CONTROLLING DIMENSION: MILLIMETER
3. DIMENSIONA AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150 (0.006)
PER SIDE
-B-
P 10 PL
M
M
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL, IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
1
1
0
J
INCHES
MIN
12.65
7.40
2.35
0.35
0.50
MILLIMETERS
M
S
S
0.25 (0.010)
T
B
A
DIM
A
B
C
D
MAX
12.95
7.60
2.65
0.49
0.90
MIN
MAX
0.510
0.299
0.104
0.019
0.035
0.499
0.292
0.093
0.014
0.020
F
F
R X 45°
G
1.27 BSC
0.050 BSC
J
K
0.25
0.10
0.32
0.25
0.010
0.020
0.012
0.035
C
M
P
R
10.05
0.25
10.56
0.75
.0395
0.010
0.415
0.029
-T-
M
K
PLASTIC DIP
(MC145146RP)
CASE 738-03
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982
20
1
11
0
2. CONTROLLING DIMENSION: INCH
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL
B
1
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH
C
L
INCHES
MIN
1.010
0.240
0.150
0.015
MILLIMETERS
DIM
A
B
C
D
E
MAX
1.070
.0260
0.180
0.022
MIN
25.66
6.10
3.81
0.39
MAX
27.17
6.60
4.57
0.55
-T-
SEATING
PLANE
K
M
0.050 BSC
1.27BSC
F
G
0.050
0.100 BSC
0.070
1.27
2.54 BSC
1.77
E
N
J
K
L
M
N
0.008
0.110
0.300 BSC
0.015
0.140
0.21
2.80
7.62 BSC
0.38
3.55
G
F
J 20 PL
0.25 (0.010)
D 20 PL
M
M
T
B
M
M
0.25 (0.010)
T
A
0.020
0.040
0.51
1.01
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili-
ty, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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相关型号：
ML145151
Parallel-Input PLL Frequency Synthesizer Interfaces with Single-Modulus Prescalers
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