ML145443 [LANSDALE]
Single-Chip 300-Baud Modem; 单芯片300波特率的调制解调器
| 型号： | ML145443 |
| 厂家： | 
LANSDALE SEMICONDUCTOR INC. |
| 描述： | Single-Chip 300-Baud Modem |
| 文件： | 总11页 (文件大小：800K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ML145442
ML145443
Single–Chip 300–Baud Modem
Legacy Device: Motorola MC145442B, MC145443B
The ML145442 and ML145443 silicon–gate CMOS single–chip low–speed
modems contain a complete frequency shift keying (FSK) modulator, demod-
ulator, and filter. These devices are compatible with CCITT V.21 (ML145442)
and Bell 103 (ML145443) specifications. Both devices provide full–duplex or
half–duplex 300–baud data communication over a pair of telephone lines.
They also include a carrier detect circuit for the demodulator section and a
duplexer circuit for direct operation on a telephone line through a simple
transformer.
P DIP 20 = RP
PLASTIC DIP
CASE 738
20
1
SOG 20 = -6P
SOG PACKAGE
CASE 751D
20
1
This Device Offers The Following Performance Features:
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
MC145442BP
LANSDALE
ML145442RP
• ML145442 Compatible with CCITT V.21
• ML145443 Compatible with Bell 103
• Low–Band and High–Band Band–Pass Filters On–Chip
• Simplex, Half–Duplex, and Full–Duplex Operation
• Originate and Answer Mode
P DIP 20 H
SO 20W
MC145442BDW ML145442-6P
P DIP 20 H
SO 20W
MC145443BP
ML145443RP
MC145443BDW ML145443-6P
• Analog Loopback Configuration for Self Test
• Hybrid Network Function On–Chip
• Carrier Detect Circuit On–Chip
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
• Adjustable Transmit Level and CD Delay Timing
• On–Chip Crystal Oscillator (3.579 MHz)
• Single +5 V Power Supply Operation
• Internal Mid–Supply Generator
PIN ASSIGNMENT
• Power–Down Mode
DSI
LB
1
2
20 TLA
19
• Pin Compatible with MM74HC943
• Capable of Driving –9 dBm into a 600 W Load
V
AG
• Operating Temperature Range = T –40° to +85°C
A
CD
3
4
18 Exl
17 TxA
CDT
RxD
5
6
16 RxA1
15 RxA2
14 SQT
13 MODE
V
DD
CDA
7
8
9
X
out
X
12
V
SS
in
FB 10
11 TxD
Page 1 of 11
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Issue Bb
ML145442, ML145443
LANSDALE Semiconductor, Inc.
BLOCK DIAGRAM
4
7
CDT
CDA
LOW–BAND
15
BPF
RxA2
3
5
CARRIER
DETECT
CD
–
+
AAF
S/H
16
RxA1
AC AMP
*
RxD
DEMOD
HIGH–BAND
BPF
10
1
FB
DSI
SMOOTHING
FILTER
2
13
17
18
–
LB
MODE
TxA
ExI
MODE
CONTROL
+
14
11
20
SQT
TxD
TLA
ANALOG
GROUND
MODULATOR
19
6
INTERNAL
V
AG
V
AG
GENERATOR
8
9
V
V
X
SAMPLING CLOCK: 77.82 kHz
SAMPLING CLOCK: 19.46 kHz
DD
SS
CLOCK
DIVIDER
out
OSCILLATOR
12
X
in
* Refer to the FB pin description.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V
)
SS
This device contains circuitry to protect the
Rating
Symbol
Value
Unit
V
inputs against damage due to high static volt-
ages or electric fields; however, it is advised that
normalprecautions be taken to avoid application
of any voltage higher than maximum rated
voltages to this high impedance circuit. For
Supply Voltage
V
DD
–0.5 to 7.0
DC Input Voltage
V
in
–0.5 to V
+ 0.5
V
DD
DC Output Voltage
V
out
–0.5 to V
+ 0.5
V
DD
proper operation it is recommended that V and
in
Clamp Diode Current, per Pin
DC Output Current, per Pin
Power Dissipation
I , I
IK OK
20
mA
mA
mW
°C
°C
V
V
be constrained to the range V
≤ (V or
out
out
SS in
I
28
) ≤ V ).
out
DD
Unused inputs must always be tied to an
P
D
500
appropriate logic voltage level (e.g., either V
SS
Operating Temperature Range
Storage Temperature Range
T
A
–40 to 85
or V ).
DD
T
stg
–65 to 150
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Symbol
Min
4.5
0
Max
Unit
V
V
DD
5.5
DC Input or Output Voltage
Input Rise or Fall Time
Crystal Frequency*
V
, V
V
DD
V
in out
t , t
—
500
5.0
ns
r
f
f
3.2
MHz
crystal
* Changing the crystal frequency from 3.579 MHz will change the output frequencies. The
change in output frequency will be proportional to the change in crystal frequency.
Page 2 of 11
www.lansdale.com
Issue Bb
LANSDALE Semiconductor, Inc.
ML145442, ML145443
DC ELECTRICAL CHARACTERISTICS (V
Characteristic
= 5.0 V 10%, T = –40° to 85°C)
DD
A
Symbol
Min
– 0.8
DD
Typ
Max
Unit
High–Level Input Voltage
LB
V
IH
V
—
—
—
—
V
X , TxD, Mode, SQT
in
3.15
Low–Level Input Voltage
High–Level Output Voltage
LB
V
—
—
—
—
0.8
1.1
V
V
IL
X
in
, TxD, Mode, SQT
V
OH
I
I
I
= 20 µA
= 2 mA
= 20 µA
CD, RxD
CD, RxD
V
– 0.1
—
—
—
—
—
OH
OH
OH
DD
3.7
—
X
V
– 0.05
out
DD
Low–Level Output Voltage
V
OL
V
I
I
I
= 20 µA
= 2 mA
= 20 µA
CD, RxD
CD, RxD
—
—
—
—
—
0.05
0.1
0.4
—
OL
OL
OL
X
out
Input Current
LB, TxD, Mode, SQT
I
in
—
—
—
—
—
10
—
—
1.0
12
20
10
µA
RxA1, RxA2 (0°
RxA1, RxA2 (–40°
T
A
T
A
85°C)
< 0°C)
X
in
Quiesent Supply Current (X or f
in
= 3.579 MHz)
I
—
—
7
10
mA
µA
pF
crystal
DD
Power–Down Supply Current
Input Capacitance
200
300
X
C
—
—
10
—
—
10
in
in
All Other Inputs
V
Output Voltage (I
=
=
10 µA)
10 µA)
V
2.4
1.1
10
2.5
1.2
20
2.6
1.3
30
V
V
AG
O
AG
CDA Output Voltage (I
V
CDA
O
Line Driver Feedback Resistor
R
kΩ
f
AC ELECTRICAL CHARACTERISTICS
(V
DD
= 5.0 V 10%, T = –40° to 85°C, Crystal Frequency = 3.579 MHz 0.1%; See Figure 1)
A
Characteristic
Min
Typ
Max
Unit
TRANSMITTER
Power Output on TxA
dBm
–13
–10
–12
–9
–11
–8
R
R
= 1.2 kΩ, R
= 1.2 kΩ, R
= ∞
= 5.5 kΩ
L
L
TLA
TLA
Second Harmonic Power
= 1.2 kΩ
—
– 56
—
dBm
R
L
RECEIVE FILTER AND HYBRID
Hybrid Input Impedance RxA1, RxA2
FB Output Impedance
40
—
50
16
—
—
—
—
kΩ
kΩ
Adjacent Channel Rejection
DEMODULATOR
–48
dBm
Receive Carrier Amplitude
Dynamic Range
–48
—
—
36
100
5
–12
—
dBm
dB
Bit Jitter (S/N = 30 dB, Input = –38 dBm, Bit Rate = 300 baud)
Bit Bias
—
—
µs
—
—
%
Carrier Detect Threshold
(CDA = 1.2 V or CDA grounded through a 0.1 µF capacitor)
On to Off
Off to On
—
—
–44
–47
—
—
dBm
Page 3 of 11
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Issue b
ML145442, ML145443
LANSDALE Semiconductor, Inc.
Table 1. Bell 103 and CCITT V.21
Frequency Characteristics
Originate Mode
Answer Mode
3.579 MHz 0.1%
Data
Bell 103 (ML145443)
Transmit
Receive
Transmit
Receive
8
X
TLA
9
Space
Mark
1070 Hz
1270 Hz
2025 Hz
2225 Hz
2025 Hz
2225 Hz
1070 Hz
1270 Hz
R
TLA
X
in
TxD
out
11
20
17
15
D
in
V
DD
TxA
CCITT V.21 (ML145442)
RxA2
Space
Mark
1180 Hz
980 Hz
1850 Hz
1650 Hz
1850 Hz
1650 Hz
1180 Hz
980 Hz
ML145442
ML145443
600 Ω
600 Ω
NOTE: Actual frequencies may be 5 Hz assuming 3.579545 MHz
crystal is used.
16
5
RxA1
CDT
4
RxD
FB
10
D
out
TEST
OUTPUT
0.1 µF
TEST
INPUT
MAXIMUM LEVEL OF OUT–OF–BAND ENERGY
RELATIVE TO THE TRANSMIT CARRIER LEVEL INTO 600Ω (kHz)
0.1 µF
0
2
3.4 4
16
64
256
C
C
FB
CDT
Figure 1. AC Characteristics Evaluation Circuit
0
PIN DESCRIPTIONS
–20
–25
V
DD
Positive Power Supply (Pin 6)
15 dB/OCTAVE
This pin is normally tied to 5.0 V.
V
SS
–55
–60
Negative Power Supply (Pin 12)
This pin is normally tied to 0 V.
V
Figure 2. Out–of–Band Energy
AG
Analog Ground (Pin 19)
ExI
External Input (Pin 18)
Analog ground is internally biased to (V
– V )/2. This
SS
DD
pin must be decoupled by a capacitor from V
to V and a
AG
SS
The external input is the non–inverting input to the line driver.
It is provided to combine an auxiliary audio signal or speech
signal to the phone line using the line driver. This pin should be
capacitor from V
AG
line used in the switched capacitor filters, limiter, and slicer in
the demodulation circuitry.
to V . Analog ground is the common bias
DD
connected to V
if not used. The average level must be the
to maintain proper operation. (See Legacy
AG
TLA
same as V
AG
Transmit Level Adjust (Pin 20)
Applications Information.)
This pin is used to adjust the transmit level. Transmit level
adjustment range is typically from –12 dBm to –9 dBm. (See
Legacy Applications Information.)
DSI
Driver Summing Input (Pin 1)
The driver summing input may be used to connect an external
signal, such as a DTMF dialer, to the phone line. A series resis-
tor, RDSI, is needed to define the voltage gain AV (see Legacy
Applications Information and Figure 6). When applying a signal
to the DSI pin, the modulator should be squelched by bringing
SQT (pin 14) to a logic high level. The voltage gain, AV, is cal-
culated by the formula AV = –Rf/R
example, a 20 kΩ resistor for R
= –20 kΩ/20 kΩ = –1). This pin must be left open if not used.
TxD
Transmit Data (Pin 11)
Binary information is input to the transmit data pin. Data
entered for transmission is modulated using FSK techniques. A
logic high input level represents a mark and a logic low repre-
sents a space (see Table 1).
(where Rf≈ 20 kΩ). For
will provide unity gain (AV
DSI
DSI
TxA
Transmit Carrier (Pin 17)
RxD
This is the output of the line driver amplifier. The transmit
carrier is the digitally synthesized sine wave output of the modu-
lator derived from a crystal oscillator reference. When a 3.579
MHz crystal is used the frequency outputs shown in Table 1
apply. (See Legacy Applications Information.)
Receive Data (Pin 6)
The receive data output pin presents the digital binary data
resulting from the demodulation of the receive carrier. If no car-
rier is present, CD high, the receive data output (RxD) is
clamped high.
Page 4 of 11
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Issue b
LANSDALE Semiconductor, Inc.
ML145442, ML145443
RxA2, RxA1
Receive Carrier (Pins 15, 16)
threshold level for longer than the turn off time. (See Legacy
Applications Information and Figure 5.)
The receive carrier is the FSK input to the demodulator through
the receive band–pass filter. RxA1 is the non–inverting input and
RxA2 is the inverting input of the receive hybrid (duplexer) oper-
ational amplifier.
CDA
Carrier Detect Adjust (Pin 7)
An external voltage may be applied to this pin to adjust the car-
rier detect threshold. The threshold hysteresis is internally fixed at
3 dB (see Legacy Applications Information).
LB
Analog Loopback (Pin 2)
Xout, Xin
Crystal Oscillator (Pins 8, 9)
When a high level is applied to this pin (SQT must be low), the
analog loopback test is enabled. The analog loopback test con-
nects the TxA pin to the RxA2 pin and the RxA1 to analog
ground. In loopback, the demodulator frequencies are switched to
the modulation frequencies for the selected mode. (See Tables 1
and 2 and Figures 4c and 4d.)
A crystal reference oscillator is formed when a 3.579 MHz
crystal is connected between these two pins. X
output of the oscillator circuit, and X (pin 9) is the input to the
oscillator circuit. When using an external clock, apply the clock to
the X (pin 9) pin and leave X
MΩ resistor and internal capacitors, typically 10 pF on X and
16 pF on X , allow the crystal to be connected without any
(pin 8) is the
out
in
(pin 8) open. An internal 10
in
out
When LB is connected to analog ground (V ), the modulator
AG
in
generates an echo cancellation tone of 2100 Hz for ML145442
CCITT V.21 and 2225 Hz for ML145443 Bell 103 systems. For
out
other external components. Printed circuit board layout should
keep external stray capacitance to a minimum.
normal operation, this pin should be at a logic low level (V ).
SS
The power–down mode is enabled when both LB and SQT are
connected to a logic high level (see Table 2).
FB
Filter Bias (Pin 10)
Table 2. Functional Table
This is the negative input to the AC amplifier. In normal opera-
tion, this pin is connected to analog ground through a 0.1µF
bypass capacitor in order to cancel the input offset voltage of the
limiter. It has a nominal input impedance of 16 kΩ (see Figure 3).
MODE
Pin 13
SQT
Pin 14
LB
Pin 2
Operating Mode
Originate Mode
Answer Mode
1
0
0
0
0
0
1
1
1
0
0
SQT
Transmit Squelch (Pin 14)
X
X
X
X
X
V
(V /2) Echo Tone
AG DD
When this input pin is at a logic high level, the modulator is
disabled. The line driver remains active if LB is at a logic low
level (see Table 2).
When both LB and SQT are connected to a logic high level (see
Table 2), the entire chip is in a power down state and all circuitry
except the crystal oscillator is disabled. Total power supply cur-
rent decreases from 10 mA (max) to 300 µA (max).
1
0
Analog Loopback
Squelch Mode
V
(V /2) Squelch Mode
AG DD
1
Power Down
MODE
Mode (Pin 13)
This input selects the pair of transmit and frequencies used dur-
ing modulation and demodulation. When a logic high level is
placed on this input, originate (Bell) or channel 1(CCITT) is
selected. When a low level is placed on this input, answer (Bell) or
channel 2 (CCITT) is selected. (See Tables 1 and 2 and Figure 4.)
FROM
BAND–PASS
FILTER
TO
+
–
CARRIER DETECT CIRCUIT
AND DEMODULATOR
CDT
Carrier Detect Timing (Pin 4)
A capacitor on this pin to V sets the amount of time the car-
SS
490 kΩ
16 kΩ
rier must be present before CD goes low (see Legacy Applications
Information for the capacitor values).
CD
10 FB
0.1 µF
Carrier Detect Output (Pin 3)
This output is used to indicate when a carrier has been sensed
by the carrier detect circuit. This output goes to a logic low level
when a valid signal above the maximum threshold level (defined
by CDA, pin 7) is maintained on the input to the hybrid circuit
longer then the response (defined by CDT, pin 4). This pin is held
at the logic low level until the signal falls below the maximum
Figure 3. AC Amplifier Circuit
Page 5 of 11
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Issue b
ML145442, ML145443
LANSDALE Semiconductor, Inc.
GENERAL DESCRIPTION
In the answer or channel 2 mode, a logic low level is placed on
MODE (pin 13) and on LB (pin 2). In this mode, the data follows
the same path except the FSK signal is routed to the high–band
band–pass filter and the sample–and–hold signal is routed through
the low–band band–pass filter (see Figure 4b).
In the analog loopback originate or channel 1 mode, a logic high
level is placed on MODE (pin 13) and on LB (pin 2). This mode is
used for a self check of the modulator, demodulator, and low–band
pass–band filter circuit. The modulator side is configured exactly
like the originate mode above except the line driver output (TxA,
pin 17) is switched to the negative input of the hybrid op–amp. The
RxA2 input pin is open in this mode and the non–inverting input of
The ML145442 and ML145443 are full–duplex low–speed
modems. They provide a 300–baud FSK signal for bidirectional
data transmission over the telephone network. They can be operated
in one of four basic configurations as determined by the state of
MODE (pin 13) and LB (pin 2).The normal (non–loopback) and
self test (loopback) modes in both answer and originate modes will
be discussed.
For an originate or channel 1 mode, a logic high level is placed
on MODE (pin 13) and a logic low level is placed on LB (pin 2). In
this mode, transmit data is input on TxD, where it is converted to a
FSK signal and routed through a low–band band–pass filter. The
filtered output signal is then buffered by the Tx op–amp line driver,
which is capable of driving –9 dBm onto a 600Ω line. The receive
signal is connected through a hybrid duplexer circuit on pins 15 and
16, RxA2 and RxA1. The signal then passes through the anti–alias-
ing filter, the sample–and–hold circuit, is switched into the
high–band band–pass filter, and then switched into the AC amplifi-
er circuit. The output of the ac amplifier circuit is routed to the
demodulator circuit and demodulated. The resulting digital data is
then output through RxD (pin 5). The carrier detect circuit receives
its signal from the output of the AC amplifier circuit and goes low
when the incoming signal is detected (see Figure 4a).
the hybrid circuit is connected to V . The sample–and–hold out-
AG
put bypasses the filter so that the demodulator receives the modu-
lated Tx data (see Figure 4c). This test checks all internal device
components except the high–band band–pass filter, which can be
checked in the answer or channel 2 mode test.
In the analog loopback or channel 2 mode, a logic low level is
placed on MODE (pin 13) and a logic high level on LB (pin 2).
This mode is used for a self check of the modulator, demodulator,
and high–band pass–band filter circuit. This configuration is exact-
ly like the originate loopback mode above, except the signal is rout-
ed through the high–band pass–band filter (see Figure 4d).
Page 6 of 11
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Issue b
LANSDALE Semiconductor, Inc.
ML145442, ML145443
15
RxA2
CARRIER
DETECT
3
CD
–
AC
AMP
LOW–BAND
BPF
AAF
S/H
16
+
RxA1
5
DEMOD
RxD
1
DSI
11
HIGH–BAND
BPF
SMOOTHING
FILTER
TxD
–
MODULATOR
17
TxA
+
18
Exl
(a) Originate/Channel 1 Mode (MODE = High, LB = Low)
15
RxA2
CARRIER
DETECT
3
CD
–
AC
AMP
LOW–BAND
BPF
AAF
S/H
16
RxA1
+
5
DEMOD
RxD
1
DSI
11
HIGH–BAND
BPF
SMOOTHING
FILTER
TxD
MODULATOR
–
17
TxA
+
18
Exl
(b) Answer/Channel 2 Mode (MODE = Low, LB = Low)
15
RxA2
CARRIER
DETECT
3
CD
–
AC
AMP
AAF
S/H
16
+
LOW–BAND
BPF
RxA1
5
DEMOD
RxD
1
DSI
11
HIGH–BAND
BPF
SMOOTHING
FILTER
–
TxD
MODULATOR
17
TxA
+
18
Exl
(c) Originate/Channel 1 Mode and Analog Loopback State (MODE = High, LB = Low)
15
16
RxA2
RxA1
CARRIER
DETECT
3
CD
–
AC
AMP
AAF
S/H
+
LOW–BAND
BPF
5
RxD
DEMOD
1
DSI
11
HIGH–BAND
BPF
SMOOTHING
FILTER
MODULATOR
–
TxD
17
TxA
+
18
Exl
(d) Answer/Channel 2 Mode and Analog Loopback State (MODE = Low, LB = Low)
Figure 4. Basic Operating Modes
Page 7 of 11
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Issue b
ML145442, ML145443
LANSDALE Semiconductor, Inc.
Legacy Applications Information
CARRIER DETECT TIMING ADJUSTMENT
sponding power output for a 600 Ω load. The voltage at TxA is
twice the value of that at ring and tip because TxA feeds the
The value of a capacitor, C
how long a received modem signal must be present above the
minimum threshold level before CD (pin 3) goes low. The
at CDT (pin 4) determines
CDT
signal through a 600 Ω resistor R to a 600 Ω line trans-
Tx
former (see Figure 7). When choosing resistor R
, keep in
TLA
mind that –9 dBm is the maximum output level allowed from a
modem onto the telephone line (in the U.S.). In addition, keep
in mind that maximizing the power output from the modem
optimizes the signal–to–noise ratio, improving accurate data
transmission.
C
capacitor also determines how long the CD pin stays
CDT
low after the received modem signal goes below the mini mum
threshold. The CD pin is used to distinguish a strong modem
signal from random noise. The following equations show the
relationship between t
, the time in seconds required for
CDL
CD to go low; t
, the time in seconds required for CD to
, the capacitor value in µF.
Table 3. Transmit Level Adjust
Output Transmit Level
CDH
go high; and C
CDT
(Typical into 600 Ω)
R
Valid signal to CD response time:
Invalid signal to CD off time:
t
t
≈ 6.4 X C
CDL
TLA
CDT
0.54 X C
–12 dBm
–11 dBm
–10 dBm
–9 dBm
∞
CDH ≈
CDT
19.8 kΩ
9.2 kΩ
5.5 kΩ
Example:
t
t
≈ 6.4 X 0.1 µF ≈ 0.64 seconds
≈ 0.54 X 0.1 µF ≈ 0.054 seconds
CDL
CDH
CARRIER DETECT THRESHOLD ADJUSTMENT
THE LINE DRIVER
The carrier detect threshold is set by internal resistors to
The line driver is a power amplifier used for driving a tele-
phone line. Both the inverting and noninverting input to the line
driver are available for transmitting externally generated tones.
Exl (pin 18) is the noninverting input to the line driver and
activate CD with a typical –44 dBm (into 600 Ω) signal and
deactivate CD with a typical –47 dBm signal applied to the
input of the hybrid circuit. The carrier detect threshold level
can be adjusted by applying an external voltage on CDA (pin
7). The following equations may be used to find the CDA volt-
gives a fixed gain of 2 (R = 50 kΩ). The average signal level
i
must be the same as V
to maintain proper operation. This
if not used.
AG
age required for a given threshold voltage. (V and V are in
on off
pin should be connected to V
AG
Vrms.)
The driver summing input (DSI, pin 1) may be used to con-
nect an external signal, such as a DTMF dialer, to the phone
line. When applying a signal to the DSI pin, the modulator
should be squelched by bringing SQT (pin 14) to a logic high
level. DSI must be left open if not used.
VCDA = 244 x V
on
off
VCDA = 345 x V
Example (Internally Set)
V
V
off
= 4.9 mV –44 dBm: VCDA = 244 x 4.9 mV = 1.2 V
on
≈
= 3.5 mV –47 dBm: VCDA = 345 x 3.5 mV = 1.2 V
R
R
≈
f
A
= –
V
DSI
Example (Externally Set)
V
V
off
= 7.7 mV –40 dBm: VCDA = 244 x 7.7 mV = 1.9 V
= 5.4 mV –43 dBm: VCDA = 345 x 5.4 mV = 1.9 V
≈
on
≈
In addition, the DSI pin is the inverting side of the line driv-
er and allows adjustable gain with a series resistor RDSI (see
Figure 6). The voltage gain, AV, is determined by the equation:
The CDA pin has an approximate Thevenin equivalent volt-
age of 1.2 V and an output impedance of 100 kΩ. When using
the internal 1.2 V reference, a 0.1 µF capacitor should be con-
nected between this pin and V (see Figure 5).
SS
TRANSMIT LEVEL ADJUSTMENT
where Rf ≈ 20 kΩ.
Example: A resistor value of 20 kΩ for R
unity gain.
will provide
DSI
A = – (20 kΩ/20 kΩ) = –1 .
V
The power output at TxA (pin 17) is determined by the value
of resistor R
that is connected between TLA (pin 20) to
values and the corre-
TLA
V
(pin 6). Table 3 shows the R
TLA
DD
Page 8 of 11
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Issue b
LANSDALE Semiconductor, Inc.
Legacy Applications Information
HYBRID
ML145442, ML145443
V
DD
ac
AMP
AUTO–NULLED
COMPARATOR
16
6 ms
RETRIGGERABLE
ONE–SHOT
3
RxA1
CD
V
ref
7
V
≈ 1.2 V
SAMPLING
CLOCK
THRESHOLD
CONTROL
CDA
CDA
4
CDT
C
CDA
0.1 µF
C
CDT
0.1 µF
Figure 5. Carrier Detect Circuit
MODULATOR
OUTPUT
R
= R
f
0
R
0
DSI
R
R
DSI
f
1
TxA
17
ExI
18
–
+
R
i
V
AG
19
Figure 6. Line Driver Using the DSI Input
Page 9 of 11
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Issue b
ML145442, ML145443
LANSDALE Semiconductor, Inc.
Legacy Applications Information
L
ML145407
Page 10 of 11
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Issue b
LANSDALE Semiconductor, Inc.
ML145442, ML145443
Legacy Applications Information
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabil-
ity, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the cus-
tomer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Page 11 of 11
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Issue b
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