FEDL610Q421-02 [LAPIS]
8-bit Microcontroller with a Built-in LCD driver;
| 型号： | FEDL610Q421-02 |
| 厂家： | 
LAPIS Semiconductor Co., Ltd. |
| 描述： | 8-bit Microcontroller with a Built-in LCD driver CD 微控制器 |
| 文件： | 总37页 (文件大小：792K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL610Q421-03
Issue Date: Feb.9, 2015
ML610Q421/ML610Q422
8-bit Microcontroller with a Built-in LCD driver
GENERAL DESCRIPTION
This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port,
UART, I2C bus interface (master), melody driver, battery level detect circuit, RC oscillation type A/D converter, 12-bit
successive approximation type A/D converter, and LCD driver, are incorporated around 8-bit CPU nX-U8/100.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture
parallel procesing. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption operation
(read operation) equivalent to mask ROM and is most suitable for battery-driven applications.
The on-chip debug function that is installed enables program debugging and programming.
FEATURES
• CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system: 16-bit instructions
− Instruction set:
Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic
shift, and so on
− On-Chip debug function
− Minimum instruction execution time
30.5 µs (@32.768 kHz system clock)
0.24 4µs (@4.096 MHz system clock)
• Internal memory
− Internal 32KBbyte Flash ROM (16K×16 bits) (including unusable 1KByte TEST area)
− Internal 1KByte Data RAM (1024×8 bits), 1KByte Display Allocation RAM (1024 x 8bit)
− Internal 100Byte RAM for display
• Interrupt controller
− 2 non-maskable interrupt sources (Internal source: 1, External source: 1)
− 20 maskable interrupt sources (Internal sources: 16, External sources: 4)
• Time base counter
− Low-speed time base counter ×1 channel
Frequency compensation (Compensation range: Approx. −488ppm to +488ppm. Compensation accuracy: Approx.
0.48ppm)
− High-speed time base counter ×1 channel
• Watchdog timer
− Non-maskable interrupt and reset
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
• Timers
−
−
8 bits × 4 channels (Timer0-3: 16-bit x 2 configuration available by using Timer0-1 or Timer2-3)
Clock frequency measurement mode (in one channel of 16-bit configuration using Timer2-3)
1/37
FEDL610Q421-03
ML610Q421/ML610Q422
• 1 kHz timer
− 10 Hz/1 Hz interrupt function
• Capture
− Time base capture × 2 channels (4096 Hz to 32 Hz)
• PWM
− Resolution 16 bits × 1 channel
• Synchronous serial port
− Master/slave selectable
− LSB first/MSB first selectable
− 8-bit length/16-bit length selectable
• UART
− TXD/RXD × 1 channel
− Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
− Positive logic/negative logic selectable
− Built-in baud rate generator
• I2C bus interface
− Master function only
− Fast mode (400 kbps@4MHｚ), standard mode (100 kbps@1MHｚ, 50kbps@500kHz)
• Melody driver
− Scale: 29 types (Melody sound frequency: 508 Hz to 32.768 kHz)
− Tone length: 63 types
− Tempo: 15 types
− Buzzer output mode (4 output modes, 8 frequencies, 16 duty levels)
• RC oscillation type A/D converter
− 24-bit counter
− Time division × 2 channels
• Successive approximation type A/D converter
− 12-bit A/D converter
− Input × 2 channels
• General-purpose ports
− Non-maskable interrupt input port × 1 channel
− Input-only port × 6 channels (including secondary functions)
− Output-only port × 3 channels (including secondary functions)
− Input/output port
ML610Q421: 22 channels (including secondary functions)
ML610Q422: 14 channels (including secondary functions)
2/37
FEDL610Q421-03
ML610Q421/ML610Q422
• LCD driver
− Dot matrix can be supported.
ML610Q421: 400 dots max. (50 seg × 8 com), 1/1 to 1/8 duty
ML610Q422: 800 dots max. (50 seg × 16 com) , 1/1 to 1/16 duty
− 1/3 or 1/4 bias (built-in bias generation circuit)
− Frame frequency selecable (approx. 64 Hz, 73 Hz, 85 Hz, and 102 Hz)
− Bias voltage multiplying clock selectable (8 types)
− Contrast adjustment (1/3 bias: 32 steps, 1/4 bias: 20 steps)
− LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable
− Programmable display allocation function (available only when 1/1~1/8 duty is selected)
• Reset
− Reset through the RESET_N pin
− Power-on reset generation when powered on
− Reset when oscillation stop of the low-speed clock is detected
− Reset by the watchdog timer (WDT) overflow
• Power supply voltage detect function
− Judgment voltages:
− Judgment accuracy:
One of 16 levels
±2% (Typ.)
• Clock
− Low-speed clock: (This LSI can not guarantee the operation withoug low-speed clock)
Crystal oscillation (32.768 kHz)
− High-speed clock:
Built-in RC oscillation (500 kHz)
Built-in PLL oscillation (8.192 MHz ±2.5%), crystal/ceramic oscillation (4.096 MHz), external clock
− Selection of high-speed clock mode by software:
Built-in RC oscillation, built-in PLL oscillation, crystal/ceramic oscillation, external clock
• Power management
− HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).
− STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are
stopped.)
− Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation
clock)
− Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals.
• Guaranteed operating range
− Operating temperature: −20°C to 70°C (P version: −40°C to +85°C)
− Operating voltage: VDD = 1.1V to 3.6V, AVDD = 2.2V to 3.6V
3/37
FEDL610Q421-03
ML610Q421/ML610Q422
•Product name – Supported Function
The line-up of the ML610Q421 and the ML610Q422 is below.
Operating
temperature
- Chip (Die) -
ROM type
Product availability
ML610Q421-xxxWA
ML610Q422-xxxWA
ML610Q421P-xxxWA
ML610Q422P-xxxWA
Flash ROM
Flash ROM
Flash ROM
Flash ROM
-20°C to +70°C
-20°C to +70°C
-40°C to +85°C
-40°C to +85°C
Yes
Yes
Yes
Yes
-120-pin plastic
TQFP -
Operating
temperature
ROM type
Product availability
ML610Q421-xxxTB
ML610Q422-xxxTB
ML610Q421P-xxxTB
ML610Q422P-xxxTB
Flash ROM
Flash ROM
Flash ROM
Flash ROM
-20°C to +70°C
-20°C to +70°C
-40°C to +85°C
-40°C to +85°C
Yes
Yes
Yes
Yes
xxx: ROM code number (xxx of the blank product is NNN)
Q: Flash ROM version
P: Wide range temperature version (P version)
WA: Chip (Die),
TB: TQFP
4/37
FEDL610Q421-03
ML610Q421/ML610Q422
BLOCK DIAGRAM
ML610Q421 Block Diagram
Figure 1 show the block diagram of the ML610Q421.
"*" indicates the secondary function of each port.
CPU (nX-U8/100)
EPSW1～3
ELR1～3
ECSR1～3
DSR/CSR
PC
GREG
0～15
PSW
LR
EA
SP
Timing
Controller
ALU
Program
Memory
(Flash)
BUS
Controller
VPP
Instruction
Decoder
Instruction
Register
On-Chip
ICE
32Kbyte
Data-bus
VDD
VSS
INT
1
SCK0*
SIN0*
SSIO
UART
I2C
RAM
1024byte
SOUT0*
RESET_N
TEST
RESET &
TEST
INT
1
Interrupt
Controller
RXD0*
TXD0*
XT0
XT1
INT
1
INT
1
OSC0*
OSC1*
OSC
WDT
TBC
SDA*
SCL*
LSCLK*
OUTCLK*
INT
4
INT
1
VDDL
VDDX
Power
PWM
INT
1
PWM0*
MD0*
1kHzTC
INT
1
INT
1
IN0*
CS0*
RS0*
RT0*
CRT0*
RCM*
IN1*
CS1*
RS1*
RT1*
Melody
Capture
×2
INT
5
RC-ADC
×2
INT
4
NMI
P00 to P03
P10 to P11
8bit Timer
×4
GPIO
P20 to P22
P30 to P35
AVDD
AVSS
P40 to P47
INT
1
PA0 to PA7
VREF
12bit-ADC
BLD
Display Allocation
RAM 1024Byte
COM0 to COM7
SEG0 to SEG49
AIN0, AIN1
LCD
Driver
Display RAM
100Byte
VL1, VL2, VL3, VL4
C1, C2, C3, C4
LCD
BIAS
Figure 1 ML610Q421 Block Diagram
5/37
FEDL610Q421-03
ML610Q421/ML610Q422
ML610Q422 Block Diagram
Figure 2 show the block diagram of the ML610Q422.
"*" indicates the secondary function of each port.
CPU (nX-U8/100)
EPSW1～3
ELR1～3
LR
ECSR1～3
DSR/CSR
PC
GREG
0～15
PSW
EA
Timing
Controller
ALU
SP
Program
Memory
(Flash)
BUS
Controller
VPP
Instruction
Decoder
Instruction
Register
On-Chip
ICE
32Kbyte
Data-bus
VDD
VSS
INT
1
SCK0*
SIN0*
SSIO
UART
I2C
RAM
1024byte
SOUT0*
RESET_N
TEST
RESET &
TEST
INT
1
Interrupt
Controller
RXD0*
TXD0*
XT0
XT1
INT
1
INT
1
OSC0*
OSC1*
OSC
WDT
TBC
SDA*
SCL*
LSCLK*
OUTCLK*
INT
4
INT
1
VDDL
VDDX
Power
PWM
INT
1
PWM0*
MD0*
1kHzTC
INT
1
INT
1
IN0*
CS0*
RS0*
RT0*
CRT0*
RCM*
IN1*
CS1*
RS1*
RT1*
Melody
Capture
×2
INT
5
RC-ADC
×2
INT
4
NMI
P00 to P03
P10 to P11
8bit Timer
×4
GPIO
P20 to P22
P30 to P35
AVDD
AVSS
INT
1
P40 to P47
VREF
12bit-ADC
BLD
Display Allocation
RAM 1024Byte
COM0 to COM15
SEG0 to SEG49
AIN0, AIN1
LCD
Driver
Display RAM
100Byte
VL1, VL2, VL3, VL4
C1, C2, C3, C4
LCD
BIAS
Figure 2 ML610Q422 Block Diagram
6/37
FEDL610Q421-03
ML610Q421/ML610Q422
PIN CONFIGURATION
ML610Q421 TQFP120 Pin Layout
90pin
61pin
60pin
91pin
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SEG49
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
PA0
SEG8
SEG7
PA1
PA2
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
VDD
P11
(NC)
P10
VSS
P03
PA3
PA4
PA5
PA6
PA7
P20
P21
P22
P40
P41
VSS
(NC)
AVSS
(NC)
VREF
AIN0
AIN1
AVDD
P02
P01
P00
C4
C3
120pin
31pin
1pin
30pin
Note:
The assignment of the pads P30 to P35 are not in order.
Figure 3 ML610Q421 TQFP120 Pin Configuration
7/37
FEDL610Q421-03
ML610Q421/ML610Q422
ML610Q422 TQFP120 Pin Layout
90pin
61pin
60pin
91pin
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
91
92
93
94
95
96
97
98
60
59
58
57
56
55
54
53
52
51
50
49
SEG49
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
99
100
101
102
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
VDD
P11
(NC)
P10
VSS
P03
48
47
46
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P20
P21
P22
P40
P41
VSS
(NC)
AVSS
(NC)
VREF
AIN0
P02
P01
P00
C4
AIN1
AVDD
C3
120pin
31pin
1pin
30pin
Note:
The assignment of the pads P30 to P35 are not in order.
Figure 4 ML610Q422 TQFP120 Pin Configuration
8/37
FEDL610Q421-03
ML610Q421/ML610Q422
ML610Q421 Chip Pin Layout & Dimension
SEG49
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
PA0
89
90
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
91
92
93
94
95
96
97
98
PA1
99
PA2
100
101
102
103
104
105
PA3
PA4
PA5
PA6
3.02mm
PA7
P20/LED0
P21/LED1
P22/LED2
P40/SDA
P41/SCL
Vss
106
107
108
109
110
111
112
39
38
VDD
P11
37
36
P10
Vss
AVSS
35
34
33
32
P03
P02
P01
P00
VREF
AIN0
113
114
AIN1
115
116
31
30
C4
C3
AVDD
2.98mm
Note:
The assignment of the pads P30 to P35 are not in order.
Chip size:
PAD count:
2.98 mm × 3.02 mm
116 pins
Minimum PAD pitch:
PAD aperture:
Chip thickness:
80 µm
70 µm × 70 µm
350 µm
Voltage of the rear side of chip: VSS level
Figure 5 ML610Q421 Chip Layout & Dimension
9/37
FEDL610Q421-03
ML610Q421/ML610Q422
ML610Q422 Chip Pin Layout & Dimension
SEG49
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
89
90
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
3.02mm
P20/LED0
P21/LED1
P22/LED2
P40/SDA
P41/SCL
Vss
106
107
108
109
110
111
112
39
38
VDD
P11
37
36
P10
Vss
AVSS
35
34
33
32
P03
P02
P01
P00
VREF
AIN0
113
114
AIN1
115
116
31
30
C4
C3
AVDD
2.98mm
Note:
The assignment of the pads P30 to P35 are not in order.
Chip size:
PAD count:
2.98 mm × 3.02 mm
116 pins
Minimum PAD pitch:
PAD aperture:
Chip thickness:
80 µm
70 µm × 70 µm
350 µm
Voltage of the rear side of chip: VSS level
Figure 6 ML610Q422 Chip Layout & Dimension
10/37
FEDL610Q421-03
ML610Q421/ML610Q422
PAD COORDINATES
ML610Q421 Pad Coordinates
Table 1 ML610Q421 Pad Coordinates
Chip Center: X=0,Y=0
PAD
No.
Pad
Name
X
Y
PAD
No.
Pad
Name
X
Y
PAD
No.
Pad
Name
X
Y
(μm) (μm)
(μm) (μm)
(μm) (μm)
1
VPP
-1240 -1404
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
PA0
1384
1384
1384
1384
1384
1384
1384
1384
1160
1080
1000
920
640
720
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
PA3
PA4
PA5
PA6
PA7
P20
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
240
160
80
2
RESET_N -1160 -1404
3
P42
P43
-1080 -1404
-1000 -1404
800
4
880
0
5
P44
-920
-840
-760
-680
-600
-520
-440
-360
-280
-200
-120
-40
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1240
-1160
-1040
-960
960
-80
6
P45
1040
1120
1200
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1200
1120
1040
960
-200
-280
-360
-440
-520
-600
-680
-840
-920
7
P46
P21
8
P47
P22
9
P30
P40
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P31
P41
P34
Vss
P32
AVss
VREF
AIN0
AIN1
AVDD
P33
840
P35
760
TEST
VDD
VDDL
Vss
680
-1384 -1092
-1384 -1172
600
40
520
120
440
VDDX
XT0
200
360
360
280
XT1
520
200
Vss
600
120
NMI
680
40
VL1
840
-40
VL2
920
-120
-200
-280
-360
-440
-520
-600
-680
-760
-840
-920
-1000
-1080
-1160
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
VL3
1000
1080
1160
1240
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
VL4
C1
C2
C3
C4
P00
P01
P02
-880
P03
-800
Vss
-660
P10
-580
P11
-420
VDD
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
-340
-240
-160
-80
0
880
80
800
160
720
240
640
320
560
400
480
480
PA1
400
560
PA2
320
11/37
FEDL610Q421-03
ML610Q421/ML610Q422
ML610Q422 Pad Coordinates
Table 2 ML610Q422 Pad Coordinates
Chip Center: X=0,Y=0
PAD
No.
Pad
Name
X
Y
PAD
No.
Pad
Name
X
Y
PAD
No.
Pad
Name
X
Y
(μm) (μm)
(μm) (μm)
(μm) (μm)
1
VPP
-1240 -1404
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
COM0
1384
1384
1384
1384
1384
1384
1384
1384
1160
1080
1000
920
640
720
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
COM11
COM12
COM13
COM14
COM15
P20
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
240
160
80
2
RESET_N -1160 -1404
3
P42
P43
-1080 -1404
-1000 -1404
800
4
880
0
5
P44
-920
-840
-760
-680
-600
-520
-440
-360
-280
-200
-120
-40
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1404
-1240
-1160
-1040
-960
960
-80
6
P45
1040
1120
1200
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1404
1200
1120
1040
960
-200
-280
-360
-440
-520
-600
-680
-840
-920
7
P46
P21
8
P47
P22
9
P30
P40
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P31
P41
P34
Vss
P32
AVss
VREF
AIN0
P33
840
P35
760
TEST
VDD
VDDL
Vss
680
AIN1
-1384 -1092
-1384 -1172
600
AVDD
40
520
120
440
VDDX
XT0
200
360
360
280
XT1
520
200
Vss
600
120
NMI
680
40
VL1
840
-40
VL2
920
-120
-200
-280
-360
-440
-520
-600
-680
-760
-840
-920
-1000
-1080
-1160
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
VL3
1000
1080
1160
1240
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
1384
VL4
C1
C2
C3
C4
P00
P01
P02
-880
P03
-800
Vss
-660
P10
-580
P11
-420
VDD
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
-340
-240
-160
COM1
-80
COM2
0
COM3
880
80
COM4
800
160
COM5
720
240
COM6
640
320
COM7
560
400
COM8
480
480
COM9
400
560
COM10
320
12/37
FEDL610Q421-03
ML610Q421/ML610Q422
PIN LIST
PAD No.
Primary function
Secondary function
Pin name I/O Function
Tertiary function
Q422 Q421 Pin name I/O
18,22, 18,22,
Function
Pin name I/O
Function
Negative power
supply pin
Vss
36,111 37,111
Positive power supply
pin
16,39 16,39
VDD
Power supply pin for
internal logic
17
17
VDDL
(internally generated)
Power supply pin for
low-speed oscillation
(internally generated)
Power supply pin for
Flash ROM
19
1
19
1
VDDX
VPP
Negative power
supply pin for
successive
approximation type
ADC
Positive power supply
pin for successive
approximation type
ADC
112
116
112
116
AVSS
AVDD
Power supply pin for
LCD bias (internally
generated)
Power supply pin for
LCD bias (internally
generated)
Power supply pin for
LCD bias (internally
generated)
Power supply pin for
LCD bias (internally
generated)
Capacitor connection
pin for LCD bias
generation
Capacitor connection
pin for LCD bias
generation
Capacitor connection
pin for LCD bias
generation
Capacitor connection
pin for LCD bias
generation
24
25
26
27
28
29
30
31
24
25
26
27
28
29
30
31
VL1
VL2
VL3
VL4
C1
C2
C3
C4
Input/output pin for
testing
15
2
15
2
TEST
RESET_N
XT0
I/O
Reset input pin
I
I
Low-speed clock
oscillation pin
Low-speed clock
oscillation pin
Reference power
supply pin for
successive
20
20
21
21
XT1
O
113
113
VREF
approximation type
ADC
13/37
FEDL610Q421-03
ML610Q421/ML610Q422
PAD No.
Primary function
Function
Successive
Secondary function
Pin name I/O Function
Tertiary function
Q422 Q421 Pin name I/O
Pin name I/O
Function
approximation type
ADC input
114
114
AIN0
I
Successive
approximation type
ADC input
Non-maskable
interrupt pin
115
23
115
23
AIN1
NMI
I
I
P00/
EXI0/
CAP0
P01/
Input port, External
interrupt 0, Capture 0
input
32
33
32
33
I
I
Input port, External
interrupt 1, Capture 1
input
EXI1/
CAP1
P02/
Input port, External
interrupt 2, UART0
receive
34
35
34
35
EXI2/
RXD0
P03/
I
I
Input port, External
interrupt 3
EXI3
P10
Input port
Input port
High-speed oscillation
High-speed oscillation
37
38
37
38
I
I
OSC0
OSC1
I
P11
O
P20/
Output port
Low-speed clock output
106
106
O
LSCLK
O
LED0
High-speed clock
output
Output port
107
108
9
107 P21/LED1
108 P22/LED2
O
O
OUTCLK
MD0
O
O
I
Output port
Melody output
RC type ADC0
oscillation input pin
Input/output port
9
P30
I/O
IN0
RC type ADC0
reference capacitor
connection pin
Input/output port
10
10
P31
I/O
CS0
O
RC type ADC0
Input/output port
Input/output port
resistor/capacitor
sensor connection pin
RC type ADC0
reference resistor
connection pin
PWM output
11
12
11
12
P34
P32
I/O
I/O
RCT0
RS0
O
O
PWM0
O
RC type ADC0 resistor
sensor connection pin
RC type ADC
Input/output port
Input/output port
13
14
13
14
P33
P35
I/O
I/O
RT0
O
O
RCM
oscillation monitor
Input/output port
Input/output port
Input/output port
Input/output port
I2C data input/output
I2C clock input/output
UART data input
SSIO data input
109
110
3
109
110
3
P40
P41
P42
P43
I/O
I/O
I/O
I/O
SDA
SCL
I/O
I/O
I
SIN0
SCK0
I
I/O
I
SSIO synchronous clock
SSIO data output
PWM output
RXD0
TXD0
SOUT0
PWM0
UART data output
4
4
O
O
Input/output port,
Timer 0/Timer 2/
PWM0 external clock
input
Input/output port,
Timer 1/Timer 3
external clock input
P44/
RC type ADC1
oscillation input pin
SSIO0 data input
5
6
5
6
I/O
I/O
IN1
I
SIN0
I
T02P0CK
RC type ADC1
reference capacitor
connection pin
P45/
SSIO0 synchronous
clock
CS1
O
SCK0
I/O
T13P1CK
RC type ADC1
Input/output port
reference resistor
connection pin
RC type ADC1 resistor
sensor connection pin
SSIO0 data output
7
8
7
8
P46
I/O
I/O
RS1
RT1
O
O
SOUT0
O
Input/output port
P47
Input/output port
Input/output port
Input/output port
Input/output port
Input/output port
98
99
PA0
PA1
PA2
PA3
PA4
I/O
I/O
I/O
I/O
I/O
100
101
102
14/37
FEDL610Q421-03
ML610Q421/ML610Q422
PAD No.
Primary function
Secondary function
Pin name I/O Function
Tertiary function
Pin name I/O
Q422 Q421 Pin name I/O
Function
Function
Input/output port
Input/output port
Input/output port
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
103
104
105
90
91
92
93
94
95
96
97
PA5
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
PA6
PA7
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
SEG0
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
15/37
FEDL610Q421-03
ML610Q421/ML610Q422
PAD No.
Primary function
Secondary function
Pin name I/O Function
Tertiary function
Q422 Q421 Pin name I/O
Function
Pin name I/O
Function
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
76
77
78
79
80
81
82
83
84
85
86
87
88
89
76
77
78
79
80
81
82
83
84
85
86
87
88
89
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
O
O
O
O
O
O
O
O
O
O
O
O
O
O
16/37
FEDL610Q421-03
ML610Q421/ML610Q422
PIN DESCRIPTION
Primary/
Secondary/
Tertiary
Pin name
I/O
I
Description
Logic
System
Reset input pin. When this pin is set to a “L” level, system reset mode is
set and the internal section is initialized. When this pin is set to a “H” level
subsequently, program execution starts. A pull-up resistor is internally
connected.
RESET_N
—
Negative
Crystal connection pin for low-speed clock.
XT0
XT1
I
O
I
—
—
—
—
—
A 32.768 kHz crystal oscillator (see measuring circuit 1) is connected to
this pin. Capacitors CDL and CGL are connected across this pin and VSS
as required.
Crystal/ceramic connection pin for high-speed clock.
A crystal or ceramic is connected to this pin (4.1 MHz max.). Capacitors
CDH and CGH (see measuring circuit 1) are connected across this pin
OSC0
Secondary
and VSS
.
OSC1
O
Secondary
—
This pin is used as the secondary function of the P10 pin(OSC0) and P11
pin(OSC1).
Low-speed clock output pin. This pin is used as the secondary function of
the P20 pin.
High-speed clock output pin. This pin is used as the secondary function of
the P21 pin.
LSCLK
O
O
Secondary
Secondary
—
—
OUTCLK
General-purpose input port
General-purpose input port.
P00-P03
I
Primary
Primary
Positive
Positive
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
General-purpose input port.
P10-P11
I
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
General-purpose output port
General-purpose output port.
P20-P22
O
Primary
Positive
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
General-purpose input/output port
General-purpose input/output port.
P30-P35
P40-P47
PA0-PA7
I/O
I/O
I/O
Primary
Primary
Primary
Positive
Positive
Positive
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
General-purpose input/output port.
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
General-purpose input/output port.
These pins are for the ML610Q421, but are not provided in the
ML610Q422.
17/37
FEDL610Q421-03
ML610Q421/ML610Q422
Primary/
Secondary/
Tertiary
Pin name
UART
I/O
Description
Logic
UART data output pin. This pin is used as the secondary function of the
P43 pin.
UART data input pin. This pin is used as the secondary function of the
P42 or the primary function of the P02 pin.
TXD0
O
I
Secondary Positive
RXD0
Primary/
Positive
Secondary
I2C bus interface
I2C data input/output pin. This pin is used as the secondary function of the
P40 pin. This pin has an NMOS open drain output. When using this pin as
a function of the I2C, externally connect a pull-up resistor.
SDA
I/O
Secondary Positive
Secondary Positive
I2C clock output pin. This pin is used as the secondary function of the P41
pin. This pin has an NMOS open drain output. When using this pin as a
function of the I2C, externally connect a pull-up resistor.
SCL
O
Synchronous serial (SSIO)
Synchronous serial clock input/output pin. This pin is used as the tertiary
function of the P41 or P45 pin.
Synchronous serial data input pin. This pin is used as the tertiary function
of the P40 or P44 pin.
Synchronous serial data output pin. This pin is used as the tertiary
function of the P42 or P46 pin.
SCK0
I/O
Tertiary
Tertiary
Tertiary
—
SIN0
I
Positive
Positive
SOUT0
O
PWM
PWM0 output pin. This pin is used as the tertiary function of the P43 or
P34 pin.
PWM0 external clock input pin. This pin is used as the primary function of
the P44 pin.
PWM0
O
O
Tertiary
Primary
Positive
—
T02P0CK
External interrupt
External non-maskable interrupt input pin. An interrupt is generated on
both edges.
External maskable interrupt input pins. Interrupt enable and edge
selection can be performed for each bit by software. These pins are used
as the primary functions of the P00-P03 pins.
Positive/
negative
Positive/
negative
NMI
I
Primary
Primary
EXI0-3
I
Capture
Capture trigger input pins. The value of the time base counter is captured
in the register synchronously with the interrupt edge selected by software.
These pins are used as the primary functions of the P00 pin(CAP0) and
P01 pin(CAP1).
Positive/
negative
Positive/
negative
CAP0
I
I
Primary
Primary
CAP1
Timer
External clock input pin used for both Timer 0 and Timer 2. The clocks for
these timers are selected by software. This pin is used as the primary
function of the P44 pin.
External clock input pin used for both Timer 1 and Timer 3. The clocks for
these timers are selected by software. This pin is used as the primary
function of the P45 pin.
T02P0CK
I
I
Primary
Primary
—
—
T13P1CK
Melody
MD0
Melody/buzzer signal output pin. This pin is used as the secondary
function of the P22 pin.
Positive/
negative
O
O
Secondary
Primary
LED drive
LED0-2
Nch open drain output pins to drive LED.
Positive/
negative
18/37
FEDL610Q421-03
ML610Q421/ML610Q422
Primary/
Secondary/
Tertiary
Pin name
I/O
Description
Logic
RC oscillation type A/D converter
Channel 0 oscillation input pin. This pin is used as the secondary function
of the P30 pin.
Channel 0 reference capacitor connection pin. This pin is used as the
secondary function of the P31 pin.
This pin is used as the secondary function of the P32 pin which is the
reference resistor connection pin of Channel 0.
Resistor sensor connection pin of Channel 0 for measurement. This pin is
used as the secondary function of the P34 pin.
Resistor/capacitor sensor connection pin of Channel 0 for measurement.
This pin is used as the secondary function of the P33 pin.
RC oscillation monitor pin. This pin is used as the secondary function of
the P35 pin.
Oscillation input pin of Channel 1. This pin is used as the secondary
function of the P44 pin.
Reference capacitor connection pin of Channel 1. This pin is used as the
secondary function of the P45 pin.
Reference resistor connection pin of Channel 1. This pin is used as the
secondary function of the P46 pin.
IN0
CS0
RS0
RT0
CRT0
RCM
IN1
I
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
I
CS1
RS1
RT1
O
O
O
Resistor sensor connection pin for measurement of Channel 1. This pin is
used as the secondary function of the P47 pin.
Successive approximation type A/D converter
Negative power supply pin for successive approximation type A/D
converter.
Positive power supply pin for successive approximation type A/D
converter.
Reference power supply pin for successive approximation type A/D
converter.
AVSS
AVDD
VREF
—
—
—
—
—
—
—
—
—
Channel 0 analog input for successive approximation type A/D converter.
AIN0
AIN1
I
I
—
—
—
—
Channel 1 analog input for successive approximation type A/D converter.
Common output pins.
LCD drive signal
COM0-7
O
—
—
—
—
Common output pins.
COM8-15
O
These pins are for the ML610Q422, but are not provided in the
ML610Q421.
Segment output pin.
SEG0-49
O
—
—
LCD driver power supply
Power supply pins for LCD bias (internally generated). Capacitors Ca, Cb,
Cc, and Cd (see measuring circuit 1) are connected between VSS and VL1,
VL2, VL3, and VL4, respectively.
VL1
VL2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VL3
VL4
Power supply pins for LCD bias (internally generated). Capacitors C12
and C34 (see measuring circuit 1) are connected between C1 and C2 and
between C3 and C4, respectively.
C1
C2
C3
C4
For testing
TEST
Power supply
VSS
Input/output pin for testing. A pull-down resistor is internally connected.
I/O
—
—
Negative power supply pin.
Positive power supply pin.
—
—
—
—
—
—
—
—
—
VDD
Positive power supply pin (internally generated) for internal logic.
VDDL
Capacitors CL0 and CL1 (see measuring circuit 1) are connected between
this pin and VSS
.
Plus-side power supply pin (internally generated) for low-speed oscillation.
Capacitor Cx (see measuring circuit 1) is connected between this pin and
VDDX
—
—
—
—
—
—
VSS
.
Power supply pin for programming Flash ROM. A pull-up resistor is
internally connected.
VPP
19/37
FEDL610Q421-03
ML610Q421/ML610Q422
TERMINATION OF UNUSED PINS
Table 3 shows methods of terminating the unused pins.
Table 3 Termination of Unused Pins
Pin
Recommended pin termination
VPP
Open
VSS
AVDD
AVSS
VSS
VREF
VSS
AIN0, AIN1
VL1, VL2, VL3, VL4
C1, C2, C3, C4
RESET_N
TEST
Open
Open
Open
Open
Open
Open
VDD or VSS
VDD
NMI
P00 to P03
P10 to P11
P20 to P22
P30 to P35
P40 to P47
PA0 to PA7
COM0 to 15
SEG0 to 49
Open
Open
Open
Open
Open
Open
Note:
It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or
the output mode since the supply current may become excessively large if the pins are left open in the high impedance input
setting.
20/37
FEDL610Q421-03
ML610Q421/ML610Q422
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
(VSS = AVSS = 0V)
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage 1
Power supply voltage 2
Power supply voltage 3
Power supply voltage 4
Power supply voltage 5
Power supply voltage 6
Power supply voltage 7
Power supply voltage 8
Power supply voltage 9
Input voltage
VDD
AVDD
VPP
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Port3–A, Ta = 25°C
Port2, Ta = 25°C
Ta = 25°C
−0.3 to +4.6
−0.3 to +4.6
−0.3 to +9.5
−0.3 to +3.6
−0.3 to +3.6
−0.3 to +1.75
−0.3 to +3.5
−0.3 to +5.25
−0.3 to +7.0
−0.3 to VDD+0.3
−0.3 to VDD+0.3
−12 to +11
V
V
V
VDDL
VDDX
VL1
V
V
V
VL2
V
VL3
V
VL4
V
VIN
V
Output voltage
VOUT
IOUT1
IOUT2
PD
V
Output current 1
mA
mA
W
°C
Output current 2
−12 to +20
Power dissipation
1.25
Storage temperature
TSTG
−55 to +150
RECOMMENDED OPERATING CONDITIONS
(VSS = AVSS = 0V)
Unit
Parameter
Symbol
TOP
Condition
Range
ML610Q421, ML610Q422
−20 to +70
−40 to +85
1.1 to 3.6
2.2 to 3.6
30k to 36k
30k to 650k
30k to 4.2M
1.0±30%
Operating temperature
°C
ML610Q421P, ML610Q422P
VDD
Operating voltage
V
AVDD
VDD = 1.1 to 3.6V
VDD = 1.3 to 3.6V
VDD = 1.8 to 3.6V
Operating frequency (CPU)
fOP
Hz
CL0
CL1
Capacitor externally connected to
µF
VDDL pin
0.1±30%
Capacitor externally connected to
VDDX pin
Capacitors externally connected to
VL1, 2, 3, 4 pins
CX
0.1±30%
1.0±30%
µF
µF
Ca, b, c, d
Capacitors externally connected
across C1 and C2 pins and across
C3 and C4 pins
C12, C34
1.0±30%
µF
21/37
FEDL610Q421-03
ML610Q421/ML610Q422
CLOCK GENERATION CIRCUIT OPERATING CONDITIONS
(VSS = 0V)
Rating
Typ.
Parameter
Symbol
fXTL
Condition
Unit
Min.
Max.
Low-speed crystal oscillation
frequency
32.768k
Hz
Recommended equivalent series
resistance value of low-speed
crystal oscillation
RL
40k
Ω
CL=6pF of
crystal
0
6
oscillation *2
CL=9pF of
crystal
Low-speed crystal oscillation
external capacitor *1
CDL/CGL
pF
oscillation
CL=12pF of
crystal
12
oscillation
High-speed crystal/ceramic
oscillation frequency
High-speed crystal oscillation
external capacitor
fXTH
4.0M / 4.096M
Hz
pF
CDH
CGH
24
24
*1: The external CDL and CGL need to be adjusted in consideration of variation of internal loading capacitance CD and CG, and
other additional capacitance such as PCB layout.
*2: When using a crystal oscillator CL = 6pF, there is a possibility that can not be adjusted by external CDL and CGL
.
OPERATING CONDITIONS OF FLASH ROM
(VSS = AVSS = 0V)
Parameter
Symbol
TOP
VDD
Condition
At write/erase
At write/erase*1
At write/erase*1
At write/erase*1
Range
0 to +40
2.75 to 3.6
2.5 to 2.75
7.7 to 8.3
80
Unit
Operating temperature
°C
Operating voltage
VDDL
VPP
CEP
V
Write cycles
cycles
years
Data retention
YDR
10
*1: Those voltages must be supplied to VDDL pin and VPP pin when programming and eraseing Flash ROM.
VPP pin has an internal pulldown resister.
22/37
FEDL610Q421-03
ML610Q421/ML610Q422
DC CHARACTERISTICS (1/5)
(VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise
specified) (1/5)
Rating
Typ.
Measuring
circuit
Parameter
Symbol
Condition
Ta = 25°C
Unit
kHz
kHz
kHz
Min.
Typ.
−10%
Typ.
−25%
Typ.
−45%
Max.
Typ.
+10%
Typ.
+25%
Typ.
+45%
500
500
500
500kHz RC oscillation
frequency
V
DD = 1.3
Ta = −20 to
+70°C
fRC
to 3.6V
Ta = −40 to
+85°C
LSCLK = 32.768kHz
VDD = 1.8 to 3.6V
PLL oscillation frequency*4
fPLL
TXTL
TRC
-2.5%
8.192
0.3
+2.5%
2
MHz
s
Low-speed crystal oscillation
start time*2
500kHz RC oscillation start
time
1
50
500
µs
High-speed crystal oscillation
TXTH
TPLL
VDD = 1.8 to 3.6V
―
―
2
1
20
10
20
start time*3
PLL oscillation start time
Low-speed oscillation stop
detect time*1
Reset pulse width
Reset noise elimination
pulse width
VDD = 1.8 to 3.6V
ms
TSTOP
PRST
PNRST
0.2
200
3
µs
0.3
Power-on reset activation
power rise time
TPOR
10
ms
*1 : When low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is
reset to shift to system reset mode.
*2 : Use 32.768KHz Crystal Oscillator C-001R (Epson Toyocom) with capacitance CGL/CDL＝0pF.
*3 : Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera).
*4 : 1024 clock average.
[Reset pulse width]
VIL1
VIL1
RESET_N
PRST
Reset pulse width (PRST
)
[Power-on reset activation power rise time]
0.9xVDD
VDD
0.1xVDD
TPOR
Power-on reset activation power rise time (TPOR
)
23/37
FEDL610Q421-03
ML610Q421/ML610Q422
DC CHARACTERISTICS (2/5)
(VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise
specified) (2/5)
Rating
Typ.
0.94
0.96
0.98
1.00
1.02
1.04
1.06
1.08
1.10
1.12
1.14
1.16
1.18
1.20
1.22
1.24
1.26
1.28
1.30
1.32
1.34
1.36
1.38
1.40
1.42
1.44
1.46
1.48
1.50
1.52
1.54
1.56
Measuring
circuit
Parameter
Symbol
Condition
CN4–0 = 00H
Unit
Min.
0.89
0.91
0.93
0.95
0.97
0.99
1.01
1.03
1.05
1.07
1.09
1.11
1.13
1.15
1.17
1.19
1.21
1.23
1.25
1.27
1.29
1.31
1.33
1.35
1.37
1.39
1.41
1.43
1.45
1.47
1.49
1.51
Max.
0.99
1.01
1.03
1.05
1.07
1.09
1.11
1.13
1.15
1.17
1.19
1.21
1.23
1.25
1.27
1.29
1.31
1.33
1.35
1.37
1.39
1.41
1.43
1.45
1.47
1.49
1.51
1.53
1.55
1.57
1.59
1.61
CN4–0 = 01H
CN4–0 = 02H
CN4–0 = 03H
CN4–0 = 04H
CN4–0 = 05H
CN4–0 = 06H
CN4–0 = 07H
CN4–0 = 08H
CN4–0 = 09H
CN4–0 = 0AH
CN4–0 = 0BH
CN4–0 = 0CH
CN4–0 = 0DH
CN4–0 = 0EH
CN4–0 = 0FH
CN4–0 = 10H
CN4–0 = 11H
CN4–0 = 12H
CN4–0 = 13H
CN4–0 = 14H *1
CN4–0 = 15H *1
CN4–0 = 16H *1
CN4–0 = 17H *1
CN4–0 = 18H *1
CN4–0 = 19H *1
CN4–0 = 1AH *1
CN4–0 = 1BH *1
CN4–0 = 1CH *1
CN4–0 = 1DH *1
CN4–0 = 1EH *1
CN4–0 = 1FH *1
V
DD = 3.0V,
VL1 voltage
VL1
V
Tj = 25°C
1
VL1 temperature
deviation
VL1 voltage
dependency
∆VL1
∆VL1
VL2
VDD = 3.0V
−1.5
5
mV/°C
VDD = 1.3 to 3.6V
20
mV/V
V
DD = 3.0V, Tj = 25°C,
500kΩ load (VL4−VSS
VDD = 3.0V,
Tj = 25°C
500kΩ load
Typ.
−10%
Typ.
−10%
Typ.
Typ.
+4%
Typ.
+4%
Typ.
+5%
VL2 voltage*２
VL3 voltage*２
VL4 voltage*２
VL1×2
)
1/3 bias
1/4 bias
1/3 bias
1/4 bias
VL1×2
VL1×3
VL1×3
VL1×4
VL3
VL4
V
(VL4−VSS
)
−10%
LCD bias voltage
generation time
TBIAS
600
ms
*1: When using 1/4 bias, the VL1 voltage is set to typ. 1.32 V (same voltage as in CN4–0 = 13H).
*2: Boost clock is 2kHz(initial) for the bias generation. C12=C34=1uF.
24/37
FEDL610Q421-03
ML610Q421/ML610Q422
DC CHARACTERISTICS (3/5)
(VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise
specified) (3/5)
Rating
Measuring
circuit
Parameter
Symbol
Condition
Unit
Min. Typ. Max.
LD2–0 = 0H
LD2–0 = 1H
LD2–0 = 2H
LD2–0 = 3H
LD2–0 = 4H
LD2–0 = 5H
LD2–0 = 6H
LD2–0 = 7H
LD2–0 = 8H
LD2–0 = 9H
LD2–0 = 0AH
LD2–0 = 0BH
LD2–0 = 0CH
LD2–0 = 0DH
LD2–0 = 0EH
LD2–0 = 0FH
1.35
1.4
1.45
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.7
2.9
BLD threshold
voltage
Typ.
−2%
Typ.
+2%
VBLD
VDD = 1.35 to 3.6V
V
BLD threshold
voltage
temperature
deviation
∆VBLD
IDD1
IDD2
IDD3
IDD4
VDD = 1.35 to 3.6V
0
%/°C
µA
Ta = 25°C
0.15 0.50
CPU: In STOP state.
Low-speed/high-speed
oscillation: stopped.
Supply current 1
Supply current 2
Supply current 3
Supply current 4
Ta = -20 to +70°C
Ta = -40 to +85°C
Ta = 25°C
0.5
5
2.50
5.00
1.3
3.5
6.0
7
1
CPU: In HALT state (LTBC,
WDT: Operating*3*5).
High-speed oscillation: Stopped.
LCD/BIAS circuits: Stopped.
CPU: In 32.768kHz operating
state.*1*3
Ta = -20 to +70°C
Ta = -40 to +85°C
Ta = 25°C
µA
Ta = -20 to +70°C
Ta = -40 to +85°C
Ta = 25°C
70
12
µA
High-speed oscillation: Stopped.
LCD/BIAS circuits: Operating.*2
16
85
CPU: In 500kHz CR operating
state.
Ta = -20 to +70°C
Ta = -40 to +85°C
100
120
µA
LCD/BIAS circuits: Operating.*2
Ta = 25°C
CPU: In 4.096MHz operating
state.*2*3
0.8
1.0
1.2
1.2
1.6
2.5
2.5
Supply current 5
Supply current 6
PLL: In oscillating state.
Ta = -20 to +70°C
Ta = -40 to +85°C
Ta = 25°C
IDD5
IDD6
mA
mA
LCD/BIAS circuits: Operating. *2
VDD = 1.8 to 3.6V
CPU: In 4.096MHz operating
state.*2
1.5
PLL: In oscillating state. *3*4
A/D: In operating state.
LCD/BIAS circuits: Operating. *2
VDD = AVDD = 3.0V
Ta = -20 to +70°C
Ta = -40 to +85°C
*1 : When the CPU operating rate is 100% (No HALT state).
*2 : All SEGs: off waveform, No LCD panel load, 1/3 bias, 1/3 duty, Frame frequency: Approx. 64 Hz, Bias voltage multiplying
clock: 1/128 LSCLK (256Hz)
*3 : Use 32.768KHz Crystal Oscillator C-001R (Epson Toyocom) with capacitance CGL/CDL＝0pF.
*4 : Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera).
*5 : Significant bits of BLKCON0~BLKCON4 registers are all “1”.
25/37
FEDL610Q421-03
ML610Q421/ML610Q422
DC CHARACTERISTICS (4/5)
(VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise
specified) (4/5)
Rating
Typ.
Measuring
circuit
Parameter
Symbol
VOH1
Condition
Unit
V
Min.
Max.
VDD
−0.5
VDD
−0.3
VDD
−0.3
IOH1 = −0.5mA, VDD = 1.8 to 3.6V
IOH1 = -0.1mA, VDD = 1.3 to 3.6V
IOH1 = -0.03mA, VDD = 1.1 to 3.6V
Output voltage 1
(P20–P22/2nd
function is
selected)
(P30–P36)
(P40–P47)
IOL1 = +0.5mA, VDD = 1.8 to 3.6V
IOL1 = +0.1mA, VDD = 1.3 to 3.6V
IOL1 = +0.03mA, VDD = 1.1 to 3.6V
0.5
0.5
0.3
(PA0–PA7)*1
VOL1
VOH2
VDD
−0.5
VDD
−0.3
VDD
−0.3
IOH1 = −0.5mA, VDD = 1.8 to 3.6V
IOH1 = -0.1mA, VDD = 1.3 to 3.6V
IOH1 = -0.03mA, VDD = 1.1 to 3.6V
Output voltage 2
(P20–P22/2nd
function is Not
selected)
VOL2
VOL3
IOL2 = +5mA, VDD = 1.8 to 3.6V
IOL3 = +3mA, VDD = 2.0 to 3.6V
(when I2C mode is selected)
0.5
0.4
2
Output voltage 3
(P40–P41)
VL4
−0.2
VOH4
VOMH4
VOMH4S
VOM4
IOH4 = −0.2mA, VL1=1.2V
IOMH4 = +0.2mA, VL1=1.2V
IOMH4S = −0.2mA, VL1=1.2V
IOM4 = +0.2mA, VL1=1.2V
IOM4S = −0.2mA, VL1=1.2V
IOML4 = +0.2mA, VL1=1.2V
VL3
+0.2
VL3
−0.2
VL2
+0.2
Output voltage 4
(COM0–15)
(SEG0–49)
VL2
−0.2
VOM4S
VOML4
VL1
+0.2
VL1
−0.2
VOML4S
VOL4
IOML4S = −0.2mA, VL1=1.2V
IOL4 = +0.2mA, VL1=1.2V
0.2
1
Output leakage
(P20–P22)
IOOH
VOH = VDD (in high-impedance state)
(P30–P35)
µA
3
(P40–P47)
IOOL
VOL = VSS (in high-impedance state)
−1
(PA0–PA7)*1
*1: ML610Q421 only
26/37
FEDL610Q421-03
ML610Q421/ML610Q422
(VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise
specified) (4/5)
Rating
Typ.
Measuring
circuit
Parameter
Symbol
IIH1
Condition
Unit
Min.
0
Max.
1
VIH1 = VDD
VDD = 1.8 to 3.6V
−600
−600
−600
20
−300
−300
−300
300
300
300
−20
-10
-2
Input current 1
(RESET_N)
IIL1
VIL1 = VSS
VIH1 = VDD
VDD = 1.3 to 3.6V
VDD = 1.1 to 3.6V
VDD = 1.8 to 3.6V
VDD = 1.3 to 3.6V
VDD = 1.1 to 3.6V
600
600
600
200
200
200
−2
IIH1
IIL1
IIH2
10
Input current 1
(TEST)
2
VIL1 = Vss
-1
µA
4
VDD = 1.8 to 3.6V
VDD = 1.3 to 3.6V
VDD = 1.1 to 3.6V
VDD = 1.8 to 3.6V
VDD = 1.3 to 3.6V
VDD = 1.1 to 3.6V
2
30
VIH2 = VDD
(when pulled-down)
Input current 2
(NMI)
0.2
0.01
−200
−200
−200
30
30
(P00–P03)
(P10–P11)
(P30–P35)
(P40–P47)
(PA0–PA7)*1
−30
−30
−30
VIL2 = VSS
(when pulled-up)
IIL2
-0.2
-0.01
1
IIH2Z
IIL2Z
VIH2 = VDD (in high-impedance state)
VIL2 = VSS (in high-impedance state)
−1
*1: ML610Q421 only
DC CHARACTERISTICS (5/5))
(VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise
specified) (5/5)
Rating
Typ.
Measuring
circuit
Parameter
Symbol
VIH1
Condition
Unit
Min.
Max.
VDD
Input voltage 1
(RESET_N)
(TEST)
0.7
×VDD
VDD = 1.3 to 3.6V
VDD = 1.1 to 3.6V
0.7
×VDD
(NMI)
VDD
(P00–P03)
(P10–P11)
(P31–P35)
(P40–P43)
(P45–P47)
(PA0–PA7)*1
0.3
×VDD
V
DD = 1.3 to 3.6V
0
0
VIL1
V
5
0.2
×VDD
VDD = 1.1 to 3.6V
0.7
×VDD
VIH2
VIL2
VDD
Input voltage 2
(P30, P44)
0.3
×VDD
0
Input pin
capacitance
(NMI)
f = 10kHz
Vrms = 50mV
Ta = 25°C
(P00–P03)
(P10–P11)
(P30–P35)
(P40–P47)
(PA0–PA7)*1
*1: ML610Q421 only
CIN
5
pF
27/37
FEDL610Q421-03
ML610Q421/ML610Q422
MEASURING CIRCUITS
MEASURING CIRCUIT 1
XT0
C4
C34
C12
32.768kHz crystal
CGH
C3
C2
XT1
P10/OSC0
C1
CDH
P11/OSC1
CV:
1µF
CL0:
CL1:
CX:
1µF
0.1µF
0.1µF
4.096MHz
crystal
V
DD AVDDVREFVDDL
VDDX
VL2 VL3 VL4 VSS AVSS
VL1
Ca,Cb,Cc,Cd:
C12,C34:
1µF
1µF
A
CGH
CDH
32.768kHz crystal:
:
:
24pF
24pF
CV
CL1 CL0 CX
Ca
Cb Cc Cd
C-001R (Epson Toyocom)
4.096MHz crystal:
HC49SFWB (Kyocera)
MEASURING CIRCUIT 2
(*2)
VIH
V
(*1)
VIL
VDD VDDL VDDX VL1 VL2
VL4 AVDDVREF VSSAVSS
VL3
(*1) Input logic circuit to determine the specified measuring conditions.
(*2) Measured at the specified output pins.
28/37
FEDL610Q421-03
ML610Q421/ML610Q422
MEASURING CIRCUIT 3
(*2)
VIH
A
RS1
VIL
VDD VDDL VDDX VL1
VL4 AVDDVREF V
SSAVSS
VL2 VL3
*1: Input logic circuit to determine the specified measuring conditions.
*2: Measured at the specified output pins.
MEASURING CIRCUIT 4
(*3)
A
VDD VDDL VDDX VL1 VL2
VL4 AVDDVREF VSSAVSS
VL3
*3: Measured at the specified output pins.
MEASURING CIRCUIT 5
VIH
(*1)
VIL
VDD VDDL VDDX VL1 VL2 VL3 VL4 AVDDVREF VSSAVSS
*1: Input logic circuit to determine the specified measuring conditions.
29/37
FEDL610Q421-03
ML610Q421/ML610Q422
AC CHARACTERISTICS (External Interrupt)
(VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise
specified)
Rating
Parameter
Symbol
TNUL
Condition
Unit
Min.
76.8
Typ.
Max.
Interrupt: Enabled (MIE = 1),
CPU: NOP operation
External interrupt disable period
106.8
µs
System clock: 32.768kHz
P00–P03
(Rising-edge interrupt)
tNUL
P00–P03
(Falling-edge interrupt)
tNUL
NMI, P00–P03
(Both-edge interrupt)
tNUL
AC CHARACTERISTICS (UART)
(VDD = 1.3 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise
specified)
Rating
Parameter
Transmit baud rate
Receive baud rate
Symbol
Condition
Unit
Min.
Typ.
Max.
tTBRT
tRBRT
BRT*1
s
s
BRT*1
−3%
BRT*1
+3%
BRT*1
*1: Baud rate period (including the error of the clock frequency selected) set with the UART0 baud rate register (UA0BRTL,H)
and the UART0 mode register 0 (UA0MOD0).
tTBRT
TXD0*
tRBRT
RXD0*
*: Indicates the secondary function of the port.
30/37
FEDL610Q421-03
ML610Q421/ML610Q422
AC CHARACTERISTICS (Synchronous Serial Port)
(VDD = 1.3 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise
specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
10
Typ.
Max.
When RC oscillation is active*2
(VDD = 1.3 to 3.6V)
When high-speed oscillation is
active*3 (VDD = 1.8 to 3.6V)
µs
µs
s
SCLK input cycle
(slave mode)
tSCYC
tSCYC
tSW
1
4
SCLK*1
SCLK output cycle
(master mode)
When RC oscillation is active*2
(VDD = 1.3 to 3.6V)
When high-speed oscillation is
active*3 (VDD = 1.8 to 3.6V)
µs
µs
s
SCLK input pulse width
(slave mode)
0.4
SCLK output pulse width
(master mode)
SCLK*1
×0.4
SCLK*1
×0.5
SCLK*1
×0.6
tSW
When RC oscillation is active*2
(VDD = 1.3 to 3.6V)
When high-speed oscillation is
active*3 (VDD = 1.8 to 3.6V)
When RC oscillation is active*2
(VDD = 1.3 to 3.6V)
500
240
500
240
SOUT output delay time
(slave mode)
tSD
ns
SOUT output delay time
(master mode)
tSD
tSS
tSS
ns
ns
ns
When high-speed oscillation is
active*3 (VDD = 1.8 to 3.6V)
SIN input
setup time
(slave mode)
80
When RC oscillation is active*2
(VDD = 1.3 to 3.6V)
When high-speed oscillation is
active*3 (VDD = 1.8 to 3.6V)
When RC oscillation is active*2
(VDD = 1.3 to 3.6V)
500
240
300
80
SIN input
setup time
(master mode)
SIN input
hold time
tSH
ns
When high-speed oscillation is
active*3 (VDD = 1.8 to 3.6V)
*1: Clock period selected with S0CK3–0 of the serial port 0 mode register (SIO0MOD1)
*2: When RC oscillation is selected with OSCM1–0 of the frequency control register (FCON0)
*3: When Crystal/ceramic oscillation, built-in PLL oscillation, or external clock input is selected with OSCM1–0 of the frequency
control register (FCON0)
tSCYC
tSW
tSW
SCLK0*
SOUT0*
SIN0*
tSD
tSD
tSS
tSH
*: Indicates the secondary function of the port.
31/37
FEDL610Q421-03
ML610Q421/ML610Q422
AC CHARACTERISTICS (I2C Bus Interface: Standard Mode 100kHz)
(VDD = 1.8 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless
otherwise specified)
Rating
Parameter
SCL clock frequency
SCL hold time
(start/restart condition)
SCL ”L” level time
Symbol
Condition
Unit
Min.
0
Typ.
Max.
100
fSCL
kHz
tHD:STA
4.0
µs
tLOW
tHIGH
4.7
4.0
µs
µs
SCL ”H” level time
SCL setup time
(restart condition)
SDA hold time
tSU:STA
4.7
µs
tHD:DAT
tSU:DAT
0
µs
µs
SDA setup time
SDA setup time
(stop condition)
Bus-free time
0.25
tSU:STO
tBUF
4.0
4.7
µs
µs
AC CHARACTERISTICS (I2C Bus Interface: Fast Mode 400kHz)
(VDD = 1.8 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless
otherwise specified)
Rating
Parameter
SCL clock frequency
SCL hold time
(start/restart condition)
Symbol
Condition
Unit
Min.
0
Typ.
Max.
400
fSCL
kHz
tHD:STA
0.6
µs
SCL ”L” level time
tLOW
tHIGH
1.3
0.6
µs
µs
SCL ”H” level time
SCL setup time
(restart condition)
SDA hold time
tSU:STA
0.6
µs
tHD:DAT
tSU:DAT
0
µs
µs
SDA setup time
SDA setup time
(stop condition)
Bus-free time
0.1
tSU:STO
tBUF
0.6
1.3
µs
µs
Start
condition
Restart
condition
Stop
condition
P40/SDA
P41/SCL
tBUF
tSU:STO
tHD:STA
tLOW tHIGH
tSU:STA tHD:STA
tSU:DAT tHD:DAT
32/37
FEDL610Q421-03
ML610Q421/ML610Q422
AC CHARACTERISTICS (RC Oscillation A/D Converter)
(VDD = 1.3 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless
otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
1
Typ.
Max.
RS0, RS1,
RT0,
RT0-1,RT1
fOSC1
fOSC2
fOSC3
Kf1
Resistors for oscillation
CS0, CT0, CS1 ≥ 740pF
kΩ
Resistor for oscillation = 1kΩ
Resistor for oscillation = 10kΩ
Resistor for oscillation = 100kΩ
RT0, RT0-1, RT1 = 1kHz
209.4
41.29
4.71
330.6
55.27
5.97
5.982
1
435.1
64.16
7.06
kHz
kHz
kHz
kHz
kHz
kHz
Oscillation frequency
VDD = 1.5V
5.567
0.99
6.225
1.01
RS to RT oscillation frequency
ratio *1
Kf2
RT0, RT0-1, RT1 = 10kHz
RT0, RT0-1, RT1 = 100kHz
Resistor for oscillation = 1kΩ
Resistor for oscillation = 10kΩ
Resistor for oscillation = 100kΩ
RT0, RT0-1, RT1 = 1kHz
VDD = 1.5V
Kf3
0.104
407.3
49.76
5.04
0.108
486.7
59.28
5.993
8.210
1
0.118
594.6
72.76
7.04
fOSC1
fOSC2
fOSC3
Kf1
Oscillation frequency
VDD = 3.0V
8.006
0.99
8.416
1.01
RS to RT oscillation frequency
ratio *1
Kf2
RT0, RT0-1, RT1 = 10kHz
RT0, RT0-1, RT1 = 100kHz
VDD = 3.0V
Kf3
0.100
0.108
0.115
*1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the
same conditions.
fOSCX(RT0−CS0 oscillation)
fOSCX(RS0−CS0 oscillation)
(x = 1, 2, 3)
fOSCX(RT0-1−CS0 oscillation)
fOSCX(RS0−CS0 oscillation)
fOSCX(RT1−CS1 oscillation)
fOSCX(RS1−CS1 oscillation)
Kfx =
,
,
CVR0
CVR1
RT0, RT0-1, RT1: 1kΩ /10kΩ/100kΩ
RS0, RS1: 10kΩ
CS0, CT0, CS1: 560pF
CVR0, CVR1: 820pF
IN0 CS0 RCT0 RS0 RT0
IN1 CS1 RS1 RT1
RCM
VIH
Frequency measurement
(fOSCX
)
(*1)
VIL
VDD VDDL
VDDX
AVDD VREFVSS AVSS
*1: Input logic circuit to
determine the specified
measuring conditions.
CV
CL1 CL0 CX
Note:
- Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors
and IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wire between IN0/IN1 and RS0/RS1. The coupling
capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise
around the node.
- When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to
the signal.
- Please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. Wiring to reserved
components may affect to the A/D conversion operation by noise the components itself may have.
33/37
FEDL610Q421-03
ML610Q421/ML610Q422
Electrical Characteristics of Successive Approximation Type A/D Converter
(VDD = 1.8 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise
specified)
Rating
Parameter
Symbol
n
Condition
Unit
bit
Min.
Typ.
Max.
12
Resolution
2.7V ≤ VREF ≤ 3.6V
2.2V ≤ VREF ≤ 2.7V
2.7V ≤ VREF ≤ 3.6V
2.2V ≤ VREF ≤ 2.7V
−4
−6
−3
−5
−6
−6
2.2
+4
Integral non-linearity error
IDL
+6
+3
Differential non-linearity error
DNL
LSB
+5
Zero-scale error
Full-scale error
Reference voltage
VOFF
FSE
VREF
+6
+6
AVDD
V
SACK = 0
(HSCLK = 375kHz to 625kHz)
SACK = 1
25
Conversion time
tCONV
φ/CH
112
(HSCLK = 1.5MHz to 4.2MHz)
φ: Period of high-speed clock (HSCLK)
AVDD
Reference
voltage
VREF
VDD
VDDL
10µF
1µF
A
0.1µF
0.1µF
VDDX
VSS
RI≤5kΩ
−
AIN0,
AIN1
1µF
+
Analog input
AVSS
0.1µF
34/37
FEDL610Q421-03
ML610Q421/ML610Q422
PACKAGE DIMENSIONS
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package
code and desired mounting conditions (reflow method, temperature and times).
35/37
FEDL610Q421-03
ML610Q421/ML610Q422
REVISION HISTORY
Page
Document No.
Date
Description
Previous Current
Edition
Edition
FEDL610Q421-01
FEDL610Q421-02
Jul. 29, 2009
Dec. 3, 2010
–
–
–
–
Final edition 1
Add to B version
Change header
Delete B version
All
3,4
All
3,4
Change from "Shipment" to " Product name – Supported
Function "
4
–
4
FEDL610Q421-03
Feb. 9, 2015
Add CLOCK GENERATION CIRCUIT OPERATING
CONDITIONS
22
Change "RESET" to " Reset pulse width (PRST)" and "
Power-on reset activation power rise time (TPOR )".
Change description in Note.
22
36
23
37
36/37
FEDL610Q421-03
ML610Q421/ML610Q422
Notes
1) The information contained herein is subject to change without notice.
2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can
break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure,
please take safety measures such as complying with the derating characteristics, implementing redundant and fire
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any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor.
3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate
the standard usage and operations of the Products.The peripheral conditions must be taken into account when designing
circuits for mass production.
4) The technical information specified herein is intended only to show the typical functions of the Products and examples of
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rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this
document; therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights
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9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the
recommended usage conditions and specifications contained herein.
10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document.
However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall have
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11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.
For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no
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Copyright 2008 - 2015 LAPIS Semiconductor Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku,
Yokohama 222-8575, Japan
http://www.lapis-semi.com/en/
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