FEDL610Q428-01 [LAPIS]
8-bit Microcontroller with a Built-in LCD driver;
| 型号： | FEDL610Q428-01 |
| 厂家： | 
LAPIS Semiconductor Co., Ltd. |
| 描述： | 8-bit Microcontroller with a Built-in LCD driver CD 微控制器 |
| 文件： | 总34页 (文件大小：724K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL610Q428-04
Issue Date: May.15, 2015
ML610Q428/ML610Q429
8-bit Microcontroller with a Built-in LCD driver
GENERAL DESCRIPTION
This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port,
UART, I2C bus interface (master), melody driver, battery level detect circuit, RC oscillation type A/D converter, and LCD
driver, are incorporated around 8-bit CPU nX-U8/100.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe line architecture
parallel procesing. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption operation
(read operation) equivalent to mask ROM and is most suitable for battery-driven applications.
The on-chip debug function that is installed enables program debugging and programming.
FEATURES
• CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system: 16-bit instructions
− Instruction set:
Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic
shift, and so on
− On-Chip debug function
− Minimum instruction execution time
30.5 µs (@32.768 kHz system clock)
0.24 4µs (@4.096 MHz system clock)
• Internal memory
− Internal 48KByte Flash ROM (24K×16 bits) (including unusable 1KByte TEST area)
− Internal 3KByte Data RAM (3072×8 bits), 1KByte Display Allocation RAM (1024 x 8bit)
− Internal 192-byte RAM for display
• Interrupt controller
− 2 non-maskable interrupt sources (Internal source: 1, External source: 1)
− 27 maskable interrupt sources (Internal sources: 19, External sources: 8)
• Time base counter
− Low-speed time base counter ×1 channel
Frequency compensation (Compensation range: Approx. −488ppm to +488ppm. Compensation accuracy: Approx.
0.48ppm)
− High-speed time base counter ×1 channel
• Watchdog timer
− Non-maskable interrupt and reset
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
• Timers
− 8 bits × 2 channels (16-bit configuration available)
• 1 kHz timer
− 10 Hz/1 Hz interrupt function
1/34
FEDL610Q428-04
ML610Q428/ML610Q429
• PWM
− Resolution 16 bits × 3 channel
• Synchronous serial port
− Master/slave selectable
− LSB first/MSB first selectable
− 8-bit length/16-bit length selectable
− Timer interrupt is used as a serial clock and selection is possible
• UART
− TXD/RXD × 1 channel
− Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
− Positive logic/negative logic selectable
− Built-in baud rate generator
• I2C bus interface
− Master function only
− Fast mode (400 kbps@4MHｚ), standard mode (100 kbps@4MHｚ, 50kbps@500kHz)
• Melody driver
− Scale: 29 types (Melody sound frequency: 508 Hz to 32.768 kHz)
− Tone length: 63 types
− Tempo: 15 types
− Buzzer output mode (4 output modes, 8 frequencies, 16 duty levels)
• RC oscillation type A/D converter
− 24-bit counter
− Time division × 2 channels
• Successive approximation type A/D converter
− 12-bit A/D converter
− Input × 2 channels
• General-purpose ports
− Non-maskable interrupt input port × 1 channel
− Input-only port × 10 channels (including secondary functions)
− Output-only port × 3 channels (including secondary functions)
− Input/output port
ML610Q428: 14 channels (including secondary functions)
ML610Q429: 20 channels (including secondary functions)
• LCD driver
− Dot matrix can be supported.
ML610Q428: 1392 dots max. (58 seg × 24 com), 1/1 to 1/24 duty
ML610Q429: 512 dots max. (64 seg × 8 com) , 1/1 to 1/8 duty
− 1/3 or 1/4 bias (built-in bias generation circuit)
− Frame frequency selecable (approx. 32Hz, 64 Hz, 73 Hz, 85 Hz, and 102 Hz)
− Bias voltage multiplying clock selectable (8 types)
− Contrast adjustment (1/3 bias: 32 steps, 1/4 bias: 20 steps)
− LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable
− Programmable display allocation function (available only when 1/1~1/8 duty is selected)
2/34
FEDL610Q428-04
ML610Q428/ML610Q429
• Reset
− Reset through the RESET_N pin
− Power-on reset generation when powered on
− Reset when oscillation stop of the low-speed clock is detected
− Reset by the watchdog timer (WDT) overflow
• Power supply voltage detect function
− Judgment voltages:
− Judgment accuracy:
One of 16 levels
±2% (Typ.)
• Clock
− Low-speed clock: (This LSI can not guarantee the operation withoug low-speed clock)
Crystal oscillation (32.768 kHz)
− High-speed clock:
Built-in RC oscillation (2M/500kHz)
Built-in PLL oscillation (8.192 MHz ±2.5%), crystal/ceramic oscillation (4.096 MHz), external clock
− Selection of high-speed clock mode by software:
Built-in RC oscillation, built-in PLL oscillation, crystal/ceramic oscillation, external clock
• Power management
− HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).
− STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are
stopped.)
− Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation
clock)
− Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals.
• Guaranteed operating range
− Operating temperature: −20°C to 70°C
− Operating voltage: VDD = 1.1V to 3.6V
3/34
FEDL610Q428-04
ML610Q428/ML610Q429
• Product name – Supported Function
The lien up to the ML610Q428and ML610Q429 is beiow.
Operating
temperature
- Chip (Die) -
ML610Q428-xxxWA
ML610Q429-xxxWA
ROM type
Flash ROM
Flash ROM
Product availability
-20°C to +70°C
-20°C to +70°C
Yes
Yes
-128-pin plastic
TQFP -
Operating
temperature
ROM type
Flash ROM
Flash ROM
Product availability
ML610Q428-xxxTB
ML610Q429-xxxTB
-20°C to +70°C
-20°C to +70°C
Yes
Yes
xxx: ROM code number (xxx of the blank product is NNN)
Q:Flash ROM version
WA: Chip
TB: TQFP
4/34
FEDL610Q428-04
ML610Q428/ML610Q429
BLOCK DIAGRAM
ML610Q428 Block Diagram
Figure 1 show the block diagram of the ML610Q428.
"*" indicates the secondary function of each port.
CPU (nX-U8/100)
EPSW1～3
ELR1～3
ECSR1～3
DSR/CSR
PC
GREG
0～15
PSW
LR
EA
SP
Timing
Controller
ALU
Program
Memory
(Flash)
BUS
Controller
VPP
Instruction
Decoder
Instruction
Register
On-Chip
ICE
48Kbyte
Data-bus
VDD
VSS
INT
1
SCK0*
SIN0*
SSIO
UART
I2C
RAM
2048byte
RESET_N
TEST
SOUT0*
RESET &
TEST
INT
1
RXD0*
TXD0*
Interrupt
Controller
XT0
XT1
INT
1
OSC0*
OSC1*
INT
1
OSC
SDA*
SCL*
WDT
TBC
LSCLK*
OUTCLK*
INT
3
VDDL
VDDX
INT
8
PWM
×3
PWM0* to PWM2*
MD0*
Power
INT
1
INT
1
Melody
GPIO
INT
1
1kHzTC
INT
5
IN0*
CS0*
RS0*
RT0*
CRT0*
RCM*
IN1*
CS1*
RS1*
RT1*
NMI
P00 to P03
P10 to P11
INT
2
RC-ADC
×2
8bit Timer
P20 to P22
×2
P30 to P35
P40 to P47
Display Allocation
RAM 1KByte
COM0 to COM23
SEG0 to SEG57
LCD
Driver
BLD
Display RAM
192Byte
VL1, VL2, VL3, VL4
C1, C2, C3, C4
LCD
BIAS
Figure 1 ML610Q428 Block Diagram
5/34
FEDL610Q428-04
ML610Q428/ML610Q429
ML610Q429 Block Diagram
Figure 2 show the block diagram of the ML610Q429.
"*" indicates the secondary function of each port.
CPU (nX-U8/100)
EPSW1～3
ELR1～3
ECSR1～3
DSR/CSR
PC
GREG
0～15
PSW
LR
EA
SP
Timing
Controller
ALU
Program
Memory
(Flash)
BUS
Controller
VPP
Instruction
Decoder
Instruction
Register
On-Chip
ICE
48Kbyte
Data-bus
VDD
VSS
INT
1
SCK0*
SIN0*
SSIO
UART
I2C
RAM
2048byte
RESET_N
TEST
SOUT0*
RESET &
TEST
INT
1
RXD0*
TXD0*
Interrupt
Controller
XT0
XT1
INT
1
OSC0*
OSC1*
INT
1
OSC
SDA*
SCL*
WDT
TBC
LSCLK*
OUTCLK*
INT
3
VDDL
VDDX
INT
8
PWM
×3
PWM0* to PWM2*
MD0*
Power
INT
1
INT
1
Melody
GPIO
INT
1
1kHzTC
INT
9
IN0*
CS0*
RS0*
RT0*
CRT0*
RCM*
IN1*
CS1*
RS1*
RT1*
NMI
P00 to P08
P10 to P11
INT
2
RC-ADC
×2
8bit Timer
P20 to P22
×2
P30 to P35
P40 to P47
PA0 to PA5
Display Allocation
RAM 1KByte
COM0 to COM7
SEG0 to SEG63
LCD
Driver
BLD
Display RAM
192Byte
VL1, VL2, VL3, VL4
C1, C2, C3, C4
LCD
BIAS
Figure 2 ML610Q429 Block Diagram
6/34
FEDL610Q428-04
ML610Q428/ML610Q429
PIN CONFIGURATION
ML610Q428 TQFP128 Pin Layout
96pin
65pin
97pin
64pin
SEG42
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P20
97
98
99
P21
P22
P40
P41
VPP
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
RESET_N
P44
P45
P46
P47
P30
P31
P34
P32
P33
P35
TEST
VDD
ML610Q428
VDDL
VSS
VDDX
XT0
XT1
P42
P43
VL1
VL2
VL3
VL4
C1
C2
128pin
33pin
1pin
32pin
(NC): No Connection
Figure 3 ML610Q428 TQFP128 Pin Configuration
7/34
FEDL610Q428-04
ML610Q428/ML610Q429
ML610Q429 TQFP128 Pin Layout
96pin
65pin
97pin
64pin
SEG42
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P20
97
98
99
P21
P22
P40
P41
VPP
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
RESET_N
P44
P45
P46
P47
P30
P31
P34
P32
P33
P35
TEST
VDD
ML610Q429
VDDL
VSS
VDDX
XT0
XT1
P42
P43
VL1
VL2
VL3
VL4
C1
C2
128pin
33pin
1pin
32pin
(NC): No Connection
Figure 4 ML610Q429 TQFP128 Pin Configuration
8/34
FEDL610Q428-04
ML610Q428/ML610Q429
ML610Q428 Chip Dimension
P20 94
P21 95
P22 96
P40 97
P41 98
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
VPP
99
RESET_N 100
P44 101
P45 102
P46 103
P47 104
P30 105
P31 106
P34 107
P32 108
P33 109
P35 110
TEST 111
VDD 112
VDDL 113
VSS 114
VDDX 115
XT0 116
Device Name
"ZF8"
ZF8
XT1 117
P42 118
P43 119
VL1 120
VL2 121
VL3 122
VL4 123
C1 124
C2 125
Device Name
"428"
428
Chip size:
PAD count:
2.99 mm × 3.11 mm
125 pins
Minimum PAD pitch:
PAD aperture:
Chip thickness:
80 µm
70 µm × 70 µm
350 µm
Voltage of the rear side of chip: VSS level
Figure 5 ML610Q428 Chip Dimension
Note:
Figure 5 is an image figure of the order of PAD, and it differs from an actual image. Refer to the PAD coordinate for detailed
arrangement.
A chip angle can be checked by the distinguishing mark of three figures.
9/34
FEDL610Q428-04
ML610Q428/ML610Q429
ML610Q429 Chip Dimension
P20 94
P21 95
P22 96
P40 97
P41 98
62 SEG42
61 SEG41
60 SEG40
59 SEG39
58 SEG38
57 SEG37
56 SEG36
55 SEG35
54 SEG34
53 SEG33
52 SEG32
51 SEG31
50 SEG30
49 SEG29
48 SEG28
47 SEG27
46 SEG26
45 SEG25
44 SEG24
43 SEG23
42 SEG22
41 SEG21
40 SEG20
39 SEG19
38 SEG18
37 SEG17
36 SEG16
35 SEG15
34 SEG14
33 SEG13
32 SEG12
31 SEG11
VPP
99
RESET_N 100
P44 101
P45 102
P46 103
P47 104
P30 105
P31 106
P34 107
P32 108
P33 109
P35 110
TEST 111
VDD 112
VDDL 113
VSS 114
VDDX 115
XT0 116
Device Name
"ZF8"
ZF8
XT1 117
P42 118
P43 119
VL1 120
VL2 121
VL3 122
VL4 123
C1 124
C2 125
Device Name
"428"
428
Chip size:
PAD count:
2.99 mm × 3.11 mm
125 pins
Minimum PAD pitch:
PAD aperture:
Chip thickness:
80 µm
70 µm × 70 µm
350 µm
Voltage of the rear side of chip: VSS level
Figure 6 ML610Q429 Chip Dimension
Note:
Figure 6 is an image figure of the order of PAD, and it differs from an actual image. Refer to the PAD coordinate for detailed
arrangement.
A chip angle can be checked by the distinguishing mark of three figures.
10/34
FEDL610Q428-04
ML610Q428/ML610Q429
PIN LIST
PAD No.
Primary function
Secondary function
Tertiary function
Q429 Q428 Pin name I/O
Function
Pin name I/O
Function
Pin name I/O
Function
Negative power supply
pin
8,114 8,114
11,112 11,112
Vss
VDD
Positive power supply
pin
Power supply pin for
internal logic (internally
generated)
113
113
VDDL
Power supply pin for
low-speed oscillation
(internally generated)
Power supply pin for
Flash ROM
115
99
115
99
VDDX
VPP
VL1
Power supply pin for
LCD bias (internally
generated)
120
120
Power supply pin for
LCD bias (internally
generated)
Power supply pin for
LCD bias (internally
generated)
121
122
123
124
125
1
121
122
123
124
125
1
VL2
VL3
VL4
C1
C2
C3
C4
Power supply pin for
LCD bias (internally
generated)
Capacitor connection
pin for LCD bias
generation
Capacitor connection
pin for LCD bias
generation
Capacitor connection
pin for LCD bias
generation
Capacitor connection
pin for LCD bias
generation
2
2
Input/output pin for
testing
111
100
116
111
100
116
TEST
RESET_N
XT0
I/O
Reset input pin
I
I
Low-speed clock
oscillation pin
Low-speed clock
oscillation pin
117
7
117
7
XT1
O
I
Non-maskable interrupt
pin
NMI
Input port, External
interrupt 0 input
Input port, External
interrupt 1 input
Input port, External
interrupt 2, UART0
receive, PWM2
external clock input
3
3
P00/EXI0
P01/EXI1
I
4
4
I
P02/EXI2
/RXD0
5
5
I
I
/P2CK
Input port, External
interrupt 3
6
6
P03/EXI3
Input port, External
interrupt 4
90
91
P04/EXI4 I/O
P05/EXI5 I/O
Input port, External
interrupt 5
Input port, External
interrupt 6
92
93
P06/EXI6 I/O
P07/EXI7 I/O
Input port, External
11/34
FEDL610Q428-04
ML610Q428/ML610Q429
PAD No.
Primary function
Function
interrupt 7
Secondary function
Tertiary function
Q429 Q428 Pin name I/O
Pin name I/O
Function
Pin name I/O
Function
Input port
Input port
Output port
High-speed oscillation
High-speed oscillation
Low-speed clock output
9
9
P10
P11
I
I
OSC0
OSC1
LSCLK
I
O
10
94
10
94
O
O
PWM2 output
P20/LED0
O
PWM2
High-speed clock
output
Output port
95
96
95
96
P21/LED1
P22/LED2
P30
O
O
OUTCLK
MD0
O
O
I
O
Output port
Melody output
RC type ADC0
oscillation input pin
RC type ADC0
Input/output port
PWM2 output
105
105
I/O
IN0
PWM2
Input/output port
reference capacitor
connection pin
106
106
P31
I/O
CS0
O
RC type ADC0
Input/output port
Input/output port
Input/output port
Input/output port
reference resistor
connection pin
108
109
107
110
108
109
107
110
P32
P33
P34
P35
I/O
I/O
I/O
I/O
RS0
RT0
O
O
O
O
O
RC type ADC0 resistor
sensor connection pin
RC type ADC0
resistor/capacitor
sensor connection pin
RC type ADC
PWM0 output
RCT0
RCM
PWM0
PWM1 output
PWM1
SIN0
O
I
oscillation monitor
Input/output port
Input/output port
Input/output port
Input/output port
I2C data input/output
I2C clock input/output
UART data input
SSIO data input
97
98
97
98
P40
P41
P42
P43
I/O
I/O
I/O
I/O
SDA
SCL
I/O
I/O
I
SSIO synchronous clock
SSIO data output
PWM0 output
SCK0 I/O
118
119
118
119
RXD0
TXD0
SOUT0
PWM0
O
O
UART data output
O
Input/output port, Timer
0/Timer 2/PWM0
external clock input
Input/output port, Timer
1/Timer 3/PWM1
external clock input
Input/output port,
PWM2 external clock
input
P44/T02P
0CK
RC type ADC1
oscillation input pin
SSIO0 data input
101
102
103
101
102
103
I/O
I/O
IN1
I
SIN0
I
RC type ADC1
reference capacitor
connection pin
RC type ADC1
reference resistor
connection pin
P45/T13P
1CK
SSIO0 synchronous
clock
CS1
O
SCK0 I/O
P46/T46P
2CK
SSIO0 data output
PWM1 output
I/O
I/O
RS1
RT1
O
O
SOUT0
PWM1
O
O
RC type ADC1 resistor
sensor connection pin
Input/output port
104 1004
P47
Input/output port
Input/output port
Input/output port
Input/output port
Input/output port
Input/output port
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
84
85
86
87
88
89
12
13
14
15
16
17
18
19
12
13
14
15
16
17
18
19
78
79
80
81
82
83
84
85
PA0
PA1
I/O
I/O
I/O
I/O
I/O
I/O
O
PA2
PA3
PA4
PA5
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
12/34
FEDL610Q428-04
ML610Q428/ML610Q429
PAD No.
Primary function
Secondary function
Pin name I/O
Tertiary function
Q429 Q428 Pin name I/O
Function
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD common pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
Function
Pin name I/O
Function
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
86
87
88
89
90
91
92
93
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
SEG0
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
13/34
FEDL610Q428-04
ML610Q428/ML610Q429
PAD No.
Primary function
Secondary function
Tertiary function
Q429 Q428 Pin name I/O
Function
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
Pin name I/O
Function
Pin name I/O
Function
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
65
66
67
68
69
70
71
72
73
74
75
76
77
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
14/34
FEDL610Q428-04
ML610Q428/ML610Q429
PIN DESCRIPTION
Primary/
Secondary/
Tertiary
Pin name
I/O
I
Description
Logic
System
Reset input pin. When this pin is set to a “L” level, system reset mode is
set and the internal section is initialized. When this pin is set to a “H” level
subsequently, program execution starts. A pull-up resistor is internally
connected.
RESET_N
—
Negative
Crystal connection pin for low-speed clock.
XT0
XT1
I
—
—
—
—
A 32.768 kHz crystal oscillator (see measuring circuit 1) is connected to
this pin. Capacitors CDL and CGL are connected across this pin and VSS
as required.
O
Crystal/ceramic connection pin for high-speed clock.
A crystal or ceramic is connected to this pin (4.1 MHz max.). Capacitors
CDH and CGH (see measuring circuit 1) are connected across this pin
OSC0
OSC1
I
Secondary
Secondary
—
—
O
and VSS
.
This pin is used as the secondary function of the P10 pin(OSC0) and P11
pin(OSC1).
Low-speed clock output pin. This pin is used as the secondary function of
the P20 pin.
High-speed clock output pin. This pin is used as the secondary function of
the P21 pin.
LSCLK
O
O
Secondary
Secondary
—
—
OUTCLK
General-purpose input port
General-purpose input port.
P00-P03
I
Primary
Primary
Positive
Positive
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
General-purpose input port.
P04-P07
I
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
These pins are for the ML610Q429, but are not provided in the
ML610Q428.
General-purpose input port.
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
P10-P11
I
Primary
Primary
Positive
Positive
General-purpose output port
General-purpose output port.
P20-P22
O
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
General-purpose input/output port
General-purpose input/output port.
P30-P35
P40-P47
PA0-PA5
I/O
I/O
I/O
Primary
Primary
Primary
Positive
Positive
Positive
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
General-purpose input/output port.
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
General-purpose input/output port.
These pins are for the ML610Q429, but are not provided in the
ML610Q428.
15/34
FEDL610Q428-04
ML610Q428/ML610Q429
Primary/
Secondary/
Tertiary
Pin name
UART
I/O
Description
Logic
UART data output pin. This pin is used as the secondary function of the
P43 pin.
UART data input pin. This pin is used as the secondary function of the
P42 or the primary function of the P02 pin.
TXD0
O
I
Secondary Positive
RXD0
Primary/Se Positive
condary
I2C bus interface
I2C data input/output pin. This pin is used as the secondary function of the
P40 pin. This pin has an NMOS open drain output. When using this pin as
a function of the I2C, externally connect a pull-up resistor.
SDA
I/O
Secondary Positive
Secondary Positive
I2C clock output pin. This pin is used as the secondary function of the P41
pin. This pin has an NMOS open drain output. When using this pin as a
function of the I2C, externally connect a pull-up resistor.
SCL
O
Synchronous serial (SSIO)
Synchronous serial clock input/output pin. This pin is used as the tertiary
function of the P41 or P45 pin.
Synchronous serial data input pin. This pin is used as the tertiary function
of the P40 or P44 pin.
Synchronous serial data output pin. This pin is used as the tertiary
function of the P42 or P46 pin.
SCK0
I/O
Tertiary
Tertiary
Tertiary
—
SIN0
I
Positive
Positive
SOUT0
O
PWM
PWM0 output pin. This pin is used as the tertiary function of the P43 or
P34 pin.
PWM0 external clock input pin. This pin is used as the primary function of
the P44 pin.
PWM1 output pin. This pin is used as the tertiary function of the P47 or
P35 pin.
PWM1 external clock input pin. This pin is used as the primary function of
the P45 pin.
PWM0
T0P0CK
PWM1
T1P1CK
PWM2
P2CK
O
I
Tertiary
Primary
Tertiary
Primary
Tertiary
Primary
Positive
—
O
I
Positive
—
PWM2 output pin. This pin is used as the tertiary function of the P20 or
P30 pin.
PWM2 external clock input pin. This pin is used as the primary function of
the P02 pin.
O
I
Positive
—
External interrupt
External non-maskable interrupt input pin. An interrupt is generated on
both edges.
External maskable interrupt input pins. Interrupt enable and edge
selection can be performed for each bit by software. These pins are used
as the primary functions of the P00-P07 pins.
Positive/
negative
Positive/
negative
NMI
I
Primary
Primary
EXI0-7
I
Timer
External clock input pin used for Timer 0. This pin is used as the primary
function of the P44 pin.
External clock input pin used for Timer 1. This pin is used as the primary
function of the P45 pin.
T0P0CK
I
I
Primary
Primary
—
—
T1P1CK
Melody
Melody/buzzer signal output pin. This pin is used as the secondary
function of the P22 pin.
Positive/
negative
MD0
O
O
Secondary
Primary
LED drive
LED0-2
Nch open drain output pins to drive LED.
Positive/
negative
16/34
FEDL610Q428-04
ML610Q428/ML610Q429
Primary/
Secondary/
Tertiary
Pin name
I/O
Description
Logic
RC oscillation type A/D converter
Channel 0 oscillation input pin. This pin is used as the secondary function
of the P30 pin.
Channel 0 reference capacitor connection pin. This pin is used as the
secondary function of the P31 pin.
This pin is used as the secondary function of the P32 pin which is the
reference resistor connection pin of Channel 0.
Resistor sensor connection pin of Channel 0 for measurement. This pin is
used as the secondary function of the P34 pin.
Resistor/capacitor sensor connection pin of Channel 0 for measurement.
This pin is used as the secondary function of the P33 pin.
RC oscillation monitor pin. This pin is used as the secondary function of
the P35 pin.
Oscillation input pin of Channel 1. This pin is used as the secondary
function of the P44 pin.
Reference capacitor connection pin of Channel 1. This pin is used as the
secondary function of the P45 pin.
Reference resistor connection pin of Channel 1. This pin is used as the
secondary function of the P46 pin.
IN0
CS0
RS0
RT0
CRT0
RCM
IN1
I
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
I
CS1
RS1
RT1
O
O
O
Resistor sensor connection pin for measurement of Channel 1. This pin is
used as the secondary function of the P47 pin.
LCD drive signal
Common output pins.
COM0-7
O
—
—
—
—
Common output pins.
COM8-23
O
These pins are for the ML610Q428, but are not provided in the
ML610Q429.
Segment output pin.
SEG0-57
O
O
—
—
—
—
Segment output pins.
SEG58-63
These pins are for the ML610Q429, but are not provided in the
ML610Q428.
LCD driver power supply
Power supply pins for LCD bias (internally generated). Capacitors Ca, Cb,
Cc, and Cd (see measuring circuit 1) are connected between VSS and VL1,
VL2, VL3, and VL4, respectively.
VL1
VL2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VL3
VL4
Power supply pins for LCD bias (internally generated). Capacitors C12
and C34 (see measuring circuit 1) are connected between C1 and C2 and
between C3 and C4, respectively.
C1
C2
C3
C4
For testing
Input/output pin for testing. A pull-down resistor is internally connected.
TEST
Power supply
VSS
I/O
—
—
Negative power supply pin.
Positive power supply pin.
—
—
—
—
—
—
—
—
—
VDD
Positive power supply pin (internally generated) for internal logic.
VDDL
Capacitors CL0 and CL1 (see measuring circuit 1) are connected between
this pin and VSS
.
Plus-side power supply pin (internally generated) for low-speed oscillation.
Capacitor Cx (see measuring circuit 1) is connected between this pin and
VDDX
—
—
—
—
—
—
VSS
.
Power supply pin for programming Flash ROM. A pull-up resistor is
internally connected.
VPP
17/34
FEDL610Q428-04
ML610Q428/ML610Q429
TERMINATION OF UNUSED PINS
Table 3 shows methods of terminating the unused pins.
Table 3 Termination of Unused Pins
Pin
Recommended pin termination
VPP
Open
Open
VL1, VL2, VL3, VL4
C1, C2, C3, C4
RESET_N
TEST
Open
Open
Open
Open
VDD or VSS
VDD
NMI
P00 to P07
P10 to P11
P20 to P22
P30 to P35
P40 to P47
PA0 to PA5
COM0 to 23
SEG0 to 63
Open
Open
Open
Open
Open
Open
Note:
It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or
the output mode since the supply current may become excessively large if the pins are left open in the high impedance input
setting.
The main difference points of ML610Q428 and ML610Q429
Table 4 The main difference points of ML610Q428 and ML610Q429.
Function
PORT0
ML610Q428
ML610Q429
P03 to P00
Nothing
P07 to P00
PA5 to PA0
PORTA
LCD COM
LCD SEG
COM23 to COM0
SEG57 to SEG0
COM7 to COM0
SEG63 to SEG0
18/34
FEDL610Q428-04
ML610Q428/ML610Q429
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
(VSS = 0V)
Parameter
Power supply voltage 1
Power supply voltage 2
Power supply voltage 3
Power supply voltage 4
Power supply voltage 5
Power supply voltage 6
Power supply voltage 7
Power supply voltage 8
Input voltage
Symbol
Condition
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Port3–A, Ta = 25°C
Port2, Ta = 25°C
Ta = 25°C
Rating
−0.3 to +4.6
−0.3 to +9.5
−0.3 to +3.6
−0.3 to +3.6
−0.3 to +1.75
−0.3 to +3.5
−0.3 to +5.25
−0.3 to +7.0
−0.3 to VDD+0.3
−0.3 to VDD+0.3
−12 to +11
Unit
V
VDD
VPP
V
VDDL
VDDX
VL1
V
V
V
VL2
V
VL3
V
VL4
V
VIN
V
Output voltage
VOUT
IOUT1
IOUT2
PD
V
Output current 1
mA
mA
mW
°C
Output current 2
−12 to +20
Power dissipation
122
Storage temperature
TSTG
−55 to +150
RECOMMENDED OPERATING CONDITIONS
(VSS = 0V)
Unit
Parameter
Operating temperature
Operating voltage
Symbol
Condition
Range
TOP
VDD
−20 to +70
°C
1.1 to 3.6
V
VDD = 1.1 to 3.6V
VDD = 1.3 to 3.6V
VDD = 1.8 to 3.6V
30k to 36k
30k to 650k
30k to 4.2M
1.0±30%
Operating frequency (CPU)
fOP
Hz
CL0
CL1
Capacitor externally connected to
VDDL pin
µF
µF
µF
0.1±30%
Capacitor externally connected to
VDDX pin
CX
0.1±30%
Capacitors externally connected to
Ca, b, c, d
1.0±30%
VL1, 2, 3, 4 pins
Capacitors externally connected
across C1 and C2 pins and across
C3 and C4 pins
C12, C34
1.0±30%
µF
19/34
FEDL610Q428-04
ML610Q428/ML610Q429
CLOCK GENERATION CIRCUIT OPERATING CONDITIONS
(VSS = 0V)
Rating
Typ.
Parameter
Symbol
fXTL
Condition
Unit
Min.
Max.
Low-speed crystal oscillation
frequency
Recommended equivalent series
resistance value of low-speed
crystal oscillation
32.768k
Hz
RL
40k
Ω
CL=6pF of
crystal
0
6
oscillation *2
CL=9pF of
crystal
Low-speed crystal oscillation
external capacitor *1
CDL/CGL
pF
oscillation
CL=12pF of
crystal
12
oscillation
High-speed crystal/ceramic
oscillation frequency
fXTH
4.0M / 4.096M
Hz
pF
CDH
CGH
24
24
High-speed crystal oscillation
external capacitor
*1: The external CDL and CGL need to be adjusted in consideration of variation of internal loading capacitance CD and CG, and
other additional capacitance such as PCB layout.
*2: When using a crystal oscillator CL = 6pF, there is a possibility that can not be adjusted by external CDL and CGL
.
20/34
FEDL610Q428-04
ML610Q428/ML610Q429
OPERATING CONDITIONS OF FLASH ROM
(VSS = 0V)
Parameter
Symbol
TOP
VDD
Condition
At write/erase
At write/erase*1
At write/erase*1
At write/erase*1
Range
0 to +40
2.75 to 3.6
2.5 to 2.75
7.7 to 8.3
80
Unit
Operating temperature
°C
Operating voltage
VDDL
VPP
CEP
V
Write cycles
cycles
years
Data retention
YDR
10
*1: In addition the power supply to VDD pin and VPP pin, within the range 2.5V to 2.75V has to be supplied to VDDL
pin when programming and eraseing Flash ROM.
DC CHARACTERISTICS (1/5)
(VDD = 1.1 to 3.6V, VSS = 0V, Ta = −20 to +70°C, unless otherwise specified) (1/5)
Rating
Typ.
Measuring
circuit
Parameter
Symbol
fRC
Condition
Ta = 25°C
=
Unit
kHz
kHz
MHz
Min.
Typ.
−10%
Typ.
Max.
Typ.
+10%
Typ.
500
500
VDD
500kHz RC oscillation frequency
PLL oscillation frequency*4
1.3 to
3.6V
Ta = −20 to
+70°C
−25%
+25%
LSCLK = 32.768kHz
VDD = 1.8 to 3.6V
fPLL
-2.5% 8.192 +2.5%
Low-speed crystal oscillation
start time*2
TXTL
TRC
0.3
50
2
2
500
20
10
20
s
500kHz RC oscillation start time
µs
1
High-speed crystal oscillation
start time*3
TXTH
TPLL
VDD = 1.8 to 3.6V
―
PLL oscillation start time
VDD = 1.8 to 3.6V
―
1
ms
Low-speed oscillation stop detect
time*1
TSTOP
PRST
PNRST
0.2
200
3
Reset pulse width
µs
Reset noise elimination
pulse width
0.3
Power-on reset activation
power rise time
TPOR
10
ms
*1: When low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is reset to shift to
system reset mode.
*2 : Use 32.768kHz crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=12pF).
*3 : Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera).
*4: 1024 clock average.
[Reset pulse width]
VIL1
VIL1
RESET_N
PRST
Reset pulse width (PRST
)
[Power-on reset activation power rise time]
0.9xVDD
VDD
0.1xVDD
TPOR
Power-on reset activation power rise time (TPOR
)
21/34
FEDL610Q428-04
ML610Q428/ML610Q429
DC CHARACTERISTICS (2/5)
(VDD = 1.1 to 3.6V, VSS = 0V, Ta = −20 to +70°C, unless otherwise specified) (2/5)
Rating
Typ.
0.94
0.96
0.98
1.00
1.02
1.04
1.06
1.08
1.10
1.12
1.14
1.16
1.18
1.20
1.22
1.24
1.26
1.28
1.30
1.32
1.34
1.36
1.38
1.40
1.42
1.44
1.46
1.48
1.50
1.52
1.54
1.56
Measuring
circuit
Parameter
Symbol
Condition
Unit
Min.
0.89
0.91
0.93
0.95
0.97
0.99
1.01
1.03
1.05
1.07
1.09
1.11
1.13
1.15
1.17
1.19
1.21
1.23
1.25
1.27
1.29
1.31
1.33
1.35
1.37
1.39
1.41
1.43
1.45
1.47
1.49
1.51
Max.
0.99
1.01
1.03
1.05
1.07
1.09
1.11
1.13
1.15
1.17
1.19
1.21
1.23
1.25
1.27
1.29
1.31
1.33
1.35
1.37
1.39
1.41
1.43
1.45
1.47
1.49
1.51
1.53
1.55
1.57
1.59
1.61
CN4–0 = 00H
CN4–0 = 01H
CN4–0 = 02H
CN4–0 = 03H
CN4–0 = 04H
CN4–0 = 05H
CN4–0 = 06H
CN4–0 = 07H
CN4–0 = 08H
CN4–0 = 09H
CN4–0 = 0AH
CN4–0 = 0BH
CN4–0 = 0CH
CN4–0 = 0DH
CN4–0 = 0EH
CN4–0 = 0FH
CN4–0 = 10H
CN4–0 = 11H
CN4–0 = 12H
CN4–0 = 13H
CN4–0 = 14H *1
CN4–0 = 15H *1
CN4–0 = 16H *1
CN4–0 = 17H *1
CN4–0 = 18H *1
CN4–0 = 19H *1
CN4–0 = 1AH *1
CN4–0 = 1BH *1
CN4–0 = 1CH *1
CN4–0 = 1DH *1
CN4–0 = 1EH *1
CN4–0 = 1FH *1
V
DD = 3.0V,
VL1 voltage
VL1
V
Tj = 25°C
1
VL1 temperature
deviation
VL1 voltage
VDD = 3.0V
∆VL1
∆VL1
VL2
−1.5
5
mV/°C
VDD = 1.3 to 3.6V
DD = 3.0V, Tj = 25°C
20
mV/V
dependency
V
Typ.
−10%
Typ.
Typ.
+4%
Typ.
+4%
VL2 voltage
VL3 voltage
VL4 voltage
VL1×2
300kΩ load (VL4−VSS
)
1/3 bias
1/4 bias
1/3 bias
1/4 bias
VL1×2
VL1×3
VL1×3
VL1×4
V
DD = 3.0V,
VL3
VL4
V
−10%
Tj = 25°C
300kΩ load
(VL4−VSS
Typ.
−10%
Typ.
+5%
)
LCD bias voltage
generation time
TBIAS
600
ms
*1: When using 1/4 bias, the VL1 voltage is set to typ. 1.32 V (same voltage as in CN4–0 = 13H).
22/34
FEDL610Q428-04
ML610Q428/ML610Q429
DC CHARACTERISTICS (3/5)
(VDD = 1.1 to 3.6V, VSS = 0V, Ta = −20 to +70°C, unless otherwise specified) (3/5)
Rating
Typ.
1.35
1.4
Measuring
circuit
Parameter
Symbol
Condition
Unit
Min.
Max.
LD2–0 = 0H
LD2–0 = 1H
LD2–0 = 2H
LD2–0 = 3H
LD2–0 = 4H
LD2–0 = 5H
LD2–0 = 6H
LD2–0 = 7H
LD2–0 = 8H
LD2–0 = 9H
LD2–0 = 0AH
LD2–0 = 0BH
LD2–0 = 0CH
LD2–0 = 0DH
LD2–0 = 0EH
LD2–0 = 0FH
1.45
1.5
1.6
1.7
1.8
1.9
BLD threshold
voltage
Typ.
−2%
Typ.
+2%
VBLD
VDD = 1.35 to 3.6V
V
2.0
2.1
2.2
2.3
2.4
2.5
2.7
2.9
BLD threshold
voltage
temperature
deviation
1
0
∆VBLD
IDD1
IDD2
IDD3
IDD4
IDD5
VDD = 1.35 to 3.6V
%/°C
µA
Ta =
25°C
0.15
0.50
2.50
1.3
3.5
7
CPU: In STOP state.
Low-speed/high-speed oscillation:
stopped.
Supply current 1
Supply current 2
Supply current 3
Supply current 4
Supply current 5
Ta = -20
to +70°C
Ta =
CPU: In HALT state (LTBC, RTC:
Operating*3*5).
0.5
25°C
µA
High-speed oscillation: Stopped.
LCD/BIAS circuits: Stopped.
Ta = -20
to +70°C
Ta =
CPU: In 32.768kHz operating
state.*1*3
High-speed oscillation: Stopped.
LCD/BIAS circuits: Operating.*2
5
25°C
µA
Ta = -20
to +70°C
12
Ta =
70
85
25°C
CPU: In 500kHz CR operating state.
LCD/BIAS circuits: Operating.*2*3
µA
Ta = -20
to +70°C
100
0.5
0.6
Ta =
0.4
25°C
CPU: In 2MHz CR operating state.
LCD/BIAS circuits: Operating.*2*3
mA
Ta = -20
to +70°C
Ta =
CPU: In 4.096MHz operating state.
PLL: In oscillating state.
0.8
1.0
1.2
25°C
Supply current 6
IDD6
mA
LCD/BIAS circuits: Operating. *2*3
Ta = -20
to +70°C
V
DD = 1.8 to 3.6V
*1 : CPU operating rate is 100% (No HALT state).
*2 : All SEGs: off waveform, No LCD panel load, 1/3 bias, 1/3 duty, Frame frequency: Approx. 64 Hz,
Bias voltage multiplying clock: 1/128 LSCLK (256Hz)
*3 : Use 32.768kHz crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=12pF).
*4 : Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera).
*5 : Significant bits of BLKCON0~BLKCON4 registers are all “1”.
23/34
FEDL610Q428-04
ML610Q428/ML610Q429
DC CHARACTERISTICS (4/5)
(VDD = 1.1 to 3.6V, VSS = 0V, Ta = −20 to +70°C, unless otherwise specified) (4/5)
Rating
Typ.
Measuring
circuit
Parameter
Symbol
Condition
Unit
Min.
VDD
−0.5
VDD
−0.3
VDD
−0.3
Max.
IOH1 = −0.5mA, VDD = 1.8 to 3.6V
IOH1 = -0.1mA, VDD = 1.3 to 3.6V
IOH1 = -0.03mA, VDD = 1.1 to 3.6V
Output voltage 1
(P20–P22/2nd
function is
selected)
(P30–P36)
VOH1
IOL1 = +0.5mA, VDD = 1.8 to 3.6V
IOL1 = +0.1mA, VDD = 1.3 to 3.6V
0.5
0.5
(P40–P47)
(PA0–PA5)*1
VOL1
VOH2
IOL1 = +0.03mA, VDD = 1.1 to 3.6V
IOH1 = −0.5mA, VDD = 1.8 to 3.6V
IOH1 = -0.1mA, VDD = 1.3 to 3.6V
0.3
VDD
−0.5
VDD
−0.3
VDD
Output voltage 2
(P20–P22/2nd
function is Not
selected)
IOH1 = -0.03mA, VDD = 1.1 to 3.6V
IOL2 = +5mA, VDD = 1.8 to 3.6V
−0.3
VOL2
VOL3
0.5
0.4
V
2
IOL3 = +3mA, VDD = 2.0 to 3.6V
(when I2C mode is selected)
Output voltage 3
(P40–P41)
VL4
−0.2
VOH4
VOMH4
VOMH4S
VOM4
IOH4 = −0.2mA, VL1=1.2V
IOMH4 = +0.2mA, VL1=1.2V
IOMH4S = −0.2mA, VL1=1.2V
IOM4 = +0.2mA, VL1=1.2V
IOM4S = −0.2mA, VL1=1.2V
IOML4 = +0.2mA, VL1=1.2V
VL3
+0.2
VL3
−0.2
VL2
+0.2
Output voltage 4
(COM0–23)
(SEG0–63)
VL2
−0.2
VOM4S
VOML4
VL1
+0.2
VL1
−0.2
VOML4S
VOL4
IOML4S = −0.2mA, VL1=1.2V
IOL4 = +0.2mA, VL1=1.2V
0.2
Output leakage
(P20–P22)
IOOH
VOH = VDD (in high-impedance state)
1
(P30–P35)
µA
3
(P40–P47)
IOOL
IIH1
VOL = VSS (in high-impedance state)
−1
(PA0–PA5)*1
VIH1 = VDD
0
−300
−300
−300
300
300
300
1
VDD = 1.8 to 3.6V
−600
−600
−600
20
−20
-10
-2
Input current 1
(RESET_N)
IIL1
VIL1 = VSS
VIH1 = VDD
VDD = 1.3 to 3.6V
VDD = 1.1 to 3.6V
VDD = 1.8 to 3.6V
VDD = 1.3 to 3.6V
VDD = 1.1 to 3.6V
600
600
600
IIH1
IIL1
IIH2
10
Input current 1
(TEST)
2
µA
4
VIL1 = Vss
-1
VDD = 1.8 to 3.6V
VDD = 1.3 to 3.6V
VDD = 1.1 to 3.6V
VDD = 1.8 to 3.6V
VDD = 1.3 to 3.6V
2
30
200
200
200
−2
Input current 2
(NMI)
(P00–P03)
(P04–P07) *1
(P10–P11)
VIH2 = VDD
(when pulled-down)
0.2
30
0.01
−200
−200
30
−30
−30
VIL2 = VSS
(when pulled-up)
IIL2
-0.2
24/34
FEDL610Q428-04
ML610Q428/ML610Q429
(P30–P35)
(P40–P47)
(PA0–PA5)*1
VDD = 1.1 to 3.6V
−200
−30
-0.01
IIH2Z
IIL2Z
VIH2 = VDD (in high-impedance state)
1
VIL2 = VSS (in high-impedance state)
−1
*1: ML610Q429 only
DC CHARACTERISTICS (5/5)
(VDD = 1.1 to 3.6V, VSS = 0V, Ta = -20 to +70°C, unless otherwise specified) (5/5)
Rating
Measuring
circuit
Parameter
Symbol
VIH1
Condition
Unit
Min.
Typ.
Max.
VDD
Input voltage 1
(RESET_N)
(TEST)
0.7
×VDD
V
DD = 1.3 to 3.6V
(NMI)
0.7
×VDD
VDD = 1.1 to 3.6V
VDD = 1.3 to 3.6V
VDD
(P00–P03)
(P04–P07) *1
(P10–P11)
(P31–P35)
(P40–P43)
(P45–P47)
(PA0–PA5)*1
0.3
×VDD
0
V
5
VIL1
0.2
×VDD
VDD = 1.1 to 3.6V
0
0.7
×VDD
VIH2
VIL2
VDD
Input voltage 2
(P30, P44)
0.3
×VDD
0
Input pin
capacitance
(NMI)
f = 10kHz
Vrms = 50mV
Ta = 25°C
(P00–P03)
(P04–P07) *1
(P10–P11)
(P30–P35)
(P40–P47)
(PA0–PA5)*1
*1: ML610Q429 only
CIN
5
pF
25/34
FEDL610Q428-04
ML610Q428/ML610Q429
MEASURING CIRCUITS
MEASURING CIRCUIT 1
XT0
C4
C34
32.768kHz crystal
CGH
C3
C2
XT1
P10/OSC0
C12
C1
CDH
P11/OSC1
VDD
CV:
CL0:
CL1:
CX:
Ca,Cb,Cc,Cd:
C12,C34:
1µF
1µF
0.1µF
0.1µF
1µF
4.096MHz
crystal
VDDL
VDDX
VL1 VL2 VL3
VL4 VSS
1µF
A
CGH
:
24pF
24pF
CV
CL1
CL0 CX
Ca
Cb Cc Cd
CDH
:
32.768kHz crystal resonator
DT-26 (Load capacitance 6pF)
(Made by KDS:DAISHINKU CORP.)
4.096MHz crystal:
HC49SFWB (Kyocera)
MEASURING CIRCUIT 2
(*2)
VIH
V
(*1)
VIL
VDD VDDL VDDX VL1 VL2
VL4
VSS
VL3
(*1) Input logic circuit to determine the specified measuring conditions.
(*2) Measured at the specified output pins.
26/34
FEDL610Q428-04
ML610Q428/ML610Q429
MEASURING CIRCUIT 3
(*2)
VIH
A
RS1
VIL
VDD VDDL VDDX VL1
VL4
VSS
VL2 VL3
*1: Input logic circuit to determine the specified measuring conditions.
*2: Measured at the specified output pins.
MEASURING CIRCUIT 4
(*3)
A
VDD VDDL VDDX VL1 VL2
VL4
VSS
VL3
*3: Measured at the specified output pins.
MEASURING CIRCUIT 5
VIH
(*1)
VIL
VDD VDDL VDDX VL1 VL2 VL3 VL4
VSS
*1: Input logic circuit to determine the specified measuring conditions.
27/34
FEDL610Q428-04
ML610Q428/ML610Q429
AC CHARACTERISTICS (External Interrupt)
(VDD = 1.1 to 3.6V, VSS = 0V, Ta = −20 to +70°C, unless otherwise specified)
Rating
Parameter
Symbol
TNUL
Condition
Unit
Min.
76.8
Typ.
Max.
Interrupt: Enabled (MIE = 1),
CPU: NOP operation
External interrupt disable period
106.8
µs
System clock: 32.768kHz
P00–P07
(Rising-edge interrupt)
tNUL
P00–P07
(Falling-edge interrupt)
tNUL
NMI, P00–P07
(Both-edge interrupt)
tNUL
AC CHARACTERISTICS (UART)
(VDD = 1.3 to 3.6V, VSS = 0V, Ta = −20 to +70°C, unless otherwise specified)
Rating
Parameter
Transmit baud rate
Receive baud rate
Symbol
Condition
Unit
Min.
Typ.
Max.
tTBRT
tRBRT
BRT*1
s
s
BRT*1
−3%
BRT*1
+3%
BRT*1
*1: Baud rate period (including the error of the clock frequency selected) set with the UART baud rate register (UA0BRTL,H)
and the UART mode register 0 (UA0MOD0).
tTBRT
TXD0*
tRBRT
RXD0*
*: Indicates the secondary function of the port.
28/34
FEDL610Q428-04
ML610Q428/ML610Q429
AC CHARACTERISTICS (Synchronous Serial Port)
(VDD = 1.3 to 3.6V, VSS = 0V, Ta = −20 to +70°C, unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
10
Typ.
Max.
When high-speed oscillation is
not active
µs
µs
s
SCLK input cycle
(slave mode)
tSCYC
tSCYC
tSW
When high-speed oscillation is
active (VDD = 1.8 to 3.6V)
1
4
SCLK*1
SCLK output cycle
(master mode)
When high-speed oscillation is
not active
µs
µs
SCLK input pulse width
(slave mode)
When high-speed oscillation is
active (VDD = 1.8 to 3.6V)
0.4
SCLK output pulse width
(master mode)
SCLK*1
×0.4
SCLK*1
×0.5
SCLK*1
×0.6
tSW
tSD
tSD
s
SOUT output delay time
(slave mode)
SOUT output delay time
(master mode)
SIN input
180
80
ns
ns
setup time
tSS
80
ns
(slave mode)
SIN input
setup time
(master mode)
SIN input
tSS
180
80
ns
ns
tSH
hold time
*1: Clock period selected with S0CK3–0 of the serial port 0 mode register (SIO0MOD1)
tSCYC
tSW
tSW
SCLK0*
SOUT0*
SIN0*
tSD
tSD
tSS
tSH
*: Indicates the secondary function of the port.
29/34
FEDL610Q428-04
ML610Q428/ML610Q429
AC CHARACTERISTICS (I2C Bus Interface: Standard Mode 100kHz)
(VDD = 1.8 to 3.6V, VSS = 0V, Ta = −20 to +70°C, unless otherwise specified)
Rating
Parameter
SCL clock frequency
Symbol
Condition
Unit
Min.
0
Typ.
Max.
100
fSCL
kHz
SCL hold time
tHD:STA
4.0
µs
(start/restart condition)
SCL ”L” level time
SCL ”H” level time
SCL setup time
(restart condition)
SDA hold time
SDA setup time
SDA setup time
(stop condition)
Bus-free time
tLOW
tHIGH
4.7
4.0
µs
µs
tSU:STA
4.7
µs
tHD:DAT
tSU:DAT
0
0.25
3.45
µs
µs
tSU:STO
tBUF
4.0
4.7
µs
µs
AC CHARACTERISTICS (I2C Bus Interface: Fast Mode 400kHz)
(VDD = 1.8 to 3.6V, VSS = 0V, Ta = −20 to +70°C, unless otherwise specified)
Rating
Parameter
SCL clock frequency
Symbol
Condition
Unit
Min.
0
Typ.
Max.
400
fSCL
kHz
SCL hold time
tHD:STA
0.6
µs
(start/restart condition)
SCL ”L” level time
SCL ”H” level time
SCL setup time
(restart condition)
SDA hold time
SDA setup time
SDA setup time
(stop condition)
Bus-free time
tLOW
tHIGH
1.3
0.6
µs
µs
tSU:STA
0.6
µs
tHD:DAT
tSU:DAT
0
0.1
0.9
µs
µs
tSU:STO
tBUF
0.6
1.3
µs
µs
Start
condition
Restart
condition
Stop
condition
P40/SDA
P41/SCL
tBUF
tSU:STO
tHD:STA
tLOW tHIGH
tSU:STA tHD:STA
tSU:DAT tHD:DAT
30/34
FEDL610Q428-04
ML610Q428/ML610Q429
AC CHARACTERISTICS (RC Oscillation A/D Converter)
(VDD = 1.3 to 3.6V, VSS = 0V, Ta = −20 to +70°C, unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
1
Typ.
Max.
RS0, RS1,
RT0,
Resistors for oscillation
CS0, CT0, CS1 ≥ 740pF
kΩ
RT0-1,RT1
fOSC1
fOSC2
fOSC3
Kf1
Kf2
Kf3
fOSC1
fOSC2
fOSC3
Kf1
Resistor for oscillation = 1kΩ
Resistor for oscillation = 10kΩ
Resistor for oscillation = 100kΩ
RT0, RT0-1, RT1 = 1kHz
209.4
41.29
4.71
5.567
0.99
330.6
55.27
5.97
435.1
64.16
7.06
kHz
kHz
kHz
kHz
kHz
kHz
Oscillation frequency
VDD = 1.5V
5.982
6.225
RS to RT oscillation frequency
ratio *1
VDD = 1.5V
1
1.01
RT0, RT0-1, RT1 = 10 kHz
RT0, RT0-1, RT1 = 100 kHz
Resistor for oscillation = 1kΩ
Resistor for oscillation = 10kΩ
Resistor for oscillation = 100kΩ
RT0, RT0-1, RT1 = 1kHz
0.108
0.118
0.104
407.3
49.76
5.04
486.7
59.28
5.993
8.210
594.6
72.76
7.04
Oscillation frequency
VDD = 3.0V
8.416
8.006
0.99
RS to RT oscillation frequency
ratio *1
VDD = 3.0V
1
1.01
RT0, RT0-1, RT1 = 10 kHz
RT0, RT0-1, RT1 = 100 kHz
Kf2
Kf3
0.108
0.115
0.100
*1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same
conditions.
fOSCX(RT0−CS0 oscillation)
fOSCX(RS0−CS0 oscillation)
(x = 1, 2, 3)
fOSCX(RT0-1−CS0 oscillation)
fOSCX(RS0−CS0 oscillation)
fOSCX(RT1−CS1 oscillation)
fOSCX(RS1−CS1 oscillation)
Kfx =
,
,
CVR0
CVR1
RT0, RT0-1, RT1: 1kΩ /10kΩ/100kΩ
RS0, RS1: 10kΩ
CS0, CT0, CS1: 560pF
CVR0, CVR1: 820pF
IN0 CS0 RCT0 RS0
IN1 CS1 RS1 RT1
RCM
RT0
VIH
Frequency measurement
(fOSCX
)
(*1)
VIL
VDD VDDL
VDDX
VSS
*1: Input logic circuit to
determine the specified
measuring conditions.
CV
CL1 CL0 CX
Note:
- Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors
and IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wire between IN0/IN1 and RS0/RS1. The coupling
capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise
around the node.
- When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to
the signal.
- Please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. Wiring to reserved
components may affect to the A/D conversion operation by noise the components itself may have.
31/34
FEDL610Q428-04
ML610Q428/ML610Q429
PACKAGE DIMENSIONS
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package
code and desired mounting conditions (reflow method, temperature and times).
32/34
FEDL610Q428-04
ML610Q428/ML610Q429
REVISION HISTORY
Page
Document No.
Date
Description
Previous Current
Edition
Edition
FEDL610Q428-01
FEDL610Q428-02
Feb.7.2011
Jun 7.2011
–
3
–
3
Formally edition 1.0
Add the P version
All
All
Change header and footer
3,18,19,
3,18,20,
20,21,22, 21,22,23,
23,26,27, 24,27,28,
Delete the P version
28,29
3,7
29,30
4
2
Delete package products
2,7
Delete the metal option of only ML610Q429’s LCD driver
Change from "Shipment" to " Product name – Supported
Function "
FEDL610Q428-03
July.25.2014
3
-
4
Add CLOCK GENERATION CIRCUIT OPERATING
CONDITIONS
19
20
Change "RESET" to "Reset pulse width (PRST)" and "
Power-on reset activation power rise time (TPOR )".
Correct the CGL’s value and the CDL’s value of DC
CHARACTERISTICS (3/5)’s note No.3
Update Package Dimensions
19
21
30
22
31
Corrected a typo.
“100kbps@1MHz HSCLK” is corrected to 100kbps@4MHz
HSCLK.
Add the ML610Q429 package product
2
-
2
FEDL610Q428-04
May.15,2015
4,8
33/34
FEDL610Q428-04
ML610Q428/ML610Q429
Notes
1) The information contained herein is subject to change without notice.
2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can
break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure,
please take safety measures such as complying with the derating characteristics, implementing redundant and fire
prevention designs, and utilizing backups and fail-safe procedures. LAPIS Semiconductor shall have no responsibility for
any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor.
3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate
the standard usage and operations of the Products.The peripheral conditions must be taken into account when designing
circuits for mass production.
4) The technical information specified herein is intended only to show the typical functions of the Products and examples of
application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property
rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this
document; therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights
owned by third parties, arising out of the use of such technical information.
5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication, consumer systems,
gaming/entertainment sets) as well as the applications indicated in this document.
6) The Products specified in this document are not designed to be radiation tolerant.
7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and
consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary
communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and
power transmission systems.
8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power
control systems, and submarine repeaters.
9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the
recommended usage conditions and specifications contained herein.
10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document.
However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall have
no responsibility for any damages arising from any inaccuracy or misprint of such information.
11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.
For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no
responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations.
12) When providing our Products and technologies contained in this document to other countries, you must abide by the
procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US
Export Administration Regulations and the Foreign Exchange and Foreign Trade Act.
13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor.
Copyright 2011 – 2015 LAPIS Semiconductor Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku,
Yokohama 222-8575, Japan
http://www.lapis-semi.com/en/
34/34
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