ML610Q408_技术文档

FEDL610Q409-05

Issue Date: May.23, 2014

ML610Q407/ML610Q408/ML61Q0409

8-bit Microcontroller with a Built-in LCD driver

GENERAL DESCRIPTION

ML610Q407/ML610Q408/ML610Q409 is a high-performance 8-bit CMOS microcontroller into which peripheral circuits, such

as synchronous serial port, UART, melody driver, RC oscillation type A/D converter, and LCD driver, are incorporated around

LAPIS Semiconductor-original 8-bit CPU nX-U8/100. ML610Q407/ML610Q408/ML610Q409 operates in both high/low-speed

mode and power-saving mode, it is most suitable for battery operated products.

The short TAT are entertained by offering MTP version ML610Q407(P)/ML610Q408(P)/ML610Q409(P).

ML610Q407P/ ML610Q408P/ML610Q409P support industrial temperature -40°C to +85°C, are added to the product lineup.

FEATURES

• CPU

− 8-bit RISC CPU (CPU name: nX-U8/100)

− Instruction system: 16-bit instructions

− Instruction set:

Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit

manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic

shift, and so on

− On-Chip debug function (MTP version only)

− Minimum instruction execution time

30.5 µs (@32.768 kHz system clock)

2µs (@500kHz system clock)

0.5µs(@2MHz system clock)

• Internal memory

− Internal 16KByte Flash ROM (8K×16 bits) (including unusable １K Byte TEST area)

− Internal 1KByte Data RAM (1024×8 bits)

• Interrupt controller

− 1 non-maskable interrupt sources

Internal source: 1 (Watch dog timer)

− 27 maskable interrupt sources

Internal sources: 14 (SSIO0, SSIO1, Timer0, Timer1, Timer2, Timer3, UART０, Melody0, RC-A/D converter, PWM0,

TBC128Hz, TBC32Hz, TBC16Hz, TBC2Hz)

External sources: 13 (P00, P01, P02, P03, P04, P50, P51, P52, P53, P54, P55, P56, P57)

(One interrupt request is generated from P50 to P57 interrupt sources.)

• Time base counter

− Low-speed time base counter ×1 channel

Frequency compensation (Compensation range: Approx. −488ppm to +488ppm. Compensation accuracy: Approx.

0.48ppm)

− High-speed time base counter ×1 channel

•

Watchdog timer

− Non-maskable interrupt and reset

− Free running

− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)

• Timers

− 8 bits × 4 channels (Timer0-3: 16-bit x 2 configuration available by using Timer0-1 or Timer2-3)

− Clock frequency measurement mode (in one channel of 16-bit configuration using Timer2-3)

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FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

• Capture

− Time base capture × 2 channels (4096 Hz to 32 Hz)

• PWM

− Resolution 16 bits × 1 channel

• Synchronous serial port

− Master/slave selectable × 2 channel

− LSB first/MSB first selectable

− 8-bit length/16-bit length selectable

• UART

− Half-Duplex Communication

− TXD/RXD × 1 channel

− Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits

− Positive logic/negative logic selectable

− Built-in baud rate generator

• Melody driver

− Scale: 29 types (Melody sound frequency: 508 Hz to 32.768 kHz)

− Tone length: 63 types

−Tempo: 15 types

− Buzzer output mode (4 output modes, 8 frequencies, 16 duty levels)

• RC oscillation type A/D converter

− 16-bit counter

− Time division × 2 channels

• General-purpose ports

− Input-only port × 5 channels (including secondary functions)

− Output-only port

ML610Q407: × 12 channels (including secondary functions)

ML610Q408: × 8 channels (including secondary functions)

ML610Q409: × 4 channels (including secondary functions)

− Input/output port × 22 channels (including secondary functions)

• LCD driver

− The number of segments

ML610Q407: 145 dots max. (29seg×5com, 30seg×4com, 31seg×3com, and 32seg×2com selectable)

ML610Q408: 165 dots max. (33seg×5com, 34seg×4com, 35seg×3com, and 36seg×2com selectable)

ML610Q409: 185 dots max. (37seg×5com, 38seg×4com, 39seg×3com, and 40seg×2com selectable)

− 1/1 to 1/5 duty

− 1/2(*), 1/3 bias (built-in bias generation circuit)

− Frame frequency selecable: approx. 64Hz, 73Hz, 85Hz, and 102Hz

− Bias voltage multiplying clock selectable (8 types)

− LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable

− Programmable display allocation function

(*) 1/2 bias is supported by A version and D version

• Reset

− Reset through the RESET_N pin

− Power-on reset generation when powered on

− Reset when oscillation stop of the low-speed clock is detected (Not supported in A version)

− Reset by the watchdog timer (WDT) overflow

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FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

• Clock

− Low-speed clock: Crystal oscillation (32.768 kHz)

(This LSI can not guarantee the operation withoug low-speed crystal oscillation clock)

− High-speed clock: Built-in RC oscillation (500 kHz, 2MHz)

• Power management

− HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).

− STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are

stopped.)

− High-speed Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8 of the

oscillation clock)

− Block Control Function: Resets and completely turns circuits of unused peripherals off.

• Guaranteed operating range

− Operating temperature: −20°C to +70°C (P version: −40°C to +85°C)

− Operating voltage: V_DD= 1.25V to 3.6V

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FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

• Product name – Supported Function

Low-speed

oscillation

stop detect reset

LCD bias

Operating

temperature

- Chip (Die) -

Product availability

1/2

1/3

ML610Q407-ｘｘｘWA

ML610Q408-ｘｘｘWA

ML610Q409-ｘｘｘWA

ML610Q407P-ｘｘｘWA

ML610Q408P-ｘｘｘWA

ML610Q409P-ｘｘｘWA

ML610Q407A- ｘｘｘ WA

-

Yes

-

-20°C to +70°C

-40°C to +85°C

-20°C to +70°C

-40°C to +85°C

Yes

-

Yes

ML610Q408A-ｘｘｘWA

ML610Q409A-ｘｘｘWA

ML610Q407D-ｘｘｘWA

ML610Q408D-ｘｘｘWA

ML610Q409D-ｘｘｘWA

ML610Q407PA-ｘｘｘWA

ML610Q408PA-ｘｘｘWA

ML610Q409PA-ｘｘｘWA

ML610Q407PD-ｘｘｘWA

ML610Q408PD-ｘｘｘWA

ML610Q409PD-ｘｘｘWA

-

Yes

-

Yes

-

Yes

-

Yes

-

LCD bias

Low-speed

oscillation

stop detect reset

-100-pin plastic

TQFP -

Operating

temperature

Product availability

1/2

1/3

ML610Q407-ｘｘｘTB

ML610Q408-ｘｘｘTB

ML610Q409-ｘｘｘTB

ML610Q407P-ｘｘｘTB

ML610Q408P-ｘｘｘTB

ML610Q409P-ｘｘｘTB

ML610Q407A-ｘｘｘTB

ML610Q408A-ｘｘｘTB

ML610Q409A-ｘｘｘTB

ML610Q407D-ｘｘｘTB

ML610Q408D-ｘｘｘTB

ML610Q409D-ｘｘｘTB

ML610Q407PAｘｘｘTB

ML610Q408PAｘｘｘTB

ML610Q409PAｘｘｘTB

ML610Q407PDｘｘｘTB

ML610Q408PDｘｘｘTB

ML610Q409PDｘｘｘTB

-

Yes

-

-20°C to +70°C

-40°C to +85°C

-20°C to +70°C

-40°C to +85°C

Yes

-

Yes

-

Yes

-

Yes

-

Yes

-

Yes

-

Yes

-

Yes

xxx: ROM code number (xxx of the blank product is NNN)

Q: MTP version

P: Wide range temperature version (P version)

A: Low-speed clock oscillation stop detection reset is disabled always and LCD 1/2 bias supported version.(A

version)

D: LCD 1/2 bias supported version (D version)

WA: Chip (Die),

TB: TQFP

4/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

BLOCK DIAGRAM

ML610Q407/ML610Q408/ML610Q409 Block Diagram

Figure 1 show the block diagram of the ML610Q407/ML610Q408/ML610Q409.

“*” indicates the secondary function of each port.

“

^(*1)”： 29seg×5com, 30seg×4com, 31seg×3com, and 32seg×2com selectable

^(*2)”： 33seg×5com, 34seg×4com, 35seg×3com, and 36seg×2com selectable

^(*3)”： 37seg×5com, 38seg×4com, 39seg×3com, and 40seg×2com selectable

CPU (nX-U8/100)

EPSW1～3

ELR1～3

LR

ECSR1～3

DSR/CSR

PC

GREG

0～15

PSW

EA

Timing

Controller

ALU

SP

Program

Memory

(MTP)

BUS

Controller

V_PP

Instruction

Decoder

Instruction

Register

On-Chip

ICE

16Kbyte

Data-bus

V_DD

V_SS

INT

2

SCK0*

SIN0*

RAM

1Kbyte

RESET_N

TEST0

TEST1_N

SSIO

×2

SOUT0*

RESET &

TEST

SCK1*

SIN1*

SOUT1*

Interrupt

Controller

XT0

XT1

INT

1

INT

1

OSC

WDT

TBC

RXD0*

TXD0*

LSCLK*

OUTCLK*

UART

PWM

INT

4

INT

1

Power

V_DDL

PWM0*

MD0*

INT

1

INT

1

IN0*

CS0*

RS0*

RT0*

CRT0*

RCM*

IN1*

CS1*

RS1*

RT1*

Melody

GPIO

Capture

×2

INT

6

RC-ADC

×2

INT

4

P00 to P04

P20 to P22, P24

P30 to P35

P40 to P47

P50 to P57

8bit Timer

×4

P60 to P67 (ML610Q407)

P60 to P63 (ML610Q408)

Display

Allocation

RAM

(*1)(*2)(*3)

COM0 to COM4

LCD

Driver

SEG0 to SEG31 (ML610Q407) ^(*1)

SEG0 to SEG35 (ML610Q408) ^(*2)

SEG0 to SEG39 (ML610Q409) ^(*3)

V_L1, V_L2, V_L3

Display

register

320bit

LCD

BIAS

C1, C2

Figure 1 ML610Q407/ML610Q408/ML610Q409 Block Diagram

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FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

PIN CONFIGURATION

ML610Q407 TQFP100 Pin Layout

(NC)

V_SS

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

(NC)

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

P20

P21

P22

P24

P00

P01

P02

P03

P04

P30

P31

P34

P32

P33

P35

P57

P56

P55

P54

P53

V_PP

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

COM4/SEG2

COM3/SEG1

COM2/SEG0

COM1

COM0

C2

(NC)

C1

(NC)

Note:

The assignment of the P30 to P35 are not in order.

Figure 2 ML610Q407 TQFP100 Pin Configuration

6/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

ML610Q408 TQFP100 Pin Layout

(NC)

V_SS

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

(NC)

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

P20

P21

P22

P24

P00

P01

P02

P03

P04

P30

P31

P34

P32

P33

P35

P57

P56

P55

P54

P53

V_PP

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

COM4/SEG2

COM3/SEG1

COM2/SEG0

COM1

COM0

C2

(NC)

C1

(NC)

Note:

The assignment of the P30 to P35 are not in order.

Figure 3 ML610Q408 TQFP100 Pin Configuration

7/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

ML610Q409 TQFP100 Pin Layout

(NC)

V_SS

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

(NC)

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

P20

P21

P22

P24

P00

P01

P02

P03

P04

P30

P31

P34

P32

P33

P35

P57

P56

P55

P54

P53

V_PP

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

COM4/SEG2

COM3/SEG1

COM2/SEG0

COM1

COM0

C2

(NC)

C1

(NC)

Note:

The assignment of the P30 to P35 are not in order.

Figure 4 ML610Q409 TQFP100 Pin Configuration

8/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

ML610Q407 Chip Pin Layout & Dimension

V_SS

P20

P21

P22

P24

67

68

69

70

71

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

44

43

42

41

40

39

P00

P01

P02

P03

P04

P30

P31

P34

P32

P33

P35

P57

P56

P55

P54

P53

V_PP

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

38 SEG11

SEG10

SEG9

35 SEG8

SEG7

37

36

34

2.23mm

33 SEG6

32 SEG5

SEG4

31

30 SEG3

29 COM4/SEG2

COM3/SEG1

28

27 COM2/SEG0

26 COM1

25 COM0

24 C2

23 C1

Y

X

2.27mm

Note:

The assignment of the pads P30 to P35 are not in order.

Chip size: 2.27 mm × 2.23 mm

PAD count: 88 pins

Minimum PAD pitch: 80µm

PAD aperture: 70µm×70µm

Chip thickness: 350µm

Voltage of the rear side of chip: V_SSlevel.

Figure 5 ML610Q407 Chip Layout & Dimension

9/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

ML610Q408 Chip Pin Layout & Dimension

V_SS

P20

P21

P22

P24

67

68

69

70

71

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

44

43

42

41

40

39

P00

P01

P02

P03

P04

P30

P31

P34

P32

P33

P35

P57

P56

P55

P54

P53

V_PP

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

38 SEG11

SEG10

SEG9

35 SEG8

SEG7

37

36

34

2.23mm

33 SEG6

32 SEG5

SEG4

31

30 SEG3

29 COM4/SEG2

COM3/SEG1

28

27 COM2/SEG0

26 COM1

25 COM0

24 C2

23 C1

Y

X

2.27mm

Note:

The assignment of the pads P30 to P35 are not in order.

Chip size: 2.27 mm × 2.23 mm

PAD count: 88 pins

Minimum PAD pitch: 80µm

PAD aperture: 70µm×70µm

Chip thickness: 350µm

Voltage of the rear side of chip: V_SSlevel.

Figure 6 ML610Q408 Chip Layout & Dimension

10/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

ML610Q409 Chip Pin Layout & Dimension

V_SS67

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

44

43

42

41

40

39

P20

P21

P22

P24

68

69

70

71

P00

P01

P02

P03

P04

P30

P31

P34

P32

P33

P35

P57

P56

P55

P54

P53

V_PP

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

38 SEG11

SEG10

SEG9

35 SEG8

SEG7

37

36

34

2.23mm

33 SEG6

32 SEG5

SEG4

31

30 SEG3

29 COM4/SEG2

COM3/SEG1

28

27 COM2/SEG0

26 COM1

25 COM0

24 C2

23 C1

Y

X

2.27mm

Note:

The assignment of the pads P30 to P35 are not in order.

Chip size: 2.27 mm × 2.23 mm

PAD count: 88 pins

Minimum PAD pitch: 80 µm

PAD aperture: 70 µm×70 µm

Chip thickness: 350 µm

Voltage of the rear side of chip: V_SSlevel.

Figure 7 ML610Q409 Chip Layout & Dimension

11/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

ML610Q407/ML610Q408/ML610Q409 Pad Coordinates

Table 1 ML610Q407/ML610Q408/ML610Q409 Pad Coordinates

Chip Center: X=0,Y=0

ML610Q407/8/9

PAD

No.

Pad

Name

PAD

No.

Pad

Name

X (µm)

Y (µm)

-1009

-840

-760

-680

-600

-520

-440

-360

-280

-200

-120

-40

40

120

200

280

360

440

520

600

680

760

840

1009

X (µm)

Y (µm)

1

P52

P51

-853

-773

-693

-613

-533

-453

-373

-293

-213

-133

-53

27

107

187

267

427

507

587

667

49

50

51

52

53

54

55

56

57

58

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

P67 ^(*1)

SEG32 ^(*2)(*3)

P66 ^(*1)

SEG33 ^(*2)(*3)

P65 ^(*1)

SEG34 ^(*2)(*3)

P64 ^(*1)

SEG35 ^(*2)(*3)

P63 ^(*1)(*2)

SEG36 ^(*3)

P62 ^(*1)(*2)

SEG37 ^(*3)

P61 ^(*1)(*2)

SEG38 ^(*3)

P60 ^(*1)(*2)

SEG39 ^(*3)

VSS

535

455

375

295

215

135

55

-25

-105

-185

1009

2

3

P50

4

P40

5

P41

6

P42

7

P43

8

P44

9

P45

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

P46

P47

59

60

61

62

63

64

65

66

-295

-375

-455

-535

-615

-695

-775

-885

1009

VDD

VSS

VDDL

XT0

XT1

RESET_N

TEST0

TEST1_N

VL1

747

827

VL2

VL3

907

C0

1029

855

C1

COM0

COM1

COM2/SEG0

COM3/SEG1

COM4/SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

-1029

--1029

-1029

850

770

690

610

530

430

350

270

190

110

P20

P21

P22

P24

P00

P01

P02

P03

P04

P30

30

-50

P31

P34

-130

-210

-290

-370

-450

-530

-610

-690

-770

-850

P32

P33

P35

P57

P56

P55

775

695

P54

P53

615

VPP

^(*1)ML610Q407 pad name, ^(*2)ML610Q408 pad name, ^(*3)ML610Q409 pad name

12/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

PIN LIST

Primary function

Function

Secondary function or Tertiary function

PIN PAD

No. No.

Secondary

/Tertiary

Pin name

I/O

Pin name I/O

Function

14,77 13,67

Vss

V_DD

Negative power supply pin

Positive power supply pin

Power supply pin for internal logic

(internally generated)

⎯

13

15

98

12

14

88

V_DDL

V_PP

⎯

Power supply pin for Flash ROM

Power supply pin for LCD bias

(internally generated or connected

to positive power supply pin)^(*2)

Power supply pin for LCD bias

(internally generated or connected

to positive power supply pin)^(*2)

Power supply pin for LCD bias

(internally generated)

Capacitor connection pin for LCD

bias generation

Capacitor connection pin for LCD

bias generation

22

23

20

21

V_L1

V_L2

⎯

24

27

28

22

23

24

V_L3

C1

C2

⎯

20

21

18

19

TEST0

I/O Test pin

⎯

TEST1_N

I

Test pin

19

17

18

17

15

16

RESET_N

XT0

I

O

Reset input pin

Low-speed clock oscillation pin

Input port,

External interrupt,

Capture 0 input

Input port,

External interrupt,

Capture 1 input

Input port,

External interrupt,

UART0 received data

Input port,

⎯

XT1

P00/EXI0/

CAP0

82

83

72

73

I

⎯

P01/EXI1/

CAP1

P02/EXI2/

RXD0

84

85

74

75

I

⎯

P03/EXI3

External interrupt

Input port,

P04/EXI4/

T02P0CK

Timer 0/Timer 2/PWM0 external

clock input

86

76

I

⎯

External interrupt

78

79

80

81

68

69

70

71

P20/LED0

P21/LED1

P22/LED2

P24/LED4

O

Output port

Secondary

LSCLK

OUTCLK

MD0

O

Low-speed clock output

High-speed clock output

Melody 0 output

PWM0

PWM0 output

RC type ADC0 oscillation input

RC type ADC0 reference

capacitor connection pin

RC type ADC0

87

88

77

78

P30

P31

I/O Input/output port

Secondary

IN0

I

CS0

O

89

79

P34

I/O Input/output port

Secondary

RCT0

O

resistor/capacitor sensor

connection pin

RC type ADC0 reference

resistor connection pin

RC type ADC0 measurement

resistor sensor connection pin

RC type ADC oscillation

monitor

90

91

92

80

81

82

P32

P33

P35

I/O Input/output port

Secondary

RS0

RT0

O

RCM

13/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

Primary function

Function

Secondary function or Tertiary function

PIN PAD

Secondary

/Tertiary

No.

Pin name

P40

I/O

Pin name I/O

Function

Secondary

Tertiary

Secondary

⎯

SIN0

⎯

I

⎯

5

4

I/O Input/output port

SSIO0 data input

⎯

SSIO0 synchronous clock

input/output

6

5

P41

Tertiary

SCK0

I/O

Secondary

Tertiary

Secondary

Tertiary

RXD0

SOUT0

TXD0

I

UART data input

SSIO0 data output

UART data output

PWM0 output

7

8

6

7

P42

P43

I/O Input/output port

O

PWM0

Input/output port,

I/O Timer 0/Timer 2/PWM0 external

clock input

RC type ADC1 oscillation input

SSIO0 data input

P44/

T02P0CK

Secondary

Tertiary

IN1

SIN0

CS1

I

9

8

9

RC type ADC1 reference

Input/output port,

Secondary

O

capacitor connection pin

SSIO0 synchronous clock

input/output

RC type ADC1 reference

resistor connection pin

SSIO0 data output

RC type ADC1 measurement

resistor sensor connection pin

Melody 0 output

10

11

P45/T13CK I/O Timer 1/Timer

input

3 external clock

Tertiary

SCK0

I/O

Secondary

Tertiary

RS1

SOUT0

RT1

O

10

P46

I/O Input/output port

12

4

11

3

P47

Secondary

Input/output port,

I/O

Secondary

Tertiary

Secondary

MD0

SIN1

⎯

O

I

⎯

P50/EXI8

External interrupt

SSIO1 data input

⎯

SSIO1 synchronous clock

input/output

Input/output port,

External interrupt

3

2

P51/EXI8

I/O

Tertiary

SCK1

I/O

Input/output port,

External interrupt

Input/output port,

External interrupt

Input/output port,

External interrupt

Secondary

Tertiary

⎯

SOUT1

⎯

O

⎯

2

1

P52/EXI8

P53/EXI8

P54/EXI8

I/O

SSIO1 data output

97

96

87

86

⎯

Secondary

Tertiary

Secondary

⎯

SIN1

⎯

I

⎯

SSIO1 data input

⎯

SSIO1 synchronous clock

input/output

Input/output port,

External interrupt

95

85

P55/EXI8

I/O

Tertiary

SCK1

I/O

Secondary

Tertiary

Input/output port,

External interrupt

Input/output port,

External interrupt

⎯

SOUT1

⎯

O

⎯

94

93

84

83

P56/EXI8

P57/EXI8

I/O

SSIO1 data output

⎯

14/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

Primary function

Function

Secondary function or Tertiary function

PIN PAD

Secondary/

No.

Pin name

I/O

Function

Tertiary

name

29

30

25

26

COM0

COM1

COM2/

SEG0

COM3/

SEG1

O

LCD common pin

⎯

31

32

33

27

28

29

O

LCD common/segment pin

⎯

COM4/

SEG2

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

52

53

54

55

56

57

58

59

60

61

62

63

64

65

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

O

LCD segment pin

Output port

LCD segment pin

Output port

LCD segment pin

Output port

LCD segment pin

Output port

LCD segment pin

Output port

LCD segment pin

Output port

LCD segment pin

Output port

LCD segment pin

Output port

LCD segment pin

⎯

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

P67^(*2)

66

67

68

69

70

71

72

73

59

60

61

62

63

64

65

66

SEG32^(*3)

P66^(*2)

SEG33^(*3)

P65^(*2)

SEG34^(*3)

P64^(*2)

SEG35^(*3)

P63^(*4)

SEG36^(*5)

P62^(*4)

SEG37^(*5)

P61^(*4)

SEG38^(*5)

P60^(*4)

SEG39^(*5)

(*¹) Internally generated, or connect to either positive power supply pin (V_DD) or power supply pin for internal logic

(V_DDL). For details, see “Chapter 22 LCD Drivers. In the user’s manual”

(*²) Pin for ML610Q407/ML610Q408.

(*³) Pin for ML610Q409.

(*⁴) Pin for ML610Q407.

(*⁵) Pin for ML610Q408/ML610Q409.

15/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

PIN DESCRIPTION

Primary/

Secondary/

Tertiary

Pin name

I/O

I

Description

Logic

System

Reset input pin. When this pin is set to a “L” level, system reset mode is

set and the internal section is initialized. When this pin is set to a “H” level

subsequently, program execution starts. A pull-up resistor is internally

connected.

RESET_N

—

Negative

Crystal connection pin for low-speed clock.

A 32.768 kHz crystal oscillator (see measuring circuit 1) is connected to

XT0

XT1

I

—

O

this pin. Capacitors CDL and CGL are connected across this pin and V_SS

Low-speed clock output pin. This pin is used as the secondary function of

the P20 pin.

High-speed clock output pin. This pin is used as the secondary function of

the P21 pin.

.

LSCLK

O

Secondary

OUTCLK

Secondary

—

General-purpose input port

General-purpose input port.

P00-P0４

I

Primary

Positive

Since these pins have secondary functions, the pins cannot be used as a

port when the secondary functions are used.

General-purpose output port

General-purpose output port.

P20-P22,P24

O

Primary

Positive

Since these pins have secondary functions, the pins cannot be used as a

port when the secondary functions are used.

General-purpose input/output port

General-purpose input/output port.

P30-P35

P40-P47

P50-P57

P60-P63

P64-P67

I/O

O

Primary

Positive

Since these pins have secondary functions, the pins cannot be used as a

port when the secondary functions are used.

General-purpose input/output port.

Since these pins have secondary functions, the pins cannot be used as a

port when the secondary functions are used.

General-purpose input/output port.

Since these pins have secondary functions, the pins cannot be used as a

port when the secondary functions are used.

General-purpose input/output port.

These pins are for the ML610Q407/ ML610Q408, but are not provided in

the ML610Q409.

General-purpose input/output port.

O

These pins are for the ML610Q407, but are not provided in the

ML610Q409.

16/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

Primary/

Secondary/

Tertiary

Pin name

UART

I/O

Description

Logic

UART data output pin. This pin is used as the secondary function of the

P43 pin.

UART data input pin. This pin is used as the secondary function of the

P42 or the primary function of the P02 pin.

TXD0

O

I

Secondary Positive

RXD0

Primary/

Positive

Secondary

Synchronous serial (SSIO)

Synchronous serial clock input/output pin. This pin is used as the tertiary

function of the P41 or P45 pin.

Synchronous serial data input pin. This pin is used as the tertiary function

of the P40 or P44 pin.

Synchronous serial data output pin. This pin is used as the tertiary

function of the P42 or P46 pin.

Synchronous serial clock input/output pin. This pin is used as the

secondary function of the P51 or P55 pin.

Synchronous serial data input pin. This pin is used as the secondary

function of the P50 or P54.

Synchronous serial data output pin. This pin is used as the secondary

function of the P52 or P56pin.

SCK0

SIN0

I/O

I

Tertiary

—

Positive

—

SOUT0

SCK1

SIN1

O

I/O

I

Tertiary

Secondary

Secondary Positive

SOUT1

O

PWM

PWM0 output pin. This pin is used as the tertiary function of the P43 or

P34 pin.

PWM0 external clock input pin. This pin is used as the primary function of

the P44 pin.

PWM0

O

I

Tertiary

Primary

Positive

—

T02P0CK

External interrupt

External maskable interrupt input pins. Interrupt enable and edge

selection can be performed for each bit by software. These pins are used

as the primary functions of the P00-P04 pins.

External maskable interrupt input pins. Interrupt enable and edge

selection can be performed for each bit by software. These pins are used

as the primary functions of the P50-P57 pins.

Positive/

negative

EXI0-4

I

Primary

Positive/

negative

EXI8

I

Capture

Capture trigger input pins. The value of the time base counter is captured

in the register synchronously with the interrupt edge selected by software.

These pins are used as the primary functions of the P00 pin(CAP0) and

P01 pin(CAP1).

Positive/

negative

Positive/

negative

CAP0

I

Primary

CAP1

Timer

External clock input pin used for Timer 0 and Timer 2. The clock for this

timer is selected by software. This pin is used as the primary function of

the P44 pin.

External clock input pin used both Timer 1 and Timer 3. The clock for this

timer is selected by software. This pin is used as the primary function of

the P45 pin.

T02P0CK

I

Primary

—

T13CK

Melody

MD0

Melody/Buzzer signal output pin. This pin is used as the secondary

function of the P22 pin and P50 pin.

Positive/

negative

O

Secondary

Primary

LED drive

LED0-2,4

Nch open drain output pins to drive LED.

Positive/

negative

17/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

Primary/

Secondary/

Tertiary

Pin name

I/O

Description

Logic

RC oscillation type A/D converter

Channel 0 oscillation input pin. This pin is used as the secondary function

of the P30 pin.

Channel 0 reference capacitor connection pin. This pin is used as the

secondary function of the P31 pin.

Resistor/capacitor sensor connection pin of Channel 0 for measurement.

This pin is used as the secondary function of the P33 pin.

This pin is used as the secondary function of the P32 pin which is the

reference resistor connection pin of Channel 0.

Resistor sensor connection pin of Channel 0 for measurement. This pin is

used as the secondary function of the P34 pin.

RC oscillation monitor pin. This pin is used as the secondary function of

the P35 pin.

Oscillation input pin of Channel 1. This pin is used as the secondary

function of the P44 pin.

Reference capacitor connection pin of Channel 1. This pin is used as the

secondary function of the P45 pin.

Reference resistor connection pin of Channel 1. This pin is used as the

secondary function of the P46 pin.

IN0

CS0

RCT0

RS0

RT0

RCM

IN1

I

Secondary

—

O

I

CS1

RS1

RT1

O

Resistor sensor connection pin for measurement of Channel 1. This pin is

used as the secondary function of the P47 pin.

LCD drive signal

Common output pins.

Segment output pins.

COM0-4

SEG0-31

O

—

O

Segment output pin. These pins are for the ML610Q408/ML610Q409, but

are not provided in the ML610Q407.

SEG32-35

—

Segment output pin. These pins are for the ML610Q409, but are not

provided in the ML610Q407/ML610Q408.

SEG36-39

O

—

LCD driver power supply

Power supply pins for LCD bias (internally generated or positive power

supply pin connected ). Depending on LCD Bias setting and V_DDvoltage

level, V_DDor V_DDLor capacitor is connected. For details of the connection

method, see user’s manual.

V_L1

V_L2

V_L3

—

Power supply pins for LCD bias (internally generated). Capacitors C12 is

connected between C1 and C2.

C1

C2

—

For testing

TEST

Input/output pin for testing. A pull-down resistor is internally connected.

Negative power supply pin.

I/O

—

Power supply

V_SS

—

Positive power supply pin for I/O, internal regulator, battery low detector,

and power-on reset.

V_DD

Positive power supply pin (internally generated) for internal logic.

Capacitor CL (see Appendix C measuring circuit 1) is connected between

V_DDL

—

this pin and V_SS

.

Power supply pin for programming Flash ROM. A pull-down resistor is

internally connected.

V_PP

18/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

TERMINATION OF UNUSED PINS

Table 2 shows methods of terminating the unused pins.

Table 2 Termination of Unused Pins

Recommended pin termination

V_PP

Open

V_DDor V_SS

Open

V_L1, V_L2, V_L3

C1, C2

RESET_N

TEST0

TEST1_N

P00 to P04

P20 to P22, P24

P30 to P35

P40 to P47

P50 to P57

P60 to P67

COM0 to 4

SEG0 to 39

Note:

It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or

the output mode since the supply current may become excessively large if the pins are left open in the high impedance input

setting.

19/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

(V_SS= 0V)

Parameter

Power supply voltage 1

Power supply voltage 2

Power supply voltage 3

Power supply voltage 4

Power supply voltage 5

Power supply voltage 6

Input voltage

Symbol

Condition

Ta = 25°C

Port3–6, Ta = 25°C

Port2, Ta = 25°C

Ta = 25°C

⎯

Rating

−0.3 to +4.6

−0.3 to +9.5

−0.3 to +3.6

−0.3 to +2.0

−0.3 to +4.0

−0.3 to +6.0

−0.3 to V_DD+0.3

−12 to +11

−12 to +20

0.9

Unit

V

V_DD

V_PP

V

V_DDL

V_L1

V

V_L2

V

V_L3

V

V_IN

V

Output voltage

V_OUT

I_OUT1

I_OUT2

PD

V

Output current 1

mA

W

°C

Output current 2

Power dissipation

Storage temperature

T_STG

−55 to +150

RECOMMENDED OPERATING CONDITIONS

(V_SS= 0V)

Unit

Parameter

Symbol

T_OP

Condition

Range

non-P version

P version

−20 to +70

−40 to +85

1.25 to 3.6

Operating temperature

°C

f_OP= 30k to 625kHz

Operating voltage

V_DD

V

f

_OP= 30k to 2.5MHz

V_DD= 1.25 to 3.6V

V_DD= 1.8 to 3.6V

1.8 to 3.6

30k to 625k

30k to 2.5M

Operating frequency (CPU)

f_OP

C_L

Hz

µF

Capacitor externally connected to

V_DDLpin

⎯

0.47±30%

0.1±30%

0.47±30%

Capacitors externally connected to

C_{a, b, c}

C₁₂

V_{L1, 2, 3}pins

Capacitors externally connected

across C1 and C2 pins

CLOCK GENERATION CIRCUIT OPERATING CONDITIONS

(V_SS= 0V)

Unit

Rating

Parameter

Symbol

f_XTL

Condition

Min.

Typ.

Max.

Low-speed crystal oscillation

frequency

⎯

32.768k

⎯

Hz

Recommended equivalent series

resistance value of low-speed

crystal oscillation

R_L

⎯

40k

Ω

C_L=6pF of crystal

oscillation

⎯

12

18

24

⎯

Low-speed crystal oscillation

external capacitor

C_L=9pF of crystal

oscillation

C_DL/C_GL

pF

C_L=12pF of

crystal oscillation

20/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

OPERATING CONDITIONS OF FLASH ROM

(V_SS= 0V)

Parameter

Symbol

T_OP

Condition

At write/erase

At write/erase^*1

⎯

Range

0 to +40

2.75 to 3.6

2.5 to 2.75

7.7 to 8.3

80

Unit

Operating temperature

°C

V_DD

Operating voltage

V_DDL

V_PP

C_EP

V

erase/program cycles

Data retention

cycles

years

Y_DR

⎯

10

^*1: Those voltages must be supplied to V_DDLpin and V_PPpin when programming and eraseing Flash ROM.

V_PPpin has an internal pulldown resister.

DC CHARACTERISTICS (1/5)

(V_DD= 1.25 to 3.6V, V_SS= 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified)

Rating

Typ.

Measuring

circuit

Parameter

Symbol

Condition

Unit

Min.

Typ.

−10%

Typ.

−25%

Typ.

−10%

Typ.

Max.

Typ.

+10%

Typ.

+25%

Typ.

+10%

Typ.

Ta = 25°C

500

2.0

V_DD= 1.25

kHz

to 3.6V

3

*

500kHz/2MHz RC oscillation

frequency

f_RC

Ta = 25°C

V

_DD= 1.80

MHz

to 3.6V

3

*

2.0

0.6

⎯

−25%

+25%

Low-speed crystal oscillation

start time*²

500kHz/2MHz RC oscillation

start time

T_XTL

T_RC

⎯

2

s

1

0.3

µs

ms

Low-speed oscillation stop

T_STOP

P_RST

⎯

12

200

⎯

16.4

⎯

41

⎯

detect time^*1

Reset pulse width

Reset noise elimination

pulse width

µs

P_NRST

⎯

0.3

Power-on reset activation

power rise time

T_POR

⎯

10

ms

*¹: When low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is

reset to shift to system reset mode.

*²: 32.768KHz Crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (C_GL=C_DL=6pF).

*³: Recommended operating temperature (Ta = −20 to +70°C, Ta = −40 to +85°C for P version)

VIL1

RESET_N

P_RST

Reset pulse width (P_RST

)

0.9xV_DD

VDD

0.1xV_DD

T_POR

Power-on reset activation power rise time (T_POR

)

21/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

DC CHARACTERISTICS (2/5)

(V_DD= 1.25 to 3.6V, V_SS= 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified)

Rating

Typ.

1.2

Measuring

circuit

Parameter

Symbol

Condition

Unit

Min.

1.1

Max.

1.3

f_OP= 30k to 625kHz

V_DDLvoltage

V_DDL

f

_OP= 30k to 2.5MHz

1.35

1.5

1.65

V_DDLtemperature

deviation *¹

1

∆V_DDL

V_DD= 3.0V

⎯

-1

⎯

mV/°C

V_DDLvoltage

⎯

5

20

mV/V

dependency *¹

*¹:V_DDLcan not exceed V_DDlevel. The maximum V_DDLbecomes V_DDlevel when the V_DDLcalculated by the temperature

deviation and voltage dependency is going to exceed the V_DDlevel.

22/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

DC CHARACTERISTICS (3/5)

(V_DD= 3.0V, V_SS= 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version)

Rating

Typ.

Measuring

circuit

Parameter

Symbol

Condition

Unit

Min.

Max.

0.8

CPU: In STOP state.

Ta= 25°C

⎯

0.4

Low-speed/high-speed

RC500kHz/2MHz oscillation:

stopped.

Supply current 1

IDD1

µA

5

*

⎯

8

CPU: In HALT state (LTBC and WDT

are Operating).*³*⁴

Ta= 25°C

⎯

0.9

⎯

5

1.8

9

Supply current 2

Supply current 3

High-speed 500kHz/2MHz

oscillation: Stopped.

IDD2

µA

5

*

LCD and BIAS circuits: Operating. *⁶

CPU: In 32.768kHz operating

state.*¹*³

Ta= 25°C

8

1

High-speed 500kHz/2MHz

oscillation: Stopped.

IDD3

µA

5

*

⎯

15

LCD and BIAS circuits: Operating. *²

Ta= 25°C

⎯

70

100

120

Supply current

4-1

CPU: In RC 500kHz operating state.

LCD and BIAS circuits: Operating. *²

IDD4-1

IDD4-2

5

*

⎯

Ta= 25°C

⎯

280

350

400

Supply current

4-2

CPU: In RC 2MHz operating state.

LCD and BIAS circuits: Operating. *²

5

*

⎯

*¹: When the CPU operating rate is 100% (No HALT state).

*²: All SEGs: off waveform, No LCD panel load, 1/3 bias, 1/3 duty, Frame frequency: Approx. 64 Hz, Bias voltage multiplying

clock: 1/128 LSCLK (256Hz)

*³: 32.768KHz Crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (C_GL=C_DL=6pF)

*⁴: Significant bits of BLKCON0~BLKCON4 registers except DLCD bit on BLKCON4 are all “1”.

*⁵: Recommended operating temperature (Ta = −20 to +70°C, Ta = −40 to +85°C for P version)

*⁶: LCD Stop mode, 1/3 bias, Bias voltage multiplying clock: 1/128 LSCLK (256Hz)

23/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

DC CHARACTERISTICS (4/5)

(V_DD= 1.25 to 3.6V, V_SS= 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified)

Rating

Measuring

circuit

Parameter

Symbol

Condition

Unit

Min.

Typ.

Max.

Output voltage 1

(P20–P22,P24/

2

selected)

(P30–P36)

V_DD

−0.5

V_DD

−0.3

⎯

IOH1 = −0.5mA, V_DD= 1.8 to 3.6V

⎯

^ndfunction is

VOH1

IOH1 = -0.03mA, V_DD= 1.25 to 3.6V

IOL1 = +0.5mA, V_DD= 1.8 to 3.6V

⎯

0.5

(P40–P47)

(P50–P57)

VOL1

VOL2

(P60-P63) ^{*1 *2}

(P64-P67) ^*1

Output voltage 2

(P20–P22,P24/

2^ndfunction is Not

selected)

IOL1 = +0.1mA, V_DD= 1.25 to 3.6V

⎯

0.3

IOL2 = +5mA, V_DD= 1.8 to 3.6V

⎯

0.5

V

2

V_L3

−0.2

VOH3

VOML3

VOML3S

VOLM3

IOH4 = −0.05mA, VL1=1.2V

IOMH4 = +0.05mA, VL1=1.2V

IOM4S = −0.05mA, VL1=1.2V

IOML4 = +0.05mA, VL1=1.2V

⎯

V_L2

+0.2

Output voltage 3

(COM0–4)

⎯

(SEG0–31)^*1

(SEG0–35)^*2

(SEG0–39)^*3

V_L2

−0.2

⎯

V_L1

+0.2

⎯

V_L1

−0.2

VOLM3S

VOL3

IOML4S = −0.05mA, VL1=1.2V

⎯

IOL4 = +0.05mA, VL1=1.2V

⎯

0.2

Output leakage

(P20–P22, P24)

(P30–P35)

IOOH

VOH = V_DD(in high-impedance state)

⎯

1

(P40–P47)

µA

3

(P50–P57)

IOOL

VOL = V_SS(in high-impedance state)

−1

⎯

(P60-P63) ^{*1 *2}

(P64-P67) ^*1

Input current 1

(RESET_N,

TEST1_N)

IIH1

IIL1

VIH1 = V_DD

VIL1 = V_SS

0

⎯

1

-600

-300

-2

Input current 2

(TEST0)

IIH2

IIL2

VIH1 = V_DD

VIL1 = V_ss

2

300

⎯

600

-1

⎯

VIH3 = V_DD,V_DD= 1.8 to 3.6V

(when pulled-down)

2

30

200

IIH3

IIL3

VIH3 = V_DD,V_DD= 1.25 to 3.6V

(when pulled-down)

µA

4

Input current 3

(P00-P04)

(P30-P35)

(P40-P47)

(P50-P57)

VIL3 = V_SS, V_DD= 1.8 to 3.6V

(when pulled-up)

-200

-30

-2

VIL3 = V_SS, V_DD= 1.25 to 3.6V

(when pulled-up)

-0.01

IIH3Z

IIL3Z

VIH3 = V_DD(in high-impedance state)

VIL3 = V_SS(in high-impedance state)

⎯

1

−1

⎯

*¹: pins for ML610Q407

*²: pins for ML610Q408

*³: pins for ML610Q409

24/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

DC CHARACTERISTICS (5/5))

(V_DD= 1.25 to 3.6V, V_SS= 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified)

Rating

Measuring

circuit

Parameter

Symbol

Condition

Unit

Min.

Typ.

Max.

V_DD

Input voltage 1

(RESET_N)

(TEST0,

0.7

×V_DD

VIH1

⎯

TEST1_N)

(P00–P04)

(P30–P35)

(P40–P47)

(P50–P57)

V

5

0.3

×V_DD

0.2

V_DD= 1.8 to 3.6V

V_DD= 1.25 to 3.6V

0

⎯

VIL1

CIN

×V_DD

Input pin

capacitance

(P00–P04)

(P30–P35)

(P40–P47)

(P50–P57)

f = 10kHz

V_rms= 50mV

Ta = 25°C

⎯

5

pF

⎯

25/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

MEASURING CIRCUITS

MEASURING CIRCUIT 1

C_GL

XT0

32.768kHz crystal

C_DL

XT1

C2

C1

C₁₂

V_DD

V_DDL

V_L2V_L3

V_SS

V_L1

C_V:

C_L:

C_a,C_b,C_c:

C₁₂:

1µF

A

0.47µF

0.1µF

0.47µF

C_V

C_L

C_c

C_a

32.768kHz crystal: DT-26 (Load capacitance 6pF)

(made by KDS:DAISHINKU CORP.)

C_GL, C_DL

:

6pF

MEASURING CIRCUIT 2

(*2)

VIH

V

(*1)

VIL

V_DDV_DDL

V_L1V_L2

V_SS

V_L3

(*1) Input logic circuit to determine the specified measuring conditions.

(*2) Measured at the specified output pins.

26/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

MEASURING CIRCUIT 3

(*2)

VIH

A

RS1

VIL

V_DDV_DDL

V_L1V_L2

V_SS

V_L3

*1: Input logic circuit to determine the specified measuring conditions.

*2: Measured at the specified output pins.

MEASURING CIRCUIT 4

(*3)

A

V_DDV_DDL

V_L1V_L2V_L3

V_SS

*3: Measured at the specified output pins.

MEASURING CIRCUIT 5

VIH

(*1)

VIL

V_DDV_DDL

V_L1V_L2

V_SS

V_L3

*1: Input logic circuit to determine the specified measuring conditions.

27/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

AC CHARACTERISTICS (External Interrupt)

(V_DD= 1.25 to 3.6V, V_SS= 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified)

Rating

Parameter

Symbol

T_NUL

Condition

Unit

Min.

76.8

Typ.

Max.

Interrupt: Enabled (MIE = 1),

CPU: NOP operation

External interrupt disable period

⎯

106.8

µs

System clock: 32.768kHz

P00–P04

(Rising-edge interrupt)

t_NUL

P00–P04

(Falling-edge interrupt)

t_NUL

P00–P04

(Both-edge interrupt)

t_NUL

AC CHARACTERISTICS (Serial Port)

(V_DD= 1.25 to 3.6V, V_SS= 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified)

Rating

Parameter

Transmit baud rate

Receive baud rate

Symbol

Condition

Unit

Min.

Typ.

Max.

t_TBRT

t_RBRT

⎯

BRT*¹

⎯

s

BRT*¹

−3%

BRT*¹

+3%

BRT*¹

*1: Baud rate period (including the error of the clock frequency selected) set with the serial port baud rate register

(SIOBRTL,H) and the serial port mode register 0 (SIOMOD0).

t_TBRT

TXD0*

t_RBRT

RXD0*

*: Indicates the secondary function of the port.

28/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

AC CHARACTERISTICS (Synchronous Serial Port)

(V_DD= 1.25 to 3.6V, V_SS= 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified)

Rating

Parameter

Symbol

Condition

Unit

Min.

10

Typ.

Max.

When RC oscillation is 500kHz

*²(V_DD= 1.25 to 3.6V)

⎯

SCLKn input cycle

(slave mode)

t_SCYC

t_SW

µs

s

When RC oscillation is 2MHz

*³(V_DD= 1.8 to 3.6V)

2

⎯

4

⎯

SCLKn*¹

⎯

SCLKn output cycle

(master mode)

⎯

When RC oscillation is 500kHz

*²(V_DD= 1.25 to 3.6V)

SCLKn input pulse width

µs

s

(slave mode)

When RC oscillation is 2MHz

*³(V_DD= 1.8 to 3.6V)

04

⎯

SCLKn output pulse width

(master mode)

SCLKn*¹

×0.4

SCLKn*¹

×0.5

SCLKn*¹

×0.6

t_SW

⎯

When RC oscillation is 500kHz

*²(V_DD= 1.25 to 3.6V)

output load 10pF

⎯

500

240

500

240

SOUTn output delay time

(slave mode)

t_SD

ns

When RC oscillation is 2MHz

*³(V_DD= 1.8 to 3.6V)

output load 10pF

When RC oscillation is 500kHz

*²(V_DD= 1.25 to 3.6V)

output load 10pF

SOUTn output delay time

(master mode)

t_SD

When RC oscillation is 2MHz

*³(V_DD= 1.8 to 3.6V)

output load 10pF

SINn input setup time

(slave mode)

t_SS

⎯

80

⎯

ns

When RC oscillation is 500kHz

*²(V_DD= 1.25 to 3.6V)

500

SINn input setup time

(master mode)

t_SS

When RC oscillation is 2MHz

*³(V_DD= 1.8 to 3.6V)

240

300

80

⎯

When RC oscillation is 500kHz

*²(V_DD= 1.25 to 3.6V)

SINn input hold time

t_SH

ns

When RC oscillation is 2MHz

*³(V_DD= 1.8 to 3.6V)

n= 0,1

*1: Clock period selected with SnCK3–0 of the serial port n mode register (SIOnMOD1)

*²: When 500kHz RC oscillation is selected by OSCM2 of the frequency control register (FCON0)

*³: When 2MHz RC oscillation is selected by OSCM2 of the frequency control register (FCON0)

t_SCYC

t_SW

SCLKn*

SOUTn*

SINn*

t_SD

t_SS

t_SH

*: Indicates the secondary function of the port (n= 0,1)

29/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

AC CHARACTERISTICS (RC Oscillation A/D Converter)

Condition for V_DD=1.8 to 3.6V

(V_DD=1.8 to 3.6V, V_SS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)

Rating

Typ.

Parameter

Symbol

Condition

Unit

Min.

1

Max.

RS0,RS1,RT0,

RT0-1,RT1

f_OSC1

Oscillation resistor

―

CS0, CT0, CS1≥740pF

kΩ

457.3

53.48

5.43

7.972

0.981

0.099

525.2

58.18

5.89

9.028

1

575.1

62.43

6.32

9.782

1.019

0.104

kHz

⎯

Resistor for oscillation=1kΩ

Resistor for oscillation=10kΩ

Resistor for oscillation=100kΩ

RT0, RT0-1, RT1=1kΩ

RT0, RT0-1, RT1=10kΩ

RT0, RT0-1, RT1=100kΩ

Oscillation frequency

V_DD= 3.0V

f_OSC2

f_OSC3

Kf1

Kf2

Kf3

RS to RT oscillation

frequency ratio ^*1

V_DD= 3.0V

0.101

*¹: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the

same conditions.

f

_OSCX(RT0-CS0 oscillation)

f_OSCX(RT0-1-CS0 oscillation)

f_OSCX(RS0-CS0 oscillation)

f_OSCX(RT1-CS1 oscillation)

f_OSCX(RS1-CS1 oscillation)

Kfx =

f_OSCX(RS0-CS0 oscillation)

( x = 1, 2, 3 )

,

CVR0

CVR1

RT0, RT0-1, RT1: 1kΩ/10kΩ/100kΩ

RS0, RS1: 10kΩ

CS0, CT0, CS1: 560pF

CVR0, CVR1: 820pF

IN0 CS0

IN1 CS1 RS1 RT1

RCM

RCT0 RS0 RT0

VIH

Frequency measurement (f_OSCX

)

(Note 1)

VIL

V_DDV_DDL

V_SS

C_V

C_L

*1: Input logic circuit to determine the

specified measuring conditions.

30/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

Condition for V_DD=1.25 to 3.6V

(V_DD=1.25 to 3.6V, V_SS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)

Rating

Typ.

Parameter

Symbol

Condition

Unit

Min.

1

Max.

RS0,RS1,RT0,

RT0-1,RT1

f_OSC1

Oscillation resistor

―

CS0, CT0, CS1≥740pF

kΩ

81.93

35.32

5.22

93.16

38.75

5.65

2.381

1

0.147

94.58

38.87

5.622

2.432

1

101.2

41.48

6.03

kHz

⎯

kHz

⎯

Resistor for oscillation=6kΩ

Resistor for oscillation=15kΩ

Resistor for oscillation=105kΩ

RT0, RT0-1, RT1=1kΩ

Oscillation frequency

V_DD= 1.5V

f_OSC2

f_OSC3

Kf1

Kf2

Kf3

f_OSC1

f_OSC2

f_OSC3

Kf1

Kf2

Kf3

2.139

0.973

0.142

85.28

35.72

5.189

2.227

0.982

0.141

2.632

1.028

0.152

103.3

41.78

6.012

2.626

1.018

0.149

RS to RT oscillation

frequency ratio ^*1

V_DD= 1.5V

RT0, RT0-1, RT1=10kΩ

RT0, RT0-1, RT1=100kΩ

Resistor for oscillation=6kΩ

Resistor for oscillation=15kΩ

Resistor for oscillation=105kΩ

RT0, RT0-1, RT1=1kΩ

RT0, RT0-1, RT1=10kΩ

RT0, RT0-1, RT1=100kΩ

Oscillation frequency

V_DD= 3.0V

RS to RT oscillation

frequency ratio ^*1

V_DD= 3.0V

0.145

*¹: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the

same conditions.

f

_OSCX(RT0-CS0 oscillation)

f_OSCX(RT0-1-CS0 oscillation)

f_OSCX(RS0-CS0 oscillation)

f_OSCX(RT1-CS1 oscillation)

f_OSCX(RS1-CS1 oscillation)

Kfx =

f

_OSCX(RS0-CS0 oscillation)

( x = 1, 2, 3 )

,

CVR0

CVR1

RT0, RT0-1, RT1: 1kΩ/10kΩ/100kΩ

RA0, RA0-1, RA1: 5kΩ

RS0, RS1: 15kΩ

CS0, CT0, CS1: 560pF

CVR0, CVR1: 820pF

IN0 CS0 RCT0 RS0

IN1 CS1 RS1 RT1

RT0

VIH

RCM

Frequency measurement (f_OSCX)

(Note 1)

VIL

V_DDV_DDL

V_SS

C_V

C_L

*1: Input logic circuit to determine the

specified measuring conditions.

Note:

- Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors

and IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wire between IN0/IN1 and RS0/RS1. The coupling

capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise

around the node.

- When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to

the signal.

- Please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. Wiring to reserved

components may affect to the A/D conversion operation by noise the components itself may have.

31/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

Package Dimensions

(Unit : mm)

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,

before you perform reflow mounting, contact our responsible sales person for the product name, package name, pin number,

package code and desired mounting conditions (reflow method, temperature and times).

32/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

Revision History

Page

Document No.

Date

Description

Previous Current

Edition

FEDL610Q409-01

FEDL610Q409-02

Nov.7,2010

Jul.12,2011

–

2

–

2

Formally edition 1

Add comment of uart half duplex communication

Add “D” version in the supply form

Change header and footer

3

All

2

All

2

Add “A” version in the supply form

2

3

2

4

Changed the description of LCD 1/2 bias supported version

FEDL610Q409-03

Jan.24,2014

Change from "Shipment" to " Product name – Supported

Function "

3

4

Correct minimum time of Power-on reset generated power

rise time

20

21

FEDL610Q409-04

FEDL610Q409-05

Mar.20,2014

May.23,2014

4

-

4

Correct the “Product name – Supported Function”

Add Clock Generation Circuit Operating Conditions

Change "RESET" to " Reset pulse width (P_RST)" and "

Power-on reset activation power rise time (T_POR)".

Correct minimum time of Power-on reset generated power

rise time

20

21

Correct the C_GL’s value and the C_DL’s value of

CHARACTERISTICS (1/5)’s note No.2

DC

33/34

FEDL610Q409-05

ML610Q407/ML610Q408/ML610Q409

NOTES

No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor

Co., Ltd.

The content specified herein is subject to change for improvement without notice.

Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage

and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass

production.

Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any

damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall bear no responsibility for

such damage.

The technical information specified herein is intended only to show the typical functions of and examples of application

circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any license to use or exercise

intellectual property or other rights held by LAPIS Semiconductor and other parties. LAPIS Semiconductor shall bear no

responsibility whatsoever for any dispute arising from the use of such technical information.

The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as

audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement

devices).

The Products specified in this document are not designed to be radiation tolerant.

While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a Product may fail

or malfunction for a variety of reasons.

Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of

physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire

control and fail-safe designs. LAPIS Semiconductor shall bear no responsibility whatsoever for your use of any Product

outside of the prescribed scope or not in accordance with the instruction manual.

The Products are not designed or manufactured to be used with any equipment, device or system which requires an

extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a

risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor

controller, fuel-controller or other safety device). LAPIS Semiconductor shall bear no responsibility in any way for use of

any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please

contact a ROHM sales representative before purchasing.

If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign

Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.

34/34


型号：	ML610Q408
厂家：	LAPIS Semiconductor Co., Ltd.
描述：	8-bit Microcontroller with a Built-in LCD driver CD 微控制器
文件：	总34页 (文件大小：426K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ML610Q408 [LAPIS]

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