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ML610Q411 [LAPIS]

8-bit Microcontroller with a Built-in LCD driver;
ML610Q411
型号： ML610Q411
厂家： LAPIS Semiconductor Co., Ltd.    LAPIS Semiconductor Co., Ltd.
描述：

8-bit Microcontroller with a Built-in LCD driver

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FEDL610Q411-04  
Issue Date: July.13, 2015  
ML610Q411/Q412  
8-bit Microcontroller with a Built-in LCD driver  
GENERAL DESCRIPTION  
ML610Q411/Q412 is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous  
serial port, UART, I2C bus interface (master), buzzer driver, battery level detect circuit, RC oscillation type A/D converter,  
12-bit successive approximation type A/D converter, and LCD driver, are incorporated around LAPIS Semiconductor -original  
8-bit CPU nX-U8/100.  
The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture  
parallel procesing. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption operation  
(read operation) equivalent to mask ROM and is most suitable for battery-driven applications. The on-chip debug function that  
is installed enables program debugging and programming.  
M L610Q411/Q412 has a dual clock, runs at 32.768kHz crystal oscillation clock or a built-in 500kHz RC oscillation clock, used  
for a system requires the accurate clock or timer.  
FEATURES  
• CPU  
− 8-bit RISC CPU (CPU name: nX-U8/100)  
− Instruction system: 16-bit instructions  
− Instruction set:  
Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit  
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic  
shift, and so on  
− On-Chip debug function  
− Minimum instruction execution time  
30.5 µs (@32.768 kHz system clock)  
2µs (@500kHz system clock)  
• Internal memory  
− Internal 16KBbyte Flash ROM (8K×16 bits) (including unusable 1KByte TEST area)  
− Internal 1KByte Data RAM (1024×8 bits)  
• Interrupt controller  
− 2 non-maskable interrupt sources  
Internal source: 1 (Watch dog timer)  
External source: 1 (NMI)  
− 19 maskable interrupt sources  
Internal sources: 15 (SSIO, SA-A/D converter, I2C, Timer0, Timer1, Timer2, Timer3, 1kHz timer, UART, RC-A/D  
converter, PWM, TBC128Hz, TBC32Hz, TBC16Hz, TBC2Hz)  
External sources: 4 (P00, P01, P02, P03)  
• Time base counter  
− Low-speed time base counter ×1 channel  
Frequency compensation (Compensation range: Approx. −488ppm to +488ppm. Compensation accuracy: Approx.  
0.48ppm)  
− High-speed time base counter ×1 channel  
1/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
•
Watchdog timer  
− Non-maskable interrupt and reset  
− Free running  
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)  
• Timers  
− 8 bits × 4 channels (Timer0-3: 16-bit x 2 configuration available by using Timer0-1 or Timer2-3)  
− Clock frequency measurement mode (in one channel of 16-bit configuration using Timer2-3)  
• 1 kHz timer  
− 10 Hz/1 Hz interrupt function  
• Capture  
− Time base capture × 2 channels (4096 Hz to 32 Hz)  
• PWM  
− Resolution 16 bits × 1 channel  
• Synchronous serial port  
− Master/slave selectable  
− LSB first/MSB first selectable  
− 8-bit length/16-bit length selectable  
• UART  
− TXD/RXD × 1 channel  
− Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits  
− Positive logic/negative logic selectable  
− Built-in baud rate generator  
• I2C bus interface  
− Master function only  
− Standard mode (50kbps)  
• Buzzer driver  
− 4 output modes, 8 frequencies, 16 duty levels  
• RC oscillation type A/D converter  
− 24-bit counter  
− Time division × 2 channels  
• Successive approximation type A/D converter  
− 12-bit A/D converter  
− Input × 2 channels  
− Conversion time: 46us/1ch@500kHz  
• General-purpose ports  
− Non-maskable interrupt input port × 1 channel  
− Input-only port × 6 channels (including secondary functions)  
− Output-only port × 3 channels (including secondary functions)  
− Input/output port  
ML610Q411: 22 channels (including secondary functions)  
ML610Q412: 14 channels (including secondary functions)  
• LCD driver  
− The number of segments  
ML610Q411: 144 dots max. (36 seg × 4 com)  
ML610Q412: 176 dots max. (44 seg × 4 com)  
− 1/1 to 1/4 duty  
− 1/3 bias (built-in bias generation circuit)  
2/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
− Frame frequency selecable (approx. 64 Hz, 73 Hz, 85 Hz, and 102 Hz)  
− Bias voltage multiplying clock selectable (8 types)  
− Contrast adjustment (32 steps)  
− LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable  
• Reset  
− Reset through the RESET_N pin  
− Power-on reset generation when powered on  
− Reset when oscillation stop of the low-speed clock is detected  
− Reset by the watchdog timer (WDT) overflow  
• Battery Level Detector  
− Threshold voltages:  
− Accuracy:  
One of 16 levels  
±2% (Typ.)  
• Clock  
− Low-speed clock: (This LSI can not guarantee the operation withoug low-speed crystal oscillation clock)  
Crystal oscillation (32.768 kHz)  
− High-speed clock:  
Built-in RC oscillation (500 kHz)  
External clock (500kH or less)  
− High-speed Clock gear: 1/2(250kHz), 1/4(125kHz), 1/8(62.5kHz: default)  
− Selection of high-speed clock mode by software:  
Built-in RC oscillation, External clock  
• Power management  
− HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).  
− STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are  
stopped.)  
− High-speed Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8 of the  
oscillation clock)  
− Block Control Function: Resets and completely turns circuits of unused peripherals off.  
• Guaranteed operating range  
− Operating temperature: −20°C to +70°C (P version: −40°C to +85°C)  
− Operating voltage: VDD = 1.1V to 3.6V, AVDD = 2.2V to 3.6V  
3/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
• Product name – Supported Function  
The line-up of the ML610Q411 and the ML610Q412 is below.  
Low-speed oscillation  
stop detect reset  
Operating  
temperature  
- Chip (Die) -  
ROM type  
Product availability  
ML610Q411-xxxWA  
ML610Q411P-xxxWA  
Flash ROM  
Flash ROM  
Yes  
Yes  
-20°C to +70°C  
-40°C to +85°C  
Yes  
Yes  
Selectable to disable  
ML610Q411PA-xxxWA  
Flash ROM  
-40°C to +85°C  
Yes  
always  
ML610Q412-xxxWA  
ML610Q412P-xxxWA  
Flash ROM  
Flash ROM  
Yes  
-20°C to +70°C  
-40°C to +85°C  
Yes  
Yes  
Yes  
-120-pin plastic  
TQFP -  
Low-speed oscillation  
stop detect reset  
Operating  
temperature  
ROM type  
Product availability  
ML610Q411-xxxTB  
ML610Q411P-xxxTB  
Flash ROM  
Flash ROM  
Yes  
Yes  
-20°C to +70°C  
-40°C to +85°C  
Yes  
Yes  
Selectable to disable  
always  
ML610Q411PA-xxxTB  
Flash ROM  
-40°C to +85°C  
Yes  
ML610Q412-xxxTB  
ML610Q412P-xxxTB  
Flash ROM  
Flash ROM  
Yes  
Yes  
-20°C to +70°C  
-40°C to +85°C  
Yes  
Yes  
xxx：ROM code number (xxx of the blank product is NNN)  
Q：Flash ROM version  
P：Wide range temperature version  
A: Low-speed clock oscillation stop detection reset is selectable to disable always (See chapter3 and chapter4 in the  
user’s manual for more detail).  
WA：Chip (Die)  
TB：TQFP  
4/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
BLOCK DIAGRAM  
ML610Q411 Block Diagram  
Figure 1 show the block diagram of the ML610Q411.  
"*" indicates the secondary function of each port.  
CPU (nX-U8/100)  
EPSW1～3  
ELR1～3  
ECSR1～3  
DSR/CSR  
PC  
GREG  
0～15  
PSW  
LR  
EA  
SP  
Timing  
Controller  
ALU  
Program  
Memory  
(Flash)  
BUS  
Controller  
VPP  
Instruction  
Decoder  
Instruction  
Register  
On-Chip  
ICE  
16Kbyte  
Data-bus  
VDD  
VSS  
INT  
1
SCK0*  
SIN0*  
SSIO  
UART  
I2C  
RAM  
1024byte  
RESET_N  
TEST  
SOUT0*  
RESET &  
TEST  
INT  
1
Interrupt  
Controller  
RXD0*  
TXD0*  
XT0  
XT1  
INT  
1
INT  
1
OSC0*  
OSC  
WDT  
TBC  
SDA*  
SCL*  
LSCLK*  
OUTCLK*  
INT  
4
INT  
1
VDDL  
VDDX  
Power  
PWM  
INT  
1
PWM0*  
BZ0*  
1kHzTC  
INT  
1
INT  
1
IN0*  
CS0*  
RCT0*  
RS0*  
RT0*  
RCM*  
IN1*  
CS1*  
RS1*  
RT1*  
Buzzer  
Capture  
×2  
INT  
5
RC-ADC  
×2  
INT  
4
NMI  
P00 to P03  
P10 to P11  
8bit Timer  
×4  
GPIO  
P20 to P22  
P30 to P35  
P40 to P47  
PA0 to PA7  
AVDD  
AVSS  
INT  
1
VREF  
12bit-ADC  
BLD  
COM0 to COM3  
SEG0 to SEG35  
AIN0, AIN1  
LCD  
Driver  
Display  
register  
144bit  
VL1, VL2, VL3  
C1, C2  
LCD  
BIAS  
Figure 1 ML610Q411 Block Diagram  
5/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
ML610Q412 Block Diagram  
Figure 2 show the block diagram of the ML610Q412.  
"*" indicates the secondary function of each port.  
CPU (nX-U8/100)  
EPSW1～3  
ELR1～3  
LR  
ECSR1～3  
DSR/CSR  
PC  
GREG  
0～15  
PSW  
EA  
Timing  
Controller  
ALU  
SP  
Program  
Memory  
(Flash)  
BUS  
Controller  
VPP  
Instruction  
Decoder  
Instruction  
Register  
On-Chip  
ICE  
16Kbyte  
Data-bus  
VDD  
VSS  
INT  
1
SCK0*  
SIN0*  
SSIO  
UART  
I2C  
RAM  
1024byte  
RESET_N  
TEST  
SOUT0*  
RESET &  
TEST  
INT  
1
Interrupt  
Controller  
RXD0*  
TXD0*  
XT0  
XT1  
INT  
1
INT  
1
OSC0*  
OSC  
WDT  
TBC  
SDA*  
SCL*  
LSCLK*  
OUTCLK*  
INT  
4
INT  
1
VDDL  
VDDX  
Power  
PWM  
INT  
1
PWM0*  
MD0*  
1kHzTC  
INT  
1
INT  
1
IN0*  
CS0*  
Melody  
Capture  
×2  
RCT0*  
RS0*  
INT  
5
RC-ADC  
×2  
RT0*  
RCM*  
INT  
4
NMI  
P00 to P03  
P10 to P11  
IN1*  
CS1*  
RS1*  
RT1*  
8bit Timer  
×4  
GPIO  
P20 to P22  
P30 to P35  
AVDD  
AVSS  
INT  
1
P40 to P47  
VREF  
12bit-ADC  
BLD  
COM0 to COM3  
SEG0 to SEG43  
AIN0, AIN1  
LCD  
Driver  
Display  
register  
176bit  
VL1, VL2, VL3  
C1, C2  
LCD  
BIAS  
Figure 2 ML610Q412 Block Diagram  
6/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
PIN CONFIGURATION  
ML610Q411 TQFP120 Pin Layout  
90pin  
61pin  
60pin  
91pin  
91  
92  
SEG21  
SEG22  
SEG23  
SEG24  
SEG25  
SEG26  
SEG27  
SEG28  
SEG29  
SEG30  
SEG31  
SEG32  
SEG33  
SEG34  
SEG35  
PA0  
PA1  
PA2  
PA3  
PA4  
PA5  
PA6  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
VSS  
VDD  
VSS  
P03  
60  
59  
58  
57  
93  
94  
95  
96  
56  
55  
54  
97  
98  
53  
99  
52  
51  
50  
49  
100  
101  
102  
103  
104  
48  
47  
46  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
45  
44  
43  
42  
P02  
P01  
P00  
NMI  
P11  
41  
40  
39  
38  
PA7  
(NC)  
P10  
37  
36  
35  
34  
(NC)  
AIN1  
AIN0  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
33  
32  
31  
120pin  
31pin  
1pin  
30pin  
(NC): No Connection  
Note:  
The assignment of the P30 to P35 are not in order.  
Figure 3 ML610Q411 TQFP120 Pin Configuration  
7/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
ML610Q412 TQFP120 Pin Layout  
90pin  
61pin  
60pin  
91pin  
91  
SEG21  
SEG22  
SEG23  
60  
59  
58  
57  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
VSS  
VDD  
VSS  
P03  
92  
93  
94  
SEG24  
SEG25  
SEG26  
SEG27  
SEG28  
SEG29  
SEG30  
SEG31  
SEG32  
SEG33  
SEG34  
SEG35  
SEG43  
SEG42  
SEG41  
SEG40  
SEG39  
SEG38  
SEG37  
SEG36  
(NC)  
95  
96  
56  
55  
54  
97  
98  
53  
99  
52  
51  
50  
49  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
48  
47  
46  
45  
44  
43  
42  
P02  
P01  
P00  
NMI  
P11  
41  
40  
39  
38  
P10  
37  
36  
35  
34  
(NC)  
AIN1  
AIN0  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
33  
32  
31  
120pin  
31pin  
1pin  
30pin  
(NC): No Connection  
Note:  
The assignment of the P30 to P35 are not in order.  
Figure 4 ML610Q412 TQFP120 Pin Configuration  
8/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
ML610Q411 Chip Pin Layout & Dimension  
SEG21 91  
SEG22 92  
SEG23 93  
SEG24 94  
SEG25 95  
SEG26 96  
SEG27 97  
SEG28 98  
SEG29 99  
SEG30 100  
SEG31 101  
SEG32 102  
SEG33 103  
SEG34 104  
SEG35 105  
PA0 106  
47 VSS  
46 VDD  
45 VSS  
44 P03  
43 P02  
42 P01  
41 P00  
40 NMI  
39 P11  
38 P10  
37 (NC)  
36 AIN1  
35 AIN0  
2.636mm  
PA1 107  
PA2 108  
PA3 109  
PA4 110  
PA5 111  
PA6 112  
PA7 113  
*
2.836mm  
* Dummy pad  
Note: These dummy pads are visible and do have any function, they are placed for a mechanical evaluation  
in LAPIS Semiconductor. Please do NOT implement wire-bonding to the dummy pad.  
Chip size:  
PAD count:  
2.836mm x 2.636mm  
95 pins  
Minimum PAD pitch:  
PAD aperture:  
Chip thickness:  
80 µm  
70 µm × 70 µm  
350 µm  
VSS level  
Voltage of the rear side of chip:  
Figure 5 ML610Q411 Chip Layout & Dimension  
9/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
ML610Q412 Chip Pin Layout & Dimension  
SEG21 91  
SEG22 92  
SEG23 93  
SEG24 94  
SEG25 95  
SEG26 96  
SEG27 97  
SEG28 98  
SEG29 99  
SEG30 100  
SEG31 101  
SEG32 102  
SEG33 103  
SEG34 104  
SEG35 105  
SEG43 106  
SEG42 107  
SEG41 108  
SEG40 109  
SEG39 110  
SEG38 111  
SEG37 112  
SEG36 113  
*
47 VSS  
46 VDD  
45 VSS  
44 P03  
43 P02  
42 P01  
41 P00  
40 NMI  
39 P11  
38 P10  
37 (NC)  
36 AIN1  
35 AIN0  
2.636mm  
2.836mm  
* Dummy pad  
Note: These dummy pads are visible and do have any function, they are placed for a mechanical evaluation  
in LAPIS Semiconductor. Please do NOT implement wire-bonding to the dummy pad.  
Chip size:  
PAD count:  
2.836mm x 2.636mm  
95 pins  
Minimum PAD pitch:  
PAD aperture:  
Chip thickness:  
80 µm  
70 µm × 70 µm  
350 µm  
Voltage of the rear side of chip: VSS level  
Figure 6 ML610Q412 Chip Layout & Dimension  
10/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
ML610Q411 Pad Coordinates  
Table 1 ML610Q411 Pad Coordinates  
Chip Center: X=0,Y=0  
PAD  
No.  
Pad  
Name  
X
Y
PAD  
No.  
Pad  
Name  
X
Y
PAD  
No.  
Pad  
Name  
X
Y
(µm) (µm)  
(µm) (µm)  
(µm) (µm)  
1
VPP  
VSS  
-1230 -1212  
-1150 -1212  
-1070 -1212  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
C2  
-
-
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
--  
SEG31  
SEG32  
SEG33  
SEG34  
SEG35  
PA0  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
160  
80  
2
-
-
3
P20  
-
-
0
4
P21  
-990  
-910  
-830  
-750  
-670  
-590  
-510  
-430  
-350  
-270  
-190  
-110  
-30  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-
-
-
-80  
5
P22  
-
-
-160  
-240  
-320  
-400  
-480  
-560  
-640  
-720  
-800  
-908  
6
P40  
-
-
7
P41  
-
-
PA1  
8
RESET_N  
P42  
-
-
PA2  
9
-
-
PA3  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
-
P43  
-
-
PA4  
P44  
1220  
1140  
1060  
980  
900  
820  
740  
660  
580  
500  
420  
340  
260  
180  
100  
20  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
960  
880  
800  
720  
640  
560  
480  
400  
320  
240  
PA5  
P45  
C1  
PA6  
P46  
VL3  
PA7  
P47  
VL2  
Dummy  
P30  
VL1  
P31  
COM3  
COM2  
COM1  
COM0  
SEG0  
SEG1  
SEG2  
SEG3  
SEG4  
SEG5  
SEG6  
SEG7  
SEG8  
SEG9  
SEG10  
SEG11  
SEG12  
SEG13  
SEG14  
SEG15  
SEG16  
SEG17  
SEG18  
SEG19  
SEG20  
SEG21  
SEG22  
SEG23  
SEG24  
SEG25  
SEG26  
SEG27  
SEG28  
SEG29  
SEG30  
P34  
50  
P32  
130  
210  
290  
370  
450  
530  
610  
690  
770  
850  
930  
1030  
1110  
1190  
-
P33  
P35  
TEST  
VDD  
VDDL  
VSS  
VDDX  
XT1  
Dummy  
XT0  
-60  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
-140  
-220  
-300  
-380  
-460  
-540  
-620  
-700  
-780  
-860  
-940  
-1020  
-1100  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
AVSS  
VREF  
AVDD  
(NC)  
(NC)  
(NC)  
(NC)  
AIN0  
AIN1  
(NC)  
P10  
-
-
-
-
-
-
1312  
1312  
-
-522  
-350  
-
1312  
1312  
1312  
1312  
1312  
1312  
1312  
1312  
1312  
1312  
-
-210  
-130  
-50  
P11  
NMI  
P00  
30  
P01  
110  
P02  
190  
P03  
270  
VSS  
350  
VDD  
430  
VSS  
510  
(NC)  
(NC)  
(NC)  
-
-
-
-
-
11/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
ML610Q412 Pad Coordinates  
Table 2 ML610Q412 Pad Coordinates  
Chip Center: X=0,Y=0  
PAD  
No.  
Pad  
Name  
X
Y
PAD  
No.  
Pad  
Name  
X
Y
PAD  
No.  
Pad  
Name  
X
Y
(µm) (µm)  
(µm) (µm)  
(µm) (µm)  
1
VPP  
VSS  
-1230 -1212  
-1150 -1212  
-1070 -1212  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
(NC)  
C2  
-
-
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
-
SEG31  
SEG32  
SEG33  
SEG34  
SEG35  
SEG43  
SEG42  
SEG41  
SEG40  
SEG39  
SEG38  
SEG37  
SEG36  
Dummy  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
160  
80  
2
-
-
3
P20  
-
-
0
4
P21  
-990  
-910  
-830  
-750  
-670  
-590  
-510  
-430  
-350  
-270  
-190  
-110  
-30  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-1212  
-
-
-
-80  
5
P22  
-
-
-160  
-240  
-320  
-400  
-480  
-560  
-640  
-720  
-800  
-908  
6
P40  
-
-
7
P41  
-
-
8
RESET_N  
P42  
-
-
9
-
-
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
-
P43  
-
-
P44  
1220  
1140  
1060  
980  
900  
820  
740  
660  
580  
500  
420  
340  
260  
180  
100  
20  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
1212  
960  
880  
800  
720  
640  
560  
480  
400  
320  
240  
P45  
C1  
P46  
VL3  
P47  
VL2  
P30  
VL1  
P31  
COM3  
COM2  
COM1  
COM0  
SEG0  
SEG1  
SEG2  
SEG3  
SEG4  
SEG5  
SEG6  
SEG7  
SEG8  
SEG9  
SEG10  
SEG11  
SEG12  
SEG13  
SEG14  
SEG15  
SEG16  
SEG17  
SEG18  
SEG19  
SEG20  
SEG21  
SEG22  
SEG23  
SEG24  
SEG25  
SEG26  
SEG27  
SEG28  
SEG29  
SEG30  
P34  
50  
P32  
130  
210  
290  
370  
450  
530  
610  
690  
770  
850  
930  
1030  
1110  
1190  
-
P33  
P35  
TEST  
VDD  
VDDL  
VSS  
VDDX  
XT1  
Dummy  
XT0  
-60  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
-140  
-220  
-300  
-380  
-460  
-540  
-620  
-700  
-780  
-860  
-940  
-1020  
-1100  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
-1312  
AVSS  
VREF  
AVDD  
(NC)  
(NC)  
(NC)  
(NC)  
AIN0  
AIN1  
(NC)  
P10  
-
-
-
-
-
-
1312  
1312  
-
-522  
-350  
-
1312  
1312  
1312  
1312  
1312  
1312  
1312  
1312  
1312  
1312  
-
-210  
-130  
-50  
P11  
NMI  
P00  
30  
P01  
110  
P02  
190  
P03  
270  
VSS  
350  
VDD  
430  
VSS  
510  
(NC)  
(NC)  
(NC)  
-
-
-
-
-
12/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
PIN LIST  
PAD  
Primary function  
Secondary function  
Tertiary function  
No.  
Pin name  
VSS  
I/O  
Function  
Pin name  
I/O  
Function  
Pin name  
I/O  
Function  
2,  
Negative power supply pin  
Positive power supply pin  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
24,45,47  
22, 46  
VDD  
⎯
⎯
⎯
Power supply pin for  
internal logic (internally  
generated)  
23  
VDDL  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Power supply pin for  
low-speed oscillation  
(internally generated)  
Power supply pin for Flash  
ROM  
25  
1
VDDX  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
VPP  
Negative power supply pin  
for successive  
28  
AVSS  
approximation type ADC  
Positive power supply pin  
for successive  
30  
AVDD  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
approximation type ADC  
Power supply pin for LCD  
bias (internally generated)  
Power supply pin for LCD  
bias (internally generated)  
Power supply pin for LCD  
bias (internally generated)  
Capacitor connection pin  
for LCD bias generation  
Capacitor connection pin  
for LCD bias generation  
65  
64  
63  
62  
61  
VL1  
VL2  
VL3  
C1  
C2  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Input/output pin for testing  
Reset input pin  
21  
8
TEST  
I/O  
I
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
RESET_N  
Low-speed clock oscillation  
pin  
Low-speed clock oscillation  
pin  
27  
26  
XT0  
XT1  
I
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
O
Reference power supply  
pin for successive  
approximation type ADC  
29  
VREF  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
13/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
PAD  
No.  
Primary function  
Secondary function  
Tertiary function  
Pin name  
AIN0  
I/O  
Function  
Pin name  
I/O  
Function  
Pin name  
I/O  
Function  
Successive approximation  
type ADC input  
35  
I
⎯
⎯
⎯
⎯
⎯
⎯
Successive approximation  
type ADC input  
36  
40  
AIN1  
I
I
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Non-maskable interrupt pin  
NMI  
P00/EXI0/  
CAP0  
Input port, External  
interrupt 0, Capture 0 input  
⎯
⎯
⎯
⎯
41  
42  
I
I
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
P01/EXI1/  
CAP1  
Input port, External  
interrupt 1, Capture 1 input  
P02/EXI2/  
RXD0  
Input port, External  
interrupt 2, UART0 receive  
⎯
⎯
⎯
⎯
⎯
43  
44  
38  
I
I
I
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Input port, External  
interrupt 3  
P03/EXI3  
P10  
OSC0  
P11  
Input port  
External clock input  
⎯
⎯
Input port  
⎯
⎯
39  
3
I
⎯
⎯
⎯
⎯
⎯
⎯
Low-speed clock  
output  
Output port  
P20/LED0  
O
LSCLK  
O
High-speed clock  
output  
Output port  
⎯
⎯
⎯
4
5
P21LED1  
P22/LED2  
P30  
O
O
OUTCLK  
MD0  
O
O
I
⎯
⎯
⎯
⎯
⎯
⎯
Output port  
Melody output  
RC type ADC0  
oscillation input pin  
RC type ADC0  
reference capacitor  
connection pin  
RC type ADC0  
resistor/capacitor  
sensor connection  
pin  
Input/output port  
15  
I/O  
IN0  
Input/output port  
Input/output port  
⎯
16  
17  
P31  
P34  
I/O  
I/O  
CS0  
O
O
⎯
⎯
PWM output  
RCT0  
PWM0  
O
RC type ADC0  
reference resistor  
connection pin  
RC type ADC0  
resistor sensor  
connection pin  
RC type ADC  
Input/output port  
Input/output port  
18  
19  
P32  
P33  
I/O  
I/O  
RS0  
RT0  
O
O
⎯
⎯
⎯
⎯
⎯
⎯
Input/output port  
Input/output port  
Input/output port  
20  
6
P35  
P40  
P41  
I/O  
I/O  
I/O  
RCM  
SDA  
SCL  
O
⎯
⎯
I
⎯
oscillation monitor  
I2C data input/output  
SSIO data input  
I/O  
I/O  
SIN0  
SCK0  
SSIO synchronous  
clock  
I2C clock input/output  
7
I/O  
Input/output port  
Input/output port  
UART data input  
UART data output  
SSIO data output  
PWM output  
9
P42  
P43  
I/O  
I/O  
RXD0  
TXD0  
I
SOUT0  
PWM0  
I
10  
O
O
Input/output port, Timer  
0/Timer 2/PWM0 external  
clock input  
Input/output port, Timer  
1/Timer 3 external clock  
input  
P44/T02P0  
CK  
RC type ADC1  
oscillation input pin  
SSIO0 data input  
11  
12  
13  
14  
I/O  
I/O  
I/O  
I/O  
IN1  
CS1  
RS1  
RT1  
I
SIN0  
SCK0  
SOUT0  
⎯
I
RC type ADC1  
reference capacitor  
connection pin  
RC type ADC1  
reference resistor  
connection pin  
RC type ADC1  
resistor sensor  
connection pin  
P45/T13P1  
CK  
SSIO0 synchronous  
clock  
O
O
O
I/O  
O
Input/output port  
Input/output port  
SSIO0 data output  
P46  
P47  
⎯
⎯
PA0(*1)  
SEG43(*2)  
PA1(*1)  
SEG42(*2)  
PA2(*1)  
SEG41(*2)  
PA3(*1)  
SEG40(*2)  
I/O  
O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Input/output port  
LCD segment pin  
Input/output port  
LCD segment pin  
Input/output port  
LCD segment pin  
Input/output port  
LCD segment pin  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
106  
107  
108  
109  
I/O  
O
I/O  
O
I/O  
O
14/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
PAD  
No.  
Primary function  
Secondary function  
Tertiary function  
Pin name  
PA4(*1)  
SEG39(*2)  
PA5(*1)  
SEG38(*2)  
PA6(*1)  
SEG37(*2)  
PA7(*1)  
SEG36(*2)  
COM0  
I/O  
I/O  
O
I/O  
O
I/O  
O
I/O  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Function  
Pin name  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
I/O  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Function  
Pin name  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
I/O  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Function  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Input/output port  
LCD segment pin  
Input/output port  
LCD segment pin  
Input/output port  
LCD segment pin  
Input/output port  
LCD segment pin  
LCD common pin  
LCD common pin  
LCD common pin  
LCD common pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
110  
111  
112  
113  
69  
68  
67  
66  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
101  
102  
103  
104  
105  
COM1  
COM2  
COM3  
SEG0  
SEG1  
SEG2  
SEG3  
SEG4  
SEG5  
SEG6  
SEG7  
SEG8  
SEG9  
SEG10  
SEG11  
SEG12  
SEG13  
SEG14  
SEG15  
SEG16  
SEG17  
SEG18  
SEG19  
SEG20  
SEG21  
SEG22  
SEG23  
SEG24  
SEG25  
SEG26  
SEG27  
SEG28  
SEG29  
SEG30  
SEG31  
SEG32  
SEG33  
SEG34  
SEG35  
(*1) Pins on ML610Q411.  
(*2) Pins on ML610Q412.  
15/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
PIN DESCRIPTION  
Primary/  
Secondary/  
Tertiary  
Pin name  
I/O  
I
Description  
Logic  
System  
Reset input pin. When this pin is set to a “L” level, system reset mode is  
set and the internal section is initialized. When this pin is set to a “H” level  
subsequently, program execution starts. A pull-up resistor is internally  
connected.  
RESET_N  
—
Negative  
Crystal connection pin for low-speed clock.  
XT0  
XT1  
I
—
—
—
—
—
—
A 32.768 kHz crystal oscillator (see measuring circuit 1) is connected to  
this pin. Capacitors CDL and CGL are connected across this pin and VSS  
as required.  
High-speed external clock input pin. This pin is used as the secondary  
function of the P10.  
Low-speed clock output pin. This pin is used as the secondary function of  
the P20 pin.  
High-speed clock output pin. This pin is used as the secondary function of  
the P21 pin.  
O
—
OSC0  
LSCLK  
I
Secondary  
Secondary  
Secondary  
O
O
OUTCLK  
General-purpose input port  
General-purpose input port.  
P00-P03  
I
Primary  
Primary  
Positive  
Positive  
Since these pins have secondary functions, the pins cannot be used as a  
port when the secondary functions are used.  
General-purpose input port.  
P10-P11  
I
Since these pins have secondary functions, the pins cannot be used as a  
port when the secondary functions are used.  
General-purpose output port  
General-purpose output port.  
P20-P22  
O
Primary  
Positive  
Since these pins have secondary functions, the pins cannot be used as a  
port when the secondary functions are used.  
General-purpose input/output port  
General-purpose input/output port.  
P30-P35  
P40-P47  
PA0-PA7  
I/O  
I/O  
I/O  
Primary  
Primary  
Primary  
Positive  
Positive  
Positive  
Since these pins have secondary functions, the pins cannot be used as a  
port when the secondary functions are used.  
General-purpose input/output port.  
Since these pins have secondary functions, the pins cannot be used as a  
port when the secondary functions are used.  
General-purpose input/output port.  
These pins are for the ML610Q411, but are not provided in the  
ML610Q412.  
16/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
Primary/  
Secondary/  
Tertiary  
Pin name  
UART  
I/O  
Description  
Logic  
UART data output pin. This pin is used as the secondary function of the  
P43 pin.  
UART data input pin. This pin is used as the secondary function of the  
P42 or the primary function of the P02 pin.  
TXD0  
O
I
Secondary Positive  
RXD0  
Primary/Se Positive  
condary  
I2C bus interface  
I2C data input/output pin. This pin is used as the secondary function of the  
P40 pin. This pin has an NMOS open drain output. When using this pin as  
a function of the I2C, externally connect a pull-up resistor.  
SDA  
I/O  
Secondary Positive  
Secondary Positive  
I2C clock output pin. This pin is used as the secondary function of the P41  
pin. This pin has an NMOS open drain output. When using this pin as a  
function of the I2C, externally connect a pull-up resistor.  
SCL  
O
Synchronous serial (SSIO)  
Synchronous serial clock input/output pin. This pin is used as the tertiary  
function of the P41 or P45 pin.  
Synchronous serial data input pin. This pin is used as the tertiary function  
of the P40 or P44 pin.  
Synchronous serial data output pin. This pin is used as the tertiary  
function of the P42 or P46 pin.  
SCK0  
SIN0  
I/O  
I
Tertiary  
Tertiary  
Tertiary  
—
Positive  
Positive  
SOUT0  
O
PWM  
PWM0 output pin. This pin is used as the tertiary function of the P43 or  
P34 pin.  
PWM0 external clock input pin. This pin is used as the primary function of  
the P44 pin.  
PWM0  
O
O
Tertiary  
Primary  
Positive  
—
T02P0CK  
External interrupt  
External non-maskable interrupt input pin. An interrupt is generated on  
both edges.  
External maskable interrupt input pins. Interrupt enable and edge  
selection can be performed for each bit by software. These pins are used  
as the primary functions of the P00-P03 pins.  
Positive/  
negative  
Positive/  
negative  
NMI  
I
Primary  
Primary  
EXI0-3  
I
Capture  
Capture trigger input pins. The value of the time base counter is captured  
in the register synchronously with the interrupt edge selected by software.  
These pins are used as the primary functions of the P00 pin(CAP0) and  
P01 pin(CAP1).  
Positive/  
negative  
Positive/  
negative  
CAP0  
I
I
Primary  
Primary  
CAP1  
Timer  
External clock input pin used for both Timer 0 and Timer 2. The clocks for  
these timers are selected by software. This pin is used as the primary  
function of the P44 pin.  
External clock input pin used for both Timer 1 and Timer 3. The clocks for  
these timers are selected by software. This pin is used as the primary  
function of the P45 pin.  
T02P0CK  
I
I
Primary  
Primary  
—
—
T13P1CK  
Buzzer  
BZ0  
Buzzer signal output pin. This pin is used as the secondary function of the  
P22 pin.  
Positive/  
negative  
O
O
Secondary  
Primary  
LED drive  
LED0-2  
Nch open drain output pins to drive LED.  
Positive/  
negative  
17/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
Primary/  
Secondary/  
Tertiary  
Pin name  
I/O  
Description  
Logic  
RC oscillation type A/D converter  
Channel 0 oscillation input pin. This pin is used as the secondary function  
of the P30 pin.  
Channel 0 reference capacitor connection pin. This pin is used as the  
secondary function of the P31 pin.  
Resistor/capacitor sensor connection pin of Channel 0 for measurement.  
This pin is used as the secondary function of the P33 pin.  
This pin is used as the secondary function of the P32 pin which is the  
reference resistor connection pin of Channel 0.  
Resistor sensor connection pin of Channel 0 for measurement. This pin is  
used as the secondary function of the P34 pin.  
RC oscillation monitor pin. This pin is used as the secondary function of  
the P35 pin.  
Oscillation input pin of Channel 1. This pin is used as the secondary  
function of the P44 pin.  
Reference capacitor connection pin of Channel 1. This pin is used as the  
secondary function of the P45 pin.  
Reference resistor connection pin of Channel 1. This pin is used as the  
secondary function of the P46 pin.  
IN0  
CS0  
RCT0  
RS0  
RT0  
RCM  
IN1  
I
Secondary  
Secondary  
Secondary  
Secondary  
Secondary  
Secondary  
Secondary  
Secondary  
Secondary  
Secondary  
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
I
CS1  
RS1  
RT1  
O
O
O
Resistor sensor connection pin for measurement of Channel 1. This pin is  
used as the secondary function of the P47 pin.  
Successive approximation type A/D converter  
Negative power supply pin for successive approximation type A/D  
converter.  
Positive power supply pin for successive approximation type A/D  
converter.  
Reference power supply pin for successive approximation type A/D  
converter.  
AVSS  
AVDD  
VREF  
—
—
—
—
—
—
—
—
—
Channel 0 analog input for successive approximation type A/D converter.  
AIN0  
AIN1  
I
I
—
—
—
—
Channel 1 analog input for successive approximation type A/D converter.  
LCD drive signal  
Common output pins.  
Segment output pins.  
COM0-3  
SEG0-35  
O
—
—
—
—
O
O
Segment output pin. These pins are for the ML610Q412, but are not  
provided in the ML610Q411.  
SEG36-43  
—
—
LCD driver power supply  
Power supply pins for LCD bias (internally generated). Capacitors Ca, Cb,  
and Cc (see measuring circuit 1) are connected between VSS and VL1, VL2,  
and VL3, respectively.  
VL1  
VL2  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VL3  
Power supply pins for LCD bias (internally generated). Capacitors C12 is  
connected between C1 and C2.  
C1  
C2  
For testing  
TEST  
Power supply  
VSS  
Input/output pin for testing. A pull-down resistor is internally connected.  
Negative power supply pin.  
I/O  
—
—
—
—
—
—
—
—
Positive power supply pin for I/O, internal regulator, battery low detector,  
and power-on reset.  
VDD  
Positive power supply pin (internally generated) for internal logic.  
Capacitors CL0 and CL1 (see measuring circuit 1) are connected between  
VDDL  
VDDX  
VPP  
—
—
—
—
—
—
—
—
—
this pin and VSS  
.
Positive power supply pin (internally generated) for low-speed oscillation.  
When using ML610Q411 and ML610Q412, connect capacitor Cx (see  
measuring circuit 1) between this pin and VSS  
.
Power supply pin for programming Flash ROM. A pull-down resistor is  
internally connected.  
18/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
TERMINATION OF UNUSED PINS  
Table 3 shows methods of terminating the unused pins.  
Table 3 Termination of Unused Pins  
Pin  
Recommended pin termination  
VPP  
Open  
VSS  
AVDD  
AVSS  
VSS  
VREF  
VSS  
AIN0, AIN1  
VL1, VL2, VL3  
C1, C2  
Open  
Open  
Open  
Open  
Open  
Open  
RESET_N  
TEST  
NMI  
P00 to P03  
P10 to P11  
P20 to P22  
P30 to P35  
P40 to P47  
PA0 to PA7  
COM0 to 3  
SEG0 to 43  
V
DD or VSS  
VDD  
Open  
Open  
Open  
Open  
Open  
Open  
Note:  
It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or  
the output mode since the supply current may become excessively large if the pins are left open in the high impedance input  
setting.  
19/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
ELECTRICAL CHARACTERISTICS  
ABSOLUTE MAXIMUM RATINGS  
(VSS = AVSS = 0V)  
Parameter  
Power supply voltage 1  
Power supply voltage 2  
Power supply voltage 3  
Power supply voltage 4  
Power supply voltage 5  
Power supply voltage 6  
Power supply voltage 7  
Power supply voltage 8  
Input voltage  
Symbol  
Condition  
Ta = 25°C  
Ta = 25°C  
Ta = 25°C  
Ta = 25°C  
Ta = 25°C  
Ta = 25°C  
Ta = 25°C  
Ta = 25°C  
Ta = 25°C  
Ta = 25°C  
Port3–A, Ta = 25°C  
Port2, Ta = 25°C  
Ta = 25°C  
⎯
Rating  
−0.3 to +4.6  
−0.3 to +4.6  
−0.3 to +9.5  
−0.3 to +3.6  
−0.3 to +3.6  
−0.3 to +1.75  
−0.3 to +3.5  
−0.3 to +5.25  
−0.3 to VDD+0.3  
−0.3 to VDD+0.3  
−12 to +11  
Unit  
V
VDD  
AVDD  
VPP  
V
V
VDDL  
VDDX  
VL1  
V
V
V
VL2  
V
VL3  
V
VIN  
V
Output voltage  
VOUT  
IOUT1  
IOUT2  
PD  
V
Output current 1  
mA  
mA  
W
°C  
Output current 2  
−12 to +20  
Power dissipation  
1.25  
Storage temperature  
TSTG  
−55 to +150  
RECOMMENDED OPERATING CONDITIONS  
(VSS = AVSS = 0V)  
Range Unit  
Parameter  
Symbol  
TOP  
Condition  
ML610Q411, ML610Q412,  
ML610Q411P, ML610Q411PA,  
ML610Q412P  
−20 to +70  
−40 to +85  
Operating temperature  
°C  
VDD  
⎯
⎯
1.1 to 3.6  
2.2 to 3.6  
Operating voltage  
V
AVDD  
30k to 36k  
46.9k to 78.1k  
VDD = 1.1 to 3.6V  
VDD = 1.3 to 3.6V  
Operating frequency (CPU)  
fOP  
Hz  
30k to 625k  
23k to 625k  
1.0±30%  
CL0  
CL1  
⎯
⎯
Capacitor externally connected to  
VDDL pin  
µF  
µF  
µF  
µF  
0.1±30%  
Capacitor externally connected to  
VDDX pin  
CX  
C1, 2, 3  
C12  
⎯
⎯
⎯
0.1±30%  
1.0±30%  
1.0±30%  
Capacitors externally connected to  
VL1, 2, 3 pins  
Capacitors externally connected  
across C1 and C2 pins  
20/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
CLOCK GENERATION CIRCUIT OPERATING CONDITIONS  
(VSS = 0V)  
Rating  
Typ.  
Parameter  
Symbol  
Condition  
Unit  
Min.  
Max.  
Low-speed crystal oscillation  
frequency  
Recommended equivalent series  
resistance value of low-speed  
crystal oscillation  
fXTL  
RL  
⎯
⎯
⎯
32.768k  
⎯
Hz  
⎯
⎯
⎯
40k  
Ω
CL=6pF of  
crystal  
0
6
⎯
⎯
oscillation *2  
CL=9pF of  
crystal  
CDL/CGL  
⎯
Low-speed crystal oscillation  
external capacitor *1  
pF  
oscillation  
CL=12pF of  
crystal  
oscillation  
⎯
⎯
⎯
12  
24  
⎯
⎯
CGH  
*1: The external CDL and CGL need to be adjusted in consideration of variation of internal loading capacitance CD and CG, and  
other additional capacitance such as PCB layout.  
*2: When using a crystal oscillator CL = 6pF, there is a possibility that can not be adjusted by external CDL and CGL  
.
OPERATING CONDITIONS OF FLASH ROM  
(VSS = AVSS = 0V)  
Parameter  
Symbol  
TOP  
VDD  
Condition  
At write/erase  
At write/erase*1  
At write/erase*1  
At write/erase*1  
⎯
Range  
0 to +40  
2.75 to 3.6  
2.5 to 2.75  
7.7 to 8.3  
80  
Unit  
Operating temperature  
°C  
Operating voltage  
V
VDDL  
VPP  
CEP  
Write cycles  
cycles  
years  
Data retention  
YDR  
⎯
10  
*1: Those voltages must be supplied to VDDL pin and VPP pin when programming and eraseing Flash ROM.  
VPP pin has an internal pulldown resister.  
21/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
DC CHARACTERISTICS (1/5)  
(VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version,  
unless otherwise specified) (1/5)  
Rating  
Typ.  
Measuring  
circuit  
Parameter  
Symbol  
fRC  
Condition  
Ta = 25°C  
Unit  
kHz  
Min.  
Typ.  
−10%  
Typ.  
Max.  
Typ.  
+10%  
Typ.  
500  
V
DD = 1.3  
500kHz RC oscillation  
frequency  
to 3.6V  
3
*
500  
0.3  
50  
kHz  
s
−25%  
+25%  
Low-speed crystal oscillation  
start time*2  
500kHz RC oscillation start  
time  
Low-speed oscillation stop  
detect time*1  
TXTL  
TRC  
⎯
⎯
⎯
⎯
2
500  
µs  
ms  
1
TSTOP  
PRST  
⎯
⎯
⎯
0.2  
200  
⎯
3
20  
⎯
Reset pulse width  
⎯
⎯
µs  
Reset noise elimination  
pulse width  
PNRST  
0.3  
Power-on reset activation  
power rise time  
TPOR  
⎯
⎯
⎯
10  
ms  
*1: When low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is  
reset to shift to system reset mode.  
*2 : Use 32.768KHz Crystal Oscillator C-001R (Epson Toyocom) with capacitance CGL/CDL＝0pF.  
*3 : Recommended operating temperature (Ta = −40 to +85°C for P version, Ta = −20 to +70°C for non-P version)  
[Reset pulse width]  
VIL1  
VIL1  
RESET_N  
PRST  
Reset pulse width (PRST  
)
[Power-on reset activation power rise time]  
0.9xVDD  
VDD  
0.1xVDD  
TPOR  
Power-on reset activation power rise time (TPOR  
)
22/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
DC CHARACTERISTICS (2/5)  
(VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version,  
unless otherwise specified) (2/5)  
Rating  
Typ.  
0.94  
0.96  
0.98  
1.00  
1.02  
1.04  
1.06  
1.08  
1.10  
1.12  
1.14  
1.16  
1.18  
1.20  
1.22  
1.24  
1.26  
1.28  
1.30  
1.32  
1.34  
1.36  
1.38  
1.40  
1.42  
1.44  
1.46  
1.48  
1.50  
1.52  
1.54  
1.56  
Measuring  
circuit  
Parameter  
Symbol  
Condition  
CN4–0 = 00H  
Unit  
Min.  
0.89  
0.91  
0.93  
0.95  
0.97  
0.99  
1.01  
1.03  
1.05  
1.07  
1.09  
1.11  
1.13  
1.15  
1.17  
1.19  
1.21  
1.23  
1.25  
1.27  
1.29  
1.31  
1.33  
1.35  
1.37  
1.39  
1.41  
1.43  
1.45  
1.47  
1.49  
1.51  
Max.  
0.99  
1.01  
1.03  
1.05  
1.07  
1.09  
1.11  
1.13  
1.15  
1.17  
1.19  
1.21  
1.23  
1.25  
1.27  
1.29  
1.31  
1.33  
1.35  
1.37  
1.39  
1.41  
1.43  
1.45  
1.47  
1.49  
1.51  
1.53  
1.55  
1.57  
1.59  
1.61  
CN4–0 = 01H  
CN4–0 = 02H  
CN4–0 = 03H  
CN4–0 = 04H  
CN4–0 = 05H  
CN4–0 = 06H  
CN4–0 = 07H  
CN4–0 = 08H  
CN4–0 = 09H  
CN4–0 = 0AH  
CN4–0 = 0BH  
CN4–0 = 0CH  
CN4–0 = 0DH  
CN4–0 = 0EH  
CN4–0 = 0FH  
CN4–0 = 10H  
CN4–0 = 11H  
CN4–0 = 12H  
CN4–0 = 13H  
CN4–0 = 14H  
CN4–0 = 15H  
CN4–0 = 16H  
CN4–0 = 17H  
CN4–0 = 18H  
CN4–0 = 19H  
CN4–0 = 1AH  
CN4–0 = 1BH  
CN4–0 = 1CH  
CN4–0 = 1DH  
CN4–0 = 1EH  
CN4–0 = 1FH  
V
DD = 3.0V,  
VL1 voltage  
VL1  
V
Tj = 25°C  
1
VL1 temperature  
deviation *1  
∆VL1  
∆VL1  
VL2  
VDD = 3.0V  
⎯
⎯
−1.5  
5
⎯
mV/°C  
VL1 voltage  
VDD = 1.3 to 3.6V  
20  
mV/V  
dependency *1  
Typ.  
−10%  
Typ.  
Typ.  
+4%  
Typ.  
+4%  
VL2 voltage  
VL3 voltage  
VL1×2  
VDD = 3.0V, Tj = 25°C  
1MΩ load (VL3−VSS  
V
)
VL3  
VL1×3  
−10%  
LCD bias voltage  
generation time  
TBIAS  
⎯
⎯
⎯
600  
ms  
*1:VL1 can not exceed VDD level. The maximum VL1 becomes VDD level when the VL1 calculated by the temperature deviation  
and voltage dependency is going to exceed the VDD level.  
23/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
DC CHARACTERISTICS (3/5)  
(VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version,  
unless otherwise specified) (3/5)  
Rating  
Typ.  
1.35  
1.4  
Measuring  
circuit  
Parameter  
Symbol  
Condition  
Unit  
Min.  
Max.  
LD3–0 = 0H  
LD3–0 = 1H  
LD3–0 = 2H  
LD3–0 = 3H  
LD3–0 = 4H  
LD3–0 = 5H  
LD3–0 = 6H  
LD3–0 = 7H  
LD3–0 = 8H  
LD3–0 = 9H  
LD3–0 = 0AH  
LD3–0 = 0BH  
LD3–0 = 0CH  
LD3–0 = 0DH  
LD3–0 = 0EH  
LD3–0 = 0FH  
1.45  
1.5  
1.6  
1.7  
1.8  
Typ.  
−2%  
1.9  
Typ.  
+2%  
BLD threshold  
voltage  
VBLD  
VDD = 1.35 to 3.6V  
V
2.0  
2.1  
1
2.2  
2.3  
2.4  
2.5  
2.7  
2.9  
BLD threshold  
voltage  
temperature  
deviation  
∆VBLD  
VDD = 1.35 to 3.6V  
⎯
0
⎯
%/°C  
µA  
CPU: In STOP state.  
Low-speed/high-speed RC500kHz  
oscillation: stopped.  
Ta= 25°C  
⎯
⎯
0.15  
0.5  
2.5  
Supply current 1  
Supply current 2  
IDD1  
5
*
⎯
CPU: In HALT state (LTBC and WDT  
are Operating. Low speed oscillation  
stop detector is Stopped).*3*4  
High-speed 500kHz oscillation:  
Stopped.  
LCD and BIAS circuits: Stopped.  
CPU: In HALT state (LTBC and WDT  
are Operating. Low speed  
oscillation stop detector is  
Stopped).*3  
Ta= 25°C  
⎯
⎯
0.5  
1.3  
3.5  
IDD2  
IDD3  
µA  
µA  
5
*
⎯
1
Ta= 25°C  
⎯
⎯
1.28  
1.6  
11  
Supply current 3  
High-speed 500kHz oscillation:  
Stopped.  
5
*
⎯
LCD and BIAS circuits: Operating. *2  
CPU: In 32.768kHz operating  
state.*1*3  
Ta= 25°C  
⎯
⎯
5.5  
7
Supply current 4  
Supply current 5  
Supply current 6  
IDD4  
IDD5  
IDD6  
µA  
µA  
High-speed 500kHz oscillation:  
Stopped.  
5
*
⎯
12  
LCD and BIAS circuits: Operating. *2  
Ta= 25°C  
⎯
⎯
80  
90  
CPU: In RC 500kHz operating state.  
LCD and BIAS circuits: Operating. *2  
5
*
⎯
100  
CPU: In RC 500kHz operating  
state.*2  
1
Ta= 25°C  
⎯
⎯
0.4  
0.5  
0.6  
LCD and BIAS circuits: Operating. *2  
A/D: In operating state.  
VDD = AVDD = 3.0V  
mA  
5
*
⎯
*1: When the CPU operating rate is 100% (No HALT state).  
*2: All SEGs: off waveform, No LCD panel load, 1/3 bias, 1/3 duty, Frame frequency: Approx. 64 Hz, Bias voltage multiplying  
clock: 1/128 LSCLK (256Hz)  
*3 : Use 32.768KHz Crystal Oscillator C-001R (Epson Toyocom) with capacitance CGL/CDL＝0pF.  
*4 : Significant bits of BLKCON0~BLKCON4 registers are all “1”.  
*5 : Recommended operating temperature (Ta = −40 to +85°C for P version, Ta = −20 to +70°C for non-P version)  
24/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
DC CHARACTERISTICS (4/5)  
(VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version,  
unless otherwise specified) (4/5)  
Rating  
Typ.  
Measuring  
circuit  
Parameter  
Symbol  
VOH1  
Condition  
Unit  
Min.  
Max.  
VDD  
−0.5  
VDD  
−0.3  
VDD  
−0.3  
⎯
IOH1 = −0.5mA, VDD = 1.8 to 3.6V  
IOH1 = -0.1mA, VDD = 1.3 to 3.6V  
IOH1 = -0.03mA, VDD = 1.1 to 3.6V  
⎯
⎯
⎯
⎯
Output voltage 1  
(P20–P22/2nd  
function is  
selected)  
(P30–P36)  
⎯
⎯
IOL1 = +0.5mA, VDD = 1.8 to 3.6V  
IOL1 = +0.1mA, VDD = 1.3 to 3.6V  
⎯
⎯
0.5  
0.5  
(P40–P47)  
(PB0–PB7)*1  
⎯
VOL1  
VOH1  
IOL1 = +0.03mA, VDD = 1.1 to 3.6V  
IOH1 = −0.5mA, VDD = 1.8 to 3.6V  
IOH1 = -0.1mA, VDD = 1.3 to 3.6V  
IOH1 = -0.03mA, VDD = 1.1 to 3.6V  
⎯
⎯
⎯
⎯
0.3  
⎯
VDD  
−0.5  
VDD  
−0.3  
VDD  
−0.3  
⎯
Output voltage 2  
(P20–P22/2nd  
function is Not  
selected)  
⎯
⎯
⎯
⎯
⎯
V
2
VOL2  
VOL3  
IOL2 = +5mA, VDD = 1.8 to 3.6V  
IOL3 = +3mA, VDD = 2.0 to 3.6V  
(when I2C mode is selected)  
0.5  
0.4  
Output voltage 3  
(P40–P41)  
⎯
VL3  
−0.2  
VOH4  
VOMH4  
VOM4S  
VOML4  
IOH4 = −0.2mA, VL1=1.2V  
IOMH4 = +0.2mA, VL1=1.2V  
IOM4S = −0.2mA, VL1=1.2V  
IOML4 = +0.2mA, VL1=1.2V  
⎯
⎯
⎯
⎯
⎯
VL2  
+0.2  
⎯
Output voltage 4  
(COM0–3)  
VL2  
−0.2  
⎯
(SEG0–35)*1  
(SEG0–43) *2  
VL1  
+0.2  
⎯
VL1  
−0.2  
VOML4S  
VOL4  
IOML4S = −0.2mA, VL1=1.2V  
⎯
⎯
⎯
IOL4 = +0.2mA, VL1=1.2V  
⎯
0.2  
Output leakage  
(P20–P22)  
IOOH  
VOH = VDD (in high-impedance state)  
⎯
⎯
1
µA  
3
(P30–P35)  
(P40–P47)  
IOOL  
IIH1  
IIL1  
VOL = VSS (in high-impedance state)  
VIH1 = VDD  
−1  
⎯
⎯
(PA0–PA7)*1  
0
⎯
−300  
−300  
300  
300  
⎯
1
-10  
-2  
Input current 1  
(RESET_N)  
VDD = 1.3 to 3.6V  
VIL1 = VSS  
−600  
−600  
10  
VDD = 1.1 to 3.6V  
VDD = 1.3 to 3.6V  
VDD = 1.1 to 3.6V  
600  
600  
⎯
200  
200  
-0.2  
-0.01  
IIH1  
IIL1  
IIH2  
VIH1 = VDD  
Input current 1  
(TEST)  
2
VIL1 = Vss  
VDD = 1.3 to 3.6V  
DD = 1.1 to 3.6V  
VDD = 1.3 to 3.6V  
DD = 1.1 to 3.6V  
-1  
µA  
4
VIH2 = VDD  
(when pulled-down)  
0.2  
30  
Input current 2  
(NMI)  
V
0.01  
−200  
−200  
30  
(P00-P03)  
(P10-P11)  
(P30-P35)  
(P40-P47)  
(PA0-PA7) *1  
VIL2 = VSS  
(when pulled-up)  
−30  
−30  
IIL2  
V
IIH2Z  
IIL2Z  
VIH2 = VDD (in high-impedance state)  
VIL2 = VSS (in high-impedance state)  
⎯
⎯
⎯
1
−1  
⎯
*1: ML610Q411  
*2: ML610Q412  
25/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
DC CHARACTERISTICS (5/5))  
(VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version,  
unless otherwise specified) (5/5)  
Rating  
Typ.  
Measuring  
circuit  
Parameter  
Symbol  
VIH1  
Condition  
Unit  
Min.  
Max.  
VDD  
Input voltage 1  
(RESET_N)  
(TEST)  
0.7  
×VDD  
VDD = 1.3 to 3.6V  
VDD = 1.1 to 3.6V  
VDD = 1.3 to 3.6V  
⎯
⎯
⎯
0.7  
×VDD  
(NMI)  
VDD  
(P00–P03)  
(P10–P11)  
(P31–P35)  
(P40–P43)  
(P45–P47)  
(PA0–PA7)*1  
Hysteresis width  
(RESET_N)  
(TEST_N)  
(NMI)  
0.3  
×VDD  
0
0
VIL1  
0.2  
×VDD  
VDD = 1.1 to 3.6V  
VDD = 2.0 to 3.6V  
⎯
0.05  
×VDD  
0.18  
×VDD  
0.4  
×VDD  
V
5
(P00–P03)  
(P10–P11)  
(P31–P35)  
(P40–P43)  
(P45–P47)  
(PA0–PA7)*1  
∆VT  
0.02  
×VDD  
0.18  
×VDD  
0.4  
×VDD  
VDD = 1.1 to 3.6V  
0.7  
×VDD  
VIH2  
VIL2  
⎯
⎯
⎯
⎯
VDD  
Input voltage 2  
(P30, P44)  
0.3  
×VDD  
0
Input pin  
capacitance  
(NMI)  
f = 10kHz  
(P00–P03)  
(P10–P11)  
(P30–P35)  
(P40–P47)  
(PA0–PA7)*1  
*1: ML610Q411  
CIN  
Vrms = 50mV  
⎯
⎯
5
pF  
⎯
Ta = 25°C  
HYSTERESIS WIDTH  
∆VT  
VDD  
Input signal  
VSS  
VDDL  
VSS  
Internal signal  
26/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
MEASURING CIRCUITS  
MEASURING CIRCUIT 1  
XT0  
32.768kHz crystal  
XT1  
C2  
C1  
P10/OSC0  
C12  
VDD AVDDV REFVDDL  
VDDX  
VL3  
VSS AVSS  
VL1 VL2  
CV:  
1µF  
1µF  
0.1µF  
0.1µF  
A
CL0:  
CL1:  
CX:  
CV  
CL1 CL0 CX  
Cc  
Ca Cb  
Ca,Cb,Cc,Cd:  
C12,C34:  
32.768kHz crystal:  
1µF  
1µF  
C-001R (Epson Toyocom)  
MEASURING CIRCUIT 2  
(*2)  
VIH  
V
(*1)  
VIL  
VDD VDDL VDDX VL1 VL2  
AVDDVREF VSSAVSS  
VL3  
(*1) Input logic circuit to determine the specified measuring conditions.  
(*2) Measured at the specified output pins.  
27/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
MEASURING CIRCUIT 3  
(*2)  
VIH  
A
RS1  
VIL  
VDD VDDL VDDX VL1 VL2  
AVDDVREF VSSAVSS  
VL3  
*1: Input logic circuit to determine the specified measuring conditions.  
*2: Measured at the specified output pins.  
MEASURING CIRCUIT 4  
(*3)  
A
VDD VDDL VDDX VL1 VL2  
AVDDVREF VSSAVSS  
VL3  
*3: Measured at the specified output pins.  
MEASURING CIRCUIT 5  
VIH  
(*1)  
VIL  
VDD VDDL VDDX VL1 VL2  
AVDDVREF VSSAVSS  
VL3  
*1: Input logic circuit to determine the specified measuring conditions.  
28/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
AC CHARACTERISTICS (External Interrupt)  
(VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version,  
unless otherwise specified)  
Rating  
Parameter  
Symbol  
TNUL  
Condition  
Unit  
Min.  
76.8  
Typ.  
Max.  
Interrupt: Enabled (MIE = 1),  
CPU: NOP operation  
External interrupt disable period  
⎯
106.8  
µs  
System clock: 32.768kHz  
P00–P03  
(Rising-edge interrupt)  
tNUL  
P00–P03  
(Falling-edge interrupt)  
tNUL  
NMI, P00–P03  
(Both-edge interrupt)  
tNUL  
AC CHARACTERISTICS (Serial Port)  
(VDD = 1.3 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version,  
unless otherwise specified)  
Rating  
Parameter  
Transmit baud rate  
Receive baud rate  
Symbol  
Condition  
Unit  
Min.  
Typ.  
Max.  
tTBRT  
tRBRT  
⎯
⎯
⎯
BRT*1  
⎯
s
s
BRT*1  
−3%  
BRT*1  
+3%  
BRT*1  
*1: Baud rate period (including the error of the clock frequency selected) set with the serial port baud rate register  
(SIOBRTL,H) and the serial port mode register 0 (SIOMOD0).  
tTBRT  
TXD0*  
tRBRT  
RXD0*  
*: Indicates the secondary function of the port.  
29/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
AC CHARACTERISTICS (Synchronous Serial Port)  
(VDD = 1.3 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version,  
unless otherwise specified)  
Rating  
Parameter  
SCLK input cycle  
Symbol  
Condition  
Unit  
Min.  
10  
Typ.  
Max.  
When high-speed oscillation is  
not active  
tSCYC  
tSCYC  
tSW  
⎯
⎯
µs  
s
(slave mode)  
SCLK output cycle  
(master mode)  
SCLK input pulse width  
(slave mode)  
⎯
⎯
SCLK*1  
⎯
⎯
When high-speed oscillation is  
not active  
4
⎯
µs  
SCLK*1  
×0.4  
SCLK*1  
×0.5  
SCLK*1  
×0.6  
SCLK output pulse width  
(master mode)  
SOUT output delay time  
(slave mode)  
SOUT output delay time  
(master mode)  
SIN input  
tSW  
tSD  
tSD  
⎯
⎯
⎯
s
⎯
⎯
⎯
⎯
500  
500  
ns  
ns  
setup time  
tSS  
⎯
80  
⎯
⎯
ns  
(slave mode)  
SIN input  
setup time  
(master mode)  
SIN input  
tSS  
tSH  
⎯
⎯
500  
300  
⎯
⎯
⎯
⎯
ns  
ns  
hold time  
*1: Clock period selected with S0CK3–0 of the serial port 0 mode register (SIO0MOD1)  
tSCYC  
tSW  
tSW  
SCLK0*  
SOUT0*  
SIN0*  
tSD  
tSD  
tSS  
tSH  
*: Indicates the secondary function of the port.  
30/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
AC CHARACTERISTICS (I2C Bus Interface: Standard Mode)  
(VDD = 1.8 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version,  
unless otherwise specified)  
Rating  
Parameter  
SCL clock frequency  
Symbol  
Condition  
Unit  
Min.  
Typ.  
50  
Max.  
fSCL  
⎯
⎯
⎯
⎯
kHz  
SCL hold time  
(start/restart condition)  
tHD:STA  
4.0  
⎯
⎯
µs  
SCL ”L” level time  
SCL ”H” level time  
tLOW  
tHIGH  
⎯
⎯
4.7  
4.0  
⎯
⎯
⎯
⎯
µs  
µs  
SCL setup time  
(restart condition)  
tSU:STA  
⎯
4.7  
⎯
⎯
µs  
SDA hold time  
SDA setup time  
tHD:DAT  
tSU:DAT  
⎯
⎯
0
⎯
⎯
⎯
⎯
µs  
µs  
0.25  
SDA setup time  
(stop condition)  
tSU:STO  
tBUF  
⎯
⎯
4.0  
4.7  
⎯
⎯
⎯
⎯
µs  
µs  
Bus-free time  
Start  
condition  
Restart  
condition  
Stop  
condition  
P40/SDA  
P41/SCL  
tBUF  
tSU:STO  
tHD:STA  
tLOW tHIGH  
tSU:STA tHD:STA  
tSU:DAT tHD:DAT  
31/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
AC CHARACTERISTICS (RC Oscillation A/D Converter)  
(VDD = 1.3 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version,  
unless otherwise specified)  
Rating  
Parameter  
Symbol  
Condition  
Unit  
Min.  
1
Typ.  
Max.  
RS0, RS1,  
RT0,  
RT0-1,RT1  
fOSC1  
fOSC2  
fOSC3  
Kf1  
Resistors for oscillation  
CS0, CT0, CS1 ≥ 740pF  
⎯
⎯
kΩ  
Resistor for oscillation = 1kΩ  
Resistor for oscillation = 10kΩ  
Resistor for oscillation = 100kΩ  
RT0, RT0-1, RT1 = 1kHz  
209.4  
41.29  
4.71  
330.6  
55.27  
5.97  
5.982  
1
435.1  
64.16  
7.06  
kHz  
kHz  
kHz  
⎯
⎯
⎯
kHz  
kHz  
kHz  
⎯
⎯
⎯
Oscillation frequency  
VDD = 1.5V  
5.567  
0.99  
6.225  
1.01  
RS to RT oscillation frequency  
ratio *1  
VDD = 1.5V  
Kf2  
RT0, RT0-1, RT1 = 10kHz  
RT0, RT0-1, RT1 = 100kHz  
Resistor for oscillation = 1kΩ  
Resistor for oscillation = 10kΩ  
Resistor for oscillation = 100kΩ  
RT0, RT0-1, RT1 = 1kHz  
Kf3  
0.104  
407.3  
49.76  
5.04  
0.108  
486.7  
59.28  
5.993  
8.210  
1
0.118  
594.6  
72.76  
7.04  
fOSC1  
fOSC2  
fOSC3  
Kf1  
Oscillation frequency  
VDD = 3.0V  
8.006  
0.99  
8.416  
1.01  
RS to RT oscillation frequency  
ratio *1  
VDD = 3.0V  
Kf2  
RT0, RT0-1, RT1 = 10kHz  
RT0, RT0-1, RT1 = 100kHz  
Kf3  
0.100  
0.108  
0.115  
*1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same  
conditions.  
f
OSCX(RT0−CS0 oscillation)  
fOSCX(RT0-1−CS0 oscillation)  
fOSCX(RS0−CS0 oscillation)  
fOSCX(RT1−CS1 oscillation)  
fOSCX(RS1−CS1 oscillation)  
Kfx =  
f
OSCX(RS0−CS0 oscillation)  
,
,
(x = 1, 2, 3)  
CVR0  
CVR1  
RT0, RT0-1, RT1: 1kΩ /10kΩ/100kΩ  
RS0, RS1: 10kΩ  
CS0, CT0, CS1: 560pF  
CVR0, CVR1: 820pF  
IN0 CS0 RCT0 RS0 RT0  
IN1 CS1 RS1 RT1  
RCM  
VIH  
Frequency measurement (fOSCX  
)
(*1)  
VIL  
VDD VDDL  
VDDX  
VSS AVSS  
AVDD VREF  
*1: Input logic circuit to  
determine the specified  
measuring conditions.  
CV  
CL1 CL0 CX  
Note:  
- Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors  
and IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wire between IN0/IN1 and RS0/RS1. The coupling  
capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise  
around the node.  
- When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to  
the signal.  
- Please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. Wiring to reserved  
components may affect to the A/D conversion operation by noise the components itself may have.  
32/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
Electrical Characteristics of Successive Approximation Type A/D Converter  
(VDD = 1.8 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version,  
unless otherwise specified)  
Rating  
Parameter  
Symbol  
n
Condition  
Unit  
bit  
Min.  
⎯
Typ.  
⎯
Max.  
12  
Resolution  
⎯
2.7V ≤ VREF ≤ 3.6V  
2.2V ≤ VREF ≤ 2.7V  
2.7V ≤ VREF ≤ 3.6V  
2.2V ≤ VREF ≤ 2.7V  
−4  
−6  
−3  
−5  
−6  
−6  
2.2  
⎯
⎯
⎯
⎯
⎯
⎯
⎯
+4  
Integral non-linearity error  
IDL  
+6  
+3  
Differential non-linearity error  
DNL  
LSB  
+5  
Zero-scale error  
Full-scale error  
Reference voltage  
VOFF  
FSE  
VREF  
⎯
⎯
⎯
+6  
+6  
AVDD  
V
23*1  
⎯
φ/CH  
Conversion time  
tCONV  
⎯
⎯
φ: Period of high-speed clock (HSCLK)  
*1: 2φ / CH is required as an interval time for each conversion in the case of consecutive A/D conversion.  
AVDD  
Reference  
voltage  
VREF  
VDD  
VDDL  
10µF  
1µF  
A
0.1µF  
0.1µF  
VDDX  
VSS  
RI≤5kΩ  
−
AIN0,  
AIN1  
1µF  
+
Analog input  
AVSS  
0.1µF  
33/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
PACKAGE DIMENSIONS  
(Unit: mm)  
Notes for Mounting the Surface Mount Type Package  
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,  
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package  
code and desired mounting conditions (reflow method, temperature and times).  
34/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
REVISION HISTORY  
Page  
Document No.  
Date  
Description  
Previous Current  
Edition  
Edition  
FEDL610Q411-01  
FEDL610Q411-02  
Jul.17,2010  
Mar.23,2011  
–
–
Formally edition 1  
3, 4, 21  
3, 4, 21  
Add the explanation of ML610Q411PC.  
Replace the package dimension (Only the format is changed.  
Package size and material are not changed.)  
Change header and footer.  
34  
34  
All  
1~3  
5
All  
1~3  
5
7
7
9
9
11  
13  
15  
16  
18~20  
21  
23  
24  
25  
27  
11  
13  
15  
16  
18~20  
22  
24  
25  
26  
27  
Delete ML610Q415 and ML610Q411PC  
FEDL610Q411-03  
Apr.15,2015  
Change from "Shipment" to "Product name － Supported  
Function"  
4
–
4
Add CLOCK GENERATION CIRCUIT OPERATING  
CONDITIONS  
21  
Change "RESET" to "Reset pulse width (PRST) " and  
"Power-on reset activation power rise time (TPOR) ".  
Change description in Note.  
21  
36  
22  
36  
Corrected a typo.  
FEDL610Q411-04  
July.13,2015  
14  
14  
-PAD No,”37” is corrected to “36”.  
-PAD No,”36” is corrected to “35”.  
35/36  
FEDL610Q411-04  
ML610Q411/ML610Q412  
Notes  
1) The information contained herein is subject to change without notice.  
2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can  
break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure,  
please take safety measures such as complying with the derating characteristics, implementing redundant and fire  
prevention designs, and utilizing backups and fail-safe procedures. LAPIS Semiconductor shall have no responsibility for  
any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor.  
3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate  
the standard usage and operations of the Products.The peripheral conditions must be taken into account when designing  
circuits for mass production.  
4) The technical information specified herein is intended only to show the typical functions of the Products and examples of  
application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property  
rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this  
document; therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights  
owned by third parties, arising out of the use of such technical information.  
5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication, consumer systems,  
gaming/entertainment sets) as well as the applications indicated in this document.  
6) The Products specified in this document are not designed to be radiation tolerant.  
7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and  
consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary  
communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and  
power transmission systems.  
8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power  
control systems, and submarine repeaters.  
9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the  
recommended usage conditions and specifications contained herein.  
10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document.  
However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall have  
no responsibility for any damages arising from any inaccuracy or misprint of such information.  
11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.  
For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no  
responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations.  
12) When providing our Products and technologies contained in this document to other countries, you must abide by the  
procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US  
Export Administration Regulations and the Foreign Exchange and Foreign Trade Act.  
13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor.  
Copyright 2010 – 2015 LAPIS Semiconductor Co., Ltd.  
2-4-8 Shinyokohama, Kouhoku-ku,  
Yokohama 222-8575, Japan  
http://www.lapis-semi.com/en/  
36/36  

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