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ML610Q418 [LAPIS]

8-bit Microcontroller with a Built-in LCD driver;
ML610Q418
型号： ML610Q418
厂家： LAPIS Semiconductor Co., Ltd.    LAPIS Semiconductor Co., Ltd.
描述：

8-bit Microcontroller with a Built-in LCD driver

CD 微控制器
文件： 总38页 (文件大小：848K)
中文：  中文翻译
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FEDL610Q418-01  
Issue Date: May, 10, 2016  
ML610Q418/ML610Q418C  
8-bit Microcontroller with a Built-in LCD driver  
GENERAL DESCRIPTION  
This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port,  
UART, I2C bus interface (master), melody driver, battery level detect circuit, RC oscillation type A/D converter, and LCD  
driver, are incorporated around 8-bit CPU nX-U8/100.  
The CPU nX-U8/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe line architecture  
parallel processing. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption  
operation (read operation) equivalent to mask ROM and is most suitable for battery-driven applications.  
The on-chip debug function that is installed enables program debugging and programming.  
FEATURES  
• CPU  
− 8-bit RISC CPU (CPU name: nX-U8/100)  
− Instruction system: 16-bit instructions  
− Instruction set:  
Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit  
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic  
shift, and so on  
− Memory model ： LARGE (see U8 instruction manual)  
− On-Chip debug function  
− Minimum instruction execution time  
30.5 µs (@32.768 kHz system clock)  
0.244µs (@4.096 MHz system clock)  
• Internal memory  
− Internal 128KByte Flash ROM (64K×16 bits) (including unusable 1KByte + 2Byte TEST area)  
− Internal 4KByte Data Flash (2K×16 bits)  
− Internal 4KByte Data RAM (4096×8 bits), 240×9bit Display Allocation RAM  
• Interrupt controller  
− 1 non-maskable interrupt sources (Internal source: 1)  
− 22 maskable interrupt sources (Internal sources: 17, External sources: 5)  
• Time base counter  
− Low-speed time base counter ×1 channel  
Frequency compensation (Compensation range: Approx. −488ppm to +488ppm. Compensation accuracy: Approx.  
0.48ppm)  
− High-speed time base counter ×1 channel  
• Watchdog timer  
− Non-maskable interrupt and reset  
− Free running  
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)  
• Timers  
− 8 bits × 4 channels (Timer0-3: 16-bit x 2 configuration available by using Timer0-1 or Timer2-3)  
− Clock frequency measurement mode (in one channel of 16-bit configuration using Timer2-3)  
1/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
• Capture  
− Time base capture × 2 channels (4096 Hz to 32 Hz)  
• PWM  
− Resolution 16 bits × 1 channel  
• Synchronous serial port  
− Master/slave selectable × 2 channel  
− LSB first/MSB first selectable  
− 8-bit length/16-bit length selectable  
• UART  
− TXD/RXD × 2channel  
− Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits  
− Positive logic/negative logic selectable  
− Built-in baud rate generator  
• I2C bus interface  
− Master function only  
− Fast mode (400 kbps@4MHｚ), standard mode (100 kbps@4MHｚ, 50kbps@500kHz)  
• Melody driver  
− Scale: 29 types (Melody sound frequency: 508 Hz to 32.768 kHz)  
− Tone length: 63 types  
− Tempo: 15 types  
− Buzzer output mode (4 output modes, 8 frequencies, 16 duty levels)  
• RC oscillation type A/D converter  
− 24-bit counter  
− Time division × 2 channels  
• Successive approximation type A/D converter (SA-ADC)  
− 12-bit A/D converter  
− Input × 4 channels  
• General-purpose ports  
− Input-only port × 6 channels (including secondary functions)  
− Output-only port × 3 channels (including secondary functions)  
− Input/output port  
ML610Q418 : 18 channels (including secondary functions)  
ML610Q418C : 26 channels (including secondary functions)  
2/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
• LCD driver  
− Dot matrix can be supported.  
ML610Q418 : 192 dots max. (48 seg × 4 com)  
ML610Q418C : 160 dots max. (40 seg × 4 com)  
− 1/1 to 1/4 duty  
− 1/2, 1/3 bias (built-in bias generation circuit)  
− Frame frequency selectable: approx. 64Hz, 73Hz, 85Hz, and 102Hz  
− Bias voltage multiplying clock selectable (8 types)  
− LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable  
− Programmable display allocation function  
• Reset  
− Reset by the RESET_N pin  
− Reset by power-on detection  
− Reset when oscillation stop of the low-speed clock is detected  
− Reset by low level detection (LLD)  
The voltage which is released from reset is selectable by the code-option: 1.1V, 1.8V (Max.)  
− Reset by the watchdog timer (WDT) 2nd overflow  
• Power supply voltage detect function  
− Judgment voltages:  
− Judgment accuracy:  
One of 16 levels  
±2% (Typ.)  
• Clock  
− Low-speed clock: (This LSI cannot guarantee the operation without low-speed clock)  
Crystal oscillation (32.768 kHz)  
− High-speed clock:  
Built-in RC oscillation (500kHz)  
Built-in PLL oscillation (8.192 MHz ±2.5%), crystal/ceramic oscillation (4.096 MHz), external clock  
− Selection of high-speed clock mode by software:  
Built-in RC oscillation, built-in PLL oscillation, crystal/ceramic oscillation, external clock  
• Power management  
− HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).  
− STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are  
stopped.)  
− Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation  
clock)  
− Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals.  
• Guaranteed operating range  
− Operating temperature: −20°C to 70°C  
− Operating voltage: VDD = 1.1V to 3.6V  
3/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
• Product name – Supported Function  
The line-up of the ML610Q418 is below.  
Operating  
temperature  
- Chip (Die) -  
ML610Q418-xxxWA  
ML610Q418C-xxxWA  
ROM type  
LCD driver  
Product availability  
Under construction  
Under construction  
192 dots max.  
(48 seg x 4 com)  
Flash ROM  
Flash ROM  
-20°C to +70°C  
-20°C to +70°C  
160 dots max.  
(40 seg x 4 com)  
-100-pin plastic  
TQFP -  
Operating  
temperature  
ROM type  
Flash ROM  
Flash ROM  
LCD driver  
Product availability  
YES  
192 dots max.  
(48 seg x 4 com)  
ML610Q418-xxxTB  
ML610Q418C-xxxTB  
-20°C to +70°C  
-20°C to +70°C  
160 dots max.  
(40 seg x 4 com)  
Under construction  
xxx: ROM code number (xxx of the blank product is NNN)  
Q:Flash ROM version  
WA: Chip  
TB: TQFP  
4/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
BLOCK DIAGRAM  
ML610Q418 Block Diagram  
Figure 1 show the block diagram of the ML610Q418.  
"*" indicates the secondary function of each port.  
CPU (nX-U8/100)  
EPSW1～3  
ELR1～3  
ECSR1～3  
DSR/CSR  
PC  
GREG  
0～15  
PSW  
LR  
EA  
SP  
Program  
Memory  
(Flash)  
128Kbyte  
+
Timing  
Controller  
ALU  
BUS  
Controller  
Data  
Flash  
4Kbyte  
Instruction  
Decoder  
Instruction  
Register  
On-Chip  
ICE  
Data-bus  
SCK0*  
SIN0*  
VDD  
VSS  
INT  
2
SSIO  
×2  
SOUT0*  
RAM  
4096byte  
SCK1*  
SIN1*  
SOUT1*  
RESET_N  
TEST0  
TEST1_N  
RESET &  
TEST  
INT  
2
RXD0*  
TXD0*  
RXD1*  
TXD1*  
Interrupt  
Controller  
UART  
×2  
XT0  
XT1  
OSC0*  
OSC1*  
INT  
1
INT  
1
OSC  
WDT  
I2C  
LSCLK*  
OUTCLK*  
SDA*  
SCL*  
INT  
1
VDDL  
Power  
Capture  
PWM  
×2  
PWM0*  
MD0*  
INT  
1
IN0*  
CS0*  
RS0*  
RT0*  
CRT0*  
RCM*  
IN1*  
CS1*  
RS1*  
RT1*  
INT  
1
INT  
4
Melody  
TBC  
RC-ADC  
×2  
INT  
5
P00 to P03  
P10 to P11  
P20 to P22  
INT  
4
8bit Timer  
×4  
P30 to P35  
P40 to P47  
P50 to P53  
GPIO  
AVDD  
AVSS  
INT  
1
Display Allocation  
RAM  
VREF  
12 bit-ADC  
BLD  
AIN0, AIN1,  
AIN2, AIN3  
COM0 to COM3  
SEG0 to SEG47  
LCD  
Driver  
Display  
register  
384bit  
VL1, VL2, VL3  
C1, C2  
LCD  
BIAS  
Figure 1 ML610Q418 Block Diagram  
5/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
ML610Q418C Block Diagram  
Figure 2 show the block diagram of the ML610Q418C.  
"*" indicates the secondary function of each port.  
CPU (nX-U8/100)  
EPSW1～3  
ELR1～3  
ECSR1～3  
DSR/CSR  
PC  
GREG  
0～15  
PSW  
LR  
EA  
SP  
Program  
Memory  
(Flash)  
128Kbyte  
+
Timing  
Controller  
ALU  
BUS  
Controller  
Data  
Flash  
4Kbyte  
Instruction  
Decoder  
Instruction  
Register  
On-Chip  
ICE  
Data-bus  
SCK0*  
SIN0*  
VDD  
VSS  
INT  
2
SSIO  
×2  
SOUT0*  
RAM  
4096byte  
SCK1*  
SIN1*  
SOUT1*  
RESET_N  
TEST0  
TEST1_N  
RESET &  
TEST  
INT  
2
RXD0*  
TXD0*  
RXD1*  
TXD1*  
Interrupt  
Controller  
UART  
×2  
XT0  
XT1  
OSC0*  
OSC1*  
INT  
1
INT  
1
OSC  
WDT  
I2C  
LSCLK*  
OUTCLK*  
SDA*  
SCL*  
INT  
1
VDDL  
Power  
Capture  
×2  
PWM  
PWM0*  
MD0*  
INT  
1
IN0*  
CS0*  
RS0*  
RT0*  
CRT0*  
RCM*  
IN1*  
CS1*  
RS1*  
RT1*  
INT  
1
INT  
4
Melody  
TBC  
RC-ADC  
×2  
INT  
5
P00 to P03  
P10 to P11  
P20 to P22  
INT  
4
8bit Timer  
×4  
P30 to P35  
P40 to P47  
P50 to P53  
P60 to P67  
GPIO  
AVDD  
AVSS  
INT  
1
Display Allocation  
RAM  
VREF  
12 bit-ADC  
BLD  
AIN0, AIN1,  
AIN2, AIN3  
COM0 to COM3  
SEG0 to SEG39  
LCD  
Driver  
Display  
register  
384bit  
VL1, VL2, VL3  
C1, C2  
LCD  
BIAS  
Figure 2 ML610Q418C Block Diagram  
6/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
PIN CONFIGURATION  
ML610Q418 TQFP100 Pin Layout  
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26  
SEG44  
SEG45  
SEG46  
SEG47  
P01  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
SEG18  
SEG17  
SEG16  
SEG15  
SEG14  
SEG13  
SEG12  
SEG11  
SEG10  
SEG9  
SEG8  
SEG7  
SEG6  
SEG5  
SEG4  
SEG3  
SEG2  
SEG1  
SEG0  
COM3  
COM2  
COM1  
COM0  
C2  
P00  
P11  
P10  
P50  
P51  
P52  
P53  
P02  
P03  
P30  
P31  
P34  
P32  
8
P33  
7
P35  
6
AIN0  
AIN1  
AIN2  
AIN3  
AVDD  
5
4
3
2
1
C1  
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  
(NC): No Connection  
Figure 3 ML610Q418 TQFP100 Pin Configurations  
7/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
ML610Q418C TQFP100 Pin Layout  
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26  
P64  
P65  
P66  
P67  
P01  
P00  
P11  
P10  
P50  
P51  
P52  
P53  
P02  
P03  
P30  
P31  
P34  
P32  
P33  
P35  
AIN0  
AIN1  
AIN2  
AIN3  
AVDD  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
SEG18  
SEG17  
SEG16  
SEG15  
SEG14  
SEG13  
SEG12  
SEG11  
SEG10  
SEG9  
SEG8  
SEG7  
SEG6  
SEG5  
SEG4  
SEG3  
SEG2  
SEG1  
SEG0  
COM3  
COM2  
COM1  
COM0  
C2  
8
7
6
5
4
3
2
1
C1  
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  
(NC): No Connection  
Figure 4 ML610Q418C TQFP100 Pin Configurations  
8/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
ML610Q418 Chip Dimension  
SEG44 76  
SEG45 77  
SEG46 78  
SEG47 79  
49 SEG17  
48 SEG16  
47 SEG15  
46 SEG14  
P01 80  
45 SEG13  
44 SEG12  
P00 81  
P11 82  
P10 83  
P50 84  
43 SEG11  
42 SEG10  
41 SEG9  
P51 85  
P52 86  
P53 87  
40 SEG8  
39 SEG7  
38 SEG6  
37 SEG5  
36 SEG4  
P02 88  
P03 89  
P30 90  
P31 91  
P34 92  
P32 93  
P33 94  
P35 95  
35 SEG3  
34 SEG2  
33 SEG1  
32 SEG0  
31 COM3  
30 COM2  
29 COM1  
28 COM0  
27 C2  
AIN0 96  
AIN1 97  
AIN2 98  
AIN3 99  
AVDD 100  
26 C1  
Chip size:  
PAD count:  
2.64 mm × 3.84 mm  
100 pins  
Minimum PAD pitch:  
PAD aperture:  
Chip thickness:  
80 µm  
70 µm × 70 µm  
350 µm  
Voltage of the rear side of chip: VSS level  
Figure 5 ML610Q418 Chip Dimension  
9/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
ML610Q418C Chip Dimension  
Chip size:  
PAD count:  
2.64 mm × 3.84 mm  
100 pins  
Minimum PAD pitch:  
PAD aperture:  
Chip thickness:  
80 µm  
70 µm × 70 µm  
350 µm  
Voltage of the rear side of chip: VSS level  
Figure 6 ML610Q418C Chip Dimension  
10/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
ML610Q418 Pad Coordinates  
Table 1 ML610Q418 Pad Coordinates  
Chip Center: X=0,Y=0  
PAD  
No.  
Pad  
Name  
X
(μm)  
Y
(μm)  
PAD  
No.  
Pad  
Name  
X
(μm)  
Y
(μm)  
PAD  
No.  
Pad  
Name  
X
(μm)  
Y
(μm)  
1
Vref  
AVSS  
VSS  
-1020  
-860  
-780  
-700  
-620  
-540  
-460  
-380  
-280  
-200  
-120  
-40  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1645  
-1565  
-1485  
-1405  
-1325  
-1245  
-1165  
-1085  
-1005  
-925  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
SEG4  
SEG5  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1060  
980  
-658  
-452  
-246  
-40  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
SEG39  
SEG40  
SEG41  
SEG42  
SEG43  
SEG44  
SEG45  
SEG46  
SEG47  
P01  
-620  
-730  
1814  
1814  
1814  
1814  
1814  
1700  
1620  
1540  
1460  
1360  
1170  
1080  
920  
2
3
SEG6  
-810  
4
P20  
SEG7  
-890  
5
P21  
SEG8  
166  
-970  
6
P22  
SEG9  
372  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
7
P40  
SEG10  
SEG11  
SEG12  
SEG13  
SEG14  
SEG15  
SEG16  
SEG17  
SEG18  
SEG19  
SEG20  
SEG21  
SEG22  
SEG23  
SEG24  
SEG25  
SEG26  
SEG27  
SEG28  
SEG29  
SEG30  
SEG31  
SEG32  
SEG33  
SEG34  
SEG35  
SEG36  
SEG37  
SEG38  
578  
8
P41  
784  
9
P42  
990  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
P43  
1196  
1335  
1415  
1495  
1575  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
P44  
P00  
P45  
P11  
P46  
40  
P10  
P47  
120  
P50  
796  
VDD  
204  
P51  
590  
VSS  
284  
P52  
384  
VDDL  
364  
900  
P53  
178  
XT0  
452  
820  
P02  
-452  
-532  
-612  
-692  
-772  
-852  
-932  
-1012  
-1153  
-1233  
-1405  
-1485  
-1611  
XT1  
612  
740  
P03  
RESET_N  
TEST0  
TEST1_N  
VL1  
692  
660  
P30  
772  
580  
P31  
852  
500  
P34  
932  
420  
P32  
VL2  
1012  
1092  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
340  
P33  
VL3  
260  
P35  
C1  
180  
AIN0  
AIN1  
AIN2  
AIN3  
AVDD  
C2  
100  
COM0  
COM1  
COM2  
COM3  
SEG0  
SEG1  
SEG2  
SEG3  
20  
-60  
-140  
-220  
-300  
-380  
-460  
-540  
11/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
ML610Q418C Pad Coordinates  
Table 2 ML610Q418C Pad Coordinates  
Chip Center: X=0,Y=0  
PAD  
No.  
Pad  
Name  
X
(μm)  
Y
(μm)  
PAD  
No.  
Pad  
Name  
X
(μm)  
Y
(μm)  
PAD  
No.  
Pad  
Name  
X
(μm)  
Y
(μm)  
1
Vref  
AVSS  
VSS  
-1020  
-860  
-780  
-700  
-620  
-540  
-460  
-380  
-280  
-200  
-120  
-40  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1814  
-1645  
-1565  
-1485  
-1405  
-1325  
-1245  
-1165  
-1085  
-1005  
-925  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
SEG4  
SEG5  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1060  
980  
-658  
-452  
-246  
-40  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
SEG39  
P60  
P61  
P62  
P63  
P64  
P65  
P66  
P67  
P01  
P00  
P11  
P10  
P50  
P51  
P52  
P53  
P02  
P03  
P30  
P31  
P34  
P32  
P33  
P35  
AIN0  
AIN1  
AIN2  
AIN3  
AVDD  
-620  
-730  
1814  
1814  
1814  
1814  
1814  
1700  
1620  
1540  
1460  
1360  
1170  
1080  
920  
2
3
SEG6  
-810  
4
P20  
SEG7  
-890  
5
P21  
SEG8  
166  
-970  
6
P22  
SEG9  
372  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
-1214  
7
P40  
SEG10  
SEG11  
SEG12  
SEG13  
SEG14  
SEG15  
SEG16  
SEG17  
SEG18  
SEG19  
SEG20  
SEG21  
SEG22  
SEG23  
SEG24  
SEG25  
SEG26  
SEG27  
SEG28  
SEG29  
SEG30  
SEG31  
SEG32  
SEG33  
SEG34  
SEG35  
SEG36  
SEG37  
SEG38  
578  
8
P41  
784  
9
P42  
990  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
P43  
1196  
1335  
1415  
1495  
1575  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
1814  
P44  
P45  
P46  
40  
P47  
120  
796  
VDD  
204  
590  
VSS  
284  
384  
VDDL  
364  
900  
178  
XT0  
452  
820  
-452  
-532  
-612  
-692  
-772  
-852  
-932  
-1012  
-1153  
-1233  
-1405  
-1485  
-1611  
XT1  
612  
740  
RESET_N  
TEST0  
TEST1_N  
VL1  
692  
660  
772  
580  
852  
500  
932  
420  
VL2  
1012  
1092  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
1214  
340  
VL3  
260  
C1  
180  
C2  
100  
COM0  
COM1  
COM2  
COM3  
SEG0  
SEG1  
SEG2  
SEG3  
20  
-60  
-140  
-220  
-300  
-380  
-460  
-540  
12/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
PIN LIST  
Quaternary function  
Primary function  
PAD No.  
Secondary function  
Tertiary function  
Pin  
name  
Pin  
name  
Pin  
name  
Pin  
name  
I/O  
Function  
I/O  
Function  
I/O  
Function  
I/O  
Function  
Q418 Q418C  
Negative power  
supply pin  
3, 16  
15  
3. 16  
15  
Vss  
VDD  
Positive power  
supply pin  
Power supply pin  
for internal logic  
(internally  
17  
2
17  
2
VDDL  
generated)  
Negative power  
supply pin for  
successive  
approximation type  
ADC  
Positive power  
supply pin for  
successive  
approximation type  
ADC  
AVSS  
100  
1
100  
1
AVDD  
Reference power  
supply pin for  
successive  
VREF  
approximation type  
ADC  
Successive  
approximation type  
ADC input  
96  
97  
98  
99  
96  
97  
98  
99  
AIN0  
AIN1  
AIN2  
AIN3  
Successive  
approximation type  
ADC input  
Successive  
approximation type  
ADC input  
Successive  
approximation type  
ADC input  
Power supply pin  
for LCD bias  
(internally  
23  
24  
25  
26  
27  
23  
24  
25  
26  
27  
VL1  
VL2  
VL3  
C1  
C2  
generated)  
Power supply pin  
for LCD bias  
(internally  
generated)  
Power supply pin  
for LCD bias  
(internally  
generated)  
Capacitor  
connection pin for  
LCD bias  
generation  
Capacitor  
connection pin for  
LCD bias  
generation  
Test pin  
21  
22  
20  
21  
22  
20  
TEST0  
I/O  
Test pin  
TEST1_N  
RESET_N  
I
I
Reset input pin  
Low-speed clock  
oscillation pin  
Low-speed clock  
oscillation pin  
Input port,  
18  
19  
18  
19  
XT0  
XT1  
I
O
P00/EXI0/  
CAP0  
External interrupt,  
Capture 0 input  
81  
81  
I
13/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
Quaternary function  
Primary function  
PAD No.  
Secondary function  
Tertiary function  
Pin  
name  
Pin  
name  
Pin  
name  
Pin  
name  
I/O  
Function  
I/O  
Function  
I/O  
Function  
I/O  
Function  
Q418 Q418C  
Input port,  
P01/EXI1/  
CAP1  
External interrupt,  
Capture 1 input  
Input port,  
External interrupt,  
UART0 received  
data  
80  
88  
80  
88  
I
I
P02/EXI2  
/RXD0  
Input port,  
P03/EXI3  
/RXD1  
External interrupt  
UART1 received  
data  
89  
89  
I
High-speed  
oscillation  
Input port  
83  
82  
4
83  
82  
4
P10  
I
OSC0  
OSC1  
I
High-speed  
oscillation  
Input port  
P11  
I
O
O
O
O
Low-speed  
clock output  
High-speed  
clock output  
Melody 0  
Output port  
Output port  
Output port  
P20/LED0  
P21/LED1  
P22/LED2  
O
O
O
LSCLK  
OUTCLK  
MD0  
5
5
6
6
output  
RC type ADC0  
oscillation  
input pin  
Input/output port  
Input/output port  
90  
91  
90  
91  
P30  
P31  
I/O  
I/O  
IN0  
I
RC type ADC0  
reference  
capacitor  
CS0  
O
connection pin  
RC type ADC0  
reference  
resistor  
connection pin  
Input/output port  
Input/output port  
93  
94  
93  
94  
P32  
P33  
I/O  
I/O  
RS0  
RT0  
O
O
RC type ADC0  
measurement  
resistor sensor  
connection pin  
RC type ADC0  
resistor/capaci  
tor sensor  
Input/output port  
PWM output  
92  
92  
P34  
I/O  
RCT0  
O
PWM0  
O
connection pin  
RC type ADC  
oscillation  
monitor  
Input/output port  
Input/output port  
Input/output port  
95  
7
95  
7
P35  
P40  
P41  
I/O  
I/O  
I/O  
RCM  
SDA  
SCL  
O
I
I2C data  
input/output  
SSIO0 data  
input  
I/O  
I/O  
SIN0  
SCK0  
SSIO0  
synchronous   
I2C clock  
input/output  
8
8
I/O  
clock  
UART0 data  
input  
UART0 data  
output  
SSIO0 data  
output  
Input/output port  
Input/output port  
9
9
P42  
P43  
I/O  
I/O  
RXD0  
TXD0  
I
SOUT0  
PWM0  
O
O
UART1 data  
output  
PWM output TXD1  
O
10  
10  
O
Input/output port,  
Timer 0/Timer  
2/PWM0 external  
clock input  
RC type ADC1  
oscillation  
input pin  
P44/T02P  
0CK  
SSIO0 data  
11  
12  
11  
12  
I/O  
I/O  
IN1  
I
SIN0  
I
input  
Input/output port,  
Timer 1/Timer 3  
external clock input  
RC type ADC  
oscillation  
monitor  
SSIO0  
synchronous   
clock  
P45/T13C  
K
CS1  
O
SCK0  
I/O  
RC type ADC  
oscillation  
monitor  
SSIO0 data  
Input/output port  
Input/output port  
13  
14  
13  
14  
P46  
P47  
I/O  
I/O  
RS1  
RT1  
O
O
SOUT0  
O
output  
RC type ADC  
oscillation  
14/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
Quaternary function  
Primary function  
PAD No.  
Secondary function  
Tertiary function  
Pin  
name  
Pin  
name  
Pin  
name  
Pin  
name  
I/O  
I/O  
I/O  
Function  
I/O  
Function  
I/O  
Function  
I/O  
Function  
Q418 Q418C  
monitor  
RC type ADC  
oscillation  
monitor  
Input/output port,  
External interrupt  
SSIO1 data  
input  
84  
85  
84  
85  
P50/EXI8  
P51/EXI8  
MD0  
O
SIN1  
I
SSIO1  
synchronous  
clock  
Input/output port,  
External interrupt  
SCK1  
I/O  
input/output  
SSIO1 data  
output  
Input/output port,  
External interrupt  
Input/output port,  
External interrupt  
UART1  
86  
87  
86  
87  
P52/EXI8  
P53/EXI8  
I/O  
I/O  
RXD1  
TXD1  
I
SOUT1  
O
received data  
UART1 data  
output  
O
LCD common pin  
LCD common pin  
LCD common pin  
LCD common pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
COM0  
COM1  
COM2  
COM3  
SEG0  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
SEG1  
SEG2  
SEG3  
SEG4  
SEG5  
SEG6  
SEG7  
SEG8  
SEG9  
SEG10  
SEG11  
SEG12  
SEG13  
SEG14  
SEG15  
SEG16  
SEG17  
SEG18  
SEG19  
SEG20  
SEG21  
SEG22  
SEG23  
SEG24  
SEG25  
SEG26  
SEG27  
SEG28  
SEG29  
SEG30  
SEG31  
SEG32  
SEG33  
SEG34  
SEG35  
SEG36  
SEG37  
SEG38  
15/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
Quaternary function  
Primary function  
PAD No.  
Secondary function  
Tertiary function  
Pin  
name  
Pin  
Pin  
name  
Pin  
name  
I/O  
Function  
I/O  
Function  
I/O  
Function  
I/O  
Function  
Q418 Q418C  
name  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
LCD segment pin  
Input/output port  
Input/output port  
Input/output port  
Input/output port  
Input/output port  
Input/output port  
Input/output port  
Input/output port  
71  
72  
73  
74  
75  
76  
77  
78  
79  
71  
72  
73  
74  
75  
76  
77  
78  
79  
SEG39  
SEG40  
SEG41  
SEG42  
SEG43  
SEG44  
SEG45  
SEG46  
SEG47  
P60  
O
O
O
O
O
O
O
O
O
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
P61  
P62  
P63  
P64  
P65  
P66  
P67  
16/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
PIN DESCRIPTION  
Primary/  
Secondary/  
Tertiary  
Pin name  
I/O  
I
Description  
Logic  
System  
Reset input pin. When this pin is set to “L” level, system reset mode is set  
and the internal section is initialized. When this pin is set to “H” level  
subsequently, program execution starts. A pull-up resistor is internally  
connected.  
RESET_N  
—
Negative  
Crystal connection pin for low-speed clock.  
XT0  
XT1  
I
—
—
—
—
A 32.768 kHz crystal oscillator (see measuring circuit 1) is connected to  
this pin. Capacitors CDL and CGL are connected across this pin and VSS  
as required.  
O
Crystal/ceramic connection pin for high-speed clock.  
A crystal or ceramic is connected to this pin (4.1 MHz max.). Capacitors  
CDH and CGH (see measuring circuit 1) are connected across this pin  
OSC0  
OSC1  
I
Secondary  
Secondary  
—
—
O
and VSS  
.
This pin is used as the secondary function of the P10 pin (OSC0) and P11  
pin (OSC1).  
Low-speed clock output pin. This pin is used as the secondary function of  
the P20 pin.  
High-speed clock output pin. This pin is used as the secondary function of  
the P21 pin.  
LSCLK  
O
O
Secondary  
Secondary  
—
—
OUTCLK  
General-purpose input port  
General-purpose input port.  
P00-P03  
I
Primary  
Primary  
Positive  
Positive  
Since these pins have secondary functions, the pins cannot be used as a  
port when the secondary functions are used.  
General-purpose input port.  
P10-P11  
I
Since these pins have secondary functions, the pins cannot be used as a  
port when the secondary functions are used.  
General-purpose output port  
General-purpose output port.  
P20-P22  
O
Primary  
Positive  
Since these pins have secondary functions, the pins cannot be used as a  
port when the secondary functions are used.  
General-purpose input/output port  
General-purpose input/output port.  
Since these pins have secondary functions, the pins cannot be used as a  
port when the secondary functions are used.  
General-purpose input/output port.  
Since these pins have secondary functions, the pins cannot be used as a  
port when the secondary functions are used.  
P30-P35  
P40-P47  
P50-P53  
I/O  
I/O  
I/O  
Primary  
Primary  
Primary  
Positive  
Positive  
Positive  
General-purpose input/output port.  
Since these pins have secondary functions, the pins cannot be used as a  
port when the secondary functions are used.  
General-purpose input/output port.  
These pins are for the ML610Q418C, but are not provided in the  
ML610Q418.  
P60-P67  
I/O  
Primary  
Positive  
17/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
Primary/  
Secondary/  
Tertiary  
Pin name  
UART  
I/O  
Description  
Logic  
UART0 data output pin. This pin is used as the secondary function of the  
P43 pin.  
UART0 data input pin. This pin is used as the secondary function of the  
P42 or the primary function of the P02 pin.  
TXD0  
O
I
Secondary Positive  
RXD0  
Primary/  
Positive  
Secondary  
UART1 data output pin. This pin is used as the quaternary function of the  
P43 pin or the secondary function of the P53.  
TXD1  
RXD1  
O
I
Secondary/ Positive  
Quaternary  
UART1 data input pin. This pin is used as the primary and secondary  
function of the P52 or the primary function of the P03 pin.  
Primary/Se Positive  
condary  
I2C bus interface  
I2C data input/output pin. This pin is used as the secondary function of the  
P40 pin. This pin has an NMOS open drain output. When using this pin as  
a function of the I2C, externally connect a pull-up resistor.  
SDA  
I/O  
Secondary Positive  
Secondary Positive  
I2C clock output pin. This pin is used as the secondary function of the P41  
pin. This pin has an NMOS open drain output. When using this pin as a  
function of the I2C, externally connect a pull-up resistor.  
SCL  
O
Synchronous serial (SSIO)  
Synchronous serial clock input/output pin. This pin is used as the tertiary  
function of the P41 or P45 pin.  
Synchronous serial data input pin. This pin is used as the tertiary function  
of the P40 or P44 pin.  
Synchronous serial data output pin. This pin is used as the tertiary  
function of the P42 or P46 pin.  
Synchronous serial clock input/output pin. This pin is used as the tertiary  
function of the P51 pin.  
Synchronous serial data input pin. This pin is used as the tertiary function  
of the P50 pin.  
Synchronous serial data output pin. This pin is used as the tertiary  
function of the P52 pin.  
SCK0  
I/O  
Tertiary  
Tertiary  
Tertiary  
Tertiary  
Tertiary  
Tertiary  
—
SIN0  
I
Positive  
Positive  
—
SOUT0  
SCK1  
SIN1  
O
I/O  
I
Positive  
Positive  
SOUT1  
O
PWM  
PWM0 output pin. This pin is used as the tertiary function of the P43 or  
P34 pin.  
PWM0 external clock input pin. This pin is used as the primary function of  
the P44 pin.  
PWM0  
O
I
Tertiary  
Primary  
Positive  
—
T0P0CK  
External interrupt  
External maskable interrupt input pins. Interrupt enable and edge  
selection can be performed for each bit by software. These pins are used  
as the primary functions of the P00-P03 pins.  
Positive/  
negative  
EXI0-3  
I
Primary  
Primary  
External maskable interrupt input pins. Interrupt enable and edge  
selection can be performed for each bit by software. These pins are used  
as the primary functions of the P50-P53 pins.  
Positive/  
negative  
EXI8  
I
Capture  
Capture trigger input pins. The value of the time base counter is captured  
in the register synchronously with the interrupt edge selected by software.  
These pins are used as the primary functions of the P00 pin (CAP0) and  
P01 pin (CAP1).  
CAP0  
I
I
Primary  
Primary  
—
—
CAP1  
Timer  
External clock input pin used for Timer 0. This pin is used as the primary  
function of the P44 pin.  
External clock input pin used for Timer 1. This pin is used as the primary  
function of the P45 pin.  
T02P0CK  
I
I
Primary  
Primary  
—
—
T13CK  
Melody  
MD0  
Melody/buzzer signal output pin. This pin is used as the secondary  
function of the P22 pin.  
Positive/  
negative  
O
O
Secondary  
Primary  
LED drive  
LED0-2  
Nch open drain output pins to drive LED.  
Positive/  
negative  
18/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
Primary/  
Secondary/  
Tertiary  
Pin name  
I/O  
Description  
Logic  
RC oscillation type A/D converter  
Channel 0 oscillation input pin. This pin is used as the secondary function  
of the P30 pin.  
Channel 0 reference capacitor connection pin. This pin is used as the  
secondary function of the P31 pin.  
This pin is used as the secondary function of the P32 pin which is the  
reference resistor connection pin of Channel 0.  
Resistor sensor connection pin of Channel 0 for measurement. This pin is  
used as the secondary function of the P34 pin.  
Resistor/capacitor sensor connection pin of Channel 0 for measurement.  
This pin is used as the secondary function of the P33 pin.  
RC oscillation monitor pin. This pin is used as the secondary function of  
the P35 pin.  
Oscillation input pin of Channel 1. This pin is used as the secondary  
function of the P44 pin.  
Reference capacitor connection pin of Channel 1. This pin is used as the  
secondary function of the P45 pin.  
Reference resistor connection pin of Channel 1. This pin is used as the  
secondary function of the P46 pin.  
IN0  
CS0  
RS0  
RT0  
CRT0  
RCM  
IN1  
I
Secondary  
Secondary  
Secondary  
Secondary  
Secondary  
Secondary  
Secondary  
Secondary  
Secondary  
Secondary  
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
I
CS1  
RS1  
RT1  
O
O
O
Resistor sensor connection pin for measurement of Channel 1. This pin is  
used as the secondary function of the P47 pin.  
Successive approximation type A/D converter  
Negative power supply pin for successive approximation type A/D  
converter.  
AVSS  
—
—
—
—
—
Positive power supply pin for successive approximation type A/D  
converter.  
Reference power supply pin for successive approximation type A/D  
converter.  
AVDD  
VREF  
—
—
—
—
Channel 0 analog input for successive approximation type A/D converter.  
AIN0  
AIN1  
AIN2  
AIN3  
I
I
I
I
—
—
—
—
—
—
—
—
Channel 1 analog input for successive approximation type A/D converter.  
Channel 2 analog input for successive approximation type A/D converter.  
Channel 3 analog input for successive approximation type A/D converter.  
LCD drive signal  
Common output pins.  
Segment output pins.  
COM0-3  
SEG0-39  
SEG40-47  
O
—
—
—
—
—
—
O
O
Segment output pins.  
These pins are for the ML610Q418, but are not provided in the  
ML610Q418C.  
LCD driver power supply  
Power supply pins for LCD bias (internally generated). Capacitors Ca, Cb,  
and Cc (see measuring circuit 1) are connected between VSS and VL1, VL2,  
and VL3 respectively.  
VL1  
VL2  
VL3  
C1  
—
—
—
—
—
—
—
—
—
Power supply pins for LCD bias (internally generated). Capacitor C12 is  
connected between C1 and C2.  
—
—
—
—
—
C2  
—
For testing  
Input/output pin for testing. A pull-down resistor is internally connected.  
Input/output pin for testing. A pull-up resistor is internally connected.  
TEST0  
TEST1_N  
Power supply  
VSS  
I/O  
I
—
—
—
—
Negative power supply pin.  
Positive power supply pin.  
—
—
—
—
—
—
—
—
—
VDD  
Positive power supply pin (internally generated) for internal logic.  
VDDL  
Capacitors CL0 and CL1 (see measuring circuit 1) are connected between  
this pin and VSS  
.
19/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
TERMINATION OF UNUSED PINS  
Table 3 shows methods of terminating the unused pins.  
Table 3 Termination of Unused Pins  
Pin  
Recommended pin termination  
VSS  
AVDD  
AVSS  
VREF  
VSS  
VSS  
AIN0, AIN1, AIN2, AIN3  
VL1, VL2, VL3  
Open  
Open  
C1, C2  
Open  
Open  
Open  
Open  
VDD or VSS  
VDD  
RESET_N  
TEST0  
TEST1_N  
P00 to P03  
P10 to P11  
P20 to P22  
P30 to P35  
P40 to P47  
P50 to P53  
P60 to P67  
COM0 to 3  
SEG0 to 47  
Open  
Open  
Open  
Open  
Open  
Open  
Open  
Note:  
It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or  
the output mode since the supply current may become excessively large if the pins are left open in the high impedance input  
setting.  
The main difference points of ML610Q418 and ML610Q418C  
Table 4 The main difference points of ML610Q418 and ML610Q418C  
Function  
LCD SEG  
PORT6  
ML610Q418  
ML610Q418C  
SEG47 to SEG0  
SEG39 to SEG0  
P60 to P67  
—
20/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
ELECTRICAL CHARACTERISTICS  
ABSOLUTE MAXIMUM RATINGS  
(VSS = 0V)  
Parameter  
Power supply voltage 1  
Power supply voltage 2  
Power supply voltage 3  
Power supply voltage 4  
Power supply voltage 5  
Power supply voltage 6  
Input voltage  
Symbol  
Condition  
Rating  
Unit  
VDD  
AVDD  
VDDL  
VL1  
Ta = 25°C  
Ta = 25°C  
−0.3 to +4.6  
−0.3 to +4.6  
−0.3 to +3.6  
−0.3 to +1.75  
−0.3 to +3.5  
−0.3 to +5.25  
−0.3 to VDD+0.3  
−0.3 to VDD+0.3  
−12 to +11  
V
V
Ta = 25°C  
V
Ta = 25°C  
V
VL2  
Ta = 25°C  
V
VL3  
Ta = 25°C  
V
VIN  
Ta = 25°C  
V
Output voltage  
VOUT  
IOUT1  
IOUT2  
PD  
Ta = 25°C  
V
Output current 1  
Port3–5, Ta = 25°C  
Port2, Ta = 25°C  
Ta = 25°C  
mA  
mA  
W
°C  
Output current 2  
−12 to +20  
Power dissipation  
0.9  
Storage temperature  
TSTG  
−55 to +150  
RECOMMENDED OPERATING CONDITIONS  
(VSS = 0V)  
Unit  
Parameter  
Symbol  
TOP  
Condition  
Range  
Operating temperature  
―
-20 to +70  
1.1 to 3.6  
1.8 to 3.6  
°C  
V
fOP = 30k to 625kHz  
fOP = 30k to 4.2MHz  
Operating voltage  
VDD  
V
VDD = 1.1～3.6V  
VDD = 1.3～3.6V  
VDD = 1.8～3.6V  
30k to 36k  
30k to 625k  
30k to 4.2M  
Operating frequency (CPU)  
fOP  
CV  
Hz  
Capacitor externally connected to  
VDD pin  
More than 2.2±30%  
µF  
µF  
CL0  
CL1  
2.2±30%  
0.1±30%  
Capacitor externally connected to  
VDDL pin  
Capacitors externally connected to  
VL1, 2, 3 pins  
Ca  
0.1±30%  
µF  
µF  
b
c
，
，
Capacitors externally connected  
across C1 and C2 pins  
C12  
0.47±30%  
21/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
CLOCK GENERATION CIRCUIT OPERATING CONDITIONS  
(VSS = 0V)  
Rating  
Typ.  
Parameter  
Symbol  
fXTL  
Condition  
Unit  
Min.  
Max.  
Low-speed crystal oscillation  
frequency  
Recommended equivalent series  
resistance value of low-speed  
crystal oscillation  
32.768k  
Hz  
RL  
40k  
Ω
CL=3pF of  
crystal  
oscillation  
CL=6pF of  
crystal  
oscillation  
CL=9pF of  
crystal  
6
Low-speed crystal oscillation  
external capacitor  
CDL/CGL  
12  
pF  
18  
oscillation  
High-speed crystal/ceramic  
oscillation frequency  
fXTH  
4.0M / 4.096M  
Hz  
pF  
CDH  
CGH  
24  
24  
High-speed crystal oscillation  
external capacitor  
OPERATING CONDITIONS OF FLASH ROM  
(VSS = 0V)  
Unit  
Rating  
Parameter  
Symbol  
Condition  
Min.  
0
Typ.  
Max.  
Flash ROM, At write/erase  
+40  
+70  
3.6  
°C  
°C  
V
Operating temperature  
Operating voltage  
Rewrite counts  
TOP  
VDD  
CEP  
Data flash memory, At write/erase  
-20  
1.8  
At write/erase  
Flash ROM  
100  
10k  
cycles  
Data flash memory  
Flash ROM  
10  
Data retention  
YDR  
years  
Data flash memory,  
10  
1000 cycles  
Chip-erase time  
tCERASE  
tBERASE  
tSERASE  
tWRITE  
85  
85  
85  
18  
100  
100  
100  
40  
ms  
ms  
ms  
µs  
Block-erase time  
Sector-erase time  
1-word (16 bits) write time  
22/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
DC CHARACTERISTICS (1/5)  
(VDD = 1.1 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C, unless otherwise specified)  
Rating  
Typ.  
Measuring  
circuit  
Parameter  
Symbol  
Condition  
Ta = 25°C  
=
Unit  
kHz  
kHz  
MHz  
Min.  
Typ.  
−10%  
Typ.  
Max.  
Typ.  
+10%  
Typ.  
500  
500  
VDD  
500kHz RC oscillation frequency  
PLL oscillation frequency*4  
fRC  
1.3 to  
3.6V  
Ta = -20 to  
+70°C  
−25%  
+25%  
LSCLK = 32.768kHz  
VDD = 1.8 to 3.6V  
fPLL  
-2.5%  
8.192 +2.5%  
Low-speed crystal oscillation start  
time*2  
TXTL  
TRC  
0.3  
50  
2
2
s
500kHz RC oscillation start time  
VDD = 1.3 to 3.6V  
500  
20  
10  
20  
µs  
High-speed crystal oscillation start  
time*3  
TXTH  
TPLL  
VDD = 1.8 to 3.6V  
―
PLL oscillation start time  
VDD = 1.8 to 3.6V  
―
1
ms  
1
Low-speed oscillation stop detect  
time*1  
TSTOP  
PRST  
PNRST  
0.2  
200  
3
Reset pulse width  
µs  
Reset noise elimination  
pulse width  
0.3  
Power-on reset activation  
power rise time  
TPOR  
10  
ms  
COLD0=0*5  
COLD0=1*5  
200  
1.1  
1.8  
1.1  
1.8  
Low level reset detection voltage  
Low level reset detection time  
Release reset voltage  
VLLR  
TLLR  
VRER  
V
µs  
V
COLD0=0*5  
COLD0=1*5  
*1: When low-speed crystal oscillation stops for duration more than the low-speed oscillation stop detect time, the system is reset to shift to  
system reset mode.  
*2 : Use 32.768kHz Crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=6pF).  
*3 : Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera).  
*4 : 1024 clock average.  
*5 : The COLD0 bit is the code-option which is set up into the Flash memory.  
Reset pulse width (PRST  
)
VIL1  
VIL1  
RESET_N  
PRST  
Reset pulse width (PRST  
)
Power-on reset activation power rise time (TPOR  
)
0.9xVDD  
VDD  
0.1xVDD  
TPOR  
Power-on reset activation power rise time (TPOR  
)
Low level reset detection time (TLLR  
)
VRER (COLD0=1)  
VDD  
VLLR (COLD0=1)  
VLLR (COLD0=0)  
VRER (COLD0=0)  
TLLR  
Release reset voltage  
Low level reset detection voltage  
Low level reset  
Low level reset detection time (TLLR  
)
23/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
DC CHARACTERISTICS (2/5)  
(VDD = 1.1 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C, unless otherwise specified)  
Rating  
Min.  
0.94  
0.96  
0.98  
1.00  
1.02  
1.04  
1.06  
1.08  
1.10  
1.12  
1.14  
1.16  
1.18  
1.20  
1.22  
1.24  
1.26  
1.28  
1.30  
1.32  
1.34  
1.36  
1.38  
1.40  
1.42  
1.44  
1.46  
1.48  
1.50  
1.52  
1.54  
1.56  
Measuring  
circuit  
Parameter  
Symbol  
Condition  
Unit  
Min.  
0.89  
0.91  
0.93  
0.95  
0.97  
0.99  
1.01  
1.03  
1.05  
1.07  
1.09  
1.11  
1.13  
1.15  
1.17  
1.19  
1.21  
1.23  
1.25  
1.27  
1.29  
1.31  
1.33  
1.35  
1.37  
1.39  
1.41  
1.43  
1.45  
1.47  
1.49  
1.51  
Min.  
0.99  
1.01  
1.03  
1.05  
1.07  
1.09  
1.11  
1.13  
1.15  
1.17  
1.19  
1.21  
1.23  
1.25  
1.27  
1.29  
1.31  
1.33  
1.35  
1.37  
1.39  
1.41  
1.43  
1.45  
1.47  
1.49  
1.51  
1.53  
1.55  
1.57  
1.59  
1.61  
CN4-0 = 00H  
CN4-0 = 01H  
CN4-0 = 02H  
CN4-0 = 03H  
CN4-0 = 04H  
CN4-0 = 05H  
CN4-0 = 06H  
CN4-0 = 07H  
CN4-0 = 08H  
CN4-0 = 09H  
CN4-0 = 0AH  
CN4-0 = 0BH  
CN4-0 = 0CH  
CN4-0 = 0DH  
CN4-0 = 0EH  
CN4-0 = 0FH  
CN4-0 = 10H  
CN4-0 = 11H  
CN4-0 = 12H  
CN4-0 = 13H  
CN4-0 = 14H  
CN4-0 = 15H  
CN4-0 = 16H  
CN4-0 = 17H  
CN4-0 = 18H  
CN4-0 = 19H  
CN4-0 = 1AH  
CN4-0 = 1BH  
CN4-0 = 1CH  
CN4-0 = 1DH  
CN4-0 = 1EH  
CN4-0 = 1FH  
VL1 voltage  
VL1  
VDD = 3.0V, Tj = 25°C  
V
1
VL1 temperature  
deviation  
VL1 voltage  
ΔVL1  
ΔVL1  
VL2  
VDD = 3.0V  
VDD = 1.3 to 3.6V  
―
―
―
-1.5  
5
―
20  
―
―
mV/°C  
mV/V  
dependency  
VL2 voltage  
1/2bias  
1/3bias  
1/2bias  
VL1×1  
VL1×2  
VDD = 3.0V,  
Tj = 25°C,  
300kΩ load  
Typ.  
×09  
Typ.  
×09  
Typ.  
×09  
VL3 voltage  
VL3  
VL1×2  
VL1×3  
―
―
V
(VL3−VSS  
)
1/3bias  
LCD bias voltage  
generation time  
TBIAS  
―
―
―
100  
ms  
24/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
DC CHARACTERISTICS (3/5)  
(VDD = 1.1 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C, unless otherwise specified)  
Rating  
Typ.  
1.35  
1.4  
Measuring  
circuit  
Parameter  
Symbol  
Condition  
Unit  
Min.  
Max.  
LD2–0 = 0H  
LD2–0 = 1H  
LD2–0 = 2H  
LD2–0 = 3H  
LD2–0 = 4H  
LD2–0 = 5H  
LD2–0 = 6H  
LD2–0 = 7H  
LD2–0 = 8H  
LD2–0 = 9H  
LD2–0 = 0AH  
LD2–0 = 0BH  
LD2–0 = 0CH  
LD2–0 = 0DH  
LD2–0 = 0EH  
LD2–0 = 0FH  
1.45  
1.5  
1.6  
1.7  
1.8  
1.9  
BLD threshold  
voltage  
Typ.  
−2%  
Typ.  
+2%  
VBLD  
VDD = 1.35 to 3.6V  
V
2.0  
2.1  
2.2  
2.3  
2.4  
2.5  
2.7  
2.9  
BLD threshold  
voltage  
temperature  
deviation  
1
0
∆VBLD  
IDD1  
IDD2  
IDD3  
IDD4  
VDD = 1.35 to 3.6V  
%/°C  
µA  
Ta = 25°C  
0.55  
0.9  
8
CPU: In STOP state.  
Low-speed/high-speed oscillation:  
stopped.  
Supply current 1  
Supply current 2  
Supply current 3  
Supply current 4  
Ta = -20  
to +70°C  
CPU: In HALT state (LTBC, RTC:  
Operating*3*5).  
Ta = 25°C  
1.1  
2.2  
9
µA  
High-speed oscillation: Stopped.  
LCD/BIAS circuits: Stopped.  
Ta = -20  
to +70°C  
CPU: In 32.768kHz operating  
state.*1*3  
Ta = 25°C  
6.5  
8
µA  
High-speed oscillation: Stopped.  
LCD/BIAS circuits: Operating.*2  
Ta = -20  
15  
to +70°C  
Ta = 25°C  
80  
100  
120  
1.1  
CPU: In 500kHz CR operating state.  
LCD/BIAS circuits: Operating.*2*3  
µA  
Ta = -20  
to +70°C  
CPU: In 4.096MHz operating  
state.*2*3  
Ta = 25°C  
1.0  
Supply current 5  
Supply current 6  
PLL: In oscillating state.  
LCD/BIAS circuits: Operating. *2  
VDD = 1.8 to 3.6V  
CPU: In 4.096MHz operating state.*2  
PLL: In oscillating state. *3*4  
A/D: In operating state.  
LCD/BIAS circuits: Operating. *2  
VDD = AVDD = 3.0V  
IDD5  
IDD6  
mA  
Ta = -20  
1.2  
to +70°C  
Ta = 25°C  
1.6  
1.7  
2.5  
mA  
Ta = -20  
to +70°C  
*1 : CPU operating rate is 100% (No HALT state).  
*2 : All SEGs: off waveform, No LCD panel load, 1/3 bias, 1/3 duty, Frame frequency: Approx. 64 Hz,  
Bias voltage multiplying clock: 1/128 LSCLK (256Hz)  
*3 : Use 32.768kHz crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=6pF).  
*4 : Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera).  
*5 : Significant bits of BLKCON0~BLKCON4 registers are all “1”.  
25/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
DC CHARACTERISTICS (4/5)  
(VDD = 1.1 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C, unless otherwise specified)  
Rating  
Typ.  
Measuring  
circuit  
Parameter  
Symbol  
Condition  
Unit  
Min.  
Max.  
Output voltage 1  
(P20–P22/2nd  
function is  
IOH1 = −0.5mA, VDD = 1.8 to 3.6V  
IOH1 = -0.1mA, VDD = 1.3 to 3.6V  
VDD−0.5  
VDD−0.3  
VOH1  
IOH1 = -0.03mA, VDD = 1.1 to 3.6V  
VDD−0.3  
selected)  
(P30–P36)  
(P40–P47)  
(P50–P53)  
(P60–P67)*1  
IOL1 = +0.5mA, VDD = 1.8 to 3.6V  
IOL1 = +0.1mA, VDD = 1.3 to 3.6V  
0.5  
0.5  
VOL1  
VOH2  
IOL1 = +0.03mA, VDD = 1.1 to 3.6V  
0.3  
IOH1 = −0.5mA, VDD = 1.8 to 3.6V  
IOH1 = -0.1mA, VDD = 1.3 to 3.6V  
IOH1 = -0.03mA, VDD = 1.1 to 3.6V  
IOL2 = +5mA, VDD = 1.8 to 3.6V  
VDD−0.5  
VDD−0.3  
VDD−0.3  
Output voltage 2  
(P20–P22/2nd  
function is Not  
selected)  
V
2
VOL2  
VOL3  
0.5  
IOL3 = +3mA, VDD = 2.0 to 3.6V  
(when I2C mode is selected)  
Output voltage 3  
(P40–P41)  
0.4  
VOH4  
VOML4  
VOML4S  
VOLM4  
VOLM4S  
VOL4  
IOH4 = −0.05mA, VL1=1.2V  
IOMH4 = +0.05mA, VL1=1.2V  
IOMH4S = −0.05mA, VL1=1.2V  
IOML4 = +0.05mA, VL1=1.2V  
IOML4S = −0.05mA, VL1=1.2V  
IOL4 = +0.05mA, VL1=1.2V  
VL3−0.2  
VL2+0.2  
Output voltage 4  
(COM0–3)  
VL2−0.2  
(SEG0–39)  
VL1+0.2  
(SEG40–47)*2  
VL1−0.2  
0.2  
Output leakage  
(P20–P22)  
(P30–P35)  
(P40–P47)  
(P50–P53)  
(P60–P67)*1  
IOOH  
VOH = VDD (in high-impedance state)  
VOL = VSS (in high-impedance state)  
1
µA  
3
IOOL  
IIH1  
−1  
VIH1 = VDD  
0
−300  
−300  
−300  
300  
300  
300  
1
−20  
-10  
-2  
Input current 1  
(RESET_N)  
(TEST1_N)  
VDD = 1.8 to 3.6V  
−600  
−600  
−600  
20  
IIL1  
VIL1 = VSS  
VIH1 = VDD  
VDD = 1.3 to 3.6V  
VDD = 1.1 to 3.6V  
VDD = 1.8 to 3.6V  
VDD = 1.3 to 3.6V  
VDD = 1.1 to 3.6V  
600  
600  
600  
IIH1  
IIL1  
IIH2  
10  
Input current 1  
(TEST0)  
2
VIL1 = Vss  
-1  
µA  
4
VDD = 1.8 to 3.6V  
VDD = 1.3 to 3.6V  
VDD = 1.1 to 3.6V  
VDD = 1.8 to 3.6V  
VDD = 1.3 to 3.6V  
VDD = 1.1 to 3.6V  
2
30  
200  
200  
200  
−2  
-0.2  
-0.01  
1
VIH2 = VDD  
(when pulled-down)  
Input current 2  
(P00–P03)  
(P10–P11)  
(P30–P35)  
(P40–P47)  
(P50–P53)  
(P60–P67)*1  
0.2  
0.01  
−200  
−200  
−200  
30  
30  
−30  
−30  
−30  
VIL2 = VSS  
(when pulled-up)  
IIL2  
IIH2Z  
IIL2Z  
VIH2 = VDD (in high-impedance state)  
VIL2 = VSS (in high-impedance state)  
−1  
*1: ML610Q418C only  
*2: ML610Q418 only  
26/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
DC CHARACTERISTICS (5/5)  
(VDD = 1.1 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C, unless otherwise specified)  
Rating  
Measuring  
circuit  
Parameter  
Symbol  
Condition  
Unit  
Min.  
Typ.  
Max.  
VDD  
Input voltage 1  
(RESET_N)  
(TEST1_N)  
(TEST0)  
(P00–P03)  
(P10–P11)  
(P31–P35)  
(P40–P43)  
(P45–P47)  
(P50–P53)  
(P60–P67)*1  
0.7  
×VDD  
VDD = 1.3 to 3.6V  
VIH1  
0.7  
×VDD  
VDD = 1.1 to 3.6V  
VDD = 1.3 to 3.6V  
VDD  
0.3  
×VDD  
0
V
5
VIL1  
0.2  
×VDD  
VDD = 1.1 to 3.6V  
0
0.7  
×VDD  
VIH2  
VIL2  
VDD  
Input voltage 2  
(P30, P44)  
0.3  
×VDD  
0
Input pin  
capacitance  
(P00–P03)  
(P10–P11)  
(P30–P35)  
(P40–P47)  
(P50–P53)  
(P60–P67)*1  
f = 10kHz  
Vrms = 50mV  
Ta = 25°C  
CIN  
5
pF  
*1: ML610Q418C only  
27/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
MEASURING CIRCUITS  
MEASURING CIRCUIT 1  
CGL  
XT0  
CDL  
XT1  
C2  
C1  
32.768 kHz  
Crystal  
C12  
CGH  
CDH  
CV  
CL0  
CL1  
Ca,Cb,Cc  
C12  
: >2.2µF  
: 2.2µF  
: 0.1µF  
: 0.1µF  
: 0.47µF  
: 6pF  
P10/OSC0  
P11/OSC1  
4.096MHz  
Crystal  
VSS AVSS  
VL1 VL2 VL3  
VDDL  
VDD AVDDVREF  
CGL,CDL  
CGH,CDH  
: 24pF  
A
32.768 kHz crystal resonator  
CV  
CL1  
CL0  
Ca Cb Cc  
DT-26 (Load capacitance 6pF)  
(Made by KDS:DAISHINKU CORP.)  
4.096MHz crystal:  
HC49SFWB (Kyocera)  
MEASURING CIRCUIT 2  
(*2)  
VIH  
V
(*1)  
VIL  
VDD VDDL VL1 VL2  
AVDD VREF VSS AVSS  
VL3  
(*1) Input logic circuit to determine the specified measuring conditions.  
(*2) Measured at the specified output pins.  
28/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
MEASURING CIRCUIT 3  
(*2)  
VIH  
A
(*1)  
VIL  
VDD VDDL VL1 VL2  
AVDD VREF VSS AVSS  
VL3  
*1: Input logic circuit to determine the specified measuring conditions.  
*2: Measured at the specified output pins.  
MEASURING CIRCUIT 4  
(*3)  
A
VDD VDDL VL1 VL2  
AVDD VREF VSS AVSS  
VL3  
*3: Measured at the specified output pins.  
MEASURING CIRCUIT 5  
VIH  
(*1)  
VIL  
VDD VDDL VL1 VL2  
AVDD VREF VSS AVSS  
VL3  
*1: Input logic circuit to determine the specified measuring conditions.  
29/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
AC CHARACTERISTICS (External Interrupt)  
(VDD = 1.1 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C, unless otherwise specified)  
Rating  
Parameter  
Symbol  
tNUL  
Condition  
Unit  
Min.  
76.8  
Typ.  
Max.  
Interrupt: Enabled (MIE = 1),  
CPU: NOP operation  
External interrupt disable period  
106.8  
µs  
System clock: 32.768kHz  
P00–P03  
(Rising-edge interrupts)  
tNUL  
P00–P03  
(Falling-edge interrupts)  
tNUL  
P00–P03  
(Both-edge interrupts)  
tNUL  
AC CHARACTERISTICS (UART)  
(VDD = 1.3 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C, unless otherwise specified)  
Rating  
Parameter  
Transmit baud rate  
Receive baud rate  
Symbol  
Condition  
Unit  
Min.  
Typ.  
Max.  
tTBRT  
tRBRT  
BRT*1  
s
s
BRT*1  
−3%  
BRT*1  
+3%  
BRT*1  
*1: Baud rate period (including the error of the clock frequency selected) set with the UART baud rate register (UA0BRTL,H)  
and the UART mode register 0 (UA0MOD0).  
tTBRT  
TXD0*  
tRBRT  
RXD0*  
*: Indicates the secondary function of the port.  
30/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
AC CHARACTERISTICS (Synchronous Serial Port)  
(VDD = 1.3 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C, unless otherwise specified)  
Rating  
Parameter  
Symbol  
Condition  
Unit  
Min.  
10  
Typ.  
Max.  
When high-speed oscillation is  
not active*2 (VDD = 1.3 to 3.6V)  
When high-speed oscillation is  
active*3 (VDD = 1.8 to 3.6V)  
µs  
µs  
s
SCLKn input cycle  
(slave mode)  
tSCYC  
tSCYC  
tSW  
1
4
SCLKn*1  
SCLKn output cycle  
(master mode)  
When high-speed oscillation is  
not active*2 (VDD = 1.3 to 3.6V)  
When high-speed oscillation is  
active*3 (VDD = 1.8 to 3.6V)  
µs  
µs  
s
SCLKn input pulse width  
(slave mode)  
0.4  
SCLKn output pulse width  
(master mode)  
SCLKn*1  
×0.4  
SCLKn*1  
×0.5  
SCLKn*1  
×0.6  
tSW  
When high-speed oscillation is  
not active*2 (VDD = 1.3 to 3.6V)  
When high-speed oscillation is  
active*3 (VDD = 1.8 to 3.6V)  
500  
240  
500  
240  
SOUTn output delay time  
(slave mode)  
tSD  
ns  
When high-speed oscillation is  
not active*2 (VDD = 1.3 to 3.6V)  
When high-speed oscillation is  
active*3 (VDD = 1.8 to 3.6V)  
SOUTn output delay time  
(master mode)  
tSD  
tSS  
tSS  
ns  
ns  
ns  
SINn input setup time  
(slave mode)  
80  
When high-speed oscillation is  
not active*2 (VDD = 1.3 to 3.6V)  
When high-speed oscillation is  
active*3 (VDD = 1.8 to 3.6V)  
500  
240  
300  
80  
SINn input setup time  
(master mode)  
When high-speed oscillation is  
not active*2 (VDD = 1.3 to 3.6V)  
When high-speed oscillation is  
active*3 (VDD = 1.8 to 3.6V)  
SINn input hold time  
n= 0,1  
tSH  
ns  
*1: Clock period selected with SnCK3–0 of the serial port n mode register (SIOnMOD1)  
*2: When RC oscillation is selected with OSCM1–0 of the frequency control register (FCON0)  
*3: When Crystal/ceramic oscillation, built-in PLL oscillation, or external clock input is selected with OSCM1–0 of the frequency  
control register (FCON0)  
tSCYC  
tSW  
tSW  
SCLKn*  
SOUTn*  
SINn*  
tSD  
tSD  
tSS  
tSH  
*: Indicates the secondary function of the port.  
31/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
AC CHARACTERISTICS (I2C Bus Interface: Standard Mode 100 kHz)  
(VDD = 1.8 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C, unless otherwise specified)  
Rating  
Parameter  
Symbol  
Condition  
Unit  
Min.  
0
Typ.  
Max.  
100  
SCL clock frequency  
fSCL  
kHz  
SCL hold time  
tHD:STA  
4.0  
µs  
(start/restart condition)  
SCL ”L” level time  
SCL ”H” level time  
SCL setup time  
(restart condition)  
SDA hold time  
tLOW  
tHIGH  
4.7  
4.0  
µs  
µs  
tSU:STA  
4.7  
µs  
tHD:DAT  
tSU:DAT  
0
0.25  
3.45  
µs  
µs  
SDA setup time  
SDA setup time  
(stop condition)  
Bus-free time  
tSU:STO  
tBUF  
4.0  
4.7  
µs  
µs  
AC CHARACTERISTICS (I2C Bus Interface: Fast Mode 400 kHz)  
(VDD = 1.8 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C, unless otherwise specified)  
Rating  
Parameter  
Symbol  
Condition  
Unit  
Min.  
0
Typ.  
Max.  
400  
SCL clock frequency  
fSCL  
kHz  
SCL hold time  
tHD:STA  
0.6  
µs  
(start/restart condition)  
SCL ”L” level time  
SCL ”H” level time  
SCL setup time  
(restart condition)  
SDA hold time  
tLOW  
tHIGH  
1.3  
0.6  
µs  
µs  
tSU:STA  
0.6  
µs  
tHD:DAT  
tSU:DAT  
0
0.1  
0.9  
µs  
µs  
SDA setup time  
SDA setup time  
(stop condition)  
Bus-free time  
tSU:STO  
tBUF  
0.6  
1.3  
µs  
µs  
Start  
condition  
Restart  
condition  
Stop  
condition  
P40/SDA  
P41/SCL  
tBUF  
tSU:STO  
tHD:STA  
tLOW tHIGH  
tSU:STA tHD:STA  
tSU:DAT tHD:DAT  
32/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
AC CHARACTERISTICS (RC Oscillation A/D Converter)  
Condition for VDD=1.8 to 3.6V  
(VDD=1.8 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C, unless otherwise specified)  
Rating  
Typ.  
Parameter  
Symbol  
Condition  
Unit  
Min.  
1
Max.  
RS0,RS1,RT0,  
RT0-1,RT1  
fOSC1  
Oscillation resistor  
―
―
CS0, CT0, CS1≥740pF  
kΩ  
457.3  
53.48  
5.43  
7.972  
0.981  
0.099  
525.2  
58.18  
5.89  
9.028  
1
575.1  
62.43  
6.32  
9.782  
1.019  
0.104  
kHz  
kHz  
kHz  
Resistor for oscillation=1kΩ  
Resistor for oscillation=10kΩ  
Resistor for oscillation=100kΩ  
RT0, RT0-1, RT1=1kΩ  
RT0, RT0-1, RT1=10kΩ  
RT0, RT0-1, RT1=100kΩ  
Oscillation frequency  
VDD = 3.0V  
fOSC2  
fOSC3  
Kf1  
Kf2  
Kf3  
RS to RT oscillation  
frequency ratio *1  
VDD = 3.0V  
0.101  
*1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the  
same conditions.  
fOSCX(RT0-CS0 oscillation)  
fOSCX(RS0-CS0 oscillation)  
( x = 1, 2, 3 )  
fOSCX(RT0-1-CS0 oscillation)  
fOSCX(RS0-CS0 oscillation)  
fOSCX(RT1-CS1 oscillation)  
fOSCX(RS1-CS1 oscillation)  
Kfx =  
,
,
CVR0  
CVR1  
RT0, RT0-1, RT1: 1kΩ/10kΩ/100kΩ  
RS0, RS1: 10kΩ  
CS0, CT0, CS1: 560pF  
CVR0, CVR1: 820pF  
IN0 CS0 RCT0 RS0  
IN1 CS1 RS1 RT1  
RCM  
RT0  
VIH  
Frequency measurement (fOSCX  
)
(Note 1)  
VIL  
VDD VDDL  
VSS  
CV  
CL  
*1: Input logic circuit to determine the  
specified measuring conditions.  
33/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
Condition for VDD=1.25 to 3.6V  
(VDD=1.25 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C, unless otherwise specified)  
Rating  
Typ.  
Parameter  
Symbol  
Condition  
Unit  
Min.  
1
Max.  
RS0,RS1,RT0,  
RT0-1,RT1  
fOSC1  
Oscillation resistor  
―
―
CS0, CT0, CS1≥740pF  
kΩ  
81.93  
35.32  
5.22  
93.16  
38.75  
5.65  
2.381  
1
0.147  
94.58  
38.87  
5.622  
2.432  
1
101.2  
41.48  
6.03  
kHz  
kHz  
kHz  
kHz  
kHz  
kHz  
Resistor for oscillation=6kΩ  
Resistor for oscillation=15kΩ  
Resistor for oscillation=105kΩ  
RT0, RT0-1, RT1=1kΩ  
Oscillation frequency  
VDD = 1.5V  
fOSC2  
fOSC3  
Kf1  
Kf2  
Kf3  
fOSC1  
fOSC2  
fOSC3  
Kf1  
Kf2  
Kf3  
2.139  
0.973  
0.142  
85.28  
35.72  
5.189  
2.227  
0.982  
0.141  
2.632  
1.028  
0.152  
103.3  
41.78  
6.012  
2.626  
1.018  
0.149  
RS to RT oscillation  
frequency ratio *1  
VDD = 1.5V  
RT0, RT0-1, RT1=10kΩ  
RT0, RT0-1, RT1=100kΩ  
Resistor for oscillation=6kΩ  
Resistor for oscillation=15kΩ  
Resistor for oscillation=105kΩ  
RT0, RT0-1, RT1=1kΩ  
RT0, RT0-1, RT1=10kΩ  
RT0, RT0-1, RT1=100kΩ  
Oscillation frequency  
VDD = 3.0V  
RS to RT oscillation  
frequency ratio *1  
VDD = 3.0V  
0.145  
*1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the  
same conditions.  
fOSCX(RT0-CS0 oscillation)  
fOSCX(RS0-CS0 oscillation)  
( x = 1, 2, 3 )  
fOSCX(RT0-1-CS0 oscillation)  
fOSCX(RS0-CS0 oscillation)  
fOSCX(RT1-CS1 oscillation)  
fOSCX(RS1-CS1 oscillation)  
Kfx =  
,
,
CVR0  
CVR1  
RT0, RT0-1, RT1: 1kΩ/10kΩ/100kΩ  
RA0, RA0-1, RA1: 5kΩ  
RS0, RS1: 15kΩ  
CS0, CT0, CS1: 560pF  
CVR0, CVR1: 820pF  
IN0 CS0 RCT0 RS0 RT0  
IN1 CS1 RS1 RT1  
VIH  
RCM  
Frequency measurement (fOSCX)  
(Note 1)  
VIL  
VDD VDDL  
VSS  
CV  
CL  
*1: Input logic circuit to determine the  
specified measuring conditions.  
Note:  
- Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors  
and IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wire between IN0/IN1 and RS0/RS1. The coupling  
capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise  
around the node.  
- When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to  
the signal.  
- Please make wiring to components (capacitor, resistor and etc.) necessary for objective measurement. Wiring to reserved  
components may affect to the A/D conversion operation by noise the components itself may have.  
34/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
Electrical Characteristics of Successive Approximation Type A/D Converter  
(VDD = 1.8 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C, unless otherwise specified)  
Rating  
Parameter  
Symbol  
n
Condition  
Unit  
bit  
Min.  
Typ.  
Max.  
12  
Resolution  
2.7V ≤ VREF ≤ 3.6V  
2.2V ≤ VREF ≤ 2.7V  
2.7V ≤ VREF ≤ 3.6V  
2.2V ≤ VREF ≤ 2.7V  
−4  
−6  
−3  
−5  
−6  
−6  
2.2  
+4  
Integral non-linearity error  
INL  
+6  
+3  
Differential non-linearity error  
DNL  
LSB  
+5  
Zero-scale error  
Full-scale error  
Reference voltage  
VOFF  
FSE  
VREF  
+6  
+6  
AVDD  
V
SACK = 0  
(HSCLK = 375kHz to 625kHz)  
SACK = 1  
25  
Conversion time  
tCONV  
φ/CH  
112  
(HSCLK = 1.5MHz to 4.2MHz)  
φ: Period of high-speed clock (HSCLK)  
AVDD  
Reference  
voltage  
VREF  
VDD  
VDDL  
1µF  
2.2µF  
0.1µF  
A
AIN0,  
AIN1,  
RI≤5kΩ  
−
1µF  
AIN2,  
AIN3  
VSS  
+
Analog input  
AVSS  
0.1µF  
35/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
PACKAGE DIMENSIONS  
(Unit: mm)  
Notes for Mounting the Surface Mount Type Package  
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,  
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package  
code and desired mounting conditions (reflow method, temperature and times).  
36/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
REVISION HISTORY  
Page  
Document No.  
Date  
May.10.2016  
Description  
Previous Current  
Edition  
–
Edition  
–
FEDL610Q418-01  
Final edition 1.0  
37/38  
FEDL610Q418-01  
ML610Q418/ML610Q418C  
Notes  
1) The information contained herein is subject to change without notice.  
2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can  
break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure,  
please take safety measures such as complying with the derating characteristics, implementing redundant and fire  
prevention designs, and utilizing backups and fail-safe procedures. LAPIS Semiconductor shall have no responsibility for  
any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor.  
3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate  
the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing  
circuits for mass production.  
4) The technical information specified herein is intended only to show the typical functions of the Products and examples of  
application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property  
rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this  
document; therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights  
owned by third parties, arising out of the use of such technical information.  
5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication, consumer systems,  
gaming/entertainment sets) as well as the applications indicated in this document.  
6) The Products specified in this document are not designed to be radiation tolerant.  
7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and  
consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary  
communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and  
power transmission systems.  
8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power  
control systems, and submarine repeaters.  
9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the  
recommended usage conditions and specifications contained herein.  
10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document.  
However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall have  
no responsibility for any damages arising from any inaccuracy or misprint of such information.  
11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.  
For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no  
responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations.  
12) When providing our Products and technologies contained in this document to other countries, you must abide by the  
procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US  
Export Administration Regulations and the Foreign Exchange and Foreign Trade Act.  
13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor.  
Copyright 2016 LAPIS Semiconductor Co., Ltd.  
2-4-8 Shinyokohama, Kouhoku-ku,  
Yokohama 222-8575, Japan  
http://www.lapis-semi.com/en/  
38/38  

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SI9135LG-T1

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SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

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SI9135_11

 SMBus Multi-Output Power-Supply Controller

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SI9136_11

 Multi-Output Power-Supply Controller

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SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

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SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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