ISPLSI1024-90LT [LATTICE]
EE PLD, 17ns, 96-Cell, CMOS, PQFP100, TQFP-100;
| 型号： | ISPLSI1024-90LT |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | EE PLD, 17ns, 96-Cell, CMOS, PQFP100, TQFP-100 时钟 输入元件 可编程逻辑 |
| 文件： | 总14页 (文件大小：395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ispLSI® 1024 Device Datasheet
June 2010
All Devices Discontinued!
Product Change Notification (PCN) #09-10 has been issued to discontinue all devices in
this data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
ispLSI 1024
Ordering Part Number
ispLSI 1024-60LJ
ispLSI 1024-80LJ
ispLSI 1024-90LJ
ispLSI 1024-60LJI
ispLSI 1024-60LT
ispLSI 1024-80LT
ispLSI 1024-90LT
ispLSI 1024-60LTI
Product Status
Discontinued
Reference PCN
PCN#09-10
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
®
ispLSI 1024
In-System Programmable High Density PLD
uFncutniocnatiloBnloalcBklDoicakgDraimagram
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— High-Speed Global Interconnect
— 4000 PLD Gates
— 48 I/O Pins, Six Dedicated Inputs
— 144 Registers
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Fast Random Logic
— Security Cell Prevents Unauthorized Copying
A0
A1
A2
A
A4
A5
A6
A
C7
C6
C5
C
C1
C0
D
D
D
Q
Q
Q
Q
Array
GLB
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 90 MHz Maximum Operating Frequency
—— tfpmdax= =1260nsMPHrzofpoargIantdiounstDrieallaaynd Military/883 Devices
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 100% Tested
Global RoutinPool RP)
B0 B1 B2 3 B4 BB6 B7
Ouut Routing Pool
• IN-SYSTEM PROGRAMMABLE
CLK
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, ReduceTimeo-
Market, and Improved Product Quality
0139-A-isp
— Reprogram Soldered Devices for Far Debgin
Descriptio
• COMBINES EASE OF USE AND THSTEM
SPEED OF PLDs WITH THE DENSITX-
IBILITY OF FIELD PROGRAMMABLE RRAYS
The ispL1024 is a High-Density Programmable Logic
Dvice contining 144 Registers, 48 Universal I/O pins,
six Ddicated Input pins, four Dedicated Clock Input pins
and lobal Routing Pool (GRP). The GRP provides
ompleteinterconnectivitybetweenalloftheseelements.
The ispLSI 1024 features 5-Volt in-system programma-
bility and in-system diagnostic capabilities. It is the first
device which offers non-volatile reprogrammability of the
logic, as well as the interconnect to provide truly
reconfigurable systems.
— Complete Programmable Device Can mbine Glue
Logic and Structured Designs
— Four Dedicated Clock put Pins
— Synchronous and AsyncronouClocks
— Flexible Pin Placement
— Optimized Glol Routing Pool Provides G
Interconnectivity
• ispDesignRT™ – OGIC COMPILR AND COM-
PLETE ISP ESIGN SYSTEMFROM HDL
SYNTHESIS ROUGH IN-SYSTEM PRGRAMING
The basic unit of logic on the ispLSI 1024 device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. C7 (see figure 1). There are a total of 24 GLBs in the
ispLSI 1024 device. Each GLB has 18 inputs, a program-
mable AND/OR/XOR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
other GLB on the device.
— Superior Qality of Results
— Tightly Integrated with Leding Vendor Tools
— Productivity Enhancing Timg Anazer, Explore
Tools, Timing Simulatoand ispAALYZER™
— PC and UNIX Platfrms
Copyright©1999LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
February 1999
1024_06
1
Specifications ispLSI 1024
Functional Block Diagram
Figure 1.ispLSI 1024 Functional Block Diagram
RESET
Generic
Logic Blocks
(GLBs)
IN 5
IN 4
I/O 47
C
I/O 46
I/O 0
I/O 45
A0
I/O 1
I/
C6
C5
C4
C3
C2
C1
I/O 2
I/O 3
A1
I/
I/O 4
A2
I/O 5
I/O 4
Global
Routing
P
I/O 6
I/O 7
A3
A4
A5
A6
A7
I/9
/O 38
I/O 37
I/O 36
GR
I/O 8
I/O 9
I/O 10
I/O 11
I/O 35
I/O 34
I/O 33
I/O 32
I/O 12
I/O 13
I/O 14
I/O 15
SDI/IN 0
SDO/IN 1
CLK 0
B2
B3
B
B5
B
B7
CLK 1
CLK 2
Clock
Distribution
Network
IOCLK 0
IOCLK 1
Megablock
Output Ro
put B
ispEN
SCLK/IN
DE3
I/O I/O I/O I/O
16 19
I/O I/O I/O I/O
24 25 26 27
I/O I/O I/O I/O
28 29 30 31
Y
0
Y
1
Y
2
Y
3
0139D_1024.eps
The device alshas 48 I/O cells, ch of hich s directly TheGRPhasasitsinputstheoutputsfromalloftheGLBs
connected to an I/O pin. Each /O celan be individually and all of the inputs from the bi-directional I/O cells. All of
programmed to be a combinatal inpt, registered in- these signals are made available to the inputs of the
put, latched input, oput or
bi-directional GLBs. Delays through the GRP have been equalized to
I/O pin with 3-state crol. Aditionally, all outputs are minimize timing skew.
polarity selectablegh oactive low. The signal
Clocks in the ispLSI 1024 device are selected using the
levelsareTTLcomagesandtheoutputdrivers
can source 4 mA or mA.
Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
alsobedrivenfromaspecialclockGLB (B4ontheispLSI
1024 device). The logic of this GLB allows the user to
create an internal clock from a combination of internal
signals within the device.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected
toaset of 16universalI/O cellsby theORP. TheI/O cells
within the Megablock also share a common Output
Enable (OE) signal. The ispLSI 1024 device contains
three of these Megablocks.
2
Specifications ispLSI 1024
1
Absolute Maximum Ratings
Supply Voltage V .................................. -0.5 to +7.0V
cc
Input Voltage Applied........................ -2.5 to V +1.0V
CC
Off-State Output Voltage Applied ..... -2.5 to V +1.0V
CC
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T ) with Power Applied ... 150°C
J
1. Stresses above those listed under the “Absolute Maximum Ratings” may case pemanent damage to the nctional
operation of the device at these or at any other conditions above those indicatihe operational sections ication
is not implied (while programming, follow the programming specification
DC Recommended Operating Conditions
SYMBOL
PARAMETER
MIN
AX.
5.25
5.5
UNITS
Commercil TA 0°to +70°C
45
5
4.5
0
Supply Voltage
V
V
V
CC
Indusal
TA = -40°C to +85°C
T= -55°C to +125°
Military/
5.5
Input Low Voltage
Input High Voltage
V
V
IL
0.8
IH
V
2.0
Vcc + 1
Table 2- 0005Aisp w/mil.eps
Capacitance (TA=25oC, f=1.0 MHz)
1
SYMBOL PARAETER
MAXIMUM
UNITS
TEST CONDITIONS
C1
Commustrial
Military
8
pf
VCC=5.0V, VIN=2.0V
edicated ICapacitance
10
10
pf
pf
V
CC=5.0V, VIN=2.0V
C2
I/nd Clock Capacitance
VCC=5.0V, VI/O, VY=2.0V
Table 2- 0006
1. Guaranteed t not 100% tesd.
Data Retention Speification
PETE
Data Retention
MINIMUM
20
MAXIMUM
UNITS
Years
Cycles
—
—
Erase/Reprogram Cy
10000
Table 2- 0008B
3
Specifications ispLSI 1024
Switching Test Conditions
Figure 2. Test Load
Input Pulse Levels
GND to 3.0V
≤ 3ns 10% to 90%
1.5V
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
+ 5V
1.5V
R
1
See figure 2
Device
Output
Test
Point
3-state levels are measured 0.5V from steady-state
active level.
Table 2- 0003
2
C
L
*
Output Load Conditions (see figure 2)
*
includes Tet Fixture and robe Capacce.
L
Test Condition
R1
R2
CL
A
470Ω
390Ω
390Ω
390Ω
390Ω
35pF
35pF
3F
5pF
B
Active High
Active Low
∞
470Ω
Active High to Z
at VOH - 0.5V
∞
C
Active Low to Z
470Ω
390Ω
5pF
at VOL + 0.5V
Table 2- 0004A
DC Electrical Characteristics
Over Recommended perating Conditions
3
SYMBOL
PARAMETER
CONDITION
MIN.
MAX.
TYP.
UNITS
V
IOL
I=-4 mA
Output Low olge
–
2.4
–
–
–
0.4
–
V
V
OL
V
igh Voltage
OH
µA
0≤ VIN ≤ VIL (MAX.)
3.5V ≤ VIN ≤ VCC
Inor I/O Low Leakage Cunt
Inpor I/O High Lekage Current
isp Input Low Leakaurre
I/O Active Pull-UCurret
Output Scuit urrent
Operaupply Current
–
-10
10
I
I
I
I
I
IL
IH
µA
–
–
µA
0V ≤ VIN ≤ VIL (MAX.)
0V ≤ VIN ≤ VIL
–
–
-150
-150
-200
190
215
IL-isp
IL-PU
µA
–
–
mA
mA
mA
VCC = 5V, VOUT = 0.5V
VIL = 0.5V, VIH = 3.0V Commercial
1
–
–
OS
2,4
–
130
135
I
CC
fTOGGLE = 1 MHz
Industrial/Military
–
1. One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.
2. Measured using six 16-bit counters.
3. Typical values are at VCC = 5V and TA = 25oC.
4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption sec-
tion of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book and CD-ROM to estimate maximum
Table 2-0007A-24 w/mil
ICC.
4
Specifications ispLSI 1024
External Timing Parameters
Over Recommended Operating Conditions
-80
-60
-90
5
2
1
TEST
PARAMETER
#
DESCRIPTION
UNITS
COND.
MIN. MAX. MIN. MAX.
MIN. MAX.
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
–
–
–
–
1
Data Propagation Delay, 4PT bypass, ORP bypass
Data Propagation Delay, Worst Case Path
–
–
15
20
–
–
–
20
25
–
t
pd1
–
–
12
17
–
ns
ns
2
3
4
5
6
7
8
9
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
pd2
3
Clock Frequency with Internal Feedback
80
5
10
7
60
38
83
90.9
58.8
125
MHz
MHz
MHz
ns
max (Int.)
1
Clock Frequency with External Feedback
–
–
max (Ext.)
(
)
tsu2 + tco1
4
Clock Frequency, Max Toggle
–
–
max (Tog.)
su1
co1
h1
–
GLB Reg. Setup Time before Clock, 4PT bypass
GLB Reg. Clock to Output Delay, ORP bypass
GLB Reg. Hold Time after Clock, 4 PT bypas
GLB Reg. Setup Time before Clock
–
–
–
10
–
–
–
8
ns
0
0
0
–
ns
10
–
13
–
–
su2
co2
h2
9
–
ns
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Dela
13 Ext. Reset Pulse Duratin
1
–
16
–
–
10
ns
0
0
0
ns
–
17
–
–
22.5
–
r1
–
15
ns
10
–
13
–
rw1
en
10
ns
14 Input to Output Enab
18
18
–
24
24
–
1
15
–
ns
15 Input to Output Disable
–
–
dis
–
ns
16 Ext. Sync. CDuraion, High
17 Ext. Sync. ClDuration, Low
5
6
wh
ns
5
–
6
wl
–
4
–
ns
18 I/O Reg. Setup Tbefore Ext. Sync. ock (Y2, Y3)
19 I/O Reg. Hold Time after Ext. Syck 2, Y3)
2
–
2.5
8.5
su5
h5
–
2
–
ns
6.5
–
–
6.5
–
ns
Table 2-0030-24/90,80,60C
1. Unless noted otherwise, all parats use a GRP los, 20 TXOR path, ORP and Y0 clock.
2. Refer to Timing Mel in this data heet for further d
3. Standard 16-Bit loadle countusing GRP feedbac
4. fmax (Toggle) may be ls tn 1/(twh + twl). is to a clock duty cycle of other than 50%.
5. Reference ing Test onditions Secti.
5
Specifications ispLSI 1024
1
Internal Timing Parameters
-90
-80
-60
2
PARAMETER
DESCRIPTION
UNITS
#
MIN. MAX. MIN. MAX.
MIN. MAX.
Inputs
–
–
1.6
2
–
–
–
2.0
3.0
–
2.7
4.0
–
t
t
t
t
t
t
t
iobp
iolat
iosu
ioh
I/O Register Bypass
–
–
20
21
22
23
24
25
26
ns
ns
ns
ns
ns
ns
ns
I/O Latch Delay
4.8
.1
–
5
1.
–
I/O Register Setup Time before Clock
I/O Register Hold Time after Clock
I/O Register Clock to Out Delay
I/O Register Reset to Out Delay
Dedicated Input Delay
7.3
1.3
–
–
–
2.4
2
3.2
3.0
2.5
.0
ioco
ior
–
–
–
din
–
GRP
–
–
–
–
–
1.2
6
2.4
0
5.0
–
–
–
–
–
1.
2.0
.0
3.8
4.5
6.3
2.0
2.7
4.0
5.0
6.0
8.3
t
t
t
t
t
t
grp1
GRP Delay, 1 GLB Load
GRP Delay, 4 GLB Loads
GRP Delay, 8 GLB Loads
GRP Delay, 12 GLB Loads
GRP Delay, 16 GLB Load
GRP Delay, 24 GLB Loads
–
–
–
–
–
27
28
29
30
31
32
ns
ns
ns
ns
ns
ns
grp4
grp8
grp12
grp16
grp24
GLB
–
–
5.2
5.7
7.0
8.2
0.8
–
–
–
6.5
7.0
8.0
9.5
1.0
–
4 Product Term ByDelay
1 Product Term/XOR PDelay
20 Product Term/XOR Path Delay
t
t
t
t
t
t
t
t
t
t
t
t
4ptbp
1ptxor
20ptxor
xoradj
gbp
33
34
35
36
37
38
39
1
2
43
44
–
–
8.6
9.3
10.6
12.7
1.3
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
3
–
–
XOR Acent Pah Delay
–
–
–
GLB Regisypass Delay
–
1.2
3.6
–
1.0
4.5
–
gsu
LB Regiter Setup Time be
GLegister Hold Tie after Clo
LB Register Clock o Output elay
GLB Register Reset tOutpuDelay
GLB Prodt Term eset to Register Delay
GLB Poduct Term Oput Enable to I/O Cell Delay
GLB Proct TeClock Delay
1.3
6.0
–
–
–
gh
–
1.6
2.0
8.0
7.8
2.0
2.5
10.0
9.0
gco
2.7
3.3
13.3
12.0
–
–
gr
–
–
–
ptre
–
–
–
ptoe
ptck
–
2.8 6.0 3.5 7.5
4.6 9.9
ORP
–
–
2.4
0.4
–
–
2.5
0.5
3.3
0.7
t
orp
y
–
–
45
46
ns
ns
ORypass Delay
torpbp
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Hard Macros.
6
Specifications ispLSI 1024
1
Internal Timing Parameters
-90
-80
-60
2
PARAMETER
DESCRIPTION
UNITS
#
MIN. MAX.
MIN. MAX. MIN. MAX.
Outputs
–
–
–
2.4
4.0
4.0
t
t
t
ob
Output Buffer Delay
–
–
3.0
5.0
5.0
–
–
–
4.0
6.7
6.7
47
48
49
ns
ns
ns
I/O Cell OE to Output Enabled
I/O Cell OE to Output Disabled
oen
odis
Clocks
3.6 3.6
.8 44
04.0
2.8 4.4
0.8 4.0
t
t
t
t
t
gy0
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
Clock Delay, Y1 or Y2 to Global GLB Clock Line
Clock Delay, Clock GLB to Global GLB Clock Lin
Clock Delay, Y2 or Y3 to I/O Cell Global Clock Le
Clock Delay, Clock GLB to I/O Cell Global Cck Li
4.5 4.5 6
3.5 5.5 4
1.0 .0 1.3
3.5 5.5 4.6 7.3
0 516.6
50
51
52
53
54
ns
ns
ns
ns
ns
gy1/2
gcp
ioy2/3
iocp
Global Reset
–
8.2
tgr
Global Reset to GLB and I/O Regiss
–
.0
–
12.0
55
ns
1. Internal Timing Parameters are not tested and are for ference only.
2. Refer to Timing Model in this data sheet for further tails.
7
Specifications ispLSI 1024
ispLSI Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Ded. In
#26
I/O Reg Bypass
GRP 4
#28
4 PT Bypass
#33
GLB Reg Bypass
#37
ORP Bypass
#46
#47
I/O Pin
#20
I/O Pin
(Output)
#48, 49
(Input)
Input
Register
GRP
Loading
Delay
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
Q
D
RST
D
Q
#45
#34, 35, 36
#55
#27, 29,
30, 31, 32
#55
#21 - 25
RST
#339,
0, 41
Reset
Clock
Control
PTs
RE
OE
CK
Distribution
Y1,2,3
Y0
#51, 52,
53, 54
#42, 43,
44
#50
1
Derivations of
t
su,
th and tco from the Prduct Term Clock
t
t
t
su
= Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) (tgsu) (tiop + tgrp4 + tptk(mi)
= (#20 + #28 + #35) + (#+ #2+ #44)
5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) + 3.5)
h
= Clock (max) + Reg h - Logi
= (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrpt20ptxor)
= (#20 + #28 #44) + (#39) - (#20 + #28 + #3
4.0 ns = (2.0 + 2.0 + 7) + (4.5) (2.0 + 2.0 + 8.0)
co
= Clock (max) + Re+ Output
= (tiob+ tgrp4 + tptck(max)) + (tgtob)
= (#20 + 8 + #4) + (#40) + (#45 +
19.0 ns .0+ 2.0 +5) + (2.0) + (2.+ 3.0)
1
Derivations
su,
th and tco from e CloGLB
t
t
t
su
= gic + Reg su - lock (min)
= (tiobp + tgrp4 + 2xor) (tgsu) - (tgy0(min) + tgco + tgcp(min))
= (#20 + #28 + 35) + (#38) (#50 + #40 + #52)
5.5 ns = (2.0 + 2.0 + 8.0(1.0) - (4.5 + 2.0 + 1.0)
h
= ClocReg - Logic
= (tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
= (#50 + 52) + (#39) - (#20 + #28 + #35)
4.0 ns = (4.5 + 2.0 5.0) + (4.5) - (2.0 + 2.0 + 8.0)
co
= Clock (max) + Reg co + Output
= (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
= (#50 + #40 + #52) + (#40) + (#45 + #47)
19.0 ns = (4.5 + 2.0 + 5.0) + (2.0) + (2.5 + 3.0)
1. Calculations are based upon timing specifications for the ispLSI 1024-80.
8
Specifications ispLSI 1024
Maximum GRP Delay vs GLB Loads
ispLSI 1024-60
6
5
4
3
2
1
ispLSI 1024-80
ispLSI 1024-90
0
4
8
12
GLB Loads
0126A-80-24-isp.eps
Power Consumption
Power consumption in the ispLSI 1024 device depends ure 3 hows the relatioship beteen power and operat-
on two primary factors: the speed at which the deve is g speed.
operating, and the number of Product Terms ued. Fig-
Figure 3. Typical Device Power Consumion s fmax
20
ispLSI 0
150
10
50
0
10
20 30
40 50 60 70 80
max (MHz)
f
Notes: Configuration of Six 16-bit Counters
Typical Current at 5V, 25˚C
I
I
can be estie ispLSI 1024 using the following equation:
= 42 + (# of PTs 0.45) + (# of nets * Max. freq * 0.008) where:
CC
CC
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The I
estimate is based on typical conditions (V
= 5.0V, room temperature) and an assumption of 2 GLB loads on
CC
CC
average exists. These values are for estimates only. Since the value of I
program in the device, the actual I
is sensitive to operating conditions and the
CC
should be verified.
CC
0127A-24-80-isp
9
Specifications ispLSI 1024
Pin Description
PLCC and JLCC
PIN NUMBERS
TQFP PIN NUMBERS
NAME
DESCRIPTION
I/O 0 - I/O 3
I/O 4 - I/O 7
22, 23, 24, 25,
26, 27, 28, 29,
30, 31, 32, 33,
37, 38, 39, 40,
41, 42, 43, 44,
45, 46, 47, 48,
56, 57, 58, 59,
60, 61, 62, 63,
64, 65, 66, 67,
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
19, 20, 21, 22,
23, 28, 29, 30,
31, 32, 33, 34,
42, 43, 44, 45,
46, 47, 48, 53,
54, 55, 56, 57,
69, 70, 71, 72,
73, 78, 79, 80,
81, 82, 83, 84,
92, 93, 94, 95,
96, 97, 98, 3,
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
5,
9,
6,
3,
7,
4,
8,
10,
11, 12, 13, 14
6,
7
4,
5,
IN 4 - IN 5
ispEN
Input - Thess are dicad input pins to tdevic
2,
91,
16
8
15
Input - Dicated in-stem programming able put pin. his pin is
brought lto enablhe programming mo. e MODE, SDI, SDO
and CLK ions bcome active.
19
1
SDI/IN 0
21
18
put - his pin performs two functionWhen EN is logic low, it
fctions an input pin to ld programing data into the device.
SDIN 0 is lso used as one ohe two ctrol pins for the isp state
maine. It is a dedicated iut pin en isN is logic high.
1
MODE/IN 3
55
34
49
—
68
35
1,
InThis pin performs twfunctio. When ispEN is logic low, it
functions as pin to cl the oation of the isp state machine. It is a
dedicated input pin whispEgic high.
1
SDO/IN 1
Output/Input - Thiin perms two functions. When ispEN is logic low,
it functions s an oput pito read serial shift register data. It is a
dedicated ut pin whispEN is logic high.
1
SCLK/IN 2
Input - This performs two functions. When ispEN is logic low, it
funcions as a ck pin for the Serial Shift Register. It is a dedicated
input n when ispN is logic high.
2
2, 12, 13,
NC
No Connt
24, 25, 26, 27,
38, 39, 49, 50,
51, 52, 63
74, 75, 7
87, 88,
RESET
Y0
20
54
17
9
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
Y1
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
67
Y2
Y3
51
50
60
59
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
1,
35, 52
53, 68
14,
61,
36, 37,
89, 90
18,
36,
15,
62,
GND
VCC
Ground (GND)
17,
10, 11, 40, 41,
65, 85, 86
VCC
66,
Table 2 - 0002C-24
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, Vcc or GND.
10
Specifications ispLSI 1024
Pin Configuration
ispLSI 1024 68-Pin PLCC Pinout Diagram
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
5
2
51
50
48
47
46
45
44
I/O 28
I/O 27
I/O 26
/O 25
I/O 2
IN 5
Y0
MODE
Y1
ispLSI 1024
VCC
VCC
GND
GND
Top View
ispEN
RESET
SDI/IN 0
I/O 0
Y3
1
1
IN2/SCLK
I/O 23
I/O 1
I/O 22
I/O 21
I/O 20
19
I/O 2
I/O 3
I/O 4
27 28 29 30 31 32 4 35 37 38 39 40 41 42 43
1. Pins have dual capab
0123C-isp.eps
ispLSI 1024 100-Pin TQFP Pinout D
1
1
1
N
NC
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
1
NC
O 43
I/O 44
I/O 45
I/O 46
I/O 47
IN5
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
2
IN3/MODE
Y0
9
Y1
V
C
10
12
13
14
16
17
18
19
20
21
22
23
24
25
VCC
VCC
1
C
NC
ispLSI 1024
1
1
NC
NC
GND
ND
is
RESE
I/1N0
I/O 0
GND
GND
Top View
Y2
Y3
2
IN2/SCLK
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 1
I/O 2
I/O 3
I/O 4
1
1
NC
NC
1
1
NC
NC
1. NC pins are not to be connected to any active signal, Vcc or GND.
2. Pins have dual function capability.
0766A-24-isp
11
Specifications ispLSI 1024
Pin Configuration
ispLSI 1024 68-Pin JLCC Pinout Diagram
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
IN 5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
6
55
54
52
50
49
48
47
46
45
44
I/O 28
I/
I/O 26
I/O 2
24
IN 3/MOD
Y1
Y0
VCC
VCC
ispLSI 1024/883
GND
ND
Y2
Top View
ispEN
RESET
SDI/IN 0
I/O 0
Y3
1
1
IN 2/SCLK
I/O 23
I/O 1
I/O 22
I/O 2
I/O 21
I0
I/O 3
I/O 4
I/O
27 28 29 30 1 32 35 37 38 39 40 41 42 43
1. Pins hacapabi.
0123-24-isp/JLCC
12
Specifications ispLSI 1024
Part Number Description
ispLSI
–
1024
XX
X
X
X
Device Family
Grade
ispLSI
Blank = Commercial
I = Industrial
Device Number
/883 = 883 Military Process
Pckage
J LC
T = TQP
H = JLCC
Power
Speed
90 = 90 MHz
80 = 80 MHz
60 = 60 MHz
fmax
f
max
max
f
L = Low
00212B-isp1024
Ordering Information
COMECIAL
fmax (MHz)
d (n)
Ordering Numbe
Package
Family
90
1
ispLSI 1024-9J
68-Pin PLCC
9
80
80
12
15
15
ispLI 14-90LT
ispSI 1024-0LJ
pLS024-80LT
100-Pin TQFP
68-Pin PLCC
100-Pin TQFP
ispLSI
6
60
20
iLSI 1024-60LJ
ispLSI 1024-60LT
68-Pin PLCC
100-Pin TQFP
USTRIAL
f
max (Mz)
t
pd ns)
Ordering Number
ispLSI 1024-60LJI
ispLSI 1024-60LTI
Package
68-Pin PLCC
100-Pin TQFP
ly
ispLSI
0
0
0
20
MILITARY/883
Hz)
t
pd (ns)
Ordering Number
Package
Family
ispLSI
SMD #
20
ispLSI 1024-60LH/883
68-Pin JLCC
5962-9476101MXC
Table 2-0041A-24-isp
Note: Lattice Semicoductor recognizes the trend in military device procurement towards
using SMD compliant devices, as such, ordering by this number is recommended.
13
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