ISPLSI2128VE-250LQN160 [LATTICE]
EE PLD, 6ns, CMOS, PQFP160, PLASTIC, QFP-160;
| 型号： | ISPLSI2128VE-250LQN160 |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | EE PLD, 6ns, CMOS, PQFP160, PLASTIC, QFP-160 时钟 输入元件 可编程逻辑 |
| 文件： | 总20页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
Lead-
ee
ispLSI 2128VE
Fr
Packag
Options
ailable!
e
3.3V In-System Programmable
SuperFAST™ High Density PLD
Av
Features
Functional Block Diagram*
• SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 6000 PLD Gates
Output Routing Pool (ORP)
D7 D6
D5
D4
Output Routing Pool (ORP)
D2
D1
D0
D3
— 128 and 64 I/O Pin Versions, Eight Dedicated Inputs
— 128 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible
with ispLSI 2128V Devices
A0
A1
C7
C6
D
Q
Q
Q
Q
A2
A3
C5
C4
D
D
D
Logic
Array
A4
A5
C3
C2
GLB
• 3.3V LOW VOLTAGE 2128 ARCHITECTURE
— Interfaces with Standard 5V TTL Devices
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 250MHz Maximum Operating Frequency
— tpd = 4.0ns Propagation Delay
A6
A7
C1
C0
Global Routing Pool (GRP)
— Electrically Erasable and Reprogrammable
— Non-Volatile
B0
B1
B2
B3
B5
B6
B7
B4
Output Routing Pool (ORP)
Output Routing Pool (ORP)
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
0139A/2128VE
*128 I/O Version Shown
• IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
Description
The ispLSI 2128VE is a High Density Programmable
Logic Device available in 128 and 64 I/O-pin versions.
The device contains 128 Registers, eight Dedicated
Input pins, three Dedicated Clock Input pins, two dedi-
cated Global OE input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 2128VE
features in-system programmability through the Bound-
ary Scan Test Access Port (TAP) and is 100% IEEE
1149.1 Boundary Scan Testable. The ispLSI 2128VE
offers non-volatile reprogrammability of the logic, as well
as the interconnect to provide truly reconfigurable sys-
tems.
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of Wired-
OR Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
The basic unit of logic on the ispLSI 2128VE device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 2128VE device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/ExclusiveORarray, andfouroutputswhichcan
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
• LEAD-FREE PACKAGE OPTIONS
Copyright©2004LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2004
2128ve_12
1
Specifications ispLSI 2128VE
Functional Block Diagram
Figure 1. ispLSI 2128VE Functional Block Diagram (128-I/O and 64-I/O Versions)
RESET
RESET
Input Bus
Input Bus
GOE 0
GOE 1
GOE 0
GOE 1
Output Routing Pool (ORP)
D6
D5
Output Routing Pool (ORP)
D2
D1
Output Routing Pool (ORP)
Megablock
Generic Logic
Megablock
Generic Logic
IN 5
IN 4
IN 5*
IN 4*
D7
D4
D0
D3
D7
D6
D5
D2
D1
D0
D4
D3
Blocks (GLBs)
Blocks (GLBs)
I/O 95
I/O 94
I/O 93
I/O 92
I/O 47
I/O 46
I/O 45
I/O 44
C7
C6
C7
C6
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
A0
A0
I/O 91
I/O 90
I/O 89
I/O 88
I/O 4
I/O 5
I/O 6
I/O 7
I/O 87
I/O 86
I/O 85
I/O 84
A1
I/O 43
I/O 42
I/O 41
I/O 40
A1
C5
C4
C5
C4
I/O 8
I/O 9
I/O 10
I/O 11
I/O 4
I/O 5
I/O 6
I/O 7
I/O 83
I/O 82
I/O 81
I/O 80
A2
A3
A2
A3
Global
Routing
Pool
Global
Routing
Pool
I/O 12
I/O 13
I/O 14
I/O 15
I/O 79
I/O 78
I/O 77
I/O 76
C3
C2
C3
C2
(GRP)
(GRP)
I/O 16
I/O 17
I/O 18
I/O 19
I/O 75
I/O 74
I/O 73
I/O 72
I/O 39
I/O 38
I/O 37
I/O 36
A4
A5
A4
A5
I/O 8
I/O 9
I/O 10
I/O 11
I/O 20
I/O 21
I/O 22
I/O 23
I/O 71
I/O 70
I/O 69
I/O 68
C1
C0
C1
C0
I/O 24
I/O 25
I/O 26
I/O 27
I/O 67
I/O 66
I/O 65
I/O 64
I/O 35
I/O 34
I/O 33
I/O 32
A6
A7
A6
A7
I/O 12
I/O 13
I/O 14
I/O 15
I/O 28
I/O 29
I/O 30
I/O 31
TDI/IN 0
TMS/IN 1
TDI/IN 0
TMS/IN 1
B0
B1
B2
B3
B5
B6
B7
B4
B0
B1
B2
B3
B5
B6
B7
B4
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
Input Bus
BSCAN
BSCAN
0139B/2128VE
0139B/2128VE.64IO
*Not available on 84-PLCC Device
The 128-I/O 2128VE contains 128 I/O cells, while the 64- Y1, Y2) or an asynchronous clock can be selected on a
I/O version contains 64 I/O cells. Each I/O cell is directly GLB basis. The asynchronous or Product Term clock
connected to an I/O pin and can be individually pro- can be generated in any GLB for its own clock.
grammed to be a combinatorial input, output or
Programmable Open-Drain Outputs
bi-directional I/O pin with 3-state control. The signal
levelsareTTLcompatiblevoltagesandtheoutputdrivers
In addition to the standard output configuration, the
can source 4mA or sink 8mA. Each output can be
outputs of the ispLSI 2128VE are individually program-
programmed independently for fast or slow output slew
mable, either as a standard totem-pole output or an
rate to minimize overall output switching noise. Device
open-drain output. The totem-pole output drives the
pins can be safely driven to 5V signal levels to support
specified Voh and Vol levels, whereas the open-drain
mixed-voltage systems.
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and
pull-up. This output configuration is controlled by a pro-
two or one ORPs are connected together to make a
grammable fuse. The default configuration when the
Megablock (see Figure 1). The outputs of the eight GLBs
device is in bulk erased state is totem-pole configuration.
are connected to a set of 32 or 16 universal I/O cells by
The open-drain/totem-pole option is selectable through
the two or one ORPs. Each ispLSI 2128VE device
the Lattice software tools.
contains four Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs andallof theinputs fromthebi-directionalI/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2128VE device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
2
Specifications ispLSI 2128VE
1
Absolute Maximum Ratings
Supply Voltage V .................................. -0.5 to +5.4V
cc
Input Voltage Applied............................... -0.5 to +5.6V
Off-State Output Voltage Applied ............ -0.5 to +5.6V
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T ) with Power Applied ... 150°C
J
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
PARAMETER
Commercial
Industrial
MIN.
3.0
MAX.
3.6
UNITS
V
V
V
V
T
T
= 0°C to + 70°C
A
A
VCC
Supply Voltage
3.0
3.6
= -40°C to + 85°C
Input Low Voltage
Input High Voltage
V – 0.5
0.8
VIL
SS
2.0
5.25
VIH
Table 2-0005/2128VE
Capacitance (TA=25°C, f=1.0 MHz)
SYMBOL
PARAMETER
Dedicated Input Capacitance
I/O Capacitance
Clock and Global Output Enable Capacitance
TYPICAL
UNITS
TEST CONDITIONS
VCC = 3.3V, V = 0.0V
8
6
pf
pf
pf
C1
C2
C3
IN
VCC= 3.3V, VI/O = 0.0V
10
VCC= 3.3V, VY = 0.0V
Table 2-0006/2128VE
Erase Reprogram Specifications
PARAMETER
MINIMUM
MAXIMUM
UNITS
Erase/Reprogram Cycles
10,000
–
Cycles
Table 2-0008/2128VE
3
Specifications ispLSI 2128VE
Switching Test Conditions
Figure 2. Test Load
Input Pulse Levels
GND to 3.0V
≤ 1.5ns 10% to 90%
1.5V
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
+ 3.3V
R
1
1.5V
See Figure 2
Device
Output
Test
Point
3-state levels are measured 0.5V from steady-state active level.
Table 2 - 0003/2128VE
R
2
C *
L
Output Load Conditions (see Figure 2)
TEST CONDITION
R1
316Ω
∞
R2
CL
A
B
348Ω
348Ω
348Ω
35pF
35pF
35pF
*C includes Test Fixture and Probe Capacitance.
L
0213A/2128VE
Active High
Active Low
316Ω
Active High to Z
at VOH-0.5V
∞
348Ω
5pF
C
Active Low to Z
at VOL+0.5V
316Ω
348Ω
5pF
Table 2-0004/2128VE
DC Electrical Characteristics
Over Recommended Operating Conditions
3
SYMBOL
PARAMETER
Output Low Voltage
Output High Voltage
CONDITION
IOL= 8 mA
MIN.
–
TYP. MAX. UNITS
–
–
–
–
–
–
–
–
0.4
–
V
V
V
V
OL
IOH = -4 mA
2.4
–
OH
Input or I/O Low Leakage Current
0V ≤ V ≤ V (Max.)
-10
10
µA
µA
µA
µA
µA
mA
I
IL
IN
IL
(VCC - 0.2)V ≤ V ≤ VCC
–
IN
Input or I/O High Leakage Current
I
IH
VCC≤ VIN ≤ 5.25V
–
10
BSCAN Input Low Leakage Current
I/O Active Pull-Up Current
0V ≤ V ≤ V
–
-150
-150
-100
I
I
I
IL-isp
IL-PU
OS1
IN
IL
0V ≤ V ≤ V
–
IN
IL
Output Short Circuit Current
VCC= 3.3V, VOUT= 0.5V
–
V = 0.0V, V = 3.0V
CC2, 4
IL
IH
–
195
–
mA
Operating Power Supply Current
I
fCLOCK = 1 MHz
Table 2-0007/2128VE
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using eight 16-bit counters.
3. Typical values are at VCC= 3.3V and TA= 25°C.
4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum ICC
.
4
Specifications ispLSI 2128VE
External Timing Parameters
Over Recommended Operating Conditions
TEST3
COND.
-250
-180
PARAMETER
#
DESCRIPTION1
UNITS
MIN. MAX. MIN. MAX.
A
A
A
–
1
2
3
4
5
6
7
8
9
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback2
–
–
4.0
6.0
–
–
–
5.0
7.5
–
ns
ns
t
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
pd1
pd2
250
158
277
2.5
–
180
125
200
3.5
–
MHz
MHz
MHz
ns
max
1
Clock Frequency with External Feedback
Clock Frequency, Max. Toggle
(
)
–
–
max (Ext.)
max (Tog.)
su1
tsu2 + tco1
–
–
–
–
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
–
–
A
–
3.0
–
3.5
–
ns
co1
0.0
3.3
–
0.0
4.5
–
ns
h1
–
–
–
ns
su2
A
–
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay, ORP Bypass
13 Ext. Reset Pulse Duration
3.7
–
4.5
–
ns
co2
0.0
–
0.0
–
ns
h2
A
–
6.0
–
7.0
–
ns
r1
3.5
–
4.0
–
ns
rw1
B
C
B
C
–
14 Input to Output Enable
6.0
6.0
4.0
4.0
–
10.0
10.0
5.0
5.0
–
ns
ptoeen
ptoedis
goeen
goedis
wh
15 Input to Output Disable
–
–
ns
16 Global OE Output Enable
–
–
ns
17 Global OE Output Disable
–
–
ns
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
1.8
1.8
2.5
2.5
ns
–
–
–
ns
wl
Table 2-0030A/2128VE
v.1.0
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
5
Specifications ispLSI 2128VE
External Timing Parameters
Over Recommended Operating Conditions
TEST3
COND.
-135
-100
PARAMETER
#
DESCRIPTION1
UNITS
MIN. MAX. MIN. MAX.
—
—
7.5
10.0
—
—
—
10.0
13.0
—
A
1
2
3
4
5
6
7
8
9
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback2
ns
ns
t
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
pd1
A
pd2
135
100
143
5.0
—
100
77
A
MHz
MHz
MHz
ns
max
1
—
—
—
—
—
A
Clock Frequency with External Feedback
Clock Frequency, Max. Toggle
(
)
max (Ext.)
max (Tog.)
su1
tsu2 + tco1
—
100
6.5
—
—
—
—
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
4.0
—
5.0
—
ns
co1
0.0
6.0
—
0.0
8.0
—
—
—
A
ns
h1
—
—
ns
su2
5.0
—
6.0
—
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay, ORP Bypass
13 Ext. Reset Pulse Duration
ns
co2
0.0
—
0.0
—
—
A
ns
h2
9.0
—
12.5
—
ns
r1
5.0
—
6.5
—
—
B
ns
rw1
12.0
12.0
7.0
7.0
—
15.0
15.0
9.0
9.0
—
14 Input to Output Enable
ns
ptoeen
ptoedis
goeen
goedis
wh
—
—
C
15 Input to Output Disable
ns
—
—
B
16 Global OE Output Enable
ns
—
—
C
17 Global OE Output Disable
ns
3.5
3.5
5.0
5.0
—
—
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
ns
—
—
ns
wl
Table 2-0030B/2128VE
v.1.0
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
6
Specifications ispLSI 2128VE
Internal Timing Parameters1
Over Recommended Operating Conditions
-250
-180
2
PARAMETER
Inputs
#
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX.
20 Input Buffer Delay
—
—
0.5
0.7
—
—
0.5
1.1
ns
ns
t
io
21 Dedicated Input Delay
tdin
GRP
grp
GLB
22 GRP Delay
—
0.2
—
0.6
ns
t
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
25 1 Product Term/XOR Path Delay
—
—
—
—
—
—
0.8
1.7
—
—
—
—
1.5
2.0
2.8
2.8
2.8
0.0
—
—
—
—
—
—
—
1.2
2.3
—
—
—
—
1.9
2.4
3.4
3.4
3.4
0.0
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
4ptbpc
4ptbpr
1ptxor
20ptxor
xoradj
gbp
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay3
28 GLB Register Bypass Delay
29 GLB Register Setup Time before Clock
30 GLB Register Hold Time after Clock
31 GLB Register Clock to Output Delay
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
gsu
—
—
gh
0.2
0.3
3.7
2.9
0.3
0.6
4.3
5.9
gco
gro
ptre
ptoe
ptck
0.8 3.6
1.0 4.0
ORP
36 ORP Delay
—
—
1.1
0.4
—
—
1.4
0.4
ns
ns
t
orp
37 ORP Bypass Delay
torpbp
Outputs
38 Output Buffer Delay
—
—
—
—
—
1.4
2.0
2.4
2.4
1.6
—
—
—
—
—
1.6
2.0
3.0
3.0
2.0
ns
ns
ns
ns
ns
t
t
t
t
t
ob
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
sl
oen
odis
goe
Clocks
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
1.0 1.0
1.2 1.2
1.2 1.2
1.4 1.4
ns
ns
t
gy0
tgy1/2
Global Reset
gr
45 Global Reset to GLB
—
3.9
—
4.4
ns
t
Table 2-0036A/2128VE
v.1.0
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
7
Specifications ispLSI 2128VE
Internal Timing Parameters1
Over Recommended Operating Conditions
-135
-100
2
PARAMETER
#
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX.
Inputs
tio
tdin
20 Input Buffer Delay
—
—
0.5
1.7
—
—
0.7
2.5
ns
ns
21 Dedicated Input Delay
GRP
22 GRP Delay
—
1.2
—
1.8
ns
tgrp
GLB
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
25 1 Product Term/XOR Path Delay
—
—
3.7
3.7
4.7
4.7
4.7
0.5
—
—
—
—
—
—
—
1.7
4.8
—
—
—
—
5.2
4.7
6.2
6.2
6.2
1.0
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
—
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay3
—
—
28 GLB Register Bypass Delay
—
29 GLB Register Setup Time before Clock
30 GLB Register Hold Time after Clock
31 GLB Register Clock to Output Delay
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
1.2
3.8
—
—
—
0.3
1.1
6.1
6.9
0.3
3.1
7.1
9.1
5.6
—
—
tptre
—
tptoe
tptck
ORP
1.6
4.6 2.6
36 ORP Delay
—
—
1.5
0.5
—
—
1.7
0.7
ns
ns
torp
37 ORP Bypass Delay
torpbp
Outputs
tob
tsl
toen
38 Output Buffer Delay
—
—
—
—
—
1.6
2.0
3.4
3.4
3.6
—
—
—
—
—
1.6
2.0
3.4
3.4
5.6
ns
ns
ns
ns
ns
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
todis
tgoe
Clocks
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
1.6
1.8
1.6 2.4
1.8 2.6
2.4
2.6
ns
ns
tgy0
tgy1/2
Global Reset
tgr
45 Global Reset to GLB
—
5.8
—
7.1
ns
Table 2-0036B/2128VE
v.1.0
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
8
Specifications ispLSI 2128VE
ispLSI 2128VE Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Comb 4 PT Bypass #23
Ded. In
#21
I/O Delay
#20
GRP
#22
Reg 4 PT Bypass
GLB Reg Bypass
#28
ORP Bypass
#37
#38,
39
I/O Pin
(Output)
I/O Pin
(Input)
#24
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
D
Q
#36
#25, 26, 27
RST
#45
#29, 30,
31, 32
Reset
Control
PTs
RE
OE
CK
#33, 34,
35
#40, 41
#43, 44
#42
Y0,1,2
GOE 0
0491/2032
Derivations of
t
su,
= Logic + Reg su - Clock (min)
= ( io + grp + 20ptxor) + ( gsu) - (
= (#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
th and tco from the Product Term Clock
t
su
t
t
t
t
tio + tgrp + tptck(min))
2.8ns = (0.5 + 0.2 + 2.8) + (0.8) - (0.5 + 0.2 + 0.8)
t
h
= Clock (max) + Reg h - Logic
= (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
= (#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
2.5ns
co
= (0.5 + 0.2 + 3.6) + (1.7) - (0.5 + 0.2 + 2.8)
t
= Clock (max) + Reg co + Output
= (tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
= (#20 + #22 + #35) + (#31) + (#36 + #38)
= (0.5 + 0.2 + 3.6) + (0.2) + (1.1 + 1.4)
7.0ns
Note: Calculations are based upon timing specifications for the ispLSI 2128VE-250L.
Table 2-0042/2128VE
v.1.0
9
Specifications ispLSI 2128VE
Power Consumption
used. Figure 3 shows the relationship between power
and operating speed.
Power consumption in the ispLSI 2128VE device de-
pends on two primary factors: the speed at which the
device is operating and the number of Product Terms
Figure 3. Typical Device Power Consumption vs fmax
350
300
ispLSI 2128VE
250
200
150
100
0
50
100
150
200
250
f
max (MHz)
Notes: Configuration of eight 16-bit counters
Typical current at 3.3V, 25¡ C
I
I
can be estimated for the ispLSI 2128VE using the following equation:
CC
CC
=
8 + (# of PTs 0.669) + (# of nets max freq 0.0026)
* * *
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The
I
estimate is based on typical conditions (V
= 3.3V, room temperature) and an assumption
CC
CC
of two GLB loads on average exists. These values are for estimates only. Since the value of
sensitive to operating conditions and the program in the device, the actual
I
is
CC
should be verified.
I
CC
0127/2128VE
10
Specifications ispLSI 2128VE
Signal Descriptions
Signal Name
Description
RESET
Active Low (0) Reset pin resets all the registers in the device.
Global Output Enable input pins.
GOE 0, GOE1
Y0, Y1, Y2
Dedicated Clock Input – These clock inputs are connected to one of the clock inputs of all the GLBs in
the device.
BSCAN
Input – Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to
enable the programming mode. The TMS, TDI, TDO and TCK controls become active.
TDI/IN 0
TCK/IN 3
TMS/IN 1
TDO/IN 2
Input – This pin performs two functions. When BSCAN is logic low, it functions as a serial data input pin
to load programming data into the device. When BSCAN is high, it functions as a dedicated input pin.
Input – This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the
Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin.
Input – This pin performs two functions. When BSCAN is logic low, it functions as a mode control pin for
the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin.
Output/Input – This pin performs two functions. When BSCAN is logic low, it functions as an output pin
to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin.
IN 4 - IN 7
GND
VCC
Dedicated Input Pins to the device.
Ground (GND)
Vcc
NC1
No Connect
I/O
Input/Output Pins – These are the general purpose I/O pins used by the logic array.
1. NC pins are not to be connected to any active signals, VCC or GND.
11
Specifications ispLSI 2128VE
Signal Locations
208-Ball
fpBGA
176-Pin
TQFP
160-Pin
PQFP
100-Ball
caBGA
100-Pin
TQFP
Signal
H3
21
19
D2
11
RESET
GOE 0, GOE 1 J16, H1
110, 23
100, 21
F9, E1
E3, F6, F8
E5
62, 13
Y0, Y1, Y2
H2, H14, J14
20, 113, 108
18, 103, 98
10, 65, 60
J1
25
23
24
15
16
59
37
87
BSCAN
TDI/IN 0
TCK/IN 3
TMS/IN 1
J3
26
F2
J15
P8
C9
107
66
97
G10
J5
60
TDO/IN 2
IN 4 - IN 7
154
140
B6
H16, A9, T8,
H4
114, 155, 67,
19
104, 141, 61,
17
E9, A6, K5, D1 66, 88, 38, 9
GND
D4, D13, G7,
G8, G9, G10,
H7, H8, H9,
H10, J7, J8,
J9, J10, K7,
K8, K9, K10,
N4, N13
24, 46, 68, 87,
109, 134, 153,
175
22, 42, 62, 79, B7, F1, G9, K6 14, 39, 61, 86
99, 122, 139,
159
VCC
NC1
D5, D6, D12,
E4, E13, F4,
F13, L4, L13,
M4, M13, N5,
N11, N12
A2, A3, A15,
A16, B1, B2,
B3, B14, B15,
B16, C2, C3,
2, 22, 43, 65,
90, 111, 131,
156
2, 20, 39, 59,
82, 101, 119,
142
A5, E2, F10, J4 12, 36, 63, 89
9, 18, 27, 36,
55, 64, 69, 78,
97, 106, 112,
115, 124, 143,
102
A8, C3, C4,
D6, D8, E7,
E10, F4, G3,
4, 21, 25, 31,
44, 50, 54, 64,
71, 75, 81, 94,
G5, H7, H8, K3 100
C14, C15, D14, 152, 157, 166
P1, P2, P3,
P13, P14, P15,
R1, R2, R3,
R14, R15, R16,
T1, T2, T15,
T16
1. NC pins are not to be connected to any active signals, VCC or GND.
12
Specifications ispLSI 2128VE
I/O Locations
208
176
TQFP
160
100
100
208
Signal fpBGA
176
TQFP
160
100
100
Signal fpBGA
PQFP caBGA TQFP
PQFP caBGA TQFP
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
J2
J4
K1
K3
K2
K4
L1
L2
L3
M1
M2
M3
N1
N2
N3
P4
T3
R4
T4
P5
R5
N6
T5
R6
P6
T6
N7
R7
P7
T7
N8
R8
T9
P9
R9
28
29
30
31
32
33
34
35
37
38
39
40
41
42
44
45
47
48
49
50
51
52
53
54
56
57
58
59
60
61
62
63
70
71
72
73
74
75
76
77
79
80
81
82
83
84
85
86
88
89
91
92
93
94
95
96
98
99
100
101
102
103
104
105
25
26
27
28
29
30
31
32
33
34
35
36
37
38
40
41
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
80
81
83
84
85
86
87
88
89
90
91
92
93
94
95
96
G1
F3
E4
H1
G2
J1
H2
K1
J2
K2
H3
J3
G4
H4
K4
H5
F5
17
18
19
20
22
23
24
26
27
28
29
30
32
33
34
35
40
41
42
43
45
46
47
48
49
51
52
53
55
56
57
58
67
68
69
70
72
73
74
76
77
78
79
80
82
83
84
85
90
91
92
93
95
96
97
98
99
1
I/O 64
I/O 65
I/O 66
I/O 67
I/O 68
I/O 69
I/O 70
I/O 71
I/O 72
I/O 73
I/O 74
I/O 75
I/O 76
I/O 77
I/O 78
I/O 79
I/O 80
I/O 81
I/O 82
I/O 83
I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
I/O 96
I/O 97
I/O 98
I/O 99
I/O 100 A7
I/O 101 C7
I/O 102 B7
I/O 103 D7
I/O 104 A6
I/O 105 C6
I/O 106 B6
I/O 107 A5
I/O 108 C5
I/O 109 B5
I/O 110 A4
I/O 111 B4
I/O 112 C4
I/O 113 A1
I/O 114 C1
I/O 115 D3
I/O 116 D2
I/O 117 D1
I/O 118 E3
I/O 119 E2
I/O 120 E1
I/O 121 F3
I/O 122 F2
I/O 123 F1
I/O 124 G4
I/O 125 G2
I/O 126 G3
I/O 127 G1
H15
H13
G16
G14
G15
G13
F16
F14
F15
E16
E14
E15
D16
C16
D15
A14
C13
B13
A13
C12
B12
D11
A12
C11
B11
D10
A11
B10
C10
D9
116
117
118
119
120
121
122
123
125
126
127
128
129
130
132
133
135
136
137
138
139
140
141
142
144
145
146
147
148
149
150
151
158
159
160
161
162
163
164
165
167
168
169
170
171
172
173
174
176
1
105
106
107
108
109
110
111
112
113
114
115
116
117
118
120
121
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
160
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
I/O 36
I/O 37
I/O 38
I/O 39
I/O 40
I/O 41
I/O 42
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
I/O 48
I/O 49
I/O 50
I/O 51
I/O 52
I/O 53
I/O 54
I/O 55
I/O 56
I/O 57
I/O 58
I/O 59
I/O 60
I/O 61
I/O 62
I/O 63
J6
K7
H6
K8
G6
J7
K9
J8
K10
J9
J10
H9
H10
G7
G8
D10
E8
F7
A10
B9
A8
C8
B8
N9
C10
D9
B10
C9
A10
B9
A9
C8
B8
D7
C7
A7
C6
E6
B5
A4
C5
A3
D5
B4
A2
B3
A1
B2
B1
C2
C1
D4
D3
D8
T10
P10
R10
N10
T11
P11
R11
T12
P12
R12
T13
R13
T14
N14
P16
N15
N16
M14
M15
M16
L15
L14
L16
K13
K15
K14
K16
J13
3
4
5
6
7
8
10
11
12
13
14
15
16
17
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2
3
5
6
7
8
13
Specifications ispLSI 2128VE
Signal Configuration
ispLSI 2128VE 208-Ball fpBGA Signal Diagram
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
I/O
79
I/O
82
I/O
86
I/O
90
I/O
94
I/O
96
I/O
I/O
I/O
I/O
I/O
NC1 NC1
NC1 NC1
A
B
C
D
E
F
A
B
C
D
E
F
IN 5
100 104 107 110
113
I/O
81
I/O
84
I/O
88
I/O
91
I/O
95
I/O
98
I/O
I/O
I/O
I/O
NC1 NC1 NC1
NC1 NC1 NC1
102 106 109 111
I/O
77
I/O
80
I/O
83
I/O
87
I/O TDO/ I/O
92
I/O
I/O
I/O
I/O
I/O
114
NC1 NC1
NC1 NC1
IN 2
97
101 105 108 112
I/O
76
I/O
78
I/O
85
I/O
89
I/O
93
I/O
99
I/O
I/O
I/O
I/O
NC1
GND VCC
VCC
VCC VCC GND
103
115 116 117
I/O
73
I/O
75
I/O
74
I/O
I/O
I/O
VCC
118 119 120
I/O
70
I/O
72
I/O
71
I/O
I/O
I/O
VCC
VCC
I/O
121 122 123
I/O
66
I/O
68
I/O
67
I/O
69
I/O I/O I/O
126 125 127
GND GND GND GND
GND GND GND GND
GND GND GND GND
GND GND GND GND
G
H
J
G
H
J
124
I/O
64
I/O
65
GOE
1
RESET
IN 4
Y1
Y2
IN 7
Y0
GOE TCK/
I/O
63
I/O
1
TDI/
IN 0
I/O
0
BSCAN
0
IN 3
I/O
62
I/O
60
I/O
61
I/O
59
I/O
5
I/O
3
I/O
4
I/O
2
K
L
K
L
I/O
58
I/O
56
I/O
57
I/O
8
I/O
7
I/O
6
VCC
VCC
VCC
VCC
ispLSI 2128VE
I/O
55
I/O
54
I/O
53
I/O
11
I/O
10
I/O
9
Bottom View
M
N
P
R
T
M
N
P
R
T
I/O
52
I/O
51
I/O
49
I/O
39
I/O
35
I/O
30
I/O
26
I/O
21
I/O
14
I/O
13
I/O
12
GND VCC VCC
VCC GND
I/O
50
I/O
44
I/O
41
I/O
37
I/O TMS/ I/O
I/O
24
I/O
19
I/O
15
NC1 NC1 NC1
NC1 NC1 NC1
33
IN 1
28
I/O
47
I/O
45
I/O
42
I/O
38
I/O
34
I/O
31
I/O
27
I/O
23
I/O
20
I/O
17
NC1 NC1 NC1
NC1 NC1 NC1
I/O
48
I/O
46
I/O
43
I/O
40
I/O
36
I/O
32
I/O
29
I/O
25
I/O
22
I/O
18
I/O
16
NC1 NC1
NC1 NC1
IN 6
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
208 BGA/2128VE
1. NCs are not to be connected to any active signals, Vcc or GND.
Note: Ball A1 indicator dot on top side of package.
14
Specifications ispLSI 2128VE
Pin Configuration
ispLSI 2128VE 176-Pin TQFP Pinout Diagram
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
I/O 78
VCC
1
2
3
4
5
6
7
8
I/O 113
VCC
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
NC1
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
NC1
IN 4
Y1
NC1
VCC
GOE 0
GND
Y2
TCK/IN 3
NC1
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
NC1
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
VCC
I/O 114
I/O 115
I/O 116
I/O 117
I/O 118
I/O 119
1NC
I/O 120
I/O 121
I/O 122
I/O 123
I/O 124
I/O 125
I/O 126
I/O 127
1NC
IN 7
Y0
RESET
VCC
GOE 1
GND
BSCAN
TDI/IN 0
1NC
I/O 0
I/O 1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
ispLSI 2128VE
Top View
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1NC
98
97
96
95
94
93
92
91
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
VCC
90
89
I/O 49
I/O 14
176-TQFP/2128VE
1. NC pins are not to be connected to any active signals, VCC or GND.
15
Specifications ispLSI 2128VE
Pin Configuration
ispLSI 2128VE 160-Pin PQFP Pinout Diagram
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
1
2
3
4
5
6
7
8
I/O 78
VCC
I/O 113
VCC
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
IN 4
I/O 114
I/O 115
I/O 116
I/O 117
I/O 118
I/O 119
I/O 120
I/O 121
I/O 122
I/O 123
I/O 124
I/O 125
I/O 126
I/O 127
IN 7
Y0
RESET
VCC
GOE 1
GND
BSCAN
TDI/IN 0
I/O 0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Y1
NC1
VCC
GOE 0
GND
ispLSI 2128VE
Top View
Y2
TCK/IN 3
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
VCC
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
VCC
82
81
I/O 49
I/O 14
160-PQFP/2128VE
1. NC pins are not to be connected to any active signal, VCC or GND.
16
Specifications ispLSI 2128VE
Signal Configuration
ispLSI 2128VE 100-Ball caBGA Signal Diagram
10
9
8
7
6
5
4
3
2
1
I/O
39
I/O
41
I/O
46
I/O
50
I/O
52
I/O
55
I/O
57
NC1
IN 5
VCC
A
B
C
D
E
F
A
B
C
D
E
F
I/O
37
I/O
40
I/O
43
TDO/
IN 2
I/O
49
I/O
54
I/O
56
I/O
58
I/O
59
GND
I/O
35
I/O
38
I/O
42
I/O
45
I/O
47
I/O
51
I/O
60
I/O
61
NC1
NC1
I/O
32
I/O
36
I/O
44
I/O
53
I/O
62
I/O
63
NC1
NC1
RESET
IN 7
I/O
33
I/O
48
I/O
2
GOE
1
NC1
IN 4
NC1
BSCAN
Y0
VCC
GOE
0
I/O
34
I/O
16
I/O
1
TDI/
IN 0
VCC
Y2
Y1
NC1
GND
TCK/
IN 3
I/O
31
I/O
30
I/O
21
I/O
12
I/O
4
I/O
0
GND
NC1
NC1
G
H
J
G
H
J
I/O
29
I/O
28
I/O
19
I/O
15
I/O
13
I/O
10
I/O
6
I/O
3
NC1
NC1
I/O
27
I/O
26
I/O
24
I/O
22
I/O
17
TMS/
IN 1
I/O
11
I/O
8
I/O
5
VCC
I/O
25
I/O
23
I/O
20
I/O
18
I/O
14
I/O
9
I/O
7
GND
IN 6
NC1
K
K
ispLSI 2128VE
Bottom View
10
9
8
7
6
5
4
3
2
1
100-BGA/2128VE
1
NCs are not to be connected to any active signals, VCC or GND.
Note: Ball A1 indicator dot on top side of package.
17
Specifications ispLSI 2128VE
Pin Configuration
ispLSI 2128VE 100-Pin TQFP Pinout Diagram
I/O 57
I/O 58
I/O 59
1NC
I/O 60
I/O 61
I/O 62
I/O 63
IN 7
Y0
RESET
VCC
GOE 1
GND
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC1
I/O 38
I/O 37
I/O 36
NC1
I/O 35
I/O 34
I/O 33
I/O 32
IN 4
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Y1
NC1
ispLSI 2128VE
VCC
GOE 0
GND
Y2
TCK/IN 3
I/O 31
I/O 30
I/O 29
I/O 28
NC1
Top View
BSCAN
TDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 3
1NC
I/O 4
I/O 5
I/O 27
I/O 26
I/O 25
I/O 6
1NC
100-TQFP/2128VE
1. NC pins are not to be connected to any active signals, VCC or GND.
18
Specifications ispLSI 2128VE
Part Number Description
ispLSI 2128VE – XXX X XXXXX X
Device Family
Device Number
Speed
Grade
Blank = Commercial
I = Industrial
Package
Q160 = 160-Pin PQFP
T176 = 176-Pin TQFP
TN176 = Lead-Free 176-Pin TQFP
B208 = 208-Ball fpBGA
BN208 = Lead-Free 208-Ball fpBGA
T100 = 100-Pin TQFP
TN100 = Lead-Free 100-Pin TQFP
B100 = 100-Ball caBGA
250 = 250 MHz
180 = 180 MHz
135 = 135 MHz
100 = 100 MHz
f
max
max*
max
max
f
f
f
*Use ispLSI 2128VE-250 for new designs
Power
L = Low
0212/2128VE
ispLSI 2128VE Ordering Information
Conventional Packaging
COMMERCIAL
ORDERING NUMBER
FAMILY
fmax (MHz)
250
tpd (ns)
4.0
I/Os
128
128
128
64
PACKAGE
176-Pin TQFP
160-Pin PQFP
208-Ball fpBGA
100-Pin TQFP
100-Ball caBGA
176-Pin TQFP
ispLSI 2128VE-250LT176
ispLSI 2128VE-250LQ160
ispLSI 2128VE-250LB208
ispLSI 2128VE-250LT100
ispLSI 2128VE-250LB100
ispLSI 2128VE-180LT176*
250
4.0
250
4.0
250
4.0
250
4.0
64
180
5.0
128
180
180
180
180
5.0
5.0
5.0
5.0
128
128
64
ispLSI 2128VE-180LQ160*
ispLSI 2128VE-180LB208*
ispLSI 2128VE-180LT100*
ispLSI 2128VE-180LB100*
160-Pin PQFP
208-Ball fpBGA
100-Pin TQFP
100-Ball caBGA
64
ispLSI
135
135
135
135
135
100
100
100
100
100
7.5
7.5
7.5
7.5
7.5
10
128
128
128
64
ispLSI 2128VE-135LT176
ispLSI 2128VE-135LQ160
ispLSI 2128VE-135LB208
ispLSI 2128VE-135LT100
ispLSI 2128VE-135LB100
ispLSI 2128VE-100LT176
ispLSI 2128VE-100LQ160
ispLSI 2128VE-100LB208
ispLSI 2128VE-100LT100
ispLSI 2128VE-100LB100
176-Pin TQFP
160-Pin PQFP
208-Ball fpBGA
100-Pin TQFP
100-Ball caBGA
176-Pin TQFP
160-Pin PQFP
208-Ball fpBGA
100-Pin TQFP
100-Ball caBGA
64
128
128
128
64
10
10
10
10
64
Table 2-0041A/2128VE
*Use ispLSI 2128VE-250 for new designs
19
Specifications ispLSI 2128VE
ispLSI 2128VE Ordering Information (Cont.)
Conventional Packaging (Cont.)
INDUSTRIAL
FAMILY
ispLSI
fmax (MHz)
135
tpd (ns)
7.5
I/Os
64
ORDERING NUMBER
PACKAGE
100-Pin TQFP
176-Pin TQFP
ispLSI 2128VE-135LT100I
ispLSI 2128VE-135LT176I
135
7.5
128
Table 2-0041B/2128VE
Lead-Free Packaging
COMMERCIAL
FAMILY
ispLSI
fmax (MHz)
250
tpd (ns)
4.0
I/Os
128
128
64
ORDERING NUMBER
ispLSI 2128VE-250LTN176
ispLSI 2128VE-250LBN208
ispLSI 2128VE-250LTN100
ispLSI 2128VE-135LTN176
ispLSI 2128VE-135LBN208
ispLSI 2128VE-135LTN100
PACKAGE
Lead-Free 176-Pin TQFP
Lead-Free 208-Ball fpBGA
Lead-Free 100-Pin TQFP
Lead-Free 176-Pin TQFP
Lead-Free 208-Ball fpBGA
Lead-Free 100-Pin TQFP
250
4.0
250
4.0
135
7.5
128
128
64
135
7.5
135
7.5
100
100
100
10
10
10
128
128
64
ispLSI 2128VE-100LTN176
ispLSI 2128VE-100LBN208
ispLSI 2128VE-100LTN100
Lead-Free 176-Pin TQFP
Lead-Free 208-Ball fpBGA
Lead-Free 100-Pin TQFP
INDUSTRIAL
FAMILY
ispLSI
fmax (MHz)
135
tpd (ns)
7.5
I/Os
128
64
ORDERING NUMBER
ispLSI 2128VE-135LTN176I
ispLSI 2128VE-135LTN100I
PACKAGE
Lead-Free 176-Pin TQFP
Lead-Free 100-Pin TQFP
135
7.5
20
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