ISPPAC-POWR604-01T44E [LATTICE]
Power Supply Support Circuit, Adjustable, 1 Channel, CMOS, PQFP44, TQFP-44;
| 型号： | ISPPAC-POWR604-01T44E |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | Power Supply Support Circuit, Adjustable, 1 Channel, CMOS, PQFP44, TQFP-44 |
| 文件： | 总30页 (文件大小：528K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ispPAC®-POWR604 Device Datasheet
June 2010
All Devices Discontinued!
Product Change Notification (PCN) #09-10 has been issued to discontinue all devices in
this data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
Ordering Part Number
ispPAC-POWR604-01T44I
ispPAC-POWR604-01TN44I
ispPAC-POWR604-01T44E
ispPAC-POWR604-01TN44E
Product Status
Discontinued
Reference PCN
ispPAC-
POWR604
PCN#09-10
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
®
ispPAC-POWR604
In-System Programmable Power Supply
Sequencing Controller and Monitor
August 2004
Data Sheet DS1032
Features
Application Block Diagram
■ Monitor and Control Multiple Power
Supplies
Voltage Monitor 6
Voltage Monitor 5
• Simultaneously monitors and sequences up to six
power supplies
-5V Supply
• Sequence controller for power-up conditions
• Provides four output control signals
• Programmable digital and analog circuitry
1.
0.1uF
6 Analog Inputs
Digital
Logic
U/ASIC
etc.
VDNP
OUT5
VMO
V2
VM
VMON
VMON5
MON6
C
B
L
P
OUT6
OUT7
OUT8
■ Embedded PLD for Sequence Control
• Implements state machine and input conditional
events
V
ispOWR604
DD
Comp1
Comp
Comp
Comp4
mp5
p6
Power Sequence
Controller
CLK
• In-System Programmable (ISP™) through JTAG
RESE
and on-chip E2CMOS®
PO
CAESETN
_IN
IN1
IN2
IN3
IN4
■ Embedded Programmable Timers
• Two Programmable 8-bit timers (32µs to 524ms)
• Programmable time delay for pulse stretching
other power supply management
INTK
CREF
DONE
0.1uF
■ Analog Comparators for Monitorig
• Six analog comparators for monitoring
• 192 precise programmable thleve
spanning 1.03V to 5.72V
Descripion
The ttice isAC®-POWR604 incorporates both in-
sysem rogrammable logic and in-system programma-
le analocircuits to perform special functions for
poer supply sequencing and monitoring. The ispPAC-
PO604 device has the capability to be configured
through software to control up to four outputs for power
spply sequencing and six comparators monitoring sup-
ply voltage limits, along with four digital inputs for inter-
facing to other control circuits or digital logic. Once
configured, the design is downloaded into the device
through a standard JTAG interface. The circuit configu-
ration and routing are stored in non-volatile E2CMOS.
PAC-Designer,® an easy-to-use Windows-compatible
software package, gives users the ability to design the
logic and sequences that control the power supplies or
regulator circuits. The user has control over timing func-
tions, programmable logic functions and comparator
threshold values as well as I/O configurations.
• Each comparator can be indepy config-
ured around standard logic supploltages of
1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5V
• Other user-definevoltages possible
• Six direct comparatooutps
■ Embedded scillator
• Built-in clock enerar, 250kHz
• Prommable k frequency
• Progle timer pre-scale
• Exterlock support
■ Programable Open-rain Outputs
• Four digital outputs for oanpower supply
control
• Expandable with ispMCH™ 4000 CPLD
■ 2.25V to 5.5Range
• In-system pble at 3.0V to 5.5V
• Industrial temre range: -40°C to +85°C
• Automotive temperature range: -40°C to +125°C
• 44-pin TQFP package
• Lead-free package option
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1
DS1032_02.1
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Power Supply Sequence Controller and Monitor
The ispPAC-POWR604 device is specifically designed as a fully-programmable power supply sequencing controller
and monitor for managing up to four separate power supplies, as well as monitoring up to six analog inputs or sup-
plies. The ispPAC-POWR604 device contains an internal PLD that is programmable by the user to implement digi-
tal logic functions and control state machines. The internal PLD connects to two programmable timers, special
purpose I/O and the programmable monitoring circuit blocks. The internal PLD and timers can be clocked by either
an internal programmable clock oscillator or an external clock source.
The voltage monitors are arranged as six independent comparators each with 192 programmable trip point set-
tings. Monitoring levels are set around the following standard voltages: 1.2V, 1.5V, 1.8V, 2.5V, 3.3V or 5.0V.
All six voltages can be monitored simultaneously (i.e., continuous-time opeation). Othenon-standard voltage lev-
els can be accounted for using various scale factors.
For added robustness, the comparators feature a variable hysteresis tscals with the voltagonitor.
Generally, a larger hysteresis is better. However, as power supplvoltages t maller, that ysteresiasingly
affects trip-point accuracy.Therefore, the hysteresis is +/-16mV or 5V supplies and scales own o +/-3mV for 1.2V
supplies, or about 0.3% of the trip point.
The programmable logic functions consist of a block of 0 inps with 41 product terms d eigt macrocells. The
architecture supports the sharing of product terms to enhnce thoverall usability
The four output pins are open-drain outputs. Thse outpun be used to drive nable lines for DC/DC converters
or other control logic associated with power upply control. The four outpe den from the macrocells.
Figure 2-1. ispPAC-POWR604 Block Diagra
ispPAC-POWR0
6
COMP1
COMP2
VMON1
COMP3
VMON2
Comparator
Outputs
COMP4
COMP5
COMP6
VMON3
VMON4
VMON5
VON6
Seqence
ontrler
PLD
Analog
Iputs
& 8
acrocell
GLB
IN1
5
4
OUT5
OUT6
OUT7
OUT8
IN2
Logic
Outputs
Digital
ps
250kHz
Internal
OSC
IN3
IN4
RESET
2 Timers
CLKIO
2-2
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Pin Descriptions
Number
Name
Pin Type
Voltage Range
Description
1
NC
—
—
—
—
—
No Connect
2
NC
—
No Connect
3
NC
—
No Connect
4
NC
—
No Connect
5
VDD
Power
2.25V-5.5V
VDDINP1, 3
VDDINP1, 3
VDDINP1, 3
VDDINP1, 3
VDD6
2.25V-5.5V3
2.25V-5.5V2
2.25V-5.5V2
2.25V-5.52
2.25V-5.5V
—
Main Power Supply
6
IN1
CMOS Input
CMOS Input
CMOS Input
CMOS Input
CMOS input
Power
Input 1
7
IN2
Input 2
8
IN3
Input 3
9
IN4
Inpu4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
RESET
VDDINP
OUT58
OUT68
OUT78
OUT88
NC
PLD eet Inpu, Active Low
igital IutPower Supply
Open-Drain Output
O/D Output
O/D Output
O/D Output
O/D Output
—
OpeDrain Output
Open-Drain Output
Open-Drain Out
No Conne
NC
—
—
No Connect
COMP6
COMP5
COMP4
COMP3
COMP2
COMP1
TCK
O/D Output
O/D Output
O/D Output
O/D Output
O/D Output
O/D Output
TTLVCMOS Input
O/D Oput
Bi-directioal I/O
Groun
2.V-5.5V2
.25V-5V2
2.V-5.5V2
2.25V-5.5V2
2.25V-5.5V2
2.25V-5.5V2
VDD
VMONomr Output (Open-Drain)
VMN5 Cmparator Output (Open-Drain)
VMONComparator Output (Open-Drain)
MON3 Comparator Output (Open-Drain)
VN2 Comparator Output (Open-Drain)
VMON1 Comparator Output (Open-Drain)
Test Clock (JTAG Pin)
Power-On-Reset Output
Clock Output (Open-Drain) or Clock Input
Ground
POR
2.5V
CLK
GND
TLVCMOS Outut
VDD
DD
VDD
VDD
Test Data Out (JTAG Pin)
Test Reset, Active Low, 50k Ohm Internal Pull-up
(JTAG Pin, Optional Use)
29
30
31
T
TDI
TTL/LVCMOS Inp
TTL/LVCOS Input
TTLLVCMOS Inpu
Test Data In, 50k Ohm Pull-up (JTAG Pin)
Test Mode Select, 50k Ohm Internal Pull-up (JTAG
Pin)
TMS
32
33
34
35
36
37
38
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
NC
Analog put
g Inp
Input
g Input
Analog Input
Analog Input
—
0V-5.72V4
0V-5.72V4
0V-5.72V4
0V-5.72V4
0V-5.72V4
0V-5.72V4
—
Voltage Monitor Input 1
Voltage Monitor Input 2
Voltage Monitor Input 3
Voltage Monitor Input 4
Voltage Monitor Input 5
Voltage Monitor Input 6
No Connect
Reference for Internal Use, Decoupling Capacitor
(.1uf Required, CREF to GND)
39
CREF
Reference
1.17V7
40
41
NC
NC
—
—
—
—
No Connect
No Connect
2-3
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Pin Descriptions (Continued)
Number
Name
Pin Type
Voltage Range
Description
42
NC
—
—
—
—
—
—
No Connect
43
NC
NC
No Connect
No Connect
44
1. IN1...IN4 are digital inputs to the PLD. The thresholds for these pins are referenced by the voltage on VDDINP.
2. The open-drain outputs can be powered independently of VDD and pulled up as high as +6.0V (referenced to ground). Exception, CLK pin
26 can only be pulled as high as VDD.
3. VDDINP can be chosen independent of V
It applies only to the four logic inputs IN1-IN4.
DD.
4. The six VMON inputs can be biased independently of VDD. The six VMON inputs can be as higas 7.0V Max (referenced to ground).
5. CLK is the PLD clock output in master mode. It is re-routed as an input in slave mode.The clock os sen software during design time.
In output mode it is an open-drain type pin and requires an external pull-up resistor (pulluvoltage must b≤ V ). Multiple ispPAC-
DD
POWR604 devices can be tied together with one acting as the master, the master can se the internck and the slave clocked
by the master. The slave needs to be set up using the clock as an input.
6. RESET is an active low INPUT pin, external pull-up resistor required. When driven low sets all nternal PLD flip-flopmay
turn “ON” or “OFF” the output pins, depending on the polarity configuration of utputs the LD. If a reset fuction is r the
other devices on the board, the PLD inputs and outputs can be used to genate these signa.The RESET cnected to the R pin can
be used if multiple ispPAC-POWR604 devices are cascaded together in exnsion moor if a manual reseutton s needed to reset the
PLD logic to the initial state. While using the ispPAC-POWR604 in howap plicatioit is recommened thther thRESET pin be
connected to the POR pin, or connect a capacitor to ground (such at ttime cnt is 10 ms with the ll-up rst) from the RESET
pin.
7. The CREF pin requires a 0.1µF capacitor to ground, near the devicin. This eference is used innally by tdevice. No additional
external circuitry should be connected to this pin.
8. The four digital outputs (pins 12-15) are named OUT5-UT8 to mpPAC-POWR1208 pin mes aallow easy design migration.
Absolute Maximum Ratings
Absolute maximum ratings are shown tablblow. Stresses above ose sted values may cause permanent
damage to the device. Functional othe device at thse r any oter conditions above those indicated in
the operating sections of this specificot implied.
Symbol
VDD
Parameter
Core supply ltage at pin
Conditions
Min.
-0.5
-0.5
-0.5
-0.5
Max.
6.0
Units
—
—
—
—
V
V
V
V
1
VDD
Digital input supvolte for IN1-IN4
Input oltage appliedigital inputs
6.0
INP
2
V
6.0
IN
VMON
Input voge apied, V
voltage mts
7.0
MON
V
istated or en drain outpuexternal voge applied
n 26 pull-up ≤ VDD)
TRI
—
-0.5
6.0
V
T
age temperature
—
—
—
-65
-55
—
150
125
260
°C
°C
°C
S
T
Abient temperatue with power applied
Maximum solderintperare (10 sec. at 1/16 in.)
A
T
SOL
1. V
is the supply pin that ntrols logic iuts IN1-IN4 only. Place 0.1µF capacitor to ground and supply the V
pin with appropriate
DDINP
DDINP
supply voltage for the given inpuogic range.
2. Digital inputs are tolo 5.5ndependent of the V
voltage.
DDINP
2-4
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Recommended Operating Conditions
Symbol
Parameter
Core supply voltage at pin
Conditions
Min.
2.25
3.0
2.25
0
Max.
5.5
5.5
5.5
5.5
6.0
Units
V
V
V
V
V
V
V
V
V
V
DD
1
Core supply voltage at pin
During E2 cell programming
DDPROG
2
Digital input supply voltage for IN1-IN4
Input voltage digital inputs
DDINP
3
IN
Voltage monitor inputs V
- V
MON6
0
MON
MON1
EEPROM, programmed at
Erase/Program
Cycles
V
= 3.0V to 5.5V
1000
—
Cycles
DD
-40°C to +85°C
Ambient temperature during
programming
T
-40
+8
°C
APROG
Power applied - strial
Power aplied - Autmove
-40
-40
°C
°C
T
Ambient temperature
A
+12
1. The ispPAC-POWR604 device must be powered from 3.0V to 5.5V during pgramming of the E2CMOS mery.
2. V is the supply pin that controls logic inputs IN1-IN4 only. Place 0.1µF pacitor tround and supply th
pin ith appropriate
INP
DDINP
supply voltge for the given input logic range.
3. Digital inputs are tolerant up to 5.5V, independent of the V
voge.
DDINP
Analog Specifications
Over Recmmended Operating Contions
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
I
Supply Curr
ntrnal Clock = 20kHz
—
5
10
mA
DD
Reference
Symbol
Parameter
Cnditions
Min.
Typ.
Max.
Units
1
V
Referenvoltage at CREF pin
T 5°C
—
1.17
—
V
REF
1. CREF pin requires a 0.1µF capitor to round.
Voltage Moniors
Symb
Paramer
npimpedance
Conditions
Min.
Typ.
Max.
Units
R
70
100
130
kΩ
IN
V
V
V
Range
Programmable age mitor rip
point (192 sts)
MON
1.03
5.72
+0.9
V
Accuracy
Tempco1
Absolute accuy of atrip point
T = 25 °C,
MON
MON
-0.9
%
V
= 3.3V
DD
Temrature ift of any trip point
-40°C to +85°C
-40°C to +125°C
50
76
ppm/ °C
ppm/ °C
HYST
Hf V
input,
V
= 3.3V, 25°C
+/- 0.3% of
trip point
setting
MON
DD
V
YST*V
(+/-3 to +/-13mV)
%
HY
MON
PSR
Trip point sensitivity to V
V
= 3.3V
0.06
%/V
DD
DD
1. See typical performance curves.
2-5
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Power-on-Reset
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
V
supply threshold beyond which POR
ramping up1
—
—
1.15
V
DD
V
V
DD
LPOR
output is guaranteed to be driven low
V
supply threshold above which POR
DD
V
output is guaranteed driven high, and device
initializes
V
ramping up1
DD
—
—
2.1
V
HPOR
1. POR tests run with 10kΩ resistor pulled up to V
DD.
AC/Transient Characteristics
Over Recommended Operating Condions
Symbol
Parameter
Conditions
Min.
Typ.
Units.
Voltage Monitors
t
Propagation Delay. Output
transitions after a step input.
Glitch filter set to 5µs
Input V + 100mV o V
PD5
—
—
5
—
—
µs
µs
- 00mV
- 100mV
TRIP
TRIP
t
Propagation Delay. Output
transitions after a step input.
Glitch filter set t20us
Input V + 100V to V
PD20
TRIP
TRIP
Oscillators
f
Internal master clock frequency Note 2
30
—
—
330
250
kHz
kHz
CLK
PLDCLK
Range
Programmable frequency range Intrnal Osc 2z
of PLD clock (8 binary steps)
1.95
PLDCLKext
Max frequency of applied
external clock source
tnal clok applied
—
—
1
MHz
Timers
Timeout
Range
Range of programmable
time-out duration (15 steps
ernal Osc 250kHz
0.03
—
524
ms
1. See Typical Performance Graphs.
2. f frequency deviation wih respect to VDD, 0.4%/volt, typical.
CLK
Digital Specifications
Over RecoOperating Conditions
Symbo
Paramete
Conditions
Min.
Typ.
Max.
Units
I
I
I
pur I/O leakage cunt, no p- 0V ≤ V ≤ V
or V
DDINP DD
IL, IH
IN
+/-10
µA
up
25 °C
Input pull-up crent (TMS, TDI,
TRST)
PU
25 °C
70
µA
V
V
Open-draioutput set LW
I
= 4mA
0.4
20
OL
SINKOUT
I
Maximm sinurrent for logic out-
pu-OU], [COMP1-
(Note 1)
SINKOUT
mA
mA
I
Totaed sink currents from all (Note 1)
outputUT, COMP]
SINKTOTAL
80
1. [OUT5-OUT8] and [COMP1-COMP6] can sink up to 20mA max. per pin for LEDs, etc. However, output voltage levels may exceed V .Total
OL
combined sink currents from all outputs (OUT, COMP) should not exceed I
.
SINKTOTAL
2-6
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
DC Input Levels: IN1-IN4
V
(V)
V
(V)
IL
IH
Standard
CMOS, LVCMOS3.3, LVTTL, TTL
LVCMOS2.5
Min.
-0.3
-0.3
Max.
0.8
Min.
2.0
Max.
5.5
0.7
1.7
5.5
Note: V
V
is the input supply pin for IN1-IN4 digital logic input pins. The logic threshold trip point of IN1-IN4 is dependent on the voltage at
DDINP
DDINP.
Transient Characteristics
Over Recommended Operating Conditions
Symbol
Parameter
Conditions
Min.
Typ.
M
Units
PLD Timing
Digital Glitch Minimum pulse width to transition through Applied to INN4
20
µs
ns
µs
Filter
glitch filter.
t
t
t
Clock to Out Delay. Rising edge of clock to Stable inpbefore
CO
SU
H
30
output transition.
clock ge (te 1)
Time that input needs to be present when Davaliefore clock
using a registered function with the clock. (No1)
2
0
Time that input needs to be held valid after old ata after clock
the clock edge when using a registed
function with the clock.
µs
t
Propagation delay internal to the
embedded PLD
PD
90
ns
µs
t
RESET pulse width
25
RST
1. External clock 1MHz. Open drain outputs p resistor to V
.
DD
Note: All the above parameters apply to signal m the digital inpu[IN1-IN4].
2-7
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Timing for JTAG Operations
Symbol
Parameter
Conditions
Min
1
Typ.
Max
Units
µs
t
t
t
t
t
t
t
t
t
t
t
t
t
Minimum clock period
TCK high time
CKMIN
200
200
15
ns
CKH
CKL
TCK low time
ns
TMS setup time
ns
MSS
MSH
DIS
TMS hold time
50
ns
TDI setup time
15
ns
TDI hold time
0
ns
DIH
TDO float to valid delay
TDO valid delay
200
200
ns
DOZX
DOV
DOXZ
RSTMIN
PWP
PWE
ns
TDO valid to float delay
Minimum reset pulse width
Time for a programming operation1
Time for an erase operation
ns
4
40
40
ns
100
100
ms
ms
1. t
represents programming pulse width for a single row of E2CMOS lls.
PWP
tPWP, E
tCKH
tCKL
tCKMIN
tCK
tMS
tDI
tCK
tSS
tMSS
tMSS tMSH
Progm and Erase cycles
executed in Run-Test/Idle
tMS
tDIS tDIH
tH
tDV
tDOX
tD
2-8
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Typical Performance Graphs
VMON Trip Point Error 25°C
Propagation Delay vs. Overdrive
7000
6000
5000
4000
3000
2000
1000
0
125
100
75
Glitch Filter = s
50
GliFilter = 5μs
-1 -0.8 -0.6 -0.4 -0.2
0
0.2 0.4 0.6 0.8
1
20
50
100
200
Trip Point Error %
InpOverdve (mV)
Note: Typical proption delay of VMON inputs to outputs
as a funvere beyond selected trip point.
ypicMON Comparatorip Poin
Accuracy vs. Temrure
3
2.5
1.5
1
0.
0
-0.5
-50
0
50
100
150
Temperature (°C)
2-9
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Table 2-1. V
Trip Point Table1
MON
1.2 low 1.2 high 1.5 low 1.5 high 1.8 low 1.8 high 2.5 low 2.5 high 3.3 low 3.3 high 5.0 low 5.0 high
1.036
1.046
1.056
1.066
1.076
1.087
1.096
1.107
1.117
1.127
1.137
1.147
1.157
1.168
1.178
1.188
1.202
1.213
1.225
1.237
1.249
1.261
1.272
1.284
1.295
1.307
1.319
1.331
1.343
1.355
1.366
1.378
1.291
1.303
1.316
1.329
1.341
1.354
1.366
1.379
1.391
1.404
1.417
1.429
1.442
1.455
1.467
1.480
1.502
1.516
1.531
1.546
1.560
1.575
1.590
1.605
1.619
1.634
1.649
1.663
1.678
1.693
1.707
1.722
1.549
1.564
1.579
1.595
1.609
1.625
1.639
1.655
1.669
1.685
1.700
1.715
1.730
1.746
1.761
1.776
1.801
1.818
1.836
1.854
1.871
1.889
1.906
1.924
1.941
1.959
1.977
1.994
2.012
2.030
2.047
65
2.153
2.173
2.195
2.216
2.237
2.258
2.279
2.300
2.320
2.342
2.363
2.3
2.40
27
2.44
2.469
2.500
2.524
2.549
2.574
2.597
2.622
2.646
2.671
2.64
2.19
2.744
2.768
2.73
818
2.841
2.866
2.842
2.869
2.897
2.926
2.952
2.981
.008
36
3.06
3.091
3120
3.147
3.175
3.203
3.30
3.25
3.297
3.328
3.361
3.394
3.425
3.458
3.489
522
3.553
3.586
3.619
3.0
3.63
3.716
3.7
3.70
4.299
4.340
4.383
4.426
4.466
4.509
4.550
4.593
4.6
4.
4.760
4.83
.846
4.886
4.929
4.991
5.038
5.088
5.138
5.185
5.235
5.282
5.332
5.379
.429
.479
5.526
5.576
5.626
5.673
5.723
1.All possible comparator trip voltages using internal attenation settin
Table 2-1 shows all possible comparator trip ot voltage settings. Te intnal resistive divider allows ranges for
1.2V, 1.8V, 2.5V, 3.3V and 5.0V. There 192 ailale voltages, angifrom 1.036V to 5.723V. In addition to the
192 voltage monitor trip points, the add dditional resirs outsithe device to divide down the voltage
and achieve virtually any voltage trip s allows the capabilitto monitor higher voltages such and 12V, 15V,
24V, etc. Voltage monitor trip points arthe graphicaser interce of the PAC-Designer software by simple
pull-down menus. The user simply selectthe given range ancorresponding trip point value. Attenuation and ref-
erence values are set internally using E2CMOS configuobnternal to the device.
Figure 2-2 shows a single cmpaator, the attn neork and reference used to program the monitor trip
points. Each of thsix comparaors are indepet in the same way.
Theory Of Opeation
The ispPAC4 incorporates rogramable voltage monitors along with digital inputs and outputs. The
eight macrocPLD inputs are from thsix voage monitors and four digital inputs. There are two embedded pro-
grammable timrs that interfacwith the PLD, along with an internal programmable oscillator.
The six independently prorammable vltage monitors each have 192 programmable trip points.
Figure 2-2 shows a silified chematic representation of one of these monitors.
2-10
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Figure 2-2. Voltage Monitors
Reference
To PLD Array
Monitor Voltage
VMON1..VMON6
3mV
Hysteresis
Each monitor consists of three major subsystems. The coof the monitor is a vltage comparator. This compara-
tor outputs a HIGH signal to the PLD array the oltage at its positive teneater than that at its negative
terminal, otherwise it outputs a LOW signal. mall aount of hystersis is rovided by the comparator to reduce
the effects of input noise.
The input signal is attenuated by a ble resistive diider efore it is fed into the comparator. This feature
is used to determine the coarse rangich the compator shod trip (e.g. 1.8V, 3.3V, 5V). Twelve possible
ranges are available from the input dividnetwork. The coparator’s negative terminal is obtained from a pro-
grammable reference source (Reference), which may tne of 16 possible values scaled in approximately
1% increments from each ther, allowing for fine tuning of the voltage monitor’s trip points. This combination of
coarse and fine adjustment upprts 192 pos-poivoltages for a given monitor circuit. Because each
monitor’s referencand input divider settings ely independent of those of the other monitor circuits, the
user can set any inpmonir to any of the 19settings.
Comparaysteresis
V
Tycal Hyeresis on Typical Hysteresis on
Oveage Range Under Voltage Range
MON
Range Setting1
5.0V
Units
mV
mV
mV
mV
mV
mV
+/- 16.2
+/- 10.7
+/- 8.1
+/- 5.8
+/- 4.9
+/- 3.9
+/- 14.0
+/- 9.2
+/- 7.0
+/- 5.0
+/- 4.2
+/- 3.4
3.3V
2.5V
1. The hysteresis scales depending on the voltage monitor range that is selected. The values show are typical
and are centered around the nominal voltage trip point for a given range selection.
PLD Architecture
The ispPAC-POWR604 digital logic is composed of an internal PLD that is programmed to perform the sequencing
functions. The PLD architecture allows flexibility in designing various state machines and control logic used for
monitoring. The macrocell shown in Figure 2-3 is the heart of the PLD. There are eight macrocells that can be used
2-11
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
to control the functional states of the sequencer state machine or other control or monitoring logic. The PLD AND
array shown in Figure 2-4 has 20 inputs and 41 product terms (PTs). The resources from the AND array feed the
eight macrocells. The resources within the macrocells share routing and contain a product-term allocation array.
The product term allocation array greatly expands the PLD’s ability to implement complex logical functions by
allowing logic to be shared between adjacent blocks and distributing the product terms to allow for wider decode
functions.
The basic macrocell has five product terms that feed the OR gate and the flip-flop. The flip-flop in each macrocell is
independently configured. It can be programmed to function as a D-Type or T-Type flip-flop. The combinatorial func-
tions are achieved through the bypass MUX function shown. By having the polarity control XOR, the logic reduction
can be best fit to minimize the number of product terms. The flip-flop’s clock dves from a common clock that can
be generated from a pre-scaled, on-board clock source or from an external . Thmacrocell also supports
asynchronous reset and preset functions, derived from product terms, the global reset iput, or the power-on reset
signal.
Figure 2-3. ispPAC-POWR604 Macrocell Block Diagram
Global Reset
Per On Reet
Global Polarity Fuse for
Init Product-Term
Block Init Product-Term
Producrm Aocation
PT4
PT3
PT2
PT1
PT0
R
P
To ORP
D/T
Q
Polarity
CLK
Clock
Macrocell Flip-Flop provides
D,T or Combinatorial
Output with Polarity
2-12
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Figure 2-4. PLD and Timer Functional Block Diagram
POR/RESET
MC0
MC1
OUT5
MC2
MC
MC4
MC5
6
MC7
OUT6
Outp
ing
Pool
AND
ARRAY
O
O
6
4
VMON[1:6]
Comparators
20 Inputs
41 PT
8 Outputs
IN[1:4]
2
BT PT
8
Timer1
8
g
Timer2
Clock Generation
2-13
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Clock and Timer Systems
Figure 2-5 shows a block diagram of the ispPAC-POWR604’s internal clock and timer systems. The PLD clock can
be programmed with eight different frequencies based on the internal oscillator frequency of 250kHz.
Figure 2-5. Clock and Timer Block
Timer1
Internal
Timer Prescaler
OSC
(Time Out Range)
250kHz
imer2
CLK
PLD Clock
Prescaler
Table 2-2. PLD Clock Prescaler1
PLD Clock Frequnc(kHz)
PLD PrscaleDivider
0
2
4
8
15.6
16
32
64
128
7.8
3.9
2
Values based o50kH
The internal tor runs at a fixed fquency of 250kHz. This main signal is then fed to the PLD clock pre-scaler
and also the Ter Clock pre-scar (Fire 2-). For the PLD Clock, the main 250kHz oscillator is divided down to
eight selectablfrequencies sown in the Table 2-2. The architecture of the clock network allows the PLD clock to
be driven to the CLK pin. This bles e user access to the PLD clock as an output for expansion mode or other
uses of the (CLK) clock pi
Schematically, whewitch s in the upper position, the internal oscillator drives the PLD clock pre-scaler and
the timer pre-scamode, the CLK pin is an open-drain output and represents the same frequency as the
PLD clock. This is en operating other devices (such as “slave” sequencing devices) in a synchronized
mode. When the switcin the lower position, the CLK pin is an input and must be driven with an external clock
source. When driven from an external source, the same PLD clock pre-scaler is available to this external clock. The
frequencies available for the PLD clock will be the external clock frequency divided by 1, 2, 4, 8, 16, 32, 64 or 128,
depending on the programmable value chosen.
The Timer Clock Pre-Scaler divides the internal 250kHz oscillator (or external clock, if selected) down before it gen-
erates the clock for the two programmable timers. The pre-scaler has eight different divider ratios: Divide by 4, 8,
16, 32, 64, 128, 256 and 512 (Table 2-3). After the clock for the timers is divided down, it is used to drive the pro-
grammable timers. The two timers share the same timer clock frequency but may have different end count values.
2-14
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
The timers can cover a range from 32us to 524ms for the internal oscillator. Longer delays can be achieved by
using the external clock as an input.
Table 2-3. Timer Values1
÷
÷
÷
÷
÷
÷
÷
÷
512
4
8
16
32
64
128
256
62 kHz
31.2 kHz
15.6 kHz
7.8 kHz
3.9 kHz
2 kHz
1 kHz
0.5 kHz
0.032 ms
0.064 ms
0.128 ms
0.256 ms
0.512 ms
1.024 ms
2.048 ms
4.096 ms
0.064 ms
0.128 ms
0.256 ms
0.512 ms
1.024 ms
2.048ms
4.096 ms
8.192 ms
0.128 ms
0.256 ms
0.512 ms
1.024 ms
2.048ms
4.096 ms
8.192 ms
16.384 ms
0.256 ms
0.512 ms
1.024 ms
2.048ms
0.512 ms
1.024 ms
2.048
024 ms
.048ms
2.04ms
496 m
4.096 ms
8.192 ms
16.384 ms
32.768 ms
4.06 ms
8.1ms
1384
32.7ms
65.536 ms
4.096 ms
8.192 ms
16.384 ms
32.768 s
65.56 ms
131.07ms
096 ms
8.192 ms
8.2 ms
6.38ms
3268 ms
65.36 ms
131.072 ms
262.144 ms
16.384 ms
32.768 ms
65.536 ms
131.072 ms
262.144 ms
524.288 ms
1. Timer values based on 250kHz clock.
For design entry, the user can select thsource for the clok and the PAC-Designer software will calculate the
appropriate delays in an easy-to-select menu format.
The control inputs for Timerand Tmer2 can be n by y of the eight PLD macrocell outputs.The reset for the
timers is a function of the GlobReset pin (REower-on reset or when the timer input goes low.The wave-
forms in Figure 2-6 how the basic timer start functions. Timer and clock divider values are specified in
during the design phae uing the PAC-signeare, while simple pull-down menus allow the user to select
the clocking e and the values for te timers and the PLD clock.
Figure 2-6. Ter Waveforms
Timer Gate
(From PLD)
Timer Period
er Period
Timer
(To PLD
Start
Timer
Timer
Expired
Reset
Timer
Start
Timer
Timer
Expired
ProgrammableTimer
Delay
ProgrammableTimer
Delay
Note that if the clock module is configured as “slave” (i.e. the CLK is an input), the actual time-out of the two timers
is determined by the external clock frequency.
2-15
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
IEEE Standard 1149.1 Interface
In-system programming of the ispPAC-POWR604 is facilitated via an IEEE 1149.1 test access port (TAP). It is used
by the ispPAC-POWR604 as a serial programming interface, boundary scan test is not supported. There are no
boundary scan logic registers in the ispPAC-POWR604 architecture. This does not prevent the ispPAC-POWR604
from functioning correctly, however, when placed in a valid serial chain with other IEEE 1149.1 compliant devices.
Since the ispPAC-POWR604 is used to powerup other devices, it should be programmed in a separate chain from
PLDs, FPGAs or other JTAG devices.
A brief description of the ispPAC-POWR604 serial interface follows. For complete details of the reference specifica-
tion, refer to the publication, Standard Test Access Port and Boundary-Scan Achitecture, IEEE Std 1149.1-1990
(which now includes IEEE Std 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for eally accessing the dige isp-
PAC-POWR604. The TAP controller is a state machine driven witode d cock inputs. Intructishifted
into an instruction register, which then determines subsequedata input, data output, nd related erations.
Device programming is performed by addressing various regists, shiftig data in, and theecuting the respec-
tive program instruction. The programming instructions traner tdatinto internal 2CMOmeory. It is these
non-volatile memory cells that determine the configuratin of e ispPAC-POWR604. By ycling he TAP controller
through the necessary states, data can also be shifted ut of te various regists to vey the current ispPAC-
POWR604 configuration. Instructions exist to accesll daregisters and peorm iernacontrol operations.
For compatibility between compliant devicetwo data registers are maed bthe IEEE 1149.1 specification.
Other registers are functionally specified, binusion is strictly optinal. nally, there are provisions for optional
user data registers that are defined by the manfactuer. The two rquid regters are the bypass and boundary-
scan registers. For ispPAC-POWR60pass egister is a 1t shift rister that provides a short path through
the device when boundary testing erations are nobeig performed. The ispPAC-POWR604, as men-
tioned earlier has no boundary-scan nd therefore o boundy scan register. All instructions relating to
boundary scan operations place the ispAC-POWR604 in te BYPASS mode to maintain compliance with the
specification.
The optional identification (ICOD) register ded in EE 1149.1 is also included in the ispPAC-POWR604.
Six additional usedata registeare included of the ispPAC-POWR604 as shown in Figure 2-7. Most of
these additional reters are used to program y the analog configuration (CFG) and PLD bits. A status
register is also provideto read the statf the alog comparators.
2-16
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Figure 2-7. TAP Registers
ANALOG COMPARATOR ARRAY (6 bits)
STATUS REGISTER (6 bits)
IDCODE REGISTER (32 bits)
UES REGISTER (16 bits)
CFG REGISTER (17 bits)
ALOG
CONFIGURATION
ENON-VOLATILE
MEMORY
CFG ADDRESS REGISTER (4 bits)
PLD DATA REGISTER (41 bits
PLD ADDRESS REGTER (43 ts)
INSTRUCN RESTER (6 bits)
REGIR (1 bit)
(68 bits)
D
AND / CH
2 NON-VOLILE
MEMORY
63 bits
TESCESS PORT
(TAP) LOGIC
OUTPUT
LATCH
DI
TCK
TDO
TAP Controller Specfics
The TAP is cby the Test Cloc(TCK) ad Test Mode Select (TMS) inputs.These inputs determine whether
an Instruction egister or Data Regisr operion is performed. Driven by the TCK input, the TAP consists of a
small 16-state ontroller. In a gven state, tcontroller responds according to the level on the TMS input as shown
in Figure 2-8. Test Data In (TD) anTS are latched on the rising edge of TCK, with Test Data Out (TDO) becom-
ing valid on the falling ede of TCK. Tre are six steady states within the controller: Test-Logic-Reset, Run-Test/
Idle, Shift-Data-Register, Puse-a-Register, Shift-Instruction-Register, and Pause-Instruction-Register. But
there is only one ststate or the condition when TMS is set high: the Test-Logic-Reset state. This allows a
reset of the test five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on
default state.
When the correct logic sequence is applied to the TMS and TCK inputs, the TAP will exit the Test-Logic-Reset state
and move to the desired state. The next state after Test-Logic-Reset is Run-Test/Idle. Until a data or instruction
scan is performed, no action will occur in Run-Test/Idle (steady state = idle). After Run-Test/Idle, either a data or
instruction scan is performed. The states of the Data and Instruction Register blocks are identical to each other dif-
fering only in their entry points. When either block is entered, the first action is a capture operation. For the Data
Registers, the Capture-DR state is very simple; it captures (parallel loads) data onto the selected serial data path
(previously chosen with the appropriate instruction). For the Instruction Register, the Capture-IR state will always
load the IDCODE instruction. It will always enable the ID Register for readout if no other instruction is loaded prior
2-17
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
to a Shift-DR operation. This, in conjunction with mandated bit codes, allows a “blind” interrogation of any device in
a compliant IEEE 1149.1 serial chain.
Figure 2-8. TAP States
Test-Logic-Reset
0
1
0
1
1
1
Select-DR-Scan
Select-IR-Scan
0
Run-Test/Idle
0
Capture-DR
0
1
1
Cpture-I
0
Shift
1
Shift-DR
0
0
1
Exit1-DR
0
Exit1-IR
0
1
0
Pause-DR
1
Pause-I
1
0
0
0
ExitDR
Exit2R
1
1
Upate-DR
Upda-IR
1 0
1
0
Note: The value shojacent to each state ansition reesents the signal present
at TMS at the time of a rising edge at TCK.
From the Capture state, thTAP trnsitions to either the Shift or Exit1 state. Normally the Shift state follows the
Capture state so that test daostatus informn be shifted out or new data shifted in. Following the Shift
state, the TAP eithreturns to the Run-Test/Idthe Exit1 and Update states or enters the Pause state via
Exit1. The Pause stais ued to temporarily the shifting of data through either the Data or Instruction
Register wan exterl operation iperformed. From the Pause state, shifting can resume by re-entering the
Shift state vt2 state or be teminated y entering the Run-Test/Idle state via the Exit2 and Update states.
If the proper ruction is shifted in dung a Sift-IR operation, the next entry into Run-Test/Idle initiates the test
mode (steady ate = test).Thiis when thdevice is actually programmed, erased or verified. All other instructions
are executed in the Update stte.
Test Instructions
Like data registersEE 149.1 standard also mandates the inclusion of certain instructions. It outlines the
function of three d six optional instructions. Any additional instructions are left exclusively for the manu-
facturer to determinstruction word length is not mandated other than to be a minimum of two bits, with only
the BYPASS and EXTT instruction code patterns being specifically called out (all ones and all zeroes respec-
tively). The ispPAC-POWR604 contains the required minimum instruction set as well as one from the optional
instruction set. In addition, there are several proprietary instructions that allow the device to be configured, verified,
and monitored. For ispPAC-POWR604, the instruction word length is 6-bits. All ispPAC-POWR604 instructions
available to users are shown in Table 2-4.
2-18
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Table 2-4. ispPAC-POWR604 TAP Instruction Table
Instruction
EXTEST
ADDPLD1
Code
Description
External Test. Defaults to BYPASS.
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
010110
010111
011000
011001
01
011
011101
011110
11111
1xxxxx
Address PLD address register (43 bits).
Address PLD column data register (81 bits).
Bulk Erase AND array.
DATAPLD1
ERASEAND1, 2
ERASEARCH1, 2
PROGPLD1, 2
PROGESF1, 2
BYPASS
READPLD1
DISCHARGE1
ADDCFG1
Bulk Erase Architect array.
Program PLD column data register into E2.
Program the Electronic Security Fusbit.
Bypass (connect TDI to TDO).
Reads PLD column data from E2 to the resr (81 bits).
Fast VPP discharge.
Address CFG array adss (4 ts).
Address CFG data 1 bits).
DATACFG1
ERASECFG1, 2
PROGCFG1, 2
READCFG1
CFGBE1, 2
SAFESTATE1
PROGRAMEN1
IDCODE
Bulk Erase CFG da
Program CFG da regnto E2.
Read CFG cumn ta from E2 to the gister (4bits).
Bulk ase all 2 memory (CFG, PLD, USand EF).
Dgital outpuZ (FET pulled L)
Enabprogram mode (SAFES
dress Ientification Coddata rgister (32 bits).
DisProgram mod(normIO)
ddress STATUS gir (6 bits).
PROGRAMDIS
ADDSTATUS
SAMPLE
ERASEUES1, 2
SHIFTUES
PROGUES1, 2
BYPASS
Sample/Preloa. Default tBypass.
Bulk Erase UES.
Reads UEatE2 and selects the UES register (16 bits).
ProgUES ata register into E2.
nect TDI to TDO).
1. When thinstructins are executed, the aced in the same mode as the instruction SAFESTATE (as
described lar) to revent invalid aotentuctive power supply sequencing.
2. ctions therase or prograthe E2CMOS memory must be executed only when the supply to the device is
t 3.0V to 5.5V.
BYPASS is onof the three reuired instructions. It selects the Bypass Register to be connected between TDI and
TDO and allows serial data btraferred through the device without affecting the operation of the ispPAC-
POWR604. The IEEE 114.1 standard efines the bit code of this instruction to be all ones (111111).
The required SAMPRELAD instruction dictates the Boundary-Scan Register be connected between TDI
and TDO. The isR604 has no boundary scan register, so for compatibility it defaults to the BYPASS
mode whenever thion is received. The bit code for this instruction is defined by Lattice as shown in
Table 2-4.
The EXTEST (external test) instruction is required and would normally place the device into an external boundary
test mode while also enabling the boundary scan register to be connected between TDI and TDO. Again, since the
ispPAC-POWR604 has no boundary scan logic, the device is put in the BYPASS mode to ensure specification com-
patibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros (000000).
The optional IDCODE (identification code) instruction is incorporated in the ispPAC-POWR604 and leaves it in its
functional mode when executed. It selects the Device Identification Register to be connected between TDI and
TDO. The Identification Register is a 32-bit shift register containing information regarding the IC manufacturer,
2-19
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
device type and version code (Figure 2-9). Access to the Identification Register is immediately available, via a TAP
data scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this
instruction is defined by Lattice as shown in Table 2-4.
Figure 2-9. ID Code
MSB
LSB
XXXX / 0000 0001 0100 0001 / 0000 0100 001 / 1
Part Number
(16 bits)
JEDEC Manufacturer
0141h = ispPAC-POWR604
Identity Code for
Lattice Semiconduct
(11 bits)
Version
(4 bits)
Cotant 1
(1 bit)
2
E
Configured
p1149.990
ispPAC-POWR604 Specific Instructions
There are 21 unique instructions specified by Lattice for e isACWR604. Theinstctios are primarily
used to interface to the various user registers and the 2CMS non-volatile memory. Aditionl instructions are
used to control or monitor other features of the device. A rief decription of each nique itruction is provided in
detail below, and the bit codes are found in Table 2-4
ADDPLD – This instruction is used to set te addess of the PLD ANDH ays for subsequent program or
read operations. This instruction also forces e utputs into the SAFSTAT.
DATAPLD – This instruction is useft PLdata into thregisteprior to programming or reading. This
instruction also forces the outputs iESTATE.
ERASEAND – This instruction will bulk e the PLD AND rray. The action occurs at the second rising edge of
TCK in Run-Test-Idle JTAG state. The device must alady be n programming mode PROGRAMEN instruction).
This instruction also forcthe outputs into the SAFESTE.
ERASEARCH – This instructin ill bulk erasARH array. The action occurs at the second rising edge
of TCK in Run-Tesdle JTAG state.The devicady be in programming mode (PROGRAMEN instruction).
This instruction also rces he outputs into the ATE.
PROGPLD struction programthe selected PLD AND/ARCH array column. The specific column is prese-
lected by usiDDPLD instruction. Te progmming occurs at the second rising edge of the TCK in Run-Test-
Idle JTAG statThe device mst alreadin programming mode (PROGRAMEN instruction) and operated at
3.3V to 5.0V. This instruction so fthe outputs into the SAFESTATE.
PROGESF – This instructiis used o program the electronic security fuse (ESF) bit. Programming the ESF bit
protects proprietary dgns fm being read out. The programming occurs at the second rising edge of the TCK in
Run-Test-Idle JTAhe evice must already be in programming mode (PROGRAMEN instruction). This
instruction also fortputs into the SAFESTATE.
READPLD – This instrion is used to read the content of the selected PLD AND/ARCH array column. This spe-
cific column is preselected by using ADDPLD instruction. This instruction also forces the outputs into the SAF-
ESTATE.
DISCHARGE – This instruction is used to discharge the internal programming supply voltage after an erase or pro-
gramming cycle and prepares ispPAC-POWR604 for a read cycle. This instruction also forces the outputs into the
SAFESTATE.
2-20
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
ADDCFG – This instruction is used to set the address of the CFG array for subsequent program or read operations.
This instruction also forces the outputs into the SAFESTATE.
DATACFG – This instruction is used to shift data into the CFG register prior to programming or reading. This
instruction also forces the outputs into the SAFESTATE.
ERASECFG – This instruction will bulk erase the CFG array. The action occurs at the second rising edge of TCK in
Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This
instruction also forces the outputs into the SAFESTATE.
PROGCFG – This instruction programs the selected CFG array column. This pecific column is preselected by
using ADDCFG instruction. The programming occurs at the second rising edgof tCK in Run-Test-Idle JTAG
state. The device must already be in programming mode (PROGRAMEN nstruction). Tis instruction also forces
the outputs into the SAFESTATE.
READCFG – This instruction is used to read the content of the selected G arry column. This smn is
preselected by using ADDCFG instruction. This instruction also frces the otpts into the SFESTAT
CFGBE – This instruction will bulk erase all E2CMOS bits (CF, PLD, ES, and ESF) in he ispPAC-POWR604.
The device must already be in programming mode (PROGRMEnstuction). This inructioalsforces the out-
puts into the SAFESTATE.
SAFESTATE – This instruction turns off all of the on-dran output transisto. Pinhat ae programmed as FET
drivers will be placed in the active low state. his instrun is effective after pdate-Instruction-Register JTAG
state.
PROGRAMEN – This instruction enables the ogramming mode of tispC-POWR604. This instruction also
forces the outputs into the SAFESTA
IDCODE – This instruction connects ut of the Identification Code Data Shift (IDCODE) Register to TDO
(Figure 2-10), to support reading out the ntification code.
Figure 2-10. IDCODE Rgister
TDO
Bit
31
Bit
30
Bit
29
it
28
Bit
27
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
PROGRAMis instruction disales the programming mode of the ispPAC-POWR604. The Test-Logic-Reset
JTAG state clso be used to cancel he proamming mode of the ispPAC-POWR604.
ADDSTATUS – This instructin is ud to both connect the status register to TDO (Figure 2-11) and latch the 6
voltage monitor (comparator outputs) io the status register. Latching of the 6 comparator outputs into the status
register occurs during Captre-Daa-egister JTAG state.
Figure 2-11. Statuer
TDO
VMON VMON VMON VMON VMON VMON
1
2
3
4
5
6
ERASEUES – This instruction will bulk erase the content of the UES E2CMOS memory. The device must already
be in programming mode (PROGRAMEN instruction) and operated. This instruction also forces the outputs into the
SAFESTATE.
SHIFTUES – This instruction both reads the E2CMOS bits into the UES register and places the UES register
between the TDI and TDO pins (as shown in Figure U), to support programming or reading of the user electronic
signature bits.
2-21
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Figure 2-12. UES Register
TDO
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
PROGUES – This instruction will program the content of the UES Register into the UES E2CMOS memory. The
device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the outputs
into the SAFESTATE.
Notes:
In all of the descriptions above, SAFESTATE refers both to the instruction and te state of the digital output pins, in
which the open-drains are tri-stated and the FET drivers are pulled low.
Before any of the above programming instructions are executed, the rspective EOS bits neee erased
using the corresponding erase instruction.
Application Example
The ispPAC-POWR604 device has six comparators to monitor rious pwer supply levelsThcomparators each
have a programmable trip point that is programmed by the er at esin time. The ouut of e cmparators feed
into the PLD logic array to drive the state machinlogor monitor logic. The utputof comparators
COMP1...COMP6 are also routed to external pins to be mnitoredirectly or can bused to rive additional control
logic if expansion is required. The comparator outparopen-drain type utput ufferand require a pull up
resistor to drive a logic high. All six comparatrs have hyresis, the hysteresiis dependent on the voltage trip
point scale that is set, it ranges from 3.4mV or th1.2V monitor supply re mV for the 5.0V monitor sup-
ply range. The comparators can be set with a point from 1.03V to 72V, ith 192 different values. The applica-
tion diagram shows a set-up that can itor ad ontrol multippowsupies. The digital outputs and inputs
are also used to interface with the s being powered
2-22
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Figure 2-13.Typical Application Example: ispPAC-POWR604 Interfacing to CPU Board Using Four Outputs,
Four Inputs and Six VMON Voltage Monitoring Signals
Voltage Monitor 6
Voltage Monitor 5
2.5-5V Supply
1.0uF
0.1uF
6 Analog Inputs
Digita
Lo
CPU/A
Card etc.
VDD VDDINP
OUT5
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
CP_RESETN
BRWNOUT_INT
LOAD_ENABLE
POWER_OK
OUT6
OUT7
OT8
V
ispPAC-POWR604
DD
Cmp1
Cop2
3
Comp4
Comp5
Comp6
Power Sequence
Controllr
CLK
RESET
POR
CARD_RESETN
WDT_IN
IN1
IN2
IN3
IN4
INT_ACK
CR
DONE
0.1uF
2-23
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Software-Based Design Environment
Design Entry Software
All functions within the ispPAC-POWR604 are controlled through a Windows-based software development tool
called PAC-Designer. PAC-Designer has an easy-to-use graphical user interface (Figure 2-14) that allows the user
to set up the ispPAC-POWR604 to perform required functions, such as timed sequences for power supply or moni-
tor trip points for the voltage monitor inputs. The software tool gives the user control over how the device drives the
outputs and the functional configurations for all I/O pins. User-friendly dialog boxes are provided to set and edit all
of the analog features of the ispPAC-POWR604. An extension to the schematic screen is the LogiBuilder design
environment (Figure 2-15) that is used to enter and edit control sequences. Agin, user-friendly dialog boxes are
provided in this window to help the designer quickly implement sequences tat tadvantage of the powerful
built-in PLD. Once the configurations are chosen and the sequence has been described by the utilities, the device
is ready to program. A standard JTAG interface is used to program the CMOS mry. The PAC-gner soft-
ware supports downloading the device through the PC’s parallel pt. Te ispPAC-POWR60repro-
grammed in-system using the software and an ispDOWNLOAD® Cable semby to compensate ons in
supply timing, sequencing or scaling of voltage monitor inputs.
Figure 2-14. PAC-Designer Schematic Screen
The user interface (Figure 14) podes access to various internal function blocks within the ispPAC-POWR604
device.
Analog Inputs: Ae programmable threshold trip-points for the comparators and pin naming conven-
tions.
Digital Inputs: Digital input naming configurations and digital inputs feed into the internal PLD for the sequence
controller.
Sequence Controller: Incorporates a PLD architecture for designing the state machine to control the order and
functions associated with the user-defined power-up sequence/monitor and control.
Logic Outputs: These pins are configured and assigned in the Logic Output Functional Block. The four digital out-
puts are open-drain and require an external pull-up resistor.
2-24
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Internal Clock: The internal clock configuration and clock prescaler values are user-programmable, as well as the
four internal programmable timers used for sequence delay.
User Electronic Signature (UES): Stores 16 bits of ID or board information in non-volatile E2CMOS.
Figure 2-15. PAC-Designer LogiBuilder Screen
Programming of the ispPAC-POWR604 ccomplished usg the Latce ispDOWNLOAD Cable. This cable con-
nects to the parallel port of a PC and is driven through the PACDesigner software. The software controls the JTAG
TAP interface and shifts the JEDEC data bits that see couration of all the analog and digital circuitry that
the user has defined during he desgn process.
Power to the devicmust be set at 3.0V to 5.5ogramming, once the programming steps have been com-
pleted, the power suply to the ispPAC-POWRbe set from 2.25V to 5V. Once programmed, the on-chip
non-volatile CMOS bhold the entie design configuration for the digital circuits, analog circuits and trip points
for comparaUpon powering tdevice p, the non-volatile E2CMOS bits control the device configuration. If
design changneed to be made such s adjuting comparator trip points or changes to the digital logic functions,
the device is sply re-programed using e ispDOWNLOAD Cable.
Design Simulation Capability
Support for functional simulon of the control sequence is provided using the design tools Waveform Editor and
Waveform Viewer. plicans are spawned from the LogiBuilder environment of PAC-Designer. The simula-
tion engine combign file with a stimulus file (edited by the user with the Waveform Editor) to produce an
output file that can bved with the Waveform Viewer (Figure 2-16).
2-25
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Figure 2-16. PAC-Designer Functional Simulation Screen
In-System Programming
The ispPAC-POWR604 is an in-system programmable device. his is ccomplished by igratinall E2CMOS
configuration memory and control logic on-chip. Programminis pemed through a 4wire, E1149.1 compli-
ant serial JTAG interface. Once a device is programmedll coguration information is stred on-chip, in non-vol-
atile E2CMOS memory cells. The specifics of he IEE 1149.1 serial interfae and ll ispPAC-POWR604
instructions are described in the JTAG interface sectiof s data sheet.
User Electronic Signature
The User Electronic Signature (UES), aows thdesgner to inclue idetificaon bits or serial numbers inside the
device, stored in E2CMOS memoryPAC-OWR604 coains 16 ES bits that can be configured by the
user to store unique data such as ID vision numbers or inntory control codes.
Electronic Security
An Electronic Security Fue (ESF) bit is provided to prent unaorized readout of the E2CMOS bit pattern. Once
programmed, this cell prevets furter access to unctinal user bits in the device. This cell can only be erased
by reprogramming the device; way the origuraton cannot be examined or copied once programmed.
Usage of this featuis optional.
Producn Programming Support
Once a final guration is determine, an ASCII format JEDEC file can be created using the PAC-Designer soft-
ware. Devices an then be ordeed throuthusual supply channels with the user’s specific configuration already
preloaded into he devices. Bvirtuf its standard interface, compatibility is maintained with existing production
programming equipment, giving customrs a wide degree of freedom and flexibility in production planning.
2-26
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Package Diagrams
44-Pin TQFP (Dimensions in Millimeters)
PIN 1 INDICATOR
0.20 C A-B
D 44X
D
3
A
E
E1
B
e
3
D
D1
8
3
TOP VIEW
4X
00 H
D
TTOM EW
SIDE VIEW
SEE DEA'
C
b
SEATING PLAN
GAUGE PLANE
H
0.20 M
C
A-B
D
A
2
A1
0.25
b
0.10 C
0.20 MIN.
1.00 REF.
0-7∞
c
1
c
L
DETAIL 'A'
b
1
BASE METAL
SECTN B-B
SYMBOL
MIN.
-
NOM.
-
MAX.
A
1.60
0.15
1.45
NOTES:
A1
A2
D
0.05
1.35
-
1. DIMENSIONAND TOLERANCING PER ANS14.5 1982.
2. ALL DIMENSINS ARE IN MILLETERS.
1.40
12.00 BSC
10.00 BSC
12.00 BSC
10.00 BSC
0.60
DATUMS A, B AND D TO BDETEMINED ADATUM PLANE H.
3.
D1
E
4. DIMENSIONS D1 AND E1 DO INCMOLD PROTRUSION.
ALLOWABLE MOLD PON I0.254 MM ON D1 AND E1
DIMENSIONS.
E1
L
5. THE TOP OF PACKASMALLER THAN THE BOTTOM
OF THE PACKAGE BY MM.
0.45
0.75
N
44
6. SECTION B-B:
e
0.80 BSC
0.37
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP.
b
0.30
0.30
0.09
0.09
0.45
0.40
0.20
0.16
7. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
TO THE LOWEST POINT ON THE PACKAGE BODY.
b1
c
0.35
0.15
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8.
c1
0.13
2-27
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Part Number Description
ispPAC-POWR604 - 01XX44X
Device Family
Device Number
Operating Temperature Range
I = Industrial (-40°C to +85°C)
E = Automotive (-40°C to +125°C)
Package
T = 4pin TQFP
T= Lead-Free 44-pin TQFP
erformance Grade
01 = Stndard
ispPAC-POWR604 Ordering Information
Conventional Packaging
Industrl
Part Number
Pckage
Pis
ispPAC-POWR604-01T44
TQFP
44
Automotive
Part Numr
Packag
Pins
ispPAC-P-01TE
QFP
44
Lead-Free Packaging
Lead-Free Indutrial
Part Number
Package
Pins
iPAPOWR604-0
TQFP
44
LAutomotive
Prt Number
ispPAC-POR604-0N44E
Package
Pins
TQFP
44
2-28
Lattice Semiconductor
ispPAC-POWR604 Data Sheet
Package Options
1
2
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
NC
VDD
IN1
IN2
IN3
IN4
VMON2
VMON1
TMS
TDI
TRST
TDO
GD
CLK
POR
T
3
4
5
ispPAC-POWR604
6
44-pin TQFP
7
8
9
10
11
RESET
VDDINP
MP1
12 13 14 15 16 17 18 19 21 2
Note: NC is no connect.
Revision History
Date
—
Version
Cnge Smary
—
Preous Lattice relase
September 2003
0
dded 125°C Amotive Rge -40°C to +125°C to Features bullets.
Added VMON tempfor 125°C 76PPM to Voltage Monitors table.
Isinkout maadded for gic outputs OUT5-8 and comparators COMP
1-6, 20mA Ma(Digital Specifications table).
Spec ed fktotal Total combined sink current from all OUT,
COMP 8mA (Digital Specifications table).
tive range added to Part Number Description section.
added for lead free packaging, Part Number Description sec-
Automotive part number added in the Ordering Information section.
Januar
August 204
02.
0
Ordering Part Number added for Lead Free packaging, Ordering Infor-
mation section.
Add R/C network to RESET pin in Application Block Diagram to acco-
modate hot-swapping.
Edited note 6 in Pin Descriptions table to support hot-swapping.
2-29
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