L-ASC10-1SG48ITR [LATTICE]
Microprocessor Circuit,;
| 型号： | L-ASC10-1SG48ITR |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | Microprocessor Circuit, |
| 文件： | 总109页 (文件大小：9055K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L-ASC10
In-System Programmable
Hardware Management Expander
June 2019
Data Sheet FPGA-DS-02038
Features
Ten Rail Voltage Monitoring and
Four Precision Trim and Margin Channels
• Closed Loop Operation
Measurement
• Voltage Scaling and VID Support
Nine General Purpose Input / Output
• 5 V tolerant I/O
Non-Volatile Fault Logging
In-system Programmable Through I2C
• Non-Volatile Configuration
• Background Programming Support
System Level Support
• 3.3 V Operation, wide input supply range 2.8 V
to 3.6 V
• UV/OV Fault Detection Accuracy - 0.2% Typ.
• Fault Detection Speed <100 µs
• High Voltage, Single Ended and Differential
Sensing
Two Channel Wide-Range Current
Monitoring and Measurement
• High-side current Measurement up to 12 V
• Programmable OC/UC Fault Detect
• Detects Current faults in < 1 µs
Three Temperature Monitoring and
Measurement Channels
• Industrial temperature range
• 48-pin QFN
• RoHS compliant and halogen-free
• Programmable OT/UT Faults Threshold
• Two channels of Temperature Monitoring using
external diodes
Applications
• One On-Chip Temperature Monitor
• Telecommunication and Networking
• Industrial, Test & Measurement
• Medical Systems
Four High-Side MOSFET Drivers
• Programmable Charge Pump
• Servers and Storage Systems
• High Reliability Systems
Application Diagram
Figure 1. Hardware Management Application Block Diagram
Up to 10 Rails
0.6 V to 5.7 V
Hot Swap Optional
POL
Rs
Input Rail
Up to 12 V
Vin
EN
Vout
Trim/FB
Trim/Margin [1:4]
HVOUT [1:4]
Voltage
Monitor [1:10]
GPIO
[1..9]
Current
Monitor
[1:2]
On-Die
Temp
NV Fault
Log
Board Temp
Transistor
ADC
L-ASC10
Temp [1:2]
On-Die Temp
Diode
Voltage, Current, Temp
Voltage, Current, Temp
(VIT) High Speed
Fault Detect/Alarms
(VIT)
Measurement and Programming
ASIC
ASC 3 Wire I/F (8 Mbps)
CPU
Resets
I2C
(WCLK, WDAT, RDAT)
ASC I/F
FPGA: MachXO2 / MachXO3 /
ECP5 / LPTM21L / LPTM21
Fan(s)
VID
SPI
Memory
JTAG Programming
© 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
www.latticesemi.com
1
FPGA-DS-02038_2.0
L-ASC10
In-System Programmable
Hardware Management Expander
Description
The L-ASC10 (Analog Sense and Control - 10 rail) is a The ASC also provides the capability of logging up to 16
status records into the on-chip nonvolatile EEPROM mem-
ory. Each record includes voltage, current and temperature
monitor signals along with digital input and output levels.
Hardware Management (Power, Thermal, and Control
Plane Management) Expander designed to be used with
Platform Manager 2, MachXO2, MachXO3, or ECP5
FPGAs to implement the Hardware Management Control
function in a circuit board. The L-ASC10 (referred to as
ASC) enables seamless scaling of power supply voltage
and current monitoring, temperature monitoring, sequence
and margin control channels. The ASC includes dedicated
interfaces supporting the exchange of monitor signal status
and output control signals with these centralized hardware
management controllers. Up to eight ASC devices can be
used to implement a hardware management system.
The dedicated ASC Interface (ASC-I/F) is a reliable serial
channel used to communicate with a Platform Manager 2,
MachXO2, MachXO3, or ECP5 FPGA in a scalable star
topology. The centralized control algorithm in the FPGA
monitors signal status and controls output behavior via this
ASC-I/F. The ASC I2C interface is used by the FPGA or an
external microcontroller for ASC background programming,
interface configuration, and additional data transfer such as
parameter measurement or I/O control or status. For exam-
ple, voltage trim targets can be set over the I2C bus and
measured voltage, current, or temperature values can be
read over the I2C bus.
The ASC provides three types of analog sense channels:
voltage (nine standard channels and one high voltage chan-
nel), current (one standard voltage and one high voltage),
and temperature (two external and one internal) as shown
in Figure 2.
The ASC also includes an on-chip output control block
(OCB) which allows certain alarms and control signals a
direct connection to the GPIOs or HVOUTs, bypassing the
ASC-I/F for a faster response. The OCB is used to connect
the fast current fault detect signal to an FPGA input directly.
It also supports functions like Hot Swap with a programma-
ble hysteretic controller.
Each of the analog sense channels is monitored through
two independently programmable comparators to support
both high/low and in-bounds/out-of-bounds (window-com-
pare) monitor functions. The current sense channels feature
a programmable gain amplifier and a fast fault detect (<1 µs
response time) for detecting short circuit events. The tem-
perature sense channels can be configured to work with dif-
ferent external transistor or diode configurations.
ASC Block Diagram
Figure 2. ASC Block Diagram
Nine general purpose 5 V tolerant open-drain digital input/
output pins are provided that can be used in a system for
controlling DC-DC converters, low-drop-out regulators
(LDOs) and optocouplers, as well as for supervisory and
general purpose logic interface functions. Four high-voltage
charge pumped outputs (HVOUT1-HVOUT4) may be con-
figured as high-voltage MOSFET drivers to control high-side
MOSFET switches. These HVOUT outputs can also be pro-
grammed as static output signals or as switched outputs (to
support external charge pump implementation) operating at
a dedicated duty cycle and frequency.
MOSFET &
Digital I/O Drive
Output Control
Block
ASC
Interface
(ASC-I/F)
ADC
Non -
Volatile
Fault Log
The ASC device incorporates four TRIM outputs for control-
ling the output voltages of DC-DC converters. Each power
supply output voltage can be maintained typically within
0.5% tolerance across various load conditions using the
Digital Closed Loop Control mode.
I2C
ADC
Interface
The internal 10-bit A/D converter can be used to monitor the
voltage and current through the I2C bus. The ADC is also
used in the digital closed loop control mode of the trimming
block.
Trim & Margin
Control
2
L-ASC10
In-System Programmable
Hardware Management Expander
DC and Switching Characteristics
Absolute Maximum Ratings
Symbol
Parameter
Conditions
Min
–0.5
–0.5
–0.5
–0.5
–0.5
–2.0
–0.5
–0.5
–2.0
–0.5
–0.5
–0.5
–0.5
–0.5
Max.
4.5
6
Units
V
VCCA
Main Power Supply
VIN_VMON
VIN_VMONGS
VIN_HIMONP
VIN_HIMONN
VDIFF_HIMON
VIN_IMONP
VIN_IMONN
VDIFF_IMON
VIN_TMONP
VIN_TMONN
VIN_GPIO
VMON input voltage
V
VMON input voltage ground sense
High voltage IMON input voltage
High voltage IMON return/ VMON input voltage
High voltage IMON differential voltage
Low voltage IMON1 input voltage
Low voltage IMON1 return voltage
Low voltage IMON1 differential voltage
TMON input voltage
6
V
13.3
13.3
2.0
6.0
6.0
2.0
VCCA
VCCA
6
V
V
V
V
V
V
V
TMON return voltage
V
Digital input voltage
V
VOUT
Open-drain output voltage
HVOUT [1:4]
13.3
6
V
GPIO[1:6],
GPIO[8:10]
V
VTRIM
ISINKMAX
TS
TRIM output voltage
–0.5
VCCA
23
V
mA
oC
Maximum Sink Current on any output
Device Storage Temperature
Ambient Temperature
–65
–40
+125
+125
TA
oC
3
L-ASC10
In-System Programmable
Hardware Management Expander
Recommended Operating Conditions
Symbol
Parameter
Main Power Supply1
Conditions
Min
2.8
–0.3
–0.2
4.5
4.5
0
Max.
3.6
Units
V
VCCA
VIN_VMON
VMON input voltage
5.9
V
VIN_VMONGS
VIN_HIMONP
VIN_HIMONN
VDIFF_HIMON
VIN_IMONP
VMON input voltage ground sense
High voltage IMON input voltage2
High voltage IMON return/ VMON input voltage2
High voltage IMON differential voltage
Low voltage IMON1 input voltage
0.3
V
13.2
13.2
500
5.9
V
V
mV
V
Low Side Sense
Disabled
0.6
Low Side Sense
Enabled
–0.3
0.6
1.0
5.9
1.0
V
V
V
VIN_IMONN
Low voltage IMON1 return voltage
Low Side Sense
Disabled
Low Side Sense
Enabled
–0.3
VDIFF_IMON
VIN_GPIO
VOUT
Low voltage IMON1 differential voltage
Digital input voltage
0
500
5.5
mV
V
–0.3
–0.3
–0.3
Open-drain output voltage
HVOUT [1:4]
13.2
5.5
V
GPIO[1:6],
GPIO[8:10]
V
TA
Ambient Temperature
–40
+85
oC
1. The VCC of the I/O bank of the MachXO2, MachXO3, ECP5, LPTM21L, or LPTM21 that is used for the ASC-I/F needs to be connected to
the VCCA of the respective ASC device. See System Connections section for more details
2. HIMON circuits are operational down to 3 V. Accuracy is guaranteed within Recommended Operating Conditions
Analog Specifications
Symbol
Parameter
Conditions
Min.
Typ.
Max
Units
ICCA
Supply Current
VCCA = 3.3 V,
Ta 25 oC
25
35
mA
ICC-HVOUT
Supply Current Adder per HVOUT
VHVOUT = 12 V,
2
mA
mA
I
SRC = 100 uA,
VCCA = 3.3 V,
Ta 25 oC
ICCPROG
Supply Current during
Programming
VCCA = 3.3 V,
Ta 25 oC
40
ESD Performance
Please refer to the Platform Manager 2 Product Family Qualification Summary for complete qualification data,
including ESD performance.
4
L-ASC10
In-System Programmable
Hardware Management Expander
Power-On Reset
Symbol
Parameter
Conditions
Min
Typ.
Max.
Units
µs
TRST
Delay from VTH to start-up state
100
TSAFE
Delay from RESETb release to ASC Safe
State Exit and I/O Release1, 2
1.8
ms
TSAFE2
TGOOD
TWRCLK
TBRO
Delay from WRCLK start to ASC Safe State
Exit and I/O Release1, 2, 3
56
µs
µs
ms
µs
Delay from I/O release to AGOOD asserted
high in FPGA section4
16
Delay from RESETb release to
1.4
WRCLK start5
Minimum duration brown out required to
trigger RESETb
1
5
TPOR
VTL
VTH
VT
Delay from Brown out to reset state
Threshold below which RESETb is LOW
Threshold above which RESETb is Hi-Z
Threshold above which RESETb is valid
Capacitive load on RESETb
13
µs
V
2.3
2.7
0.8
V
V
CL
200
pF
1. Both TSAFE and TSAFE2 must complete before I/O are released from Safe State.
2. During the calibration period before TSAFE and TSAFE2, the ASC may ignore RESETb being driven low. After TSAFE and TSAFE2, the ASC
can be reset by another device by driving RESETb low.
3. Safe State is released at ASC after a fixed number (64) of WRCLK cycles (typ. 8 MHz frequency) and three ASC-I/F data packets are prop-
erly detected.
4. AGOOD asserted in the FPGA on the next ASC-I/F packet after I/O exits Safe State as ASC.
5. Parameter is dependent on the FPGA configuration refresh time during POR. See Platform Manager 2, MachXO2, MachXO3, or ECP5 data
sheet for details.
Figure 3. ASC Power-On Reset
VTH
TBRO
VCCA
VTL
VT
TRST
TPOR
RESETb
TSAFE2
TSAFE
I/O
Release
TGOOD
AGOOD
TWRCLK
WRCLK
Brownout Behavior
Power On Reset - Startup
5
L-ASC10
In-System Programmable
Hardware Management Expander
Voltage Monitors1
Symbol
Parameter
Input Resistance
Input Capacitance
Programmable trip-point Range
Conditions
Min
Typ
65
8
Max
Units
k
RVMON_in
CVMON_in
55
75
pF
V
MON Range
0.075
5.734
0.7
Volts
%
V
MON Accuracy
Absolute accuracy of any trip-point VMON voltage > 0.650 V
– Differential VMON pins
0.2
Single-ended VMON pins
VMON voltage > 0.650 V
0.3
1
0.9
%
%
VMON HYST
Hysteresis of any trip-point (relative
to setting)
VMON CMR
VZ Sense
Differential VMON Common mode
rejection ratio
60
dB
Low Voltage Sense Trip Point Error
– Differential VMON1-4
Trip Point = 0.075 V
Trip Point = 0.150 V
Trip Point = 0.300 V
Trip Point = 0.545 V
Trip Point = 0.080 V
Trip Point = 0.155 V
Trip Point = 0.310 V
Trip Point = 0.565 V
–5
+5
mV
mV
mV
mV
mV
mV
mV
mV
–5
+5
–10
–15
–10
–15
–25
–55
+10
+15
+10
+15
+25
+55
Low Voltage Sense Trip Point Error
– Single-Ended VMON5-9
High Voltage Monitor
HVMON Range High Voltage VMON programmable
trip-point range
0.3
13.2
1.0
Volts
%
HVMON Accuracy HVMON Absolute accuracy of any
trip-point
HVMON voltage > 1.8 V
0.4
VZ Sense
Low Voltage Sense Trip Point Error -
HVMON pin
Trip Point = 0.220 V
Trip Point = 0.425 V
Trip Point = 0.810 V
Trip Point = 1.280 V
–20
–35
+20
+35
mV
mV
mV
mV
–75
+75
–130
+130
1. VMON accuracy may degrade based on SSO conditions of hardware management controller ASC-I/F. See the System Connections section
for more details.
6
L-ASC10
In-System Programmable
Hardware Management Expander
Current Monitors
Symbol
Parameter
Conditions
Min
Typ
Max
Units
IIMONPleak
IMON1P input leakage
Low Side Sense Disabled
Fast Trip Point Vsns =
500 mV
–2
250
µA
Low Side Sense Enabled
Fast Trip Point Vsns =
500 mV
–2
–2
40
2
µA
µA
µA
µA
IIMONNleak
IMON1N input leakage
Low Side Sense Disabled
Fast Trip Point Vsns =
500 mV
Low Side Sense Enabled –200
Fast Trip Point Vsns =
500 mV
2
IHIMONPleak
IHIMONNleak
HIMONP input leakage
Fast Trip Point Vsns =
500 mV
550
350
HIMONN_HVMON input leakage
µA
%
I
I
I
MONA/B Accuracy2 HIMON, IMON1A/B Comparator
Gain = 100x
8
5
Trip Point accuracy
Gain = 50x
%
Gain = 25x
3
%
Gain = 10x
2
%
MONA/B Gain
Programmable Gain Setting
Four settings in software
10
25
50
100
8
V/V
V/V
V/V
V/V
%
MONF Accuracy2 Fast comparator trip-point accuracy Vsns1 = 50 mV, 100 mV, or
150 mV
Vsns = 200 mV, 250 mV,
or 300 mV
5
3
%
%
Vsns = 400 mV or
500 mV
tIMONF
Fast comparator response time
1
µs
1. Vsns is the differential voltage between IMON1P and IMON1N (or HIMONP and HIMONN).
2. IMON accuracy may degrade based on SSO conditions of hardware management controller ASC-I/F. See the System Connections section
for more details.
7
L-ASC10
In-System Programmable
Hardware Management Expander
ADC Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Bits
µs
Resolution
10
tCONVERT
Conversion Time from I2C Request
200
Voltage Monitors
VVMON-IN
Input Range Full scale
Programmable
0
0
2.048
5.91
V
Attenuator = 1
Programmable
Attenuator = 3
LSB
ADC Step Size
Programmable
2
6
mV
Attenuator = 1
Programmable
Attenuator = 3
EVMON-attenuator
Error due to attenuator
Programmable
+/– 0.1
%
V
Attenuator = 3
High Voltage Monitor
VHVMON-IN Input Range Full scale
Programmable
Attenuator = 4
0
0
8.192
13.21
Programmable
Attenuator = 8
LSB
ADC Step Size
Programmable
Attenuator = 4
8
mV
Programmable
Attenuator = 8
16
EHVMON-attenuator Error due to attenuator
Programmable
+/–0.2
+/–0.4
%
%
Attenuator = 4
Programmable
Attenuator = 8
Current Monitors
tIMON-sample
VIMON-IN
LSB
Sample period of HIMON and
IMON1 conversions for averaged
value
4 Settings via I2C
1
2
4
8
ms
mV
mV
command
Input Range Full scale1
Programmable Gain 10x
Programmable Gain 25x
Programmable Gain 50x
Programmable Gain 100x
Programmable Gain 10x
Programmable Gain 25x
Programmable Gain 50x
Programmable Gain 100x
0
0
0
0
200
80
40
20
ADC Step Size
0.2
0.08
0.04
0.02
1. Differential voltage applied across HIMONP/IMON1P and HIMONN/IMON1N before programmable gain amplification.
8
L-ASC10
In-System Programmable
Hardware Management Expander
ADC Error Budget Across Entire Operating Temperature Range
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TADC Error
Total ADC Measurement Error Measurement Range 600 mV - 2.048 V,
8
+/– 4
8
mV
at Any Voltage (Differential
Analog Inputs)1, 3
VMONxGS > –100 mV, Attenuator =1
Measurement Range 600 mV - 2.048 V,
VMONxGS > –200 mV, Attenuator =1
+/– 6
mV
Measurement Range 0 - 2.048 V,
VMONxGS > –200 mV, Attenuator =1
+/– 10
+/– 4
mV
mV
Total Measurement Error at
Any Voltage (Single-Ended
Analog Inputs including
IMON)1, 2, 3
Measurement Range 600 mV - 2.048 V,
Attenuator =1
–8
8
1. Total error, guaranteed by characterization, includes INL, DNL, Gain, Offset, and PSR specs of the ADC.
2. Programmable gain error on IMON not included.
3. ADC accuracy may degrade based on SSO conditions of hardware management controller ASC-I/F. See the System Connections section
for more details
Temperature Monitors
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TMON_REMOTE Temp Error – Remote Sensor Ta=–40 to +85 ºC
1
ºC
Accuracy1, 7
Td=–64 to 150 ºC
TMON_INT
Accuracy7
Internal Sensor – Relative to Ta=–40 to +85 ºC
ambient6
1
ºC
ºC
ºC
TMON
Resolution
Measurement Resolution
0.25
TMON Range
Programmable threshold
range
–64
155
TMON Offset
Temperature offset
Programmable in software
–64
0
63.75
63
ºC
ºC
TMON
Hysteresis of trip points
Programmable in software
Hysteresis
2
tTMON_settle
Temperature measurement
settling time3
Measurement Averaging Coefficient = 1
Measurement Averaging Coefficient = 8
Measurement Averaging Coefficient = 16
Programmable in software
15
ms
ms
ms
120
240
Tn
Ideality Factor n
0.9
2
Tlimit
Temperature measurement
limit4
160
ºC
pF
CTMON
Maximum capacitance
between TMONP and TMONN
pins
200
200
RTMONSeries
Equivalent external resistance
to sensor5
ohms
1. Accuracy number is valid for the use of a grounded collector pnp configuration, programmed with proper ideality factor, and 16x measure-
ment filter enabled. Any other device or configuration can have additional errors, including beta, series resistance and ideality factor accu-
racy. See the Temperature Monitors section for more details.
2. Settling time based on one TMON enabled. For multiple TMONs, settling time can be multiplied by the number of enabled TMON channels.
3. Settling time is defined as the time it takes a step change to settle to 1% of the measured value.
4. All values above Tlimit read as 0x3FF over I2C. There is no cold temperature limiting reading, although performance is not specified below
–64 oC.
5. This is the maximum series resistance which the TMON circuit can compensate out. Equivalent series resistance includes all board trace
wiring (TMONP and TMONN) as well as parasitic base and emitter resistances. Re=1/gm should not be included as part of series resis-
tance.
6. Internal sensor is subject to self-heating, dependent on PCB design and device configuration. Self-heating not included in published accu-
racy.
7. TMON accuracy may degrade based on SSO conditions of hardware management controller ASC-I/F. See the System Connections section
for more details.
9
L-ASC10
In-System Programmable
Hardware Management Expander
Digital Specifications
Symbol
Parameter
Conditions
Min
Typ
Max
Units
IIL,IIH
Input Leakage, no pull-up,
+/– 10
µA
pull-down2
IPD
Active Pull-Down Current2
GPIO[1:10] configured as Inputs, Inter-
nal Pull-Down enabled
200
175
35
µA
µA
µA
µA
V
IPD-ASCIF
IOH-HVOUT
IPU-RESETb
VIL
Input Leakage (WDAT and
WRCLK)3
Internal Pull-Down
Output Leakage Current
HVOUT[1:4] in open drain mode and
pulled up to 12 V
100
0.8
Input Pull-Up Current
(RESETb)
–50
Voltage input, logic low
GPIO[1:10]
SCL, SDA
30%
VCCA
VIH
Voltage input, logic high
GPIO[1:10]
SCL, SDA
2.0
V
V
70%
VCCA
VOL
HVOUT[1:4] (open drain
mode)
ISINK = 10 mA
ISINK = 20 mA
0.8
GPIO[1:6], GPIO[8:10]
All digital outputs
1
ISINKTOTAL
130
mA
1. Sum of maximum current sink from all digital outputs combined. Reliable operation is not guaranteed if this value is exceeded.
2. During safe-state, all GPIO default to output, see the Safe State of Digital Outputs section for more details. GPIO[1:6] and GPIO[10] default
to active low output. This will result in a leakage current dependent on the input voltage which can exceed the specified input leakage
3. WRCLK and WDAT pins may see transients above 1 mA in hot socket conditions. DC levels will remain below 1 mA.
High Voltage FET Drivers
Symbol
Parameter
Conditions
Min
Typ
12
Max
Units
VPP
Gate driver output voltage
Four settings in software
Volts
10
8
6
IOUTSRC
Gate driver source current
(HIGH state)
Four settings in software
Four settings in software
Two settings in software
12.5
25
µA
µA
50
100
100
250
500
3000
15.625
31.25
IOUTSINK
Gate driver sink current
(LOW state)
Frequency
Duty Cycle
Switched Mode Frequency
kHz
Switched Mode Programma- Programmable in software
ble Duty Cycle Range
6.25
93.75
%
%
Duty Cycle step size
6.25
10
L-ASC10
In-System Programmable
Hardware Management Expander
Margin/Trim DAC Output Characteristics
Symbol
Parameter
Conditions
Min
Typ.
Max.
Units
Resolution
8 (7 +
sign)
Bits
FSR
Full scale range
+/– 320
2.5
mV
mV
µA
µA
V
LSB
LSB step size
IOUT
Output source/sink current
Tri-state mode leakage
–200
200
ITRIM_Hi-Z
BPZ
0.1
0.6
Bipolar zero output voltage
(code=80h)
Four settings in software
0.8
1.0
1.25
tS
TrimCell output voltage settling DAC code changed from 80H to FFH or
2.5
ms
time1
80H to 00H
Single DAC code change
256
µs
pF
C_LOAD
TOSE
Maximum load capacitance
50
Total open loop supply voltage Full scale DAC corresponds to +/– 5%
error2
supply voltage variation
–1%
+1%
V/V
1. To 1% of set value with 50 pF load connected to trim pins.
2. Total resultant error in the trimmed power supply output voltage referred to any DAC code due to DAC’s INL, DNL, gain, output impedance,
offset error and bipolar offset error across the temperature, and VCCA ranges of the device.
Fault Log
Symbol
Parameter
Conditions
Min
Typ.
Max.
Units
Records
Number of available fault log
records in EEPROM
16
Records
tfaultTrigger
tfaultRecord
tfaultWrite
Minimum active time of trigger
signal to start fault recording
64
µs
ms
ms
Time to copy fault record to
EEPROM
5
Time to complete writing fault
record in EEPROM
10
Oscillator
Symbol
Parameter
Internal ASC0 Clock
Externally Applied Clock
Conditions
Min
7.6
7.6
Typ.
Max.
8.4
Units
MHz
MHz
CLKASC
8
8
CLKext
8.4
11
L-ASC10
In-System Programmable
Hardware Management Expander
Propagation Delays
Symbol
Parameter
Conditions
Glitch Filter Off
Min
Typ.
Max.
Units
Voltage Monitors
tVMONtoFPGA
Propagation delay VMON
input to signal update at FPGA
48
96
µs
µs
µs
µs
Glitch Filter ON
Glitch Filter Off
Glitch Filter ON
2
tVMONtoOCB
Propagation delay VMON
input to output update at OCB
16
64
Current Monitors
tIMONtoFPGA
Propagation delay IMON input Glitch Filter Off
48
96
µs
µs
µs
µs
µs
to signal update at FPGA
Glitch Filter ON
2
tIMONtoOCB
Propagation delay IMON input Glitch Filter Off
16
64
1
to output update at OCB
Glitch Filter ON
2
tIMONFtoOCB
Propagation delay IMONF
input to output update at OCB
Temperature Monitors
tTMONtoFPGA
Propagation delay TMON
Monitor Alarm Filter Depth = 1
Monitor Alarm Filter Depth = 16
15
ms
ms
input to signal update at
240
FPGA1
GPIO – Inputs
tGPIOtoFPGA
Propagation delay GPIO input
to signal update at FPGA
32
32
32
32
µs
ns
2
tGPIOtoOCB
Propagation delay GPIO input
to output update at OCB
50
50
GPIO – Outputs
tFPGAtoGPIO
Propagation delay FPGA sig-
nal update to GPIO output
µs
ns
3
tOCBtoGPIO
Propagation delay OCB input
to output update at GPIO
HVOUT
tFPGAtoHVOUT
Propagation delay FPGA sig-
nal update to HVOUT output
µs
ns
3, 4
tOCBtoHVOUT
Propagation delay OCB input
to output update at HVOUT
110
TRIM DAC
tFPGAtoTrimOE
Propagation delay FPGA sig-
nal update to TRIM_OE
update
µs
1. Propagation delay based on one TMON enabled. For multiple TMONs, propagation delay can be multiplied by the number of enabled TMON
channels.
2. OCB output propagation delays measured using time delay to GPIO output from OCB. Propagation delay is measured on falling GPIO out-
puts. Rising output propagation time will be dependent on external pull-up resistor.
3. OCB input propagation delays measured using time delay from GPIO input to OCB. Propagation delay is measured on falling GPIO outputs.
Rising output propagation time will be dependent on external pull-up resistor.
4. HVOUT propagation delay measured with HVOUT in open-drain mode, with switched mode disabled. Propagation delay in charge pump
mode is dependent on external load and HVOUT settings.
12
L-ASC10
In-System Programmable
Hardware Management Expander
ASC Interface (ASC-I/F) Timing Specifications1
Symbol
fwrclk
tASC_HLD
Parameter
Conditions
Min
Typ
Max
Units
MHz
ns
WRCLK frequency
8
Hold time between WRCLK
falling edge and WDAT transi-
tion
0
tASC_SU
Setup time between WDAT
transition and WRCLK rising
edge
25
ns
ns
tASC_OUT
Delay from WRCLK falling
edge to RDAT transition
50
1. All timing conditions valid for VCCIO = 3.3 V at FPGA ASC-I/F and ASC VCCA range of 2.8 V to 3.6 V.
Figure 4. ASC Interface (ASC-I/F) Timing Diagram
WRCLK
tASC HLD
_
WDAT
tASC_SU
RDAT
tASC_OUT
I2C Port Timing Specifications
Symbol
Parameter
Min.
Max.
400
Units
kHz
fMAX
Maximum SCL clock frequency
1. ASC supports the following modes:
a. Standard-mode (Sm), with a bit rate up to 100 kbit/s (user and configuration mode)
b. Fast-mode (Fm), with a bit rate up to 400 kbit/s (user and configuration mode)
2. Refer to the I2C specification for timing requirements.
13
L-ASC10
In-System Programmable
Hardware Management Expander
Theory of Operation
Hardware Management System
The ASC Hardware Management Expander is designed to seamlessly increase the number of analog sense and
control channels in the hardware management section of a circuit board. The device functions as a hardware man-
agement expander in systems with the Lattice Platform Manager 2, MachXO2, MachXO3, or ECP5 FPGAs. The
functional blocks for analog voltage, current and temperature monitoring, measurement, and control are built into
the ASC. The ASC depends on the Platform Manager 2, MachXO2, MachXO3, or ECP5 FPGA to interpret the ana-
log monitor status signals and provide control commands.
The Platform Manager 2, MachXO2, MachXO3, or ECP5 FPGA includes the hardware management control logic
and other plug-in IP components to support functions like Fan Control, or Voltage by Identification (VID). ASC
devices can be added to the hardware management system to scale with application requirements and are con-
nected to the same Platform Manager 2, MachXO2, MachXO3, or ECP5 FPGA. This architecture supports a single
centralized hardware management logic design, with up to eight distributed ASC devices. The basic system con-
cept is shown in Figure 5. The connections are described in detail in the System Connections section.
Figure 5. Hardware Management System with ASC Hardware Management Expander
To Additional
ASC Devices
Platform Manager 2 / MachXO2 /
ASC Hardware Management Expander
MachXO3 / ECP5 FPGA
MOSFET & Digital I/O Drive
(HVOUTs &GPIO)
Output Control
Block
Hardware
Management
Control Logic
Analog Monitors, Inputs
Outputs, Trim Controls
ASC-I/F
Logic
ASC
Interface
(ASC-I/F)
ADC
Non-
Volatile
Fault Log
Programming,
Trim Targets
IP Components
(Fan Control, VID, etc.)
2
2
I
C
I
C
ADC
Interface
Interface
Analog Measurements
Trim & Margin
Control
To Additional
ASC Devices
The Hardware Management System is configured using Platform Designer, a part of Lattice Diamond software.
Platform Designer provides an easy to use graphical and spreadsheet based interface. Platform Designer automat-
ically generates the device memory configuration based on the options selected in the software. See the For Fur-
ther Information section for more details.
14
L-ASC10
In-System Programmable
Hardware Management Expander
Voltage Monitor Inputs
The ASC provides ten independently programmable voltage monitor input circuits. There are nine standard voltage
channels and one high voltage channel. The standard voltage channels are shown in Figure 6, while the high volt-
age channel is described in the High Voltage Monitor section. Two individually programmable trip-point compara-
tors are connected to each voltage monitoring input. Each comparator reference has programmable trip points over
the range of 0.075 V to 5.734 V. The 75 mV ‘zero-detect’ threshold allows the voltage monitors to determine if a
monitored signal has dropped to ground level. This feature is especially useful for determining if a power supply’s
output has decayed to a substantially inactive condition after it has been switched off.
Figure 6. ASC Voltage Monitors
To ADC
CompA/Window
Differential
Input Buffer X*
Select
Comp A
VMONx
VMONx_A
Logic Signal
VMONxGS*
Trip Point A
Glitch
Filter
TO
ASC-I/F
& OCB
Comp B
VMONx_B
Logic Signal
Glitch
Filter
Trip Point B
Analog Input
Window Control
Filtering
VMONx Status
I2C Interface Unit
*Differential Input Buffer X and VMONxGS pins are not present for single-ended VMON x inputs.
Figure 6 shows the functional block diagram of one of the nine voltage monitor inputs - ‘x’ (where x = 1...9). Each
voltage monitor can be divided into three sections: Analog Input, Window Control, and Filtering. The first section
provides a differential input buffer to monitor the power supply voltage through VMONx (to sense the positive termi-
nal of the supply) and VMONxGS (to sense the power supply ground). Differential voltage sensing minimizes inac-
curacies in voltage measurement with ADC and monitor thresholds due to the potential difference between the
ASC device ground and the ground potential at the sensed node on the circuit board.
The voltage output of the differential input buffer is monitored by two individually programmable trip-point compara-
tors, shown as Comp A and Comp B. The differential input buffer shown above is not present for any of the single-
ended VMON inputs. VMON1-4 are differential inputs, while VMON5-10 are single-ended.
Each comparator outputs a HIGH signal to the ASC-I/F if the voltage at its positive terminal is greater than its pro-
grammed trip point setting; otherwise it outputs a LOW signal. The VMON4A and VMON9A comparators also out-
put their status signals to the OCB.
Hysteresis is provided by the comparators to reduce false triggering as a result of input noise. The hysteresis pro-
vided by the voltage monitor is a function of the input divider setting. Table 1 lists the typical hysteresis versus volt-
age monitor trip-point.
AGOOD Logic Signal
All the VMON, IMON and TMON comparators auto-calibrate following a power-on reset event. During this time, the
digital glitch filters are also initialized. This process completion is signaled by an internally generated logic signal:
AGOOD. The ASC-I/F will not begin communicating valid VMON status bits or receiving GPIO control signals until
the AGOOD signal is initialized.
15
L-ASC10
In-System Programmable
Hardware Management Expander
Programmable Over-Voltage and Under-Voltage Thresholds
Figure 7 shows the power supply ramp-up and ramp-down voltage waveforms. Because of hysteresis, the compar-
ator outputs change state at different thresholds depending on the direction of excursion of the monitored power
supply.
Figure 7. Power Supply Voltage Ramp-up and Ramp-down Waveform and the Resulting Comparator Output
(a) and Corresponding to Upper and Lower Trip Points (b)
UTP
LTP
(a)
(b)
Comparator Logic Output
During power supply ramp-up the comparator output changes from logic zero to one when the power supply volt-
age crosses the upper trip point (UTP). During ramp down the comparator output changes from logic state one to
zero when the power supply voltage crosses the lower trip point (LTP). To monitor for over voltage fault conditions,
the UTP should be used. To monitor under-voltage fault conditions, the LTP should be used. The upper and lower
trip points are automatically selected in software depending on whether the user is monitoring for an over-voltage
condition or an under-voltage condition. Table 1 shows the comparator hysteresis versus the trip-point range.
Table 1. Voltage Monitor Comparator Hysteresis vs. Trip-Point
Trip-point Range (V)
Hysteresis (mV)
Low Limit
0.66
High Limit
0.79
0.9
8
0.79
10
0.94
1.12
1.33
1.58
1.88
2.24
2.66
3.16
3.76
4.82
5.73
0.57
12
1.12
14
1.33
17
1.58
20
1.88
24
2.24
28
2.66
34
3.16
40
4.05
51
61
4.82
0.075
0 (Disabled)
16
L-ASC10
In-System Programmable
Hardware Management Expander
The window control section of the voltage monitor circuit is an AND gate (with inputs: an inverted COMPA “ANDed”
with COMPB signal) and a multiplexer that supports the ability to develop a ‘window’ function in hardware. Through
the use of the multiplexer, voltage monitor’s ‘A’ output may be set to report either the status of the ‘A’ comparator, or
the window function of both comparator outputs. The voltage monitor’s ‘A’ output indicates whether the input signal
is between or outside the two comparator thresholds. Important: This windowing function is only valid in cases
where the threshold of the ‘A’ comparator is set to a value higher than that of the ‘B’ comparator. Table 2 shows the
operation of window function logic.
Table 2. Voltage Monitoring Window Logic
Window
(B and Not A)
Input Voltage
Comp A
Comp B
Comment
VIN < Trip-Point B < Trip-Point A
Trip-Point B <VIN < Trip-Point A
Trip-Point B < Trip-Point A < VIN
0
0
1
0
1
1
0
1
0
Outside window, low
Inside window
Outside window, high
Note that when the ‘A’ output of the voltage monitor circuit is set to windowing mode, the ‘B’ output continues to
monitor the output of the ‘B’ comparator. This can be useful in that the ‘B’ output can be used to augment the win-
dowing function by determining if the input is above or below the windowing range.
The third section in the voltage monitor circuit is a glitch filter. When enabled, glitches of less than 64 µs will not
result in the comparator output changing. This results in a comparator output delay of 64 µs (typical) for all compar-
ator transitions. This is especially useful for reducing the possibility of false triggering from noise that may be pres-
ent on the voltages being monitored. When the filter is disabled, the comparator output will be delayed by 16 µs
(typical). See the Propagation Delays section for more details.
The comparator status can be read from the I2C interface. For details on the I2C interface, please refer to the I2C
Interface section of this data sheet.
Current Monitor Inputs
The ASC provides two current monitor circuits as shown in Figure 8. This includes a low-voltage current monitor
(with a common mode voltage up to around 6V, see V
in Recommended Operating Conditions section)
IN_IMONP
and a high-voltage current monitor (with a common mode voltage range of up to around 13 V, see V
in
IN_HIMONP
Recommended Operating Conditions section). The low-voltage and high-voltage current monitors share the same
basic functional blocks, which are described in this section. Only the low-voltage current monitor supports the low-
side sensing mode (shown in Figure 8). The high-voltage current monitor shares input pins with the high-voltage
monitor described in the next section.
The current monitor circuits have a differential input that is connected to an external shunt resistor. The differential
input goes to a pair of programmable gain amplifiers (PGA) and a fast comparator. The output of PGA A is con-
nected to the ADC and the programmable trip point comparator A. The output of PGA B is connected to the pro-
grammable trip point comparator B. The output of the fast comparator is routed to the on-chip Output Control Block
(OCB). This signal is useful for fast overcurrent or short circuit shutdown scenarios.
17
L-ASC10
In-System Programmable
Hardware Management Expander
Figure 8. ASC Current Monitor
ASC
Low-Side Sense Mode**
Trip Point F
HIMON_F / IMON_F
To OCB (Fast Fault Detection)
FAST
To ADC
Window Mode Select
Comp A
HIMONP
IMON1P
HIMON_A / IMON1_A
Logic Signal
External Current
Sense Resistor
PGA A
HIMONN_HVMON
IMON1N
Trip Point A
Glitch
Filter
TO
HIMON_B /
IMON1_B
Logic Signal
ASC-I/F
PGA B
and OCB
Comp B
Direction of
current flow
Glitch
Filter
Trip Point B
To HVMON*
Voltage
Monitor
Pre-Amplified Input
Amplified Input
Window Control
Filtering
IMON Status
I2C Interface Unit
*HVMON signal is only present in HIMON Current Monitor
**Low-Side Sense is only present in low-voltage IMON Current Monitor
The Current Monitors can be divided into four sections: Pre-Amplified Input, Amplified Input, Window Control, and
Filtering. The first section includes the differential input pins IMON1P and IMON1N (low-voltage current monitor) or
HIMONP and HIMONN_HVMON (high-voltage current monitor). These pins are connected to the PGA circuits as
well as the direct differential connection to the Fast Fault Detector.
The differential input is monitored by the fast fault detector. The fast fault detector has coarse accuracy and eight
programmable trip points. The key feature of the fast fault detector is its response time. The fast fault detector out-
puts a HIGH signal to the OCB if the differential voltage across the current sensing shunt exceeds the programmed
trip point setting. The current shunt is normally connected on the high-side of the input voltage. However, the low-
voltage current monitor also supports low-side sensing. The low-side sensing mode should be enabled when sens-
ing negative voltage supplies (such as –48 V) or if the current sense resistor is placed in the return line between the
load and ground. This insures proper operation of the fast comparator in a low-side sensing circuit.
Table 3 shows the available trip points for the fast fault detector vs. three frequently used sense resistor values.
Table 3. Fast Fault Detector Current Trip Points vs. Frequently Used Sense Resistor Values
Frequently Used Sense Resistor Value
Trip Point Setting
1 Milliohm
50 A
5 Milliohm
10 A
10 Milliohm
5 A
50 mV
100 mV
150 mV
200 mV
250 mV
300 mV
400 mV
500 mV
100 A
150 A
200 A
250 A
300 A
400 A
500 A
20 A
10 A
30 A
15 A
40 A
20 A
50 A
25 A
60 A
30 A
80 A
40 A
100 A
50 A
18
L-ASC10
In-System Programmable
Hardware Management Expander
The Programmable Gain Amplifiers have gain settings of 10x, 25x, 50x, and 100x. The PGA circuits amplify the
voltage differential across the current shunt and pass the results to the amplified input section of the current moni-
tor.
The Amplified Input section provides two individually programmable trip-point comparators, shown as Comp A and
Comp B above. Each comparator supports four different trip points. Combining these trip points with the respective
PGA settings, 16 unique threshold levels are selected for each current monitor.
Table 4 shows the available voltage differential trip points.
Table 4. Comparator Trip Points
Programmable Gain Amplifier Setting (V/V)
Trip Point Setting
10 x
25 x
50 x
100 x
1
2
3
4
75 mV
100 mV
140 mV
190 mV
30.5 mV
40.5 mV
56.5 mV
77 mV
15.5 mV
20.5 mV
28.5 mV
39 mV
8 mV
10.5 mV
14.5 mV
20 mV
The output of PGA A is also passed to the on-chip ADC. The current is measured and averaged by the ADC at reg-
ular intervals, as described in the Current Measurement with ADC section of the datasheet.
The window control section of the current monitor circuit is an AND gate (with inputs: an inverted COMPA “ANDed”
with COMPB signal) and a multiplexer that supports the ability to develop a ‘window’ function in hardware, similar to
the voltage monitor window function. Through the use of the multiplexer, the current monitor’s ‘A’ output may be set
to report either the status of the ‘A’ comparator, or the window function of both comparator outputs. The current
monitor’s ‘A’ output indicates whether the input signal is between or outside the two comparator thresholds. Impor-
tant: This windowing function is only valid in cases where the threshold of the ‘A’ comparator is set to a value higher
than that of the ‘B’ comparator. Table 5 shows the operation of window function logic.
Table 5. IMON Window Mode Behavior
Window
(B and Not A)
Input Voltage
Comp A
Comp B
Comment
IIN < Trip-Point B < Trip-Point A
Trip-Point B <IIN < Trip-Point A
Trip-Point B < Trip-Point A < IIN
0
0
1
0
1
1
0
1
0
Outside window, low
Inside window
Outside window, high
Note that when the ‘A’ output of the current monitor circuit is set to windowing mode, the ‘B’ output continues to
monitor the output of the ‘B’ comparator. This can be useful in that the ‘B’ output can be used to augment the win-
dowing function by determining if the input is above or below the windowing range.
The fourth section in the current monitor circuit is a glitch filter. When enabled, glitches of less than 64 µs will not
result in the comparator output changing. This results in a comparator output delay of 64 µs (typical) for all compar-
ator transitions. This is especially useful for reducing the possibility of false triggering from noise that may be pres-
ent on the currents being monitored. When the filter is disabled, the comparator output will be delayed by 16 µs
(typical). See the Propagation Delays section for more details.
The comparator status can be read from the I2C interface. For details on the I2C interface, please refer to the I2C
Interface section of this data sheet.
High Voltage Monitor
The High Voltage Monitor circuit is a single-ended high voltage monitor (HVMON) which is connected to the same
input pin as the High Voltage Current Monitor (HIMONN_HVMON). Figure 9 shows the single-ended monitor cir-
cuit, which monitors the voltage on the HIMON pin. Extending the input voltage range with an external voltage
19
L-ASC10
In-System Programmable
Hardware Management Expander
divider as described in AN6041, Extending the VMON Input Range of Power/Platform Management Devices is not
recommended for the HVMON inputs.
Figure 9. HVMON Monitor Circuit
From Current
Monitor
HIMONN_HVMON
To ADC
Comp A/Window
Select
Comp A
HVMON_A
Logic Signal
Trip Point A
Glitch
Filter
TO
ASC-I/F
HVMON_B
Comp B
Logic Signal
Glitch
Filter
Trip Point B
Analog Input
Window Control
Filtering
VMONx Status
I2C Interface Unit
The HVMON follows the same structure as the Voltage Monitor circuits. Two individually programmable trip-point
comparators are connected to the HIMONN_HVMON pin voltage. Each of the comparator references has 408 pro-
grammable trip points, over a range of 0.227 V to 13.226 V.
The functional block diagram, shown in Figure 9, is a similar structure to the other single-ended Voltage Monitor cir-
cuits. Each comparator outputs a HIGH signal to the ASC-I/F if the voltage at its positive terminal is greater than its
programmable trip point setting. A hysteresis of approximately 1% of the setpoint is provided by the comparators to
reduce false triggering. Table 6 shows a typical hysteresis versus voltage monitor trip point.
Table 6. HVMON Hysteresis vs Trip Point Range
Trip-point Range (V)
Hysteresis (mV)
Low Limit
1.91
High Limit
2.27
2.7
22
2.27
28
2.69
3.2
30
3.16
3.76
4.43
5.24
6.17
7.20
8.43
9.87
11.52
13.2
1.28
38
3.72
44
4.40
52
5.18
61
6.04
72
84
7.08
8.29
99
9.68
115
11.17
0.23
133
0 (Disabled)
The Over-Voltage and Under-Voltage thresholds, along with the window mode and glitch filter, are identical to the
features described in the voltage monitor section.
20
L-ASC10
In-System Programmable
Hardware Management Expander
VMON and IMON Measurement with the On-Chip Analog to Digital Converter (ADC)
The ASC has an on-chip analog to digital converter that can be used for measuring the voltages at the VMON
inputs or the currents at the IMON inputs. This ADC is also used in closed loop trimming of DC-DC converters.
Closed loop trimming is covered later in this document.
Figure 10. ADC Monitoring VMON and IMON
HIMON PGA
Output
+
_
VMON1
IMON1 PGA
Output
To closed
Loop Trim
Circuit
Programmable Digital
Multiplier
Programmable Analog
Attenuation
+
_
x8 / x4
x3 / x1
VMON4
VMON5
ADC
÷3 / ÷1
To I2C
ADC Readout
Register
Internal
VREF -
2.048V
HVMON*
÷8 / ÷4
To I2C
IMON/HIMON
Average
IMON/HIMON
Averaging
VMON9
Register
ADC Control
Logic
From Closed
From I2C ADC
Loop Trim Circuit MUX Address
Figure 10 shows the ADC circuit arrangement within the ASC device. The ADC can measure all analog input volt-
ages up to 2.048V through the multiplexer, ADC MUX. The ADC MUX receives inputs from the High Voltage IMON
Programmable Amplifier (PGA), the IMON1 PGA, the High Voltage Monitor (HVMON) at the HIMONN_HVMON
pin, and the VMON MUX. The VMON voltages can be attenuated (divided by three) or unattenuated (divided by
one). The divided-by-three setting is used to measure voltages from 0 V to 6 V range and divided-by-one setting is
used to measure the voltages from 0 V to 2 V range. The HVMON voltage requires attenuation, with settings for
divided by eight (voltages between 8 V and 13.2 V) or divided by four (voltages between 8 V and 0 V). The HIMON
and IMON1 PGA output voltages must be kept below 2.0 V for proper ADC operation since they are not attenuated.
The ADC control logic manages the MUX and attenuation settings. The control logic manages conversion requests
from I2C and the Closed Loop Trim Circuit. The control logic also schedules regular IMON1 and HIMON conver-
sions, which are subsequently averaged and stored for user access. These IMON conversions are configured
through the I2C bus and filtered using an eight sample, weighted averaging scheme.
The control logic also sets the digital multiplication factor. This results in VMON and HVMON voltages, regardless
of attenuation setting, maintaining a 2 mV per LSB scale. (See Calculation section for more details). The IMON1/
HIMON voltages are not multiplied.
A microcontroller or FPGA IP can place a request for any VMON or IMON voltage measurement at any time
through the I2C bus. After the receipt of an I2C command, the control logic will connect the ADC to the I2C selected
VMON or IMON through the ADC MUX. The ADC output is then latched into the I2C readout registers.
21
L-ASC10
In-System Programmable
Hardware Management Expander
Calculation
The algorithm to convert the ADC code to the corresponding VMON / HVMON voltage takes into consideration the
relevant attenuation setting. In other words, if the attenuation is set to divide-by-eight, then the 10-bit ADC result is
automatically multiplied by eight to calculate the actual voltage at that VMON input. Thus, the I2C readout register is
13 bits instead of 10 bits. The other attenuator settings are also automatically compensated using the digital multi-
plier. The following formula can always be used to calculate the actual voltage from the ADC code.
Voltage at the VMONx Pins
VMON= ADC code (13 bits, converted to decimal) * 2 mV
The ADC code includes the ADC_VALUE_HIGH (8 bits) and ADC_VALUE_LOW (5 bits) read from I2C interface
Calculating the HIMON or IMON1 current is slightly more complex, and requires knowledge about the current PGA
setting and the resistance value of the current sense shunt resistor. The PGA has four settings (x10, x25, x50, and
x100) which are automatically set in the software based on the trip point selection, while the current sensing resis-
tance is chosen by the customer.
Current at the HIMON / IMON1 Pins
IMON current = ADC code (13 bits, converted to decimal) * 2 mV / (PGAsetting x Rsense)
Temperature Monitor Inputs
The ASC provides two external temperature monitor inputs and one internal temperature monitor as shown in
Figure 11.
Figure 11. Temperature Monitor
Offset
Ideality
TMON1
TMON2
Temperature
Sensor Interface
Temperature
Conversion
Measurement
Average Filter
ADC
I2C Register
TMON_INT
Comp A
Monitor
Alarm Filter
To
ASC-I/F
Trip Point A
Hysteresis A
Comp B
To
ASC-I/F
Monitor
Alarm Filter
Trip Point B
Hysteresis B
The independently programmable temperature monitor inputs can be used with internal substrate diodes on micro-
processors, FPGAs, ASICs, or with low cost external NPN or PNP transistors. The temperature sensor interface
block includes programmable support for a variety of sensor configurations as shown in Figure 12. The sensor con-
figuration settings available in the design software are described in Table 7.
22
L-ASC10
In-System Programmable
Hardware Management Expander
Figure 12. Remote TMON Diode Configurations
a
b
c
TMON_p
TMON_n
TMON_p
TMON_p
TMON_n
TMON_n
Recommended Configurations
d
e
TMON_p
TMON_p
Not Recommended
Table 7. Remote TMON Diode Configurations
Sensor
Configuration
Auto-
Compensation
Series Resistance
Compensation
Figure Number
Accuracy
Beta Compensated
PNP
11-a
Effective
Effective
Specified in recommended operat-
ing conditions
Differential PNP
11-b / 11-c
11-d / 11-e
Not effective
Not effective
Effective
Dependent on variance
or NPN or Diode
Single Ended
Not Effective
Not specified
The temperature sensor interface block also has built-in circuits to automatically compensate for the series resis-
tance of the PCB traces to the sensor as well as the intrinsic device resistance. In addition, the interface block has
circuits to compensate for the variable Beta () of the transistor sensor when it is connected in the configuration
shown in Figure 12-a. (In order for the variable compensation circuit to be effective it must be able to measure the
base current separately from the collector current.) For a discrete PNP or NPN transistor with high (approximately
100 or greater) the effect of variable beta is typically negligible. However, most substrate diode temperature sen-
sors will have a low value which can vary considerably over temperature and current density making this a very
useful feature.
The temperature signal information is converted to digital data by the dedicated TMON ADC. The digital data is
scaled and converted to a two’s complement, 11-bit temperature reading by the Temperature Conversion block.
o
The measurement resolution is 0.25 C per bit. The temperature conversion block takes into account the user
entered ideality factor and offset value.
The ideality factor (also known as the emission coefficient or the N-factor) is a measure of how closely a real diode
follows the ideal diode equation. In a real diode imperfections allow some recombination to occur in the junctions or
by other methods which are not accounted for in the ideal equation. The ASC temperature conversion block is opti-
mized for an ideality factor of 1 so any errors in the actual ideality factor of the sensor will produce a proportional
error in the temperature value (in Kelvins). The diode ideality factor can be programmed in the range from 0.9 to 2.0
to match the actual ideality factor of the sensor.
An approximate value for the ideality factor for a 2N3904 NPN transistor is 1.004 and for a 2N3906 PNP transistor
is 1.008. A substrate diode temperature sensor will typically have an ideality factor published in its data sheet.
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In-System Programmable
Hardware Management Expander
Uncertainty can be introduced in temperature measurement by using an approximate value rather than the actual
value for a 2N3904 or a 2N3906 transistor. This can lead to an error of around 0.4 oC. If the ideality factor for the
transistor being used is not published it can be determined by the ASC using the following procedure.
1. Force the system temperature to a known value (Tref).
2. With the ASC ideality factor set to 1.000, record the temperature value calculated (Tnocal).
3. Convert the Tref and Tnocal to Kelvin.
4. Divide the Tnocal (K) by Tref (K).
The result will be the actual ideality factor to be entered for the given TMON channel in the design software.
Note: The calibration is only as accurate as the Tref value. Any errors in the test equipment used will be transferred
to the ASC readings.
The temperature conversion block also provides user programmable temperature offset from –64 ºC to 63.75 ºC for
each channel’s digital data to mitigate errors due to self-heating of the sensor, systematic offset and other unfore-
seen errors.
The conversion block also includes programmable output values for detected short or open conditions at the moni-
tor input. The output levels are shown in Table 8.
Table 8. Temperature Measurement Fault Readings
Fault
Short
Open
0
1
–255.75 oC
255.75 oC
255.75 oC
–255.75 oC
The converted temperature data for each channel is stored in two registers and can be read out via I2C, after the
programmable Measurement Averaging filter. For more details about the data register format, please refer to Mea-
surement and Control Register Access in the I2C Interface section of this data sheet.
The programmable measurement filter performs exponential averaging. Data is available immediately after one
update cycle and is continually averaged using the programmable filter coefficients of 1, 8, or 16 per channel. The
filtering equation is shown below:
TempMeasx
FiltCo–1
FiltCo
----------------------------------------
-----------------------
+ TempAvex – 1
TempAvex =
FiltCo
When the temperature input changes it will require some settling time for the new value to be fully reflected in the
results register due to the averaging filter. The settling time will vary depending upon how many channels are
enabled and the programmed averaging coefficient. The settling time for various averaging coefficients and number
of channels is shown in Table 9.
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In-System Programmable
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Table 9. Temperature Measurement Settling Time1
Measurement
Averaging Coefficient
Number of
Channels Enabled
Average Settling Time
(ms)
1
8
1
1
1
2
2
2
3
3
3
14.2
114
228
28.4
227
454
42.6
341
682
16
1
8
16
1
8
16
1. Values are approximate and are not guaranteed by characterization.
In addition to the direct temperature measurement the ASC has a temperature comparison function. The digital
data of each channel is monitored by two trip-point comparators, shown as Comp A and Comp B in Figure 11. The
digital temperature data monitored at the comparators is not processed by the measurement averaging filters.
Each comparator reference has programmable trip points over the range of –64 ºC to 155 ºC with resolution of 1ºC.
Whenever the monitored temperature is above the trip point, the comparator output is set to one. The comparator
outputs are transmitted over the ASC-I/F to the FPGA, depending on the setting of the Alarm Filter.
The two comparators each support programmable Hysteresis of 0 ºC to 63 ºC. When a comparator is used for over-
temperature monitoring the programmed hysteresis value is subtracted from the trip point and when the compara-
tor is used for under-temperature monitoring the programmed hysteresis value is added to the trip point. The hys-
teresis behavior is displayed in Figure 13 and Figure 14.
Figure 13. Monitor Alarm Signal Behavior - Overtemperature (OT) Setting
Trip Point
Hysteresis
Trip Point - Hysteresis
Monitor Alarm
Signal
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In-System Programmable
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Figure 14. Monitor Alarm Signal Behavior - Undertemperature (UT) Setting
+
Trip Point Hysteresis
Hysteresis
Trip Point
Monitor Alarm
Signal
Each comparator can be individually selected as either over-temperature or under-temperature operation.
A programmable Alarm Filter (separate from the measurement averaging filter) is available at the output of the
comparators. The depth of this filter is programmable from 1 to 16. The filter monitors the comparator alarm output
each time the temperature measurement is refreshed. The filter counts up each time the comparator alarm value is
1, and down each time the comparator alarm value is 0. When the filter counter reaches the programmed filter
depth, the TMONx_A or TMONx_B signal are set to one.
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Digital Inputs/Outputs
The ASC has four dedicated digital outputs (HVOUTs) and nine General Purpose Input/Output (GPIO) pins. The
four HVOUT pins can be configured as high-voltage FET drivers or Open Drain outputs. This provides a high
degree of flexibility when interfacing to power supply control inputs or other external logic signals.
The nine GPIO pins can be configured as inputs or Open Drain outputs. Figure 15 shows a block diagram of the
GPIO circuitry. When configured as inputs, GPIO1 through GPIO10 inputs are registered and made available to the
FPGA using the ASC-I/F. GPIO5 through GPIO10 are also made available to the Output Control Block (OCB)
directly without being registered. When configured as outputs, GPIO1 through GPIO10 are controlled by the ASC-
I/F. Table 10 shows a summary of the input and output sources for each GPIO pin.
Table 10. GPIO Input and Output Sources
GPIO
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO71
GPIO8
GPIO9
GPIO10
ASC-I/F Input
OCB Input
ASC-I/F output
OCB output
Hysteretic control
Y
Y
N
N
Y
Y
N
Y
N
Y
Y
N
Y
Y
Y
Y
N
Y
N
N
Y
Y
Y
N
N
Y
Y
Y
N
N
N/A
Y
N/A
Y
N/A
Y
N/A
N
N/A
N
Y
Y
Y
N
N
Y
Y
Y
N
N
1. GPIO7 is not bonded out.
Figure 15. GPIO Block Diagram
Input Buffer
Digital Input
To OCB **
Digital Input
To ASC-I/F
GPIOx
Pin
Digital Control
From ASC-I/F
or
From OCB *
Open Drain
Output Buffer
* Digital Control comes from OCB for GPIO 2 and 3.
Digital Control comes from ASC-I/F for remaining GPIO.
** Only available for GPIO 5, 6, 7, 8, 9 and 10.
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In-System Programmable
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Output Control Block
The ASC Output Control Block (OCB) is used to control GPIO2, GPIO3, and the four HVOUTs. The Output Control
Block has two modes of operation available; Direct Output control and Hysteretic Feedback control as shown in
Figure 16.
Direct Output control is supported by various inputs which include the I2C registers, GPIO pins 5-10 (when config-
ured as inputs), the VMON4A and VMON9A comparator output signals, and the Fast IMON1 and Fast HIMON
comparator output signals. These inputs are individually selectable for each of the outputs. When these inputs are
used with the Direct Output control mode they provide a fast path for control which has very low propagation delay.
The outputs in the OCB can also be controlled from the FPGA Logic over the ASC Interface (ASC-I/F) with the nor-
mal propagation delays. See the Propagation Delays section for more details.
Figure 16. Output Control Block – Simplified Diagram
FPGA Logic (ASC–I/F)
GPIO2
I2C
Direct Output
GPIO5-10
VMON4_A and VMON9_A
Fast HIMON, IMON1
GPIO3
Control
HVOUT1
HVOUT2
HVOUT3
HVOUT4
Output
Routing
FPGA Logic (ASC–I/F)
VMON5 and VMON6
HIMON, IMON1
Hysteretic Feedback
Control
The OCB outputs can also be configured for Hysteretic Feedback control if desired. In the Hysteretic Feedback
control mode the output will be switched on and off based upon the feedback signal chosen. The available feed-
back signals are the HIMON, IMON1, VMON5, or VMON6 trip points. As the feedback signal changes it will turn
the output on or off depending upon whether it is above or below the chosen set-point and depending upon the out-
put polarity. The user logic can switch between the high and low trip points of a signal to provide additional flexibil-
ity. In addition, the FPGA Logic can be dynamically selected to provide the feedback signal over the ASC-I/F which
allows the user logic to change from a conditional output to a static value.
One example of how the Hysteretic feedback control feature can be used is to modulate a high-voltage FET driver
using the FPGA logic and the trip points to control the rate of modulation over different voltage ranges - such as in
a Hot Swap application. The design software provides an easy to use interface for configuring the device as a hot
swap controller. The software will generate the required device settings and control algorithm automatically.
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In-System Programmable
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Figure 17. HVOUT Output Routing MUX Block Diagram
OCB Routing MUX
FPGA Logic (ASC-I/F)
I2C
0
1
2
3
4
5
6
7
8
9
GPIO5
GPIO6
GPIO7
Polarity MUX
1
GPIO8
GPIO9
GPIO10
HVOUT
PWM
(1 - 4)
IMON1_F
0
HIMON_F
VMON4_A
VMON9_A
HIMON – HCM1
IMON1 – HCM2
VMON5 – HCM3
VMON6 – HCM4
10
11
12
13
14
15
Configuration Memory
Configuration Memory
Figure 17 is a generic HVOUT routing diagram that applies to all the HVOUTs and provides a bit more detail than
the simplified diagram in Figure 16. The MUX on the left is configured by Platform Designer software and selects
from either the 12 direct control signals at the top or the four Hysteretic Control Module (HCM) signals at the bot-
tom. The software is also used to select normal or inverted control. The features and configuration of the PWM and
HVOUT blocks are covered in the High Voltage Outputs section. If PWM is enabled then the output of the Polarity
MUX will enable or disable the PWM; otherwise the HVOUT will be on or off based on the Polarity Mux output sig-
nal.
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In-System Programmable
Hardware Management Expander
Figure 18. GPIO Output Routing MUX Block Diagram
OCB Routing MUX
FPGA Logic (ASC-I/F)
I2C
0
1
2
3
4
5
6
7
8
9
GPIO5
GPIO6
GPIO7
Polarity MUX
GPIO8
GPIO9
1
GPIO10
GPIO
(2 – 3)
IMON1_F
HIMON_F
VMON4_A
VMON9_A
HIMON – HCM1
IMON1 – HCM2
VMON5 – HCM3
VMON6 – HCM4
0
10
11
12
13
14
15
Configuration Memory
Configuration Memory
Figure 18 is a generic GPIO routing diagram that applies to GPIO2 & GPIO3 and it provides a bit more detail than
the simplified diagram in Figure 16. The MUX on the left is configured by Platform Designer software and selects
from either the 12 direct control signals at the top or the four Hysteretic Control Module (HCM) signals at the bot-
tom. The software is also used to select normal or inverted control. The GPIO pin will be on or off based on the
Polarity Mux output signal.
Figure 19 is a diagram of Hysteretic Control Module #1 (HCM1) which is a little more complex than the other HCMs
in the device. It is unique in that it is the only HCM that supports a dynamic selection of the Trip Point from the table;
while the other HCMs can only dynamically switch between two comparator outputs (for example a low and high
setting). The software configures the Trip Point MUX to either use a fixed configuration HIMON trip point or the
dynamic HIMON trip point which is set by the FPGA Logic based upon the operating conditions. The output of the
HIMON comparator is inverted before sending it to the Hysteretic Enable MUX.
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In-System Programmable
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Figure 19. OCB HIMON HCM1 Block Diagram
OCB Inverter
HIMON_A
Trip Point MUX
HIMON Comparator*
0
1
Configuration Memory Trip Point
FPGA Logic Trip Point (ASC-I/F)
Configuration Memory
Static Control MUX
Hysteretic Enable MUX
1
HIMON – HCM1
(To Output Routing Muxes)
0
GPIO2
GPIO3
0
1
2
3
4
5
6
7
HVOUT1
HVOUT2
HVOUT3
HVOUT4
Control Signals from FPGA Logic
(ASC-I/F)
FPGA Logic (ASC-I/F)
Configuration Memory
* HIMON Windowing and Glitch Filters are not shown in this diagram for clarity.
The input to the OCB inverter is from the glitch filter.
The Hysteretic Enable MUX is controlled by the FPGA Logic over the ASC-I/F. The HIMON comparator signal is
selected when the Hysteretic mode is enabled and the HVOUT or GPIO is controlled based on the voltage sensed
at the HIMON input pins. When the Hysteretic mode is disabled the HVOUT or GPIO is controlled by the output of
the Static Control MUX. All the input signals to the Static Control MUX come from the FPGA Logic over the ASC-
I/F. Typically the Static Control MUX is configured by the software to connect to the corresponding output being
controlled by the HCM. For example, if HCM1 is selected for HVOUT2, then the Static Control MUX would also be
set to HVOUT2. In this manner when Hysteretic Mode is disabled it is just like setting the OCB Routing MUX to
zero where the FPGA Logic controls the HVOUT or GPIO over the ASC-I/F.
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In-System Programmable
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Figure 20. OCB IMON1 HCM2 Block Diagram
IMON1
Configuration Memory Trip Point A
Comparator MUX
OCB Inverter
0
1
IMON1
Comparators*
Configuration Memory Trip Point B
FPGA Logic (ASC-I/F)
Static Control MUX
Hysteretic Enable MUX
1
IMON1 – HCM2
(To Output Routing
GPIO2
0
1
2
3
4
5
6
7
Muxes)
0
GPIO3
HVOUT1
HVOUT2
HVOUT3
HVOUT4
Control Signals from FPGA Logic
(ASC-I/F)
FPGA Logic (ASC-I/F)
Configuration Memory
* IMON Windowing and Glitch Filters are not shown in this diagram for clarity.
The input to the comparator MUX is from the glitch filters.
Figure 20 is a diagram of Hysteretic Control Module #2 (HCM2) which is also an IMON based HCM. The software
is used to select both the A and B trip points, while the FPGA Logic is used to dynamically switch between the two
comparator outputs. The output of the Comparator MUX is inverted before sending it to the Hysteretic Enable MUX.
The Hysteretic Enable MUX is controlled by the FPGA Logic over the ASC-I/F. The Comparator MUX output signal
is selected when the Hysteretic mode is enabled and the HVOUT or GPIO is controlled based on the voltage
sensed at the IMON1 input pins. When the Hysteretic mode is disabled the HVOUT or GPIO is controlled by the
output of the Static Control MUX. All the input signals to the Static Control MUX come from the FPGA Logic over
the ASC-I/F. Typically the Static Control MUX is configured by the software to connect to the corresponding output
being controlled by the HCM.
When using the hysteretic mode in hot swap applications, the design software will automatically configure the
muxes and generate the control algorithm. See the For Further Information section for more details.
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In-System Programmable
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Figure 21. OCB VMON5 HCM3 Block Diagram
VMON5
Configuration Memory Trip Point A
Comparator MUX
OCB Inverter
0
1
VMON5
Comparators*
Configuration Memory Trip Point B
FPGA Logic (ASC-I/F)
Static Control MUX
Hysteretic Enable MUX
1
VMON5 – HCM3
(To Output Routing
GPIO2
0
1
2
3
4
5
6
7
Muxes)
0
GPIO3
HVOUT1
HVOUT2
HVOUT3
HVOUT4
Control Signals from FPGA Logic
(ASC-I/F)
FPGA Logic (ASC-I/F)
Configuration Memory
* VMON5 Windowing and Glitch Filters are not shown in this diagram for
clarity. The input to the comparator MUX is from the glitch filters.
Figure 21 is a diagram of Hysteretic Control Module #3 (HCM3) which is a VMON based HCM. The software is
used to select both the A and B trip points, while the FPGA Logic is used to dynamically switch between the two
comparator outputs. The output of the Comparator MUX is inverted before sending it to the Hysteretic Enable MUX.
The Hysteretic Enable MUX is controlled by the FPGA Logic over the ASC-I/F. The Comparator MUX output signal
is selected when the Hysteretic mode is enabled and the HVOUT or GPIO is controlled based on the voltage
sensed at the VMON5 input pins. When the Hysteretic mode is disabled the HVOUT or GPIO is controlled by the
output of the Static Control MUX. All the input signals to the Static Control MUX come from the FPGA Logic over
the ASC-I/F. Typically the Static Control MUX is configured by the software to connect to the corresponding output
being controlled by the HCM.
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In-System Programmable
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Figure 22. OCB VMON6 HCM4 Block Diagram
VMON6
Configuration Memory Trip Point A
Comparator MUX
OCB Inverter
0
1
VMON6
Comparators*
Configuration Memory Trip Point B
FPGA Logic (ASC-I/F)
Static Control MUX
Hysteretic Enable MUX
1
0
VMON6 – HCM4
(To Output Routing
Muxes)
GPIO2
0
1
2
3
4
5
6
7
GPIO3
HVOUT1
HVOUT2
HVOUT3
HVOUT4
Control Signals from FPGA Logic
(ASC-I/F)
FPGA Logic (ASC-I/F)
Configuration Memory
* VMON6 Windowing and Glitch Filters are not shown in this diagram for
clarity. The input to the comparator MUX is from the glitch filters.
Figure 22 is a diagram of Hysteretic Control Module #4 (HCM4) which is a second VMON based HCM. The soft-
ware is used to select both the A and B trip points but, the FPGA Logic is used to dynamically switch between the
two comparator outputs. The output of the Comparator MUX is inverted before sending it to the Hysteretic Enable
MUX.
The Hysteretic Enable MUX is controlled by the FPGA Logic over the ASC-I/F. When the Comparator MUX output
signal is selected the Hysteretic mode is enabled and the HVOUT or GPIO is controlled based on the voltage
sensed at the VMON6 input pins. When the Hysteretic mode is disabled the HVOUT or GPIO is controlled by the
output of the Static Control MUX. All the input signals to the Static Control MUX come from the FPGA Logic over
the ASC-I/F. Typically the Static Control MUX is configured by the software to connect to the corresponding output
being controlled by the HCM.
The Platform Designer software has component interfaces that are used to simplify the task of configuring the OCB
blocks discussed in this section. For example, the Hot Swap component provides a functional interface for the
designer while setting the trip points for VMONs and IMONs, and routing them to HVOUTs using OCB paths.
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In-System Programmable
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High Voltage Outputs
In addition to being usable as digital Open Drain outputs the four HVOUT pins can be configured as high-voltage
FET drivers. Figure 23 shows the details of the HVOUT circuitry.
Figure 23. HVOUT Block Diagram
Charge Pump
Vpp
I
SOURCE
HVOUTx
Pin
ISINK
Switched Mode Select
Digital Control
from OCB
Switched Mode
Control
HVOUT / Open Drain Select
When the HVOUT is configured as a high-voltage FET driver the output either sources current from a charge pump
or sinks current. The output level at the pin can rise to a configurable maximum voltage. The maximum voltage lev-
els that are required depend on the gate-to-source threshold of the FET being driven and the power supply voltage
being switched. The maximum voltage level needs to be sufficient to bias the gate-to-source threshold on and also
accommodate the load voltage at the FET’s source with the source pin of the FET tied to the supply of the target
board. Using this arrangement allows the system to provide a wide range of ramp rates for the FET driver.
The HVOUT FET driver outputs a configurable source current (ISOURCE) in order to charge the FET gate. When the
driver is turned off, it outputs a configurable sink current (ISINK) to discharge the FET gate. The Isink setting also
includes a fast turn off setting. See the High Voltage Outputs section in DC and Switching Characteristics for more
details.
The four HVOUT pins can also be configured as switched mode outputs in either the high-voltage FET driver or
Open Drain mode. This is useful when the HVOUT is driving a High side MOSFET controlling a supply greater than
6 V. This feature is also useful for driving a MOSFET in a charge pump circuit to generate voltages above 12 volts.
The switched output duty cycle can be configured from 6.25% up to 93.75% in step sizes of 6.25% and the fre-
quency can be configured as either 15.625 kHz or 31.25 kHz. This flexibility allows the output to be configured to
drive a wide variety of circuit components for a design. The rise and fall of the switched mode outputs may not com-
plete with certain combinations of the charge pump settings (VPP, ISOURCE, ISINK) and the switched mode settings
(Duty Cycle and Frequency). The configuration should be chosen with the output circuit in mind.
35
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In-System Programmable
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Safe State of Digital Outputs
During power-up the GPIO will be configured as outputs and will be in the “Safe-State” as defined in Table 11. The
HVOUTs will be configured in the FET driver mode during power-up. When the ASC completes the power up
sequence then the HVOUT and GPIO control is transferred to the ASC-I/F or OCB depending upon the configura-
tion. The ASC will indicate that it has completed the power up sequence by asserting the AGOOD signal to the
FPGA using the ASC-I/F.
Table 11. GPIO and HVOUT Safe-State definitions
I/O
SAFE-STATE
Low
HVOUT1
HVOUT2
HVOUT3
HVOUT4
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO8
GPIO9
GPIO10
Low
Low
Low
Low
Low
Low
Low
Low
Low
Hi-Z
Hi-Z
Low
Controlling Power Supply Output Voltage by Trim and Margin Block
One of the key features of the ASC is its ability to make adjustments to the power supplies that it may also be mon-
itoring and/or sequencing. This is accomplished through the Trim and Margin Block of the device.
As shown in Figure 24 the Trim and Margin Block can adjust voltages of up to four different power supplies through
the DACs built-in the Trim Cells. The DC-DC blocks in the figure represent virtually any type of DC power supply
that has a trim or feedback input. This can be an off-the-shelf unit or custom circuit designed around a switching
regulator IC. The interface between ASC and the power supply shown in diagram by a resistor actually represents
a resistor network.
The individual ASC-I/F control signals for each Trimcell are:
• ASCx_TRIMx_CLTE — This is a closed loop trim enable signal of a TrimCell. When ASCx_TRIMx_CLTE =1 the
closed loop trimming for the DC-DC power supply connected to the TrimCell is enabled.
• ASCx_TRIMx_P0 and ASCx_TRIMx_P1 — These are two closed loop Trim Profile select signals used to select
the active voltage profile of a TRIM cell.
• ASCx_TRIMx_OE — This control signal enables the DAC output of a TrimCell. When ASCx_TRIMx_OE=1 the
DAC output of the Trim cell is active.
Other inputs to the TrimCell are:
• ADC — This input to the Trim cell is from the ADC which converts each VMON voltage into digital. The ADC input
is used by the Trim Cell for controlling the closed loop trim operation.
• I2C interface — Internal registers of the TrimCell can be accessed via I2C interface. The Platform Designer soft-
ware provides control signals which can be programmed to restrict I2C access to the ASC.
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In-System Programmable
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Next to each DC-DC converter, three example voltages are shown. These example voltages correspond to the
operating voltage profile of the corresponding TrimCell. As shown in Figure 24, the active operating profile for each
TrimCell is selected independently (of other TrimCells) using TRIMx_P0 and TRIMx_P1 signals.
Figure 24. ASC Margin/Trim Block
DC-DC Output Voltage
ASC Margin/Trim Block
Controlled by Profiles
V
V
OUT
IN
TRIM1_P1 TRIM1_P0
V
OUT
Voltage profile 0
0
0
1
TRIM1_CLTE
DC-DC
Trim-in
R1*
R2*
R3*
TRIM1_P0, TRIM1_P1
TRIM1_OE
Voltage profile 1
Voltage profile 2
0
1
1
0
1.05
0.96
Trim 1
TrimCell #1
DAC
ADC Input
from VMON1
I2C
V
OUT
TRIM2_P1 TRIM2_P0
VOUT
Voltage profile 0
0
0
1.2
TRIM2_CLTE
DC-DC
TRIM2_P0, TRIM2_P1
TRIM2_OE
Trim 2
Voltage profile 1
Voltage profile 2
0
1
1
0
1.28
DAC
TrimCell #2
Trim-in
1.14
I2C
ADC Input
from VMON2
V
V
IN
OUT
TRIM3_P1 TRIM3_P0
VOUT
Voltage profile 0
0
0
1.5
TRIM3_CLTE
DC-DC
Voltage profile 1
Voltage profile 2
0
1
1
0
1.57
1.42
TRIM3_P0, TRIM3_P1
TRIM3_OE
Trim 3
TrimCell #3
DAC
Trim-in
I2C
ADC Input
from VMON3
V
V
OUT
IN
TRIM4_P1 TRIM4_P0
VOUT
Voltage profile 0
0
0
3.3
TRIM4_CLTE
DC-DC
R4*
Voltage profile 1
Voltage profile 2
0
1
1
0
3.46
TRIM4_P0, TRIM4_P1
TRIM4_OE
Trim 4
TrimCell #4
DAC
Trim-in
3.13*
I2C
ADC Input
from VMON4
*Indicates resistor network, see Figure 25.
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In-System Programmable
Hardware Management Expander
There are four independently enabled TrimCells in the ASC device for controlling up-to four individual power sup-
plies. Each Trimcell can generate up-to three trimming voltages to control the output voltage of the DC-DC con-
verter.
Figure 25. TrimCell Driving a Typical DC-DC Converter
V
OUT
V
IN
V
OUT
DC-DC
Converter
R
3
R
1
TrimCell
#N
Trim
DAC
R
2
Figure 25 shows an example resistor network between the TrimCell #N in the ASC and the DC-DC converter. The
values of these resistors depend on the type of DC-DC converter used and its operating voltage range. The calcu-
lation to determine the values of the resistors R1, R2, and R3 is performed automatically in the Platform Designer
software.
TrimCell Architecture
The TrimCell block diagram is shown in Figure 26. Each TrimCell can be used in either of two modes to control an
8-bit DAC. The output of the DAC can be used to apply a voltage to trim an external power supply or DC-DC con-
verter. The Trim Configuration Mode is selected in the Platform Designer software; the default mode is Trim Cal-
culator, and the optional mode is Manual. Manual mode applies the user specified DAC Codes directly to the DAC
Register. The Trim Calculator mode is the Closed Loop Trim Mode where feedback from the corresponding VMON
is compared to a programmable Voltage Setpoint Register and the result is used to update the DAC register.
Manual Mode
Shown in the upper portion of Figure 26, PROFILE 0, PROFILE 1, PROFILE 2 are 8-bit DAC Codes that are written
in the EEPROM memory during programming. The active DAC Code for each TrimCell is independently chosen
based on ASC-I/F signals TRIMx_P0 / TRIMx_P1. The active DAC Code is written to the DAC Register whenever
the TRIMx_P0, TRIMx_P1 signals change. As shown, the PROFILE 0 DAC Code written in configuration memory
can be overwritten by I2C commands during run-time. The I2C access to the PROFILE 0 DAC Code can be
restricted based on the ASC I2C write protect feature that can be enabled during configuration (see the I2C Inter-
face section for more details).
Closed Loop Trim Mode
Shown in the lower portion of Figure 26, PROFILE 0, PROFILE 1 and PROFILE 2 are 12-bit Setpoints, which are
written in the EEPROM memory during programming. The active Setpoint for each TrimCell is independently cho-
sen based on ASC-I/F signals TRIMx_P0 / TRIMx_P1. This Setpoint is copied to the Voltage Setpoint Register
whenever the TRIMx_P0, TRIMx_P1 signals change. As shown, the PROFILE 0 Setpoint written in configuration
memory can be overwritten by I2C commands during run-time. The I2C access to the PROFILE 0 Setpoint can be
restricted based on the ASC I2C write protect feature that can be enabled during configuration (see the I2C Inter-
face section for more details). The Digital Closed Loop Trim Logic (near the center of Figure 26) compares the Volt-
age Setpoint Register with the corresponding VMON voltage (digitized by the ADC) to make active adjustments to
the 8-bit DAC Register. The Closed Loop Trim is enabled on a per channel basis, depending on the ASC-I/F signal
TRIMx_CLTE. See the Digital Closed Loop Trim Mode section for additional details on this mode of operation.
38
L-ASC10
In-System Programmable
Hardware Management Expander
DAC Output Control
The DAC output of the TrimCell is enabled using ASC-I/F signal TRIMx_OE. When enabled, the DAC register value
is converted to an analog voltage and output on the TRIMx pin. When disabled, the DAC output is high impedance.
The Trim Configuration Mode sets how the DAC Register is controlled (either Manual or Closed Loop Trim) and is
programmed into the EEPROM memory. The Trim Configuration Mode is set by the user in the Trim/Margin view of
Platform Designer software based on the selection of either Manual or Trim Calculator. The DAC output values
versus configuration settings are shown in Table 12.
Figure 26. TrimCell Architecture
DAC Codes
8
8
PROFILE 2 DAC CODE
(Configuration Memory)
TRIMCELL ARCHITECTURE
10
01
00
PROFILE 1 DAC CODE
(Configuration Memory)
8
8
PROFILE 0 DAC CODE
(Configuration Memory)
2
I2C Voltage Register
TRIMx_P0, TRIMx_P1
(ASC-I/F)
ASC I2C Write
I2C Controller
Voltage Profiles
12
12
PROFILE 2 Setpoint
(Configuration Memory)
10
12
01
TRIMx
Voltage
Setpoint
Register
Digital
Closed Loop
Trim Logic
12
8
8
PROFILE 1 Setpoint
(Configuration Memory)
DAC
8
00
12
PROFILE 0 Setpoint
(Configuration Memory)
12
2
TRIMx_OE
(ASC-I/F)
I2C Voltage Register/
VID Setpoint
TRIMx_CLTE
(ASC-I/F)
ADC Output
(VMONx)
Trim Configuration Mode
ASC I2C Write
(I2C Trim Bypass Bit or Configuration Memory)
(Manual–Bypass/Closed Loop Trim)
(Configuration Memory)
TRIMx_P0, TRIMx_P1
(ASC-I/F)
I2C Controller
Table 12. DAC Output Value vs. Configuration Settings
Trim Configuration Mode
TRIMx_CLTE
TRIMx_OE
DAC Output Value
Hi-Z
(Platform Designer Software)
(ASC –I/F)
(ASC- I/F)
x
x
x
0
1
Manual
DAC Code
(Bypass)
Trim Calculator
(Closed Loop Trim Mode)
0
1
1
1
Held at last updated value
by Closed Loop Trim
Logic. Reset value is 80h.
Trim Calculator
(Closed Loop Trim Mode)
Dynamically updated
based on measured
VMONx voltage and Digi-
tal Closed Loop Trim
Logic.
39
L-ASC10
In-System Programmable
Hardware Management Expander
VID Selection
The ASC can be configured to support VID (Voltage Identification) control using the TRIM block. The control sig-
nals and VID tables are created using the Platform Designer software. As shown in Figure 26, the VID mechanism
uses the I2C interface to control the VID Setpoint (duplicated as PROFILE 0 Setpoint). The I2C access to the VID
Setpoint can be restricted based on the ASC I2C write protect feature that can be set during configuration.
Digital Closed Loop Trim Mode
Closed loop trim mode operation can be used when tight control over the DC-DC converter output voltage at a
desired value is required. The closed loop trim mechanism operates by comparing the measured output voltage of
the DC-DC converter with the internally stored Voltage Setpoint. The difference between the Voltage Setpoint and
the actual DC-DC converter voltage generates an error voltage. This error voltage adjusts the DC-DC converter
output voltage toward the Voltage Setpoint. This operation iterates until the Voltage Setpoint and the DC-DC con-
verter voltage are equal. The closed loop trim hardware then continues monitoring the converter voltage and
adjusts the converter output voltage as necessary. Figure 27 shows the closed loop trim operation of a TrimCell. At
regular intervals (as determined by the Update Rate Control register) the ASC device initiates the closed loop
power supply voltage correction cycle through the following blocks
• Volatile Voltage Setpoint Register stores the desired output voltage (set by the TRIMx_P0 and TRIMx_P1 ASC-I/F
signals)
• On-chip ADC is used to measure the voltage of the DC-DC converter
• Three-state comparator is used to compare the measured voltage from the ADC with the Voltage Setpoint Regis-
ter contents. The output of the three state comparator can be one of the following:
– +1 if the setpoint voltage is greater than the DC-DC converter voltage
– –1 if the setpoint voltage is less than the DC-DC converter voltage
– 0 if the setpoint voltage is equal to the DC-DC converter voltage
• Channel polarity control determines the polarity of the error signal (Polarity is set on a per channel basis in con-
figuration memory)
• Closed loop trim register is used to compute and store the DAC code corresponding to the error voltage. The
contents of the Closed Loop Trim will be incremented or decremented depending on the channel polarity and the
three-state comparator output. If the three-state comparator output is 0, the closed loop trim register contents are
left unchanged.
• The DAC in the TrimCell is used to generate the analog error voltage that adjusts the attached DC-DC converter
output voltage.
Figure 27. Digital Closed Loop Trim Operation
DAC PROFILE MUX
ASC
OUTPUT
PROFILE SETPOINT
MUX OUTPUT
TRIMx UPDATE
POLARITY
(Configuration Memory)
TRIMx BYPASS
CONTROL
(Configuration Memory)
Three-State
DIGITAL
COMPARE
(+1/0/-1)
TRIMx
+/-1
TRIMIN
DC-DC
COMVERTER
DAC
UPDATE
RATE
CONTROL
VMONx
VOUT
GND
ADC
TRIMx
ACTIVE SETPOINT
(I2C)
CLT UPDATE RATE*
(Configuration Memory)
TRIMx_CLTE
(ASC-I/F)
* CLT UPDATE RATE parameter is shared between all four TRIM Cells
40
L-ASC10
In-System Programmable
Hardware Management Expander
The closed loop trim cycle interval is programmable and is set by the update rate control register. Table 13 lists the
programmable update interval that can be selected by the update rate register. The update rate register is set in
configuration memory and is shared between all TRIM cells.
Table 13. Closed Loop Trim Update Rates
CLT Update Rate Settings
860 µs
1.72 ms
13.8 ms
27.6 ms
There is a one-to-one relationship between the selected TrimCell and the corresponding VMON input for the closed
loop operation. For example, if TrimCell 3 is used to control the power supply in the closed loop trim mode, VMON3
must be used to monitor its output power supply voltage. The closed loop operation can only be started by assert-
ing the TRIMx_CLTE ASC-I/F signal.
TrimCell at Start-up
The status of registers and the TrimCell output during start-up or POR of the ASC is as follows.
1. The TRIM DAC output is High-Z.
2. DAC register is based on Trim configuration Mode.
Trim Configuration Mode for TRIMx channel
TRIMx DAC register
(Platform Designer Software)
Manual
Profile 0 DAC code is copied to the DAC register.
Trim Calculator
Value of 80h (Bipolar-zero) is copied to the DAC reg-
ister.
3. The Closed Loop Trim Logic is disabled.
4. Profile 0 Setpoint is copied to the Voltage Setpoint Register.
The DAC output mode can be enabled (TRIMx_OE) at any time by the user logic, depending on the application
requirements. Normally the chosen profile (TRIMx_P0, TRIMx_P1) setpoint should be loaded and the DAC output
enabled when the application is ready for trimming. If closed loop trimming is to be used, the user logic should
enable the closed loop trim (TRIMx_CLTE) after the DAC output and trim profile have already been configured.
Details of the Digital to Analog Converter (DAC)
Each trim cell has an 8-bit bipolar DAC to set the trimming voltage as shown in Figure 28. The full-scale output volt-
age of the DAC is +/– 320 mV. A code of 80H results in the DAC output set at its bi-polar zero value.
The voltage output from the DAC is added to a programmable offset value and the resultant voltage is then applied
to the trim output buffer. The offset voltage is typically selected to be approximately equal to the DC-DC converter
open circuit trim node voltage. This results in maximizing the DC-DC converter output voltage range.
The programmed offset value can be set to 0.6 V, 0.8 V, 1.0 V or 1.25 V. This value selection is stored in configura-
tion memory. The configuration memory is loaded with the value set in EEPROM memory at power-on. It can be
updated during runtime via I2C commands.
The combined offset and DAC output is applied to the TRIM cell output buffer. Each output buffer is controlled by a
unique TRIMx_OE signal via the ASC-I/F. When TRIMx_OE = 0, the corresponding TRIMx Pad will be placed in a
high impedance state. Setting TRIMx_OE = 1 will enable the output buffer, resulting in the combined offset and
DAC output being applied to the TRIM output pin.
41
L-ASC10
In-System Programmable
Hardware Management Expander
The default state at power-on reset is TRIMx_OE = 0. The TRIM cell will maintain this setting until the ASC-I/F
communication is successfully established. This ensures that the TRIM function will remain in a passive, high
impedance state, until it is enabled the user control logic.
Figure 28. Offset Voltage is Added to DAC Output Voltage to Derive Trim Pad Voltage
TRIM Cell
DAC
7 bits + Sign
(-320mV to +320mV)
8
TRIMx
Pad
TRIMx Setpoint
Register
TRIMx_OE
(from ASC-I/F)
Offset
(0.6V,0.8V,1.0V,1.25V)
Configuration
Memory
42
L-ASC10
In-System Programmable
Hardware Management Expander
Fault Logging and User Tag Memory
The ASC contains the following storage space used with Fault Logging or User Tag operation:
• Non-volatile EEPROM memory array which has 16 rows where each row stores 7 bytes of data.
• A volatile memory register which stores 7 bytes of data.
The ASC can be configured to choose this memory, either for User Tag Operation or Fault Log Operation through
Platform Designer Software. Figure 29 shows the interface to the EEPROM memory and Volatile register for data
access.
Figure 29. Access to EEPROM and Volatile Memory for Fault Logging/User Tag Operation
Fault Log Mode
(I2C Read/Erase/Enable)
Volatile Register
1 X 7 Bytes
Fault Log Mode
ASC(I/F)
• Fault Record Data
• Fault Trigger
• Fault Log Full
• Fault Log in Progress
EEPROM
16 X 7 Bytes
User Tag Mode
(I2C Read/Write/Erase)
User Tag Memory
When the ASC is configured for User Tag Mode, the memory block can be used as a scratch pad memory for criti-
cal data, board serialization, board revision logs, programmed pattern identification or as general data storage in
EEPROM.
As shown in Figure 29, in the User Tag Mode, data can be read, written or erased from the EEPROM or Volatile
Register via the I2C interface of the ASC. For more details, please refer to User Tag Memory Access in the I2C
Interface section of this data sheet.
Fault Log Memory
When the ASC is configured for Fault Log Mode, the memory block is used to record the status of the ASC GPIOs,
VMON, IMON, TMON and other significant logic signals on the occurrence of the user defined fault trigger condi-
tion. The ASC can also be used with Platform Manager 2, MachXO2, MachXO3, or ECP5 devices to log faults to
User Flash Memory (UFM) or external SPI flash. See TN1277, Fault Logging Using Platform Manager 2 for more
details.
Each fault record has seven bytes, six bytes of ASC specific data and one byte of user specified FPGA signals. The
ASC Fault Log Record Memory Map is shown in Table 14. Erased fault records and fault records which have not
been written yet will read all zeros.
43
L-ASC10
In-System Programmable
Hardware Management Expander
Table 14. Fault Log Record Memory Map
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
User bit3
X
Bit 2
User bit2
GPIO6
Bit 1
User bit1
GPIO5
Bit 0
User bit0
GPIO4
0
1
2
3
4
5
6
User bit7
AGOOD
GPIO3
User bit6
GPIO10
GPIO2
User bit5
GPIO9
User bit4
GPIO8
GPIO1
HVOUT4
HVMONB
VMON6B
VMON2B
TMONINB
HVOUT3
HVMONA
VMON6A
VMON2A
TMONINA
HVOUT2
VMON9B
VMON5B
VMON1B
1
HVOUT1
VMON9A
VMON5A
VMON1A
0
IMON1B
VMON8B
VMON4B
TMON2B
1
IMON1A
VMON8A
VMON4A
TMON2A
HIMONB
VMON7B
VMON3B
TMON1B
HIMONA
VMON7A
VMON3A
TMON1A
The ASC can be configured to store fault log data either in the EEPROM array or the Volatile register.
The EEPROM memory array can store up to 16 fault log records. When the fault log memory is full no further fault
log records can be stored in the EEPROM and any future trigger signals will be ignored.
The volatile register can also be used to store faults. The volatile fault log contains only one record of 7 bytes and
each time the trigger signal is asserted the current data will be stored in the register overwriting any previous data.
In order to preserve the volatile register fault log data it must be read back prior to the next assertion of the trigger
signal.
The following control signals for ASC based Fault Logging are defined in the Platform Designer software for use in
the FPGA logic:
• Fault_Log_Trigger: This user defined signal is used to initiate fault log recording. Recording is initiated by tog-
gling the fault log trigger signal high based on the FPGA logic. The Fault log trigger signal should be set high for
a minimum period (see Recommended Operating Conditions section). The fault log trigger signal initiates fault
log recording for all ASCs in the system. Readback must be disabled for the fault log recording to begin.
• ASCx_Fault_Log_Full: This ASC-I/F signal reports to the user logic when the EEPROM for the given ASC is full.
• ASCx_Fault_Log_In_Progress: This ASC-I/F signal reports to the user logic when a fault log operation for the
given ASC is in progress.
When the ASC is configured for Fault Log Operation, the Fault Record Data frame, as shown in Table 14, is cap-
tured every 16 us. When the fault log trigger signal is asserted, the captured data is stored in the selected memory.
This includes the user bits in the fault record. These user bits are not used for any other ASC functions.
The read-back function of the Fault Log must be enabled in order to read or erase the Fault Log. The read-back is
enabled using the I2C interface. As shown in Figure 29, the Fault Log contents can be read or erased from the
EEPROM or the volatile register via the I2C interface of the ASC.
When the user enables the read-back of the fault log contents, the fault log recording is disabled and must be re-
enabled by the user after the read-back is completed in order to store future fault log events. For more information
about reading, erasing and enabling the fault log recording refer to Fault Log Memory Access in the I2C Interface
section of this data sheet.
44
L-ASC10
In-System Programmable
Hardware Management Expander
System Connections
The ASC device is a hardware management expander, designed for use in systems which use either the Platform
Manager 2, MachXO2, MachXO3, or ECP5 FPGA as the hardware management controller. Platform Manager sys-
tem designs can be built using several combinations of Lattice devices as listed in Table 15. In order for the ASC to
function properly as a hardware management expander, there are a number of mandatory connections to the hard-
ware management controller. The overall set of required connections between the ASC and the hardware manage-
ment controller are shown in Figure 30 thru Figure 32 below. The required connections include Clock, Reset, ASC
Interface (ASC-I/F) and I2C. These connections are assigned and managed using Diamond software and the Plat-
form Designer tool. Each of the connection requirements is described below.
Table 15. Platform Manager 2 Design Options
Central Hardware Manager
LPTM21
Hardware Management Expander
LPTM21L or L-ASC10
Number of Expanders Supported1, 2
0 – 3
0 – 3
1 – 8
1 – 8
1 – 8
LPTM21L
MachXO2
MachXO3
ECP5
LPTM21L or L-ASC10
LPTM21L or L-ASC10
LPTM21L or L-ASC10
LPTM21L or L-ASC10
1. Platform Manager 2 designs with 6 hardware expanders are best supported with MachXO2 and MachXO3 devices of 2k LUTs or larger.
2. Platform Manager 2 designs with 8 hardware expanders are best supported with MachXO2 and MachXO3 devices of 4k LUTs or larger.
Figure 30. System Connections - ASC and Platform Manager 2
ASC2
+3.3 V
+3.3 V
ASCCLK
WRCLK
WDAT
VCCA
PIOx1
PIOx2
PIOx3
VCC
VCCIO_0
VCCIO_1
RDAT
PIOx4
RESETb
VCCA(+3.3V)
(Optional ASC)
I2C_ADDR
4.4 k
GND
SCL
SDA
SCL_M
SDA_M
Platform Manager 2
LPTM21*
ASC1
+3.3 V
ASCCLK
WRCLK
WDAT
VCCA
PIOx 5
PIOx 6
PIOx 7
RDAT
PIOx 8
RESETb
ASC Section
(Mandatory ASC)
(ASC0)
RESETb
I2C_ADDR
VCCA
2.2 k
GND
SCL_S
SDA_S
SCL
SDA
ASCCLK
* LPTM21L (100-ball package) has I2C master and slave connected internally
Note: Hardware connections may require additional passive components not shown, see TN1225, Platform Man-
ager 2 Hardware Checklist for more details.
45
L-ASC10
In-System Programmable
Hardware Management Expander
Figure 31. System Connections - ASC and MachXO2, or MachXO3
+3.3 V
ASC0
+3.3 V
ASCCLK
WRCLK
WDAT
VCCA
PCLKTx_Y
PIOx1
VCC
PIOx2
PIOx3
VCCIO_0
RDAT
VCCIO_1
PIOx4
RESETb
VCCA(+3.3V)
(Mandatory ASC)
I2C_ADDR
SCL
SDA
SCL
SDA
GND
MachXO2/
MachXO3
+3.3 V
ASC1
ASCCLK
WRCLK
WDAT
VCCA
PIOx5
PIOx6
PIOx7
RDAT
PIOx8
RESETb
(Optional ASC)
I2C_ADDR
2.2 k
GND
SCL
SDA
Note: Hardware connections may require additional passive components not shown, see TN1225, Platform Man-
ager 2 Hardware Checklist for more details.
46
L-ASC10
In-System Programmable
Hardware Management Expander
Figure 32. System Connections - ASC and ECP5
+3. 3V
+3. 3V
ECP5
SPI Flash
MCLK
CSSPIN
MOSI
MISO
IO2
CLK
CS
VCC
TDI
TDO
MOSI / DQ1*
MISO / DQ2*
DQ2
JTAG Programmer or Chain
TCK
TMS
IO3
DQ3
CFG2
CFG1
ASC0
Example Supply Sequencing Implementaꢀon:
CFG0
May Require RC Delays.
PCLKTx_Y(ASC0_CLK)
PIOx0(wrclk_0)
PIOx1(wdat_0)
PIOx2(rdat_0)
ASCCLK
WRCLK
WDAT
RDAT
RESETb
SCL
VCCA
DC/DC 1
3.3V
2.5 V
1.1 V
VIN
VIN
EN
VOUT
PGOOD
VCCIOx
VCCIO8
PIOx3(ASC0_RSTN)
PIOx4(I2C_scl)
DC/DC 2
PIOx5(I2C_sda)
SDA
I2C_ADDR
VIN
EN
VOUT
VCCAUX
PGOOD
VCCCORE
ASCx
DC/DC 3
ASCCLK
WRCLK
WDAT
RDAT
RESETb
SCL
VCCA
VIN
EN
VOUT
PIOx6(wrclk_x)
PIOx7(wdat_x)
PGOOD
PIOx8(rdat_x)
PIOx9(ASCx_RSTN_I)
I2C_ADDR
SDA
Note: Hardware connections may require additional passive components not shown, see TN1225, Platform Man-
ager 2 Hardware Checklist for more details.
Clock Requirements
The ASC has an internal 8 MHz clock source which is used by the device during startup. Once startup has suc-
cessfully completed, the ASC will switch to the ASC-I/F system clock signal (WRCLK) for operation. The hardware
management controller provides the WRCLK signal for each ASC in the system. This ensures that the system is
fully synchronized to a common clock source to minimize any differences in timing.
The ASC has a built-in detection circuit for WRCLK loss. If a loss of WRCLK is detected, the ASC will reset itself
and pull RESETb low. The device I/O will return to safe state, as described in the Safe State of Digital Outputs sec-
tion.
The ASC internal clock signal is made available on the ASCCLK pin of the ASC0 device for use as the system
source clock. This signal is connected internally in the Platform Manager 2 device (see Figure 30), making the
ASCCLK pin a no-connect in Platform Manager 2 systems. In systems using the MachXO2, MachXO3, or ECP5
and external ASC devices, the ASC0 ASCCLK will be enabled and must be connected to a MachXO2, MachXO3,
or ECP5 primary clock input, as shown in Figure 31 and Figure 32. The hardware connection and MachXO2,
MachXO3, or ECP5 pin assignment must be made by the user in the design software. All other ASC devices (both
optional and mandatory) in the system will disable their ASCCLK output signal and this pin should be treated as a
no connect.
47
L-ASC10
In-System Programmable
Hardware Management Expander
An external 8 MHz clock source can be used as the system clock instead of the ASC0 ASCCLK. In this case, the
ASCCLK output will be disabled, and the external clock should be connected to a primary clock pin on MachXO2,
MachXO3, or ECP5 FPGA or to the ASCCLK pin on Platform Manager 2. The user must specify that an external
clock source is being used in software.
Reset Requirements
The ASC RESETb pin is used for synchronizing the ASCs with the Platform Manager 2, MachXO2, MachXO3, or
ECP5 FPGA device. The RESETb pin should not be driven by any external device as this will adversely affect the sys-
tem operation. A software reset signal for the internal logic can be created using a PIO pin on the Platform Manager 2,
MachXO2, MachXO3, or ECP5 device.
The external ASCs for a project can be designated as either Mandatory or Optional. The Mandatory or Optional
designation determines how the RESETb pins must be connected and how the system will treat the Reset signal
from each ASC. The Mandatory or Optional designation must be specified in the design software.
A Mandatory ASC is required to be present at system start-up. The RESETb pins for all mandatory ASCs must be
connected to the RESETb pin on the Platform Manager 2 (as shown in Figure 30). The ASC0 device is always con-
sidered mandatory (this includes the internal ASC section of Platform Manager 2, which is always designated as
ASC0). If any one of the mandatory ASCs cannot be detected by the hardware management controller, the system
will be held in reset. Any of the mandatory ASCs which experience a critical issue (such as loss of WRCLK signal)
will hold the Reset signal low, keeping the system in reset.
In MachXO2, MachXO3, ECP5, and Platform Manager 2 systems, the ASC0_RESETb and other mandatory ASC
reset signals must be connected to a PIO externally, as shown in Figure 30 and Figure 31. This PIO should be
assigned to the ASC0_RSTN signal in the design software.
An Optional ASC is not required to be present at system start-up. This designation can be used for ASCs placed on
plug in modules or optional boards in a system. The RESETb pin of each optional ASC should be connected to a
unique PIO pin on the Platform Manager 2, MachXO2, MachXO3, or ECP5 FPGA. Each reset signal is treated indi-
vidually, so that only the registers associated with a particular Optional ASC will reset when the reset input is driven
low. The rest of the system, both Mandatory and other Optional ASCs, will continue to operate normally without
interruption.
ASC Interface and I2C Connections
The ASC uses two communication links to transfer information between the ASC and the Platform Manager 2,
MachXO2, MachXO3, or ECP5 FPGA. These are the ASC Interface (ASC-I/F) and I2C bus. These two links are
used for different types of information and both must be connected properly for the system to operate correctly.
The ASC-I/F bus uses three signals: WRCLK, WDAT, and RDAT. The ASC-I/F bus operates at 8 MHz and includes
error checking and reporting capabilities. The ASC-I/F pins on external ASC devices must be connected to three
PIO pins on the Platform Manager 2, MachXO2, MachXO3, or ECP5 device. These three PIO pins are assigned
using the design software. The design software will automatically instantiate the interface for communicating with
the ASC devices. Each ASC device requires its own unique ASC-I/F link, as shown in Figure 30 and Figure 31.
The VCCA pin for an external ASC0 device must be connected to the VCCIO of the I/O bank used for the PIO
assignment of WRCLK, WDAT, RDAT. Care should be taken that the I/O bank used for the ASC-I/F link is not
exposed to significant SSO noise, as this can degrade the performance of the analog monitors. See TN1225, Plat-
form Manager 2 Hardware Checklist for more details.
The I2C bus uses the SDA and SCL pins and operates at 100 to 400 kHz. The user must connect the SDA and SCL
pins on the ASC to the SDA_M/SCL_M pins on the Platform Manager 2 (Figure 30), or the SDA/SCL pins on the
MachXO2 or MachXO3 (Figure 31). The ECP5 does not have dedicated I2C pins, so any I/O pins can be assigned
to I2C_sda and I2C_scl, as long as the supply for the I/O bank is connected to the VCCA of the ASC (Figure 32).
The Platform Manager 2 also requires connections between the SDA_M/SCL_M and the SDA_S/SCL_S pins.
External pull-up resistors to VCCA are required in all configurations. See the I2C Interface section for full details.
48
L-ASC10
In-System Programmable
Hardware Management Expander
I2C Interface
I2C is a low-speed serial interface protocol designed to enable communications among a number of devices on a
circuit board. The ASC supports the I2C communications protocol 7-bit addressing. The I2C interface of the ASC is
used for programming by the master FPGA or other system processor. The interface is also used for accessing
measurement and control functions and fault log memory on the device. Figure 33 shows a typical I2C configura-
tion, in which one or more ASC devices are slaved to a Platform Manager 2, MachXO2, MachXO3, or ECP5 FPGA.
SDA is used to carry data signals, while SCL provides a synchronous clock signal. The 7-bit address of the ASC is
determined by EEPROM programming and the resistor setting on the I2C_ADDR pin.
Figure 33. ASC Devices in an I2C System
V+
SDA (DATA)
To Other I2C Devices
(Microcontroller, ASC2
SCL (CLOCK)
and others)
SDA
SCL
SDA
SCL
SDA
SCL
Platform Manager 2 /
MachXO2 /
ASC1
(I2C SLAVE)
ASC2
(I2C SLAVE)
MachXO3 /
ECP5
(I2C MASTER)
In the I2C protocol, the bus is controlled by a single MASTER device at any given time. This master device gener-
ates the SCL clock signal and coordinates all data transfers to and from a number of slave devices. The ASC is
designed as an I2C slave. In a multiple ASC system configuration, all ASCs share the same I2C bus. This shared
I2C bus is used by the Platform Manager 2, MachXO2, MachXO3, or ECP5 master to program the ASC devices.
Each slave device is assigned a unique address. Any 7-bit address can be assigned to the ASC, however one
should note that several addresses are reserved by the I2C standard and should not be assigned to the ASC to
ensure bus compatibility. These are shown in Table 16.
Table 16. I2C Reserved Slave Device Addresses
Address
0000 000
0000 000
0000 001
0000 010
0000 011
0000 1xx
1111 0xx
1111 1xx
R/W bit
I2C Function Description
General Call Address
Start Byte
0
1
X
X
X
X
1
CBUS Address
Reserved
Reserved
HS-mode master code
10-bit addressing
Device ID
X
49
L-ASC10
In-System Programmable
Hardware Management Expander
The 7-bit address of the ASC device is set based on both a configuration memory parameter and the pin state of
I2C_ADDR (see Figure 33). The 4 MSB of the slave address are programmable and stored in configuration mem-
ory. The 4 MSB are common between all ASC devices used in a platform management configuration. The 4 MSB in
all blank ASC devices are set to 1100.
Figure 34. I2C Slave Address Construction
1 1 0 0 0 0 0
Set in Configuration Memory
Common to All ASCs
Set by Resistor at I2C_ADDR
Specified per ASC
The 3 LSB of the slave address are set by connecting the I2C_ADDR pin to ground via a given resistor value. The
seven states of the 3 LSB have a one to one correspondence with the ASC number designation in the platform
management configuration. Table 17 shows the relationship between the resistor values and the 3 LSB of the I2C
Address / ASC device number. Resistors with 1% accuracy should be used to ensure proper address resolution.
Two ASC device numbers do not require a resistor: ASC0 (I2C_ADDR connected directly to ground) and ASC7
(I2C_ADDR connected directly to V
).
CCA
Table 17. R
Value vs. ASC Device Number
addr
Raddr Value
3 LSB of I2C Slave Address
ASC Device Number
None (Tie to GND)
2.2 kΩ
4.4 kΩ
7 kΩ
10 kΩ
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
14 kΩ
18 kΩ
None (Tie to VCCA
)
Figure 35 shows an example configuration of the I2C Slave Address. In this example, the ASC Device is ASC2. The
I2C_ADDR pin is tied to ground via a 4.4 kΩ resistor as specified by the value for ASC2 in Table 17. The configura-
tion memory in this example is programmed with the common 4 MSB for all ASC devices in the system, 1100. The
constructed I2C slave address is shown at the bottom of the diagram: 1100 010 (0x62).
Figure 35. I2C Address Resolution Example
Configuration Memory
4MSB = 1100
ASC2
I2C_ADDR
R
addr = 4.4 kΩ
Slave Address = 1100 010
The ASC supports a dedicated 8-bit instruction set. These instructions are divided as follows among device pro-
gramming instructions, measurement and control access, and fault log/user tag memory access. The ASC also
supports configuration memory protection.
50
L-ASC10
In-System Programmable
Hardware Management Expander
The ASC’s I2C interface allows data to be both written to and read from the device. A data write transaction, as
shown in Figure 36, consists of the following operations:
1. Start the bus transaction
2. Transmit the slave address (7 bits) along with a low write bit
3. Transmit the instruction code as described in Table 18 (8 bits)
4. Transmit the first data byte to be written (8 bits). Note some instructions do not include data bytes, while others
support multiple data bytes. For information on which instructions support multiple data bytes, see individual
instruction details
5. Stop the bus transaction
To start the transaction, the master device holds the SCL line high while pulling SDA low. Address, instruction code
and data bits are then transferred on each successive SCL pulse, in consecutive byte frames of 9 SCL pulses. Data
is transferred on the first 8 SCL clocks in each frame, while an acknowledge signal is asserted by the slave device
on the 9th clock in each frame. The first frame contains the 7-bit slave address, with bit 8 held low to indicate a
write operation. The second frame contains the instruction code indicating the type of data to be written. The
remaining frames contain the actual data to be written. The number of allowed or required data frames is deter-
mined by the instruction code used and is described in the Instruction Codes section.
Figure 36. I2C Write Operation
SCL
SDA
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A6
A5
A4
A3
A2
A1
A0 R/W ACK
C7
C6
C5
C4
C3
C2
C1
C0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
OPTIONAL
ADDITIONAL
DATA BYTES
START
DEVICE ADDRESS (7 BITS)
INSTRUCTION CODE (8 BITS)
DATA BYTE (8 BITS)
STOP
Note: Shaded Bits Asserted by Slave
See Individual Instruction Descriptions for Data Byte Details
Reading a data byte from the ASC requires two separate bus transactions, as shown in Figure 37. The first trans-
action writes the device address with write bit, and then the instruction code indicating the type of data to be read.
This transaction typically ends after the second frame since no data is being written to the slave. However, some
instruction codes include additional frames, such as address information for the type of data to be read. See the
Instruction Codes section for more information about the number of allowed or required data frames. No stop con-
dition is issued at the end of the first step, to ensure that the full read operation is completed properly.
The second transaction performs the actual read, beginning with the issuing of a repeated start condition. A
repeated start is a start condition issued by the master which does not follow a stop condition. This prevents the
bus from being released by the master. The first frame contains the 7-bit slave address with the R/W bit held high.
In the second frame, the ASC asserts data out on the bus in response to the SCL signal. Note that the acknowl-
edge signal in the second frame is asserted by the master device and not the ASC. Depending on the instruction
code, the ASC may assert additional data bytes in response to additional SCL frames depending on the instruction
as detailed in the Instruction Codes section. The master completes the transaction by issuing a stop condition.
51
L-ASC10
In-System Programmable
Hardware Management Expander
Figure 37. I2C Read Operation
STEP 1: WRITE INSTRUCTION CODE FOR READ OPERATION
SCL
SDA
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A6
A5
A4
A3
A2
A1
A0 R/W ACK
C7
C6
C5
C4
C3
C2
C1
C0
ACK
A7
A6
A5
A4
A3
A2
A1
A0 ACK
NO
STOP
ISSUED
START
SLAVE ADDRESS (7 BITS)
INSTRUCTION CODE (8 BITS)
OPTIONAL: ADDRESS BYTE (8 BITS)
STEP 2: READ DATA FROM THAT REGISTER
SCL
SDA
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A6
A5
A4
A3
A2
A1
A0
ACK
D7
D6
D5
D4
D3
D2
D1
D0 ACK*
R/W
OPTIONAL
ADDITIONAL
DATA BYTES
STOP
SLAVE ADDRESS (7 BITS)
DATA BYTE (8 BITS)
REPEATED
START
Note: Shaded Bits Asserted by Slave
See Individual Instruction Descriptions for Data and Address Byte Details
* After final data byte read, master should NACK before issuing the STOP command
52
L-ASC10
In-System Programmable
Hardware Management Expander
Instruction Codes
The ASC device supports a set of 8-bit instruction codes. These instructions are used to access EEPROM pro-
gramming functions, shadow register programming functions, measurement and control functions, and User Tag or
Fault Log memories. The instruction space is shown in Table 18. Each set of instructions is described in more detail
in the following sections. Do not read or write to instruction codes marked reserved.
Table 18. I2C Instruction Summary
Instruction Code
0x01
Instruction Name
Instruction Group
N/A
RESERVED
READ_ID
0x02
Device Status and Mode Management
0x03
READ_STATUS
0x04
ENABLE_PROG
0x05
ENABLE_USER
0x06-0x24
0x25
RESERVED
N/A
READ_CFG_EEPROM
RESERVED
ASC Configuration Memory Access
N/A
0x26-0x30
0x31
WRITE_CFG_REG
ASC Configuration Memory Access
0x32
WRITE_CFG_REG_wMASK
READ_CFG_REG
0x33
0x34
READ_ALL_CFG_REG
LOAD_CFG_REG
0x35
0x36-0x40
0x41
RESERVED
N/A
TRIM1_CLT_P0_SET
TRIM2_CLT_P0_SET
TRIM3_CLT_P0_SET
TRIM4_CLT_P0_SET
RESERVED
Closed Loop Trim Setpoint Access
0x42
0x43
0x44
0x45-0x50
0x51
N/A
WRITE_MEAS_CTRL
READ_MEAS_CTRL
RESERVED
Measurement and Control Register Access
0x52
0x53-0x60
0x61
N/A
ERASE_USER_TAG_EEPROM
WRITE_USER_TAG_REG
READ_USER_TAG_REG
PROG_USER_TAG_EEPROM
READ_USER_TAG_EEPROM
RESERVED
User Tag Memory Access
0x62
0x63
0x64
0x65
0x66-0x70
0x71
N/A
ERASE_FAULT_EEPROM
RESERVED
Fault Log Memory Access
N/A
0x72
0x73
READ_FAULT_VOLATILE_REG
READ_FAULT_ENABLE
READ_FAULT_RECORD_EEPROM
READ_ALL_FAULT_EEPROM
RESERVED
Fault Log Memory Access
0x74
0x75
0x76
0x77-0xFF
N/A
53
L-ASC10
In-System Programmable
Hardware Management Expander
Each instruction is described in detail in the following sections. The description includes information about the indi-
vidual instruction code, the instruction format and any associated write or read addresses or data. The instruction
format uses the following notation:
I2C Instruction Format Key (See Figure 37 for details of each condition or bit):
• S – Start Condition
• A[6:0] – Slave Address
• W – Write Bit (Logic 0)
• A – Acknowledge Bit
• NA – Not Acknowledge Bit
• Sr – Repeated Start Condition
• R – Read Bit (Logic 1)
• P – Stop Bit
• Shaded Bits (A) – Bits asserted by the slave
Device Status and Mode Management
There are several miscellaneous registers from the programming flow which are useful or required for completing
separate operations (such as entering the programming mode to enable the User Tag memory access).
Table 19. Device Status and Mode Management Instruction Codes
Instruction Code
0x01
Instruction Name
RESERVED
Read/Write
Description
N/A
0x02
0x03
0x04
READ_ID
R
R
Read the device ID Code
READ_STATUS
ENABLE_PROG
Read the ASC Status Register
W
Enable the programming mode (correct two
byte key required)
0x05
ENABLE_USER
W
Enable the device user mode
The READ_ID instruction is used to verify that the slave device is an ASC or the ASC section of Platform Manager 2.
The device IDCODES are shown in Table 20. The format for the READ_ID instruction is shown in Figure 38.
Figure 38. READ_ID Instruction Format
SLAVE
ADDRESS
SLAVE
ADDRESS
INSTRUCTION
CODE
DEVICE ID
S
A[6:0]
W
A
0x02
A
Sr
A[6:0]
R
A
ID[7:0]
NA
P
Table 20. ASC ID Codes
Device
ID Code
0x88
ASC Hardware Management Expander
ASC Section of LPTM21
0x8A
ASC Section of LPTM21L
0x8A
54
L-ASC10
In-System Programmable
Hardware Management Expander
The READ_STATUS instruction provides readout access to the two byte status register of the ASC. The
READ_STATUS instruction provides information about the status of the ASC fault log memory, the current chip
mode (Programming Mode or User Mode), and the status of the DONE bit of the I2C address resolution and the
configuration memory. The READ_STATUS instruction format is shown in Figure 39. The ASC_Status_Register bit
mapping is shown in Figure 40.
Figure 39. READ_STATUS - I2C Instruction Format
ASC_STATUS
REGISTER LO
ASC_STATUS
REGISTER_HI
SLAVE
ADDRESS
SLAVE
ADDRESS
INSTRUCTION
CODE
_
S
A[6:0]
W
A
0x03
A
Sr
A[6:0]
R
A
R[7:0]
A
R[15:8]
NA
P
Figure 40. ASC_Status Register
ASC_STATUS_REGISTER_LO (Read)
DUALBOOT_CRC
_ERROR
CFGARRAY_
DONE
I2CSA_DONE
b5
PROG_MODE
b4
RESERVED
b3
CFG_SHADOW_
REG_REFRESH
RESERVED
b1
ERASE
b0
b7
b6
b2
ASC_STATUS_REGISTER_HI (Read)
PROGRAM
b15
FAULT_UT_
ERASE
FAULT_PROG
b13
FAULT_LOG_
FULL
FAULT_CNT[3]
b11
FAULT_CNT[2]
b10
FAULT_CNT[1]
b9
FAULT_CNT[0]
b8
b14
b12
The individual status bits are described below:
• DUALBOOT_CRC_ERROR – Reset to logic 0 at power up and at the beginning of a dual-boot configuration write
I2C instruction. Logic 1 when a CRC error is encountered during dual-boot configuration.
• CFGARRAY_DONE – Logic 1 if the configuration memory done bit has been programmed (set to 1 at the proper
completion of an EEPROM programming operation)
• I2CSA_DONE – Logic 1 if the chip I2C slave address I2CSADone has been programmed (set to 1 at the proper
completion of an EEPROM programming operation)
• PROG_MODE – Logic 1 if the chip is in programming mode, Logic 0 if the chip is in user mode
• RESERVED
• CFG_SHADOW_REG_REFRESH –Set to Logic 1 if Configuration EEPROM data was copied into corresponding
shadow registers just after a Reset or after the shadow register refresh I2C instruction is given. This bit is cleared
just after the status register is read out.
• ERASE – Logic 1 if any EEPROM Erase operation is in progress
• PROGRAM – Logic 1 if any EEPROM Program operation is in progress
• FAULT_UT_ERASE – Logic 1 if the ASC Fault Log or User Tag memory is currently being erased
• FAULT_PROG – Logic 1 if the ASC Fault Log data is being programmed into Fault Log EEPROM array
• FAULT_LOG_FULL – Logic 1 if all rows of the ASC Fault Log EEPROM have been programmed
• FAULT_CNT [3:0] – 4-bit value that is equal to the last row of ASC Fault Log EEPROM that has been pro-
grammed with fault log data. Row 0 up to Row FAULT_CNT have been programmed with Fault Log Data.
55
L-ASC10
In-System Programmable
Hardware Management Expander
The ENABLE_PROG instruction places the ASC into the programming mode. The instruction requires that a spe-
cific key code is written along with it in order to ensure that the programming mode is not entered unintentionally.
The ENABLE_PROG instruction should only be used by the Lattice delivered programming algorithms or to write or
erase the User Tag memory. The ASC_PROG_KEY is a two byte value of 0xE53D. The ENABLE_PROG instruc-
tion format is shown in Figure 41.
Figure 41. ENABLE_PROG - I2C Instruction Format
SLAVE
ADDRESS
INSTRUCTION
CODE
PROG_KEY
LOW
PROG_KEY
HIGH
S
A[6:0]
W
A
0x04
A
0x3D
A
0xE5
A
P
After completing a user tag operation, it is important to exit the programming mode and return to user mode. This
will prevent unintentional programming operations. The ENABLE_USER instruction will return the ASC to the user
mode. The ENABLE_USER instruction format is shown in Figure 42.
Figure 42. ENABLE_USER - I2C Instruction Format
SLAVE
ADDRESS
INSTRUCTION
CODE
S
A[6:0]
W
A
0x05
A
P
ASC Configuration Memory Access
The I2C interface is used for programming the ASC device. The ASC device includes an EEPROM configuration
memory which stores the device configuration in non-volatile memory. The ASC device also includes a set of
shadow registers, which are used during runtime by the device to determine operational thresholds, output con-
trols, etc. At power-on reset, the device automatically copies the EEPROM configuration memory to the shadow
registers, provided the EEPROM done bit is set in the ASC Status Register. The EEPROM configuration settings
are automatically generated by the Platform Designer software tool.
The I2C interface unit provides access to both the non-volatile EEPROM memory and the configuration shadow
registers for erase, programming, and verify operations. The EEPROM memory is background programmed. It can
be copied to the configuration shadow registers at the end of programming by an additional I2C instruction. The
EEPROM configuration memory map is automatically generated by the Platform Designer software. The flow and
usage of the EEPROM instructions is handled by the Lattice Diamond Programmer software (for PC-based pro-
gramming) or the Lattice deployment tool (for programming the device via a tester or an on-board microcontroller
using the I2C embedded solution). Lattice recommends using these software tools to access the EEPROM config-
uration programming instruction space.
The I2C interface can also be used to re-configure the shadow registers directly. These instructions provide access
to individual voltage monitor thresholds, temperature measurement settings, and other device configuration param-
eters. Some configuration shadow registers are implemented as master/slave pairs. These shadow registers do not
update operational parameters immediately after I2C configuration writes to the master shadow register. They sup-
port an additional load instruction which updates all slave shadow registers from the master shadow registers at
the same time. Other shadow registers are implemented as a single master-only register. These registers update
their operation (or reset the associated circuit) immediately after an I2C configuration write. The configuration mem-
ory architecture is shown in Figure 43. The ASC Configuration Registers section details which registers support the
additional load instruction. The configuration registers can be accessed in user mode, although overwriting the reg-
isters can be protected through additional device settings. The configuration register access instructions are shown
in Table 21.
56
L-ASC10
In-System Programmable
Hardware Management Expander
Figure 43. Configuration Memory Architecture
To TRIM Circuits
To VMON Circuits
I2C_LOAD_
CFG_REG
Configuration
Shadow Registers
(Master)
Configuration Shadow
Registers
(Slave)
To IMON Circuits
Power On
Reset
Configuration
EEPROM
To HVOUT, OCB, GPIO Circuits
To TRIM Circuits
To TMON Circuits
Configuration
Shadow Registers
(Master-Only)
I2C_READ_CFG_REG
I2C_READ_ALL_CFG_REG
Programming
Algorithms*
I2C_WRITE_CFG_REG
I2C_WRITE_CFG_REG_wMASK
* - EEPROM access algorithms generated by
Lattice Design Software
Table 21. Configuration Register Instruction Codes
Instruction Code
Instruction Name
Read/Write
Description
0x25
READ_CFG_EEPROM
R
Read out the selected configura-
tion EEPROM byte or bytes
0x31
0x32
0x33
0x34
0x35
WRITE_CFG_REG
WRITE_CFG_REG_wMASK
READ_CFG_REG
W
W
R
Write configuration data byte to
addressed register
Write masked configuration data
bits to addressed register
Read addressed configuration reg-
ister
READ_ALL_CFG_REG
LOAD_CFG_REG
R
Read all configuration registers,
starting at address 0x00
W
Load the slave shadow configura-
tion registers from the I2C master
shadow configuration registers (not
all registers supported, see
Table 22)
The configuration registers and address map are shown in the tables in the ASC Configuration Registers section.
The tables in this section also describe which registers support the LOAD_CFG_REG instruction.
Special configuration memory parameters (such as the Write Protect setting, User Tag / Fault Log mode, and UES
bits) can only be modified in EEPROM. They cannot be modified using configuration register instructions. This
increases the reliability of the device operation.
The READ_CFG_EEPROM instruction is used to readout the contents of an addressed byte or bytes of configura-
tion EEPROM. This instruction will readout the configuration data stored in the EEPROM memory – this is not nec-
essarily the current device configuration. The current device configuration can be readout using the
READ_CFG_REG or READ_ALL_CFG_REG commands. The address map for the configuration EEPROM is the
same as the configuration register map. The READ_CFG_EEPROM instruction is the only mechanism for reading
out the User Electronic Signature (described in Table 70). The READ_CFG_EEPROM is a two-step transaction
operation, as shown in Figure 44. In the first step, a write transaction is performed with the 0x25 instruction, and an
57
L-ASC10
In-System Programmable
Hardware Management Expander
8-bit address code corresponding to a specific memory address (defined in the ASC Configuration Registers sec-
tion). In the second step, a read transaction is used to read the EEPROM memory contents. The memory address
will auto-increment to support reading multiple bytes in a single transaction. This means a single transaction can
support reading the entire configuration address map (120 bytes), if the starting address of 0x00 is used. A stop
condition will complete the read transaction, this can be issued after any number of bytes have been read.
Figure 44. READ_EEPROM - I2C Instruction Format
DATA
[ADDRESS]
DATA
[ADDRESS +1]
SLAVE
ADDRESS
SLAVE
ADDRESS
INSTRUCTION
CODE
MEMORY
ADDRESS
S
A[6:0]
W
A
0x25
A
M_A[7:0]
A
Sr
A[6:0]
R
A
D0[7:0]
A
D1[7:0]
A*
P
Optional: Read up to 120
additional data bytes
* After final data byte read, master should NACK before issuing the STOP command
The WRITE_CFG_REG instruction is used to write configuration data to an addressed register. The instruction for-
mat includes an address byte and at least one data byte, as shown in Figure 45. Additional data bytes can be writ-
ten in a single transaction as the configuration register address will increment automatically. A stop condition will
complete the write transaction, this can be issued after any number of bytes have been written. The
WRITE_CFG_REG instruction should be used with caution, as many of the configuration registers are used to
define multiple device options. In many cases, the WRITE_CFG_REG_wMASK instruction is a more reliable
method for updating a single configuration parameter. For configuration registers which support the
LOAD_CFG_REG instruction, the slave shadow registers will not be updated until the LOAD_CFG_REG instruc-
tion is executed. Master-only shadow registers will be updated immediately, and in some cases will reset their cir-
cuitry (see the ASC Configuration Registers section).
Figure 45. WRITE_CFG_REG - I2C Instruction Format
SLAVE
ADDRESS
INSTRUCTION
CODE
REGISTER
ADDRESS
DATA
[ADDRESS]
DATA
[ADDRESS + 1]
S
A[6:0]
W
A
0x31
A
R_A[7:0]
A
D0[7:0]
A
D1[7:0]
A
P
Optional: Write up to100
additional data bytes
The WRITE_CFG_REG_wMASK instruction is used to write the masked configuration data bits to an addressed
master register. The instruction format includes an address byte and at least one mask byte / data byte pair, as
shown in Figure 46. Additional mask and data byte pairs can be written in a single transaction as the configuration
register address will increment automatically. A stop condition will complete the write transaction, this can be
issued after any number of data and mask pairs have been written. This instruction will not modify the configuration
bits set to 1 in the mask byte. Those configuration bits will keep their current value. Bit locations set to 0 in the mask
byte will be modified by the data byte. For configuration registers which support the LOAD_CFG_REG instruction,
the slave shadow registers will not be updated until the LOAD_CFG_REG instruction is executed. Master-only
shadow registers will be updated immediately, and in some cases will reset their circuitry.
Figure 46. WRITE_CFG__REG_wMASK - I2C Instruction Format
SLAVE
ADDRESS
INSTRUCTION
CODE
REGISTER
ADDRESS
MASK
[ADDRESS]
DATA
[ADDRESS]
MASK
[ADDRESS+ 1]
DATA
[ADDRESS + 1]
S
A[6:0]
W
A
0x32
A
R_A[7:0]
A
M0[7:0]
A
D0[7:0]
A
M1[7:0]
A
D1[7:0]
A
P
Optional: Write up to 100
additional mask/data byte pairs,
depending on start address
58
L-ASC10
In-System Programmable
Hardware Management Expander
Using the WRITE_CFG_REG_wMASK Instruction Format
The WRITE_CFG_REG_wMASK instruction is the preferred instruction for updating a single programmable device
parameter. As an example, the following I2C write transaction can be used to update only the VMON4_A threshold.
The example will update the A_TRIP_FINE to a value of hex 0x0A (binary 001010) See Table 28 for more details.
1. Start the bus transaction.
2. Transmit the device address (7 bits) along with a low write bit.
3. Transmit the 0x32 instruction code (WRITE_CFG_REG_wMASK.)
4. Transmit the 0x1F address byte (VMON4_CFG0 register as defined by Table 28).
5. Transmit 0x3F as the MASK0 byte (only A_TRIP_FINE[1:0] will be modified, B_TRIP_SELECT[5:0] will main-
tain its current configuration).
6. Transmit the data to be written to the two highest bits of VMON4_CFG0 (0x80 corresponds to
A_TRIP_FINE[1:0] = 10).
7. Transmit 0xF0 as the next mask byte (address will auto-increment to 0x20, the VMON4_CFG1 register). Only
A_TRIP_FINE[5:2] will be modified. Other VMON4_CFG1 parameters will be unchanged.
8. Transmit the data to be written to the four lowest bits of VMON4_CFG1 (0x02 corresponds to
A_TRIP_FINE[5:2] = 0010).
9. Stop the bus transaction.
10. Start an additional bus transaction using the LOAD_CFG_REG instruction (see Figure 48).
The configuration register settings can also be readout over I2C. This is accomplished using the READ_CFG_REG
instruction and the READ_ALL_CFG_REG instruction. The READ_CFG_REG is a two-step transaction operation,
as shown in Figure 47. In the first step, a write transaction is performed with the 0x33 instruction, and an 8-bit
address code corresponding to a specific register address (defined in the ASC Configuration Registers section). In
the second step, a read transaction is used to read the register contents. The register address will auto-increment
to support reading multiple registers in a single transaction. This means a single transaction can support reading
the entire configuration address map (102 bytes), if the starting address of 0x00 is used. A stop condition will com-
plete the read transaction, this can be issued after any number of bytes have been read.
Figure 47. READ_CFG_REG - I2C Instruction Format
DATA
[ADDRESS]
DATA
[ADDRESS +1]
SLAVE
ADDRESS
SLAVE
ADDRESS
INSTRUCTION
CODE
MEMORY
ADDRESS
S
A[6:0]
W
A
0x33
A
R_A[7:0]
A
Sr
A[6:0]
R
A
D0[7:0]
A
D1[7:0]
A*
P
Optional: Read up to 101
additional data bytes
* After final data byte read, master should NACK before issuing the STOP command
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In-System Programmable
Hardware Management Expander
The READ_ALL_CFG instruction works in a similar way to the READ_CFG_REG. The difference is that the
READ_ALL_CFG instruction always starts at register address 0x00. Multiple data bytes can be read out in a single
transaction, with the register address auto-incrementing after each byte is read. The entire configuration register
memory space can be read out with a single transaction (102 data bytes). A stop condition will complete the read
transaction, this can be issued after any number of bytes have been read. The format for the
READ_ALL_CFG_REG instruction is shown in Figure 48.
Figure 48. READ_ALL_CFG_REG - I2C Instruction Format
DATA
DATA
SLAVE
ADDRESS
SLAVE
ADDRESS
INSTRUCTION
CODE
[ADDRESS = 0x00] [ADDRESS = 0x01]
S
A[6:0]
W
A
0x34
A
Sr
A[6:0]
R
A
D0[7:0]
A
D1[7:0]
A*
P
Optional: Read up to 101
additional data bytes
* After final data byte read, master should NACK before issuing the STOP command
The LOAD_CFG_REG instruction is used to load the data from the I2C master shadow registers to the slave
shadow registers. All the slave shadow registers are loaded at once when the instruction is received. The
LOAD_CFG_REG instruction should be used after WRITE_CFG_REG and WRITE_CFG_REG_wMask updates to
the I2C configuration registers are completed. This instruction is useful for updating multiple parameters which
affect the operation of a single circuit (such as a VMON or IMON), as these parameters are often spread across
multiple configuration addresses. Note that certain configuration registers (such as temperature monitor or trim
profiles) do not support this instruction. These master-only shadow registers are updated immediately by a
WRITE_CFG_REG instruction, they do not require a LOAD_CFG_REG instruction. The format for the
LOAD_CFG_REG instruction is shown in Figure 49.
Figure 49. LOAD_CFG_REG - I2C Instruction Format
SLAVE
ADDRESS
INSTRUCTION
CODE
S
A[6:0]
W
A
0x35
A
P
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L-ASC10
In-System Programmable
Hardware Management Expander
ASC Configuration Registers
The ASC Configuration registers are grouped below by function and shown in the following tables:
• Table 22, Trim Configuration Register Summary
• Table 28, Voltage Monitor Configuration Register Summary
• Table 37, Current Monitor Configuration Register Summary
• Table 43, Temperature Monitor Configuration Register Summary
• Table 51, High Voltage Output Configuration Register Summary
• Table 60, Output Control Block Configuration Register Summary
• Table 65, GPIO Input Configuration Register Summary
• Table 67, Write Protect and User Tag Configuration Register
• Table 70, UES Memory Summary
• Table 71, Reserved Configuration Addresses
The configuration register address space is 8-bits (0x00-0xFF). The registers contain the configuration information
for all the analog blocks in the ASC. These registers are automatically populated with their configuration informa-
tion at power on reset, either from the ASC EEPROM memory or external memory through Dual Boot algorithm.
These registers should not be confused with the Measurement and Control registers described in a later section.
The measurement and control registers are used to read voltage, current, and temperature measurements and are
accessed with a different set of instructions.
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L-ASC10
In-System Programmable
Hardware Management Expander
Table 22. Trim Configuration Register Summary
Register
Reconfiguration
Address
Register Name
Trim1_P1_Lo1
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Trim1_P1_Set [7:0]
Details
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
Trim1_Trim2_P1_Hi Trim1_P1_Set[11:8]
Trim2_P1_Set[11:8]
Trim3_P1_Set [11:8]
Trim1_P2_Set[11:8]
Trim3_P2_Set [11:8]
Trim2_P1_Lo1
Trim3_P1_Lo1
Trim2_P1_Set [7:0]
Trim3_P1_Set [7:0]
Trim3_Trim4_P1_Hi Trim3_P1_Set [11:8]
Trim4_P1_Lo1
Trim1_P2_Lo1
Trim4_P1_Set [7:0]
Trim1_P2_Set [7:0]
Master-Only
(Immediate Update)
Trim1_Trim2_P2_Hi Trim1_P2_Set[11:8]
Trim2_P1_Lo1
Trim3_P2_Lo1
Trim2_P2_Set [7:0]
Trim3_P2_Set [7:0]
Trim3_Trim4_P2_Hi Trim3_P2_Set [11:8]
Trim4_P1_Lo1
Trim1_P0_Lo1
Trim4_P1_Set [7:0]
Trim1_P0_Set [7:0]
Trim1_P0_Hi_Cfg
Trim2_P0_Lo1
POL BYP
Trim2_P0_Set [7:0]
POL BYP ATT
Trim3_P0_Set [7:0]
POL BYP ATT
Trim4_P0_Set [7:0]
POL BYP ATT
ATT
x
x
x
x
Trim1_P0_Set[11:8]
Trim2_P0_Set[11:8]
Trim3_P0_Set[11:8]
Trim4_P0_Set[11:8]
Trim2_P0_Hi_Cfg
Trim3_P0_Lo1
Master/Slave
(LOAD_CFG_REG supported)
Trim3_P0_Hi_Cfg
Trim4_P0_Lo1
Trim4_P0_Hi_Cfg
Trim_CLT_Rate
Trim_DAC_BPZ
RATE[1:0]
D4_BPZ[1:0] D3_BPZ[1:0] D2_BPZ[1:0] D1_BPZ[1:0]
1.When the bypass bit (manual mode) is set, the lower 8-bits of the profile set-point are the profile DAC registers shown in Figure 26.
Closed Loop Trim Configuration Registers
The ASC configuration memory specifies the operation of the closed loop trim circuitry, described in the Controlling
Power Supply Output Voltage by Trim and Margin Block section. Each of the configurable parameters, shown in
Table 22, are described in the following section.
Trimx_Py_Set [11:0] (Trim1_P0 … Trim4_P2) – Trim Channel Profile Setpoints 0, 1 and 2
The Trim profile setpoints are configured as 12 bit numbers, where each bit corresponds to 2 mV. The equation
below (which is a reversal of the calculation equation found in the ADC section) describes how to calculate the trim
target.
TRIM_SETPOINT_CODE (12_bits, converted to binary) = ROUND (Target Voltage / 2mV)
Each of the 4 Trim channels supports three separate programmable setpoints, as shown in Table 22. The P1 and
P2 setpoints for each channel do not support the LOAD_CFG_REG instruction and are updated immediately after
being written by I2C instructions. It is not recommended to update these registers during operation. Updating the
trim setpoint is best accomplished using the Closed Loop Trim Register Access instructions.
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L-ASC10
In-System Programmable
Hardware Management Expander
POL – Polarity
The Polarity setting for each trim channel determines the closed loop trim behavior of trim voltage control versus
output voltage feedback, as shown in Figure 27. The polarity settings are described in Table 23.
Table 23. POL Setting vs Closed Loop Trim Polarity
POL
Closed Loop Trim Polarity
Positive
0
1
Negative
BYP – Bypass
The Bypass setting for each trim channel determines whether the trim output voltage is controlled by the closed
loop trim circuitry or by the stored profile DAC codes, as shown in Figure 26. When the Trim-DAC circuitry is in
bypass mode, the lower 8-bits of the profile set-point are the profile DAC registers shown in Figure 26. The bypass
settings are described in Table 24.
Table 24. BYP Setting vs Trim Voltage Source
BYP
Trim Voltage Source
Closed Loop Trim Logic (Trim Calculator)
Profile DAC Code (Manual)
0
1
ATT – Attenuator Enable
The Attenuator Enable setting for each trim channel determines whether the monitored DC-DC output voltage
needs to be attenuated before ADC measurement, as shown in Figure 10. DC-DC output voltages above 2 V need
to be attenuated. The attenuator settings are described in Table 25.
Table 25. ATT Setting vs Attenuation Value
ATT
0
Attenuation Value
÷ 1 (no attenuation)
÷ 3
1
RATE[1:0] – Closed Loop Trim Update Rate
The Closed Loop Trim update rate is a common setting for all four trim channels. The available settings are shown
in Table 26.
Table 26. RATE[1:0] Setting vs Closed Loop Trim Update Rate
RATE[1:0]
Update Rate
860 µs
00
01
10
11
1.72 ms
13.8 ms
27.6 ms
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L-ASC10
In-System Programmable
Hardware Management Expander
Dx_BPZ (DAC1_BPZ … DAC4_BPZ) – DAC Bi-Polar Zero Output Voltage
The DAC Bi-Polar Zero Output Voltage for each channel determines the Trim outputs Bi-Polar Zero voltage as
shown in Figure 28. There are four available settings shown in Table 27.
Table 27. Dx_BPZ[1:0] Setting vs DAC Bi-Polar Zero Output Voltage
Dx_BPZ[1:0]
DAC BPZ Voltage
00
01
10
11
0.6V
0.8V
1.0V
1.25V
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L-ASC10
In-System Programmable
Hardware Management Expander
Voltage Monitor Configuration Registers
Table 28. Voltage Monitor Configuration Register Summary
Register
Address
Register Name
VMON1_Config0
VMON1_Config1
VMON1_Config2
VMON2_Config0
VMON2_Config1
VMON2_Config2
VMON3_Config0
VMON3_Config1
VMON3_Config2
VMON4_Config0
VMON4_Config1
VMON4_Config2
VMON5_Config0
VMON5_Config1
VMON5_Config2
VMON6_Config0
VMON6_Config1
VMON6_Config2
VMON7_Config0
VMON7_Config1
VMON7_Config2
VMON8_Config0
VMON8_Config1
VMON8_Config2
VMON9_Config0
VMON9_Config1
VMON9_Config2
HVMON_Config0
HVMON_Config1
HVMON_Config2
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
V1_ATF[1:0] V1_BTF[5:0]
Reconfiguration Details
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
1
1
GBP WM V1_ATF[5:2]
V1_BTC[3:0]
V1_ATC[3:0]
V2_ATF[1:0] V2_BTF[5:0]
1
1
GBP WM V2_ATF[5:2]
V2_BTC[3:0]
V2_ATC[3:0]
V3_ATF[1:0] V3_BTF[5:0]
1
1
GBP WM V3_ATF[5:2]
V3_BTC[3:0]
V3_ATC[3:0]
V4_ATF[1:0] V4_BTF[5:0]
1
1
GBP WM V4_ATF[5:2]
V4_BTC[3:0]
V4_ATC[3:0]
V5_ATF[1:0] V5_BTF[5:0]
1
1
GBP WM V5_ATF[5:2]
V5_BTC[3:0]
V5_ATC[3:0]
Master/Slave
(LOAD_CFG_REG supported)
V6_ATF[1:0] V6_BTF[5:0]
1
1
GBP WM V6_ATF[5:2]
V6_BTC[3:0]
V6_ATC[3:0]
V7_ATF[1:0] V7_BTF[5:0]
1
1
GBP WM V7_ATF[5:2]
V7_BTC[3:0]
V7_ATC[3:0]
V8_ATF[1:0] V8_BTF[5:0]
1
1
GBP WM V8_ATF[5:2]
V8_BTC[3:0]
V8_ATC[3:0]
V9_ATF[1:0] V9_BTF[5:0]
1
1
GBP WM V9_ATF[5:2]
V9_BTC[3:0]
V9_ATC[3:0]
HV_ATF[1:0] HV_BTF[5:0]
1
1
GBP WM HV_ATF[5:2]
HV_BTC[3:0]
HV_ATC[3:0]
The ASC configuration memory specifies the operation of the voltage monitor (VMON), described in the Voltage
Monitor Inputs section. The voltage monitor (VMON1-VMON9 and HVMON) trip points, glitch filter setting, and win-
dow mode are configurable over I2C. The configuration registers are summarized in Table 28.
Vx_ATF[5:0], Vx_ATC[3:0], Vx_BTF[5:0], Vx_BTC[3:0] (V1_ATF … V9_BTC) – Voltage Monitor Fine and
Coarse, A and B Trip Points
Each voltage monitor includes programmable trip points A and B, corresponding to the two comparators for each
voltage monitor input pin. The A and B trip points of the Differential Voltage Monitors (VMON1 - VMON4) are
defined based on the fine and coarse settings shown in Table 29 (for over-voltage monitoring) and Table 30 (for
under-voltage monitoring). The A and B trip points of the Single-Ended Voltage Monitors (VMON5-VMON9) are
defined based on the fine and coarse settings shown in Table 31 (for over-voltage monitoring) and Table 32 (for
under-voltage monitoring). Fine and Coarse settings outside of the table range are prohibited. There is no program-
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L-ASC10
In-System Programmable
Hardware Management Expander
mable setting for over or under voltage. Based on the type of voltage monitoring, choose the applicable table. For
more details on over and under voltage monitoring, see the Programmable Over-Voltage and Under-Voltage
Thresholds discussion in the voltage monitor inputs section. Setting the trip point to the Low-Voltage sense row
(Fine Range 0x21) disables hysteresis for that voltage monitor input for both under and over voltage detection.
Table 29. Trip Point for Over-Voltage Detection (Differential VMON1-VMON4)
Fine Range
Setting
Coarse Range Setting
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0x00
0.795
0.790
0.786
0.782
0.778
0.773
0.769
0.765
0.761
0.756
0.752
0.748
0.744
0.739
0.735
0.731
0.727
0.723
0.718
0.714
0.710
0.706
0.701
0.697
0.693
0.689
0.684
0.680
0.676
0.672
0.668
0.947 1.127
0.942 1.121
0.937 1.115
0.931 1.109
0.926 1.103
0.921 1.097
0.916 1.091
0.911 1.085
0.906 1.079
0.901 1.073
0.896 1.067
0.891 1.061
0.886 1.055
0.881 1.049
0.876 1.043
0.871 1.037
0.866 1.031
0.861 1.025
0.856 1.019
0.851 1.013
0.846 1.007
0.841 1.001
0.836 0.995
0.831 0.989
0.826 0.983
0.821 0.977
0.816 0.971
0.810 0.965
0.805 0.959
0.800 0.953
0.795 0.947
1.341
1.334
1.327
1.320
1.313
1.306
1.299
1.291
1.284
1.277
1.270
1.263
1.256
1.249
1.241
1.234
1.227
1.220
1.213
1.206
1.199
1.191
1.184
1.177
1.170
1.163
1.156
1.149
1.141
1.134
1.127
1.589
1.581
1.572
1.564
1.555
1.547
1.538
1.530
1.521
1.513
1.504
1.497
1.488
1.480
1.472
1.463
1.455
1.446
1.438
1.429
1.421
1.412
1.404
1.395
1.387
1.378
1.370
1.362
1.353
1.345
1.336
1.897
1.887
1.876
1.866
1.856
1.846
1.836
1.826
1.816
1.806
1.796
1.786
1.775
1.765
1.755
1.745
1.735
1.725
1.715
1.705
1.695
1.685
1.674
1.664
1.654
1.644
1.634
1.624
1.614
1.604
1.594
2.259
2.247
2.235
2.223
2.211
2.199
2.187
2.175
2.163
2.151
2.139
2.127
2.115
2.103
2.091
2.079
2.066
2.054
2.042
2.030
2.018
2.006
1.994
1.982
1.970
1.958
1.946
1.934
1.922
1.910
1.898
2.677
2.663
2.648
2.634
2.620
2.605
2.591
2.577
2.563
2.548
2.534
2.520
2.505
2.492
2.478
2.464
2.449
2.435
2.421
2.406
2.392
2.378
2.364
2.349
2.335
2.321
2.307
2.292
2.278
2.264
2.249
3.172
3.156
3.139
3.122
3.105
3.088
3.071
3.055
3.038
3.021
3.004
2.987
2.970
2.953
2.936
2.919
2.902
2.885
2.868
2.851
2.835
2.819
2.802
2.785
2.768
2.751
2.734
2.717
2.700
2.683
2.666
3.779
3.759
3.739
3.719
3.699
3.679
3.658
3.638
3.618
3.598
3.578
3.558
3.537
3.517
3.497
3.478
3.458
3.438
3.417
3.397
3.377
3.357
3.337
3.317
3.296
3.276
3.256
3.236
3.216
3.196
3.176
4.848
4.822
4.797
4.771
4.746
4.720
4.694
4.668
4.642
4.616
4.590
4.565
4.539
4.513
4.487
4.462
4.436
4.410
4.384
4.359
4.333
4.307
4.281
4.255
4.229
4.203
4.178
4.153
4.127
4.101
4.075
5.775
5.744
5.713
5.683
5.652
5.621
5.590
5.559
5.529
5.498
5.468
5.437
5.406
5.375
5.345
5.314
5.283
5.252
5.221
5.191
5.160
5.130
5.099
5.068
5.038
5.007
4.976
4.945
4.914
4.884
4.853
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1c
0x1d
0x1e
Low-Voltage Sense
0.150 0.178
0x21
0.075
0.089 0.106
0.126
0.212
0.252
0.300
0.356
0.457
0.545
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In-System Programmable
Hardware Management Expander
Table 30. Trip Point for Under-Voltage Detection (Differential VMON1-VMON4)
Fine Range
Setting
Coarse Range Setting
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0x00
0.786
0.782
0.778
0.773
0.769
0.765
0.761
0.756
0.752
0.748
0.744
0.739
0.735
0.731
0.727
0.723
0.718
0.714
0.710
0.706
0.701
0.697
0.693
0.689
0.684
0.680
0.676
0.672
0.668
0.663
0.659
0.937 1.115
0.931 1.109
0.926 1.103
0.921 1.097
0.916 1.091
0.911 1.085
0.906 1.079
0.901 1.073
0.896 1.067
0.891 1.061
0.886 1.055
0.881 1.049
0.876 1.043
0.871 1.037
0.866 1.031
0.861 1.025
0.856 1.019
0.851 1.013
0.846 1.007
0.841 1.001
0.836 0.995
0.831 0.989
0.826 0.983
0.821 0.977
0.816 0.971
0.810 0.965
0.805 0.959
0.800 0.953
0.795 0.947
0.790 0.941
0.785 0.935
1.327
1.320
1.313
1.306
1.299
1.291
1.284
1.277
1.270
1.263
1.256
1.249
1.241
1.234
1.227
1.220
1.213
1.206
1.199
1.191
1.184
1.177
1.170
1.163
1.156
1.149
1.141
1.134
1.127
1.120
1.113
1.572
1.564
1.555
1.547
1.538
1.530
1.521
1.513
1.504
1.497
1.488
1.480
1.472
1.463
1.455
1.446
1.438
1.429
1.421
1.412
1.404
1.395
1.387
1.378
1.370
1.362
1.353
1.345
1.336
1.328
1.319
1.876
1.866
1.856
1.846
1.836
1.826
1.816
1.806
1.796
1.786
1.775
1.765
1.755
1.745
1.735
1.725
1.715
1.705
1.695
1.685
1.674
1.664
1.654
1.644
1.634
1.624
1.614
1.604
1.594
1.584
1.573
2.235
2.223
2.211
2.199
2.187
2.175
2.163
2.151
2.139
2.127
2.115
2.103
2.091
2.079
2.066
2.054
2.042
2.030
2.018
2.006
1.994
1.982
1.970
1.958
1.946
1.934
1.922
1.910
1.898
1.886
1.874
2.648
2.634
2.620
2.605
2.591
2.577
2.563
2.548
2.534
2.520
2.505
2.492
2.478
2.464
2.449
2.435
2.421
2.406
2.392
2.378
2.364
2.349
2.335
2.321
2.307
2.292
2.278
2.264
2.249
2.235
2.221
3.139
3.122
3.105
3.088
3.071
3.055
3.038
3.021
3.004
2.987
2.970
2.953
2.936
2.919
2.902
2.885
2.868
2.851
2.835
2.819
2.802
2.785
2.768
2.751
2.734
2.717
2.700
2.683
2.666
2.649
2.632
3.739
3.719
3.699
3.679
3.658
3.638
3.618
3.598
3.578
3.558
3.537
3.517
3.497
3.478
3.458
3.438
3.417
3.397
3.377
3.357
3.337
3.317
3.296
3.276
3.256
3.236
3.216
3.196
3.176
3.156
3.136
4.797
4.771
4.746
4.720
4.694
4.668
4.642
4.616
4.590
4.565
4.539
4.513
4.487
4.462
4.436
4.410
4.384
4.359
4.333
4.307
4.281
4.255
4.229
4.203
4.178
4.153
4.127
4.101
4.075
4.049
4.023
5.713
5.683
5.652
5.621
5.590
5.559
5.529
5.498
5.468
5.437
5.406
5.375
5.345
5.314
5.283
5.252
5.221
5.191
5.160
5.130
5.099
5.068
5.038
5.007
4.976
4.945
4.914
4.884
4.853
4.822
4.792
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1c
0x1d
0x1e
Low-Voltage Sense
0.150 0.178
0x21
0.075
0.089 0.106
0.126
0.212
0.252
0.300
0.356
0.457
0.545
67
L-ASC10
In-System Programmable
Hardware Management Expander
Table 31. Trip Point for Over-Voltage Detection (Single-Ended VMON5-VMON9)
Fine Range
Setting
Coarse Range Setting
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xa
0xb
0x0
0.799
0.794
0.790
0.786
0.782
0.777
0.773
0.769
0.765
0.760
0.756
0.752
0.748
0.743
0.739
0.735
0.731
0.727
0.722
0.718
0.714
0.710
0.705
0.701
0.697
0.693
0.688
0.684
0.680
0.676
0.672
0.952 1.133
0.947 1.126
0.942 1.120
0.936 1.114
0.931 1.108
0.926 1.102
0.921 1.096
0.916 1.090
0.911 1.084
0.906 1.078
0.901 1.072
0.896 1.066
0.891 1.060
0.886 1.054
0.881 1.048
0.875 1.042
0.870 1.036
0.865 1.030
0.860 1.024
0.855 1.018
0.850 1.012
0.845 1.006
0.840 1.000
0.835 0.994
0.830 0.988
0.825 0.982
0.820 0.976
0.814 0.970
0.809 0.964
0.804 0.958
0.799 0.952
1.347
1.340
1.333
1.326
1.319
1.312
1.305
1.297
1.290
1.283
1.276
1.269
1.262
1.255
1.247
1.240
1.233
1.226
1.219
1.212
1.205
1.197
1.190
1.183
1.176
1.169
1.162
1.155
1.147
1.140
1.133
1.597
1.589
1.580
1.572
1.563
1.555
1.546
1.538
1.529
1.521
1.512
1.504
1.495
1.487
1.479
1.470
1.462
1.453
1.445
1.436
1.428
1.419
1.411
1.402
1.394
1.385
1.376
1.368
1.359
1.351
1.342
1.907
1.897
1.886
1.875
1.865
1.855
1.845
1.835
1.825
1.815
1.805
1.795
1.784
1.774
1.764
1.754
1.744
1.734
1.724
1.714
1.704
1.694
1.683
1.673
1.663
1.653
1.643
1.633
1.622
1.612
1.602
2.270
2.258
2.246
2.234
2.222
2.210
2.198
2.186
2.174
2.162
2.150
2.138
2.125
2.113
2.101
2.089
2.076
2.064
2.052
2.040
2.028
2.016
2.004
1.992
1.980
1.968
1.956
1.944
1.932
1.920
1.908
2.688
2.674
2.659
2.645
2.631
2.616
2.602
2.588
2.574
2.559
2.545
2.531
2.516
2.501
2.487
2.473
2.458
2.444
2.430
2.415
2.401
2.387
2.373
2.358
2.344
2.330
2.316
2.301
2.287
2.273
2.258
3.185
3.168
3.151
3.134
3.117
3.100
3.083
3.067
3.050
3.033
3.016
2.999
2.982
2.965
2.948
2.931
2.914
2.897
2.880
2.863
2.847
2.830
2.813
2.796
2.779
2.762
2.745
2.728
2.711
2.694
2.677
3.794
3.774
3.754
3.734
3.714
3.694
3.673
3.653
3.633
3.613
3.593
3.573
3.552
3.532
3.512
3.491
3.471
3.451
3.430
3.410
3.390
3.370
3.350
3.330
3.309
3.289
3.269
3.249
3.229
3.209
3.189
4.868
4.842
4.816
4.790
4.765
4.739
4.713
4.687
4.661
4.635
4.609
4.584
4.558
4.532
4.506
4.479
4.453
4.427
4.401
4.376
4.350
4.324
4.298
4.272
4.246
4.220
4.195
4.169
4.143
4.117
4.091
5.798
5.767
5.736
5.706
5.675
5.644
5.613
5.582
5.552
5.521
5.489
5.458
5.427
5.396
5.366
5.335
5.304
5.273
5.242
5.212
5.181
5.150
5.119
5.088
5.058
5.027
4.996
4.965
4.934
4.904
4.873
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xa
0xb
0xc
0xd
0xe
0xf
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1a
0x1b
0x1c
0x1d
0x1e
Low-Voltage Sense
0.155 0.186
0x21
0.080
0.093 0.110
0.132
0.220
0.262
0.310
0.370
0.475
0.565
68
L-ASC10
In-System Programmable
Hardware Management Expander
Table 32. Trip Point for Under-Voltage Detection (Single-Ended VMON5-VMON9)
Fine Range
Setting
Coarse Range Setting
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xa
0xb
0x0
0.790
0.786
0.782
0.777
0.773
0.769
0.765
0.760
0.756
0.752
0.748
0.743
0.739
0.735
0.731
0.727
0.722
0.718
0.714
0.710
0.705
0.701
0.697
0.693
0.688
0.684
0.680
0.676
0.672
0.667
0.663
0.942 1.120
0.936 1.114
0.931 1.108
0.926 1.102
0.921 1.096
0.916 1.090
0.911 1.084
0.906 1.078
0.901 1.072
0.896 1.066
0.891 1.060
0.886 1.054
0.881 1.048
0.875 1.042
0.870 1.036
0.865 1.030
0.860 1.024
0.855 1.018
0.850 1.012
0.845 1.006
0.840 1.000
0.835 0.994
0.830 0.988
0.825 0.982
0.820 0.976
0.814 0.970
0.809 0.964
0.804 0.958
0.799 0.952
0.794 0.946
0.789 0.940
1.333
1.326
1.319
1.312
1.305
1.297
1.290
1.283
1.276
1.269
1.262
1.255
1.247
1.240
1.233
1.226
1.219
1.212
1.205
1.197
1.190
1.183
1.176
1.169
1.162
1.155
1.147
1.140
1.133
1.125
1.118
1.580
1.572
1.563
1.555
1.546
1.538
1.529
1.521
1.512
1.504
1.495
1.487
1.479
1.470
1.462
1.453
1.445
1.436
1.428
1.419
1.411
1.402
1.394
1.385
1.376
1.368
1.359
1.351
1.342
1.334
1.325
1.886
1.875
1.865
1.855
1.845
1.835
1.825
1.815
1.805
1.795
1.784
1.774
1.764
1.754
1.744
1.734
1.724
1.714
1.704
1.694
1.683
1.673
1.663
1.653
1.643
1.633
1.622
1.612
1.602
1.592
1.581
2.246
2.234
2.222
2.210
2.198
2.186
2.174
2.162
2.150
2.138
2.125
2.113
2.101
2.089
2.076
2.064
2.052
2.040
2.028
2.016
2.004
1.992
1.980
1.968
1.956
1.944
1.932
1.920
1.908
1.896
1.884
2.659
2.645
2.631
2.616
2.602
2.588
2.574
2.559
2.545
2.531
2.516
2.501
2.487
2.473
2.458
2.444
2.430
2.415
2.401
2.387
2.373
2.358
2.344
2.330
2.316
2.301
2.287
2.273
2.258
2.244
2.230
3.151
3.134
3.117
3.100
3.083
3.067
3.050
3.033
3.016
2.999
2.982
2.965
2.948
2.931
2.914
2.897
2.880
2.863
2.847
2.830
2.813
2.796
2.779
2.762
2.745
2.728
2.711
2.694
2.677
2.660
2.643
3.754
3.734
3.714
3.694
3.673
3.653
3.633
3.613
3.593
3.573
3.552
3.532
3.512
3.491
3.471
3.451
3.430
3.410
3.390
3.370
3.350
3.330
3.309
3.289
3.269
3.249
3.229
3.209
3.189
3.168
3.148
4.816
4.790
4.765
4.739
4.713
4.687
4.661
4.635
4.609
4.584
4.558
4.532
4.506
4.479
4.453
4.427
4.401
4.376
4.350
4.324
4.298
4.272
4.246
4.220
4.195
4.169
4.143
4.117
4.091
4.065
4.039
5.736
5.706
5.675
5.644
5.613
5.582
5.552
5.521
5.489
5.458
5.427
5.396
5.366
5.335
5.304
5.273
5.242
5.212
5.181
5.150
5.119
5.088
5.058
5.027
4.996
4.965
4.934
4.904
4.873
4.842
4.811
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xa
0xb
0xc
0xd
0xe
0xf
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1a
0x1b
0x1c
0x1d
0x1e
Low-Voltage Sense
0.155 0.186
0x21
0.080
0.093 0.110
0.132
0.220
0.262
0.310
0.370
0.475
0.565
69
L-ASC10
In-System Programmable
Hardware Management Expander
GBP – Glitch Filter Bypass
Each of the voltage monitors include a glitch filter at each of the trip point comparator outputs as shown in Figure 6.
This glitch filter can be bypassed dependent on the GBP setting shown in Table 33.
Table 33. GBP Setting vs Glitch Bypass Behavior
GBP
Glitch Filter Setting
Glitch Filter On
0
1
Glitch Filter Bypassed
WM – Window Mode
Each of the voltage monitors include a selectable window mode, as described in Table 2. The window mode setting
is shown in Table 34.
Table 34. WM Setting vs Window Mode Value
WM
0
Window Mode
Off
On
1
HV_ATF[5:0], HV_ATC[3:0], HV_BTF[5:0], HV_BTC[3:0] – High Voltage Monitor Fine and Coarse, A and B
Trip Points
The High Voltage Monitor (HVMON) is configured in a similar fashion to the low voltage monitor inputs. The key dif-
ference from the low voltage monitor inputs is the trip point table. The HVMON range is up to 13.2 V, as reflected in
Table 35 (Over-Voltage Trip Points) and Table 36 (Under-Voltage Trip Points). Setting the trip point to the Low-Volt-
age sense row (Fine Range 0x21) disables hysteresis for that voltage monitor input for both under and over voltage
detection.
70
L-ASC10
In-System Programmable
Hardware Management Expander
Table 35. Trip-Point for Over-Voltage Detection (HVMON)
Fine Range
Setting
Coarse Range Setting
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xa
0xb
0x0
2.269
2.257
2.245
2.233
2.221
2.208
2.196
2.184
2.172
2.160
2.148
2.136
2.124
2.112
2.100
2.088
2.076
2.064
2.052
2.040
2.027
2.015
2.003
1.991
1.979
1.967
1.955
1.943
1.931
1.919
1.907
2.694 3.193
2.680 3.176
2.666 3.159
2.651 3.142
2.637 3.125
2.623 3.108
2.608 3.091
2.594 3.074
2.580 3.057
2.565 3.040
2.551 3.023
2.537 3.006
2.522 2.989
2.508 2.972
2.494 2.955
2.479 2.938
2.465 2.921
2.451 2.904
2.436 2.887
2.422 2.870
2.408 2.853
2.393 2.836
2.379 2.819
2.365 2.803
2.350 2.786
2.336 2.769
2.322 2.752
2.307 2.735
2.293 2.718
2.279 2.701
2.264 2.684
3.748
3.729
3.709
3.689
3.669
3.649
3.629
3.609
3.589
3.569
3.549
3.529
3.509
3.489
3.469
3.449
3.429
3.410
3.390
3.370
3.350
3.330
3.310
3.290
3.270
3.250
3.230
3.210
3.190
3.170
3.150
4.421
4.398
4.374
4.351
4.327
4.304
4.280
4.257
4.233
4.210
4.186
4.163
4.139
4.116
4.092
4.069
4.045
4.021
3.998
3.974
3.951
3.927
3.904
3.880
3.857
3.833
3.810
3.786
3.763
3.739
3.716
5.207
5.179
5.152
5.124
5.096
5.068
5.041
5.013
4.985
4.958
4.930
4.902
4.875
4.847
4.819
4.791
4.764
4.736
4.708
4.681
4.653
4.625
4.598
4.570
4.542
4.515
4.487
4.459
4.431
4.404
4.376
6.137
6.104
6.071
6.039
6.006
5.974
5.941
5.908
5.876
5.843
5.810
5.778
5.745
5.712
5.680
5.647
5.614
5.582
5.549
5.517
5.484
5.451
5.419
5.386
5.353
5.321
5.288
5.255
5.223
5.190
5.157
7.160
7.121
7.083
7.045
7.007
6.969
6.931
6.893
6.855
6.817
6.779
6.741
6.703
6.664
6.626
6.588
6.550
6.512
6.474
6.436
6.398
6.360
6.322
6.284
6.246
6.207
6.169
6.131
6.093
6.055
6.017
8.382
8.337
8.293
8.248
8.204
8.159
8.114
8.070
8.025
7.981
7.936
7.891
7.847
7.802
7.758
7.713
7.669
7.624
7.579
7.535
7.490
7.446
7.401
7.356
7.312
7.267
7.223
7.178
7.134
7.089
7.044
9.819 11.455 13.218
9.767 11.394 13.147
9.714 11.333 13.077
9.662 11.272 13.007
9.610 11.212 12.936
9.558 11.151 12.866
9.505 11.090 12.796
9.453 11.029 12.725
9.401 10.968 12.655
9.349 10.907 12.585
9.297 10.846 12.515
9.244 10.785 12.444
9.192 10.724 12.374
9.140 10.663 12.304
9.088 10.602 12.233
9.035 10.541 12.163
8.983 10.480 12.093
8.931 10.419 12.022
8.879 10.358 11.952
8.826 10.298 11.882
8.774 10.237 11.811
8.722 10.176 11.741
8.670 10.115 11.671
8.618 10.054 11.601
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xa
0xb
0xc
0xd
0xe
0xf
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1a
0x1b
0x1c
0x1d
0x1e
8.565
8.513
8.461
8.409
8.356
8.304
8.252
9.993 11.530
9.932 11.460
9.871 11.390
9.810 11.319
9.749 11.249
9.688 11.179
9.627 11.108
Low-Voltage Sense
0.425 0.504
0x21
0.220
0.260 0.308
0.361
0.593
0.692
0.810
0.949
1.108
1.280
71
L-ASC10
In-System Programmable
Hardware Management Expander
Table 36. Trip-Point for Under-Voltage Detection (HVMON)
Fine Range
Setting
Coarse Range Setting
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xa
0xb
0x0
2.245
2.233
2.221
2.208
2.196
2.184
2.172
2.160
2.148
2.136
2.124
2.112
2.100
2.088
2.076
2.064
2.052
2.040
2.027
2.015
2.003
1.991
1.979
1.967
1.955
1.943
1.931
1.919
1.907
1.895
1.883
2.666 3.159
2.651 3.142
2.637 3.125
2.623 3.108
2.608 3.091
2.594 3.074
2.580 3.057
2.565 3.040
2.551 3.023
2.537 3.006
2.522 2.989
2.508 2.972
2.494 2.955
2.479 2.938
2.465 2.921
2.451 2.904
2.436 2.887
2.422 2.870
2.408 2.853
2.393 2.836
2.379 2.819
2.365 2.803
2.350 2.786
2.336 2.769
2.322 2.752
2.307 2.735
2.293 2.718
2.279 2.701
2.264 2.684
2.250 2.667
2.236 2.650
3.709
3.689
3.669
3.649
3.629
3.609
3.589
3.569
3.549
3.529
3.509
3.489
3.469
3.449
3.429
3.410
3.390
3.370
3.350
3.330
3.310
3.290
3.270
3.250
3.230
3.210
3.190
3.170
3.150
3.130
3.110
4.374
4.351
4.327
4.304
4.280
4.257
4.233
4.210
4.186
4.163
4.139
4.116
4.092
4.069
4.045
4.021
3.998
3.974
3.951
3.927
3.904
3.880
3.857
3.833
3.810
3.786
3.763
3.739
3.716
3.692
3.669
5.152
5.124
5.096
5.068
5.041
5.013
4.985
4.958
4.930
4.902
4.875
4.847
4.819
4.791
4.764
4.736
4.708
4.681
4.653
4.625
4.598
4.570
4.542
4.515
4.487
4.459
4.431
4.404
4.376
4.348
4.321
6.071
6.039
6.006
5.974
5.941
5.908
5.876
5.843
5.810
5.778
5.745
5.712
5.680
5.647
5.614
5.582
5.549
5.517
5.484
5.451
5.419
5.386
5.353
5.321
5.288
5.255
5.223
5.190
5.157
5.125
5.092
7.083
7.045
7.007
6.969
6.931
6.893
6.855
6.817
6.779
6.741
6.703
6.664
6.626
6.588
6.550
6.512
6.474
6.436
6.398
6.360
6.322
6.284
6.246
6.207
6.169
6.131
6.093
6.055
6.017
5.979
5.941
8.293
8.248
8.204
8.159
8.114
8.070
8.025
7.981
7.936
7.891
7.847
7.802
7.758
7.713
7.669
7.624
7.579
7.535
7.490
7.446
7.401
7.356
7.312
7.267
7.223
7.178
7.134
7.089
7.044
7.000
6.955
9.714 11.333 13.077
9.662 11.272 13.007
9.610 11.212 12.936
9.558 11.151 12.866
9.505 11.090 12.796
9.453 11.029 12.725
9.401 10.968 12.655
9.349 10.907 12.585
9.297 10.846 12.515
9.244 10.785 12.444
9.192 10.724 12.374
9.140 10.663 12.304
9.088 10.602 12.233
9.035 10.541 12.163
8.983 10.480 12.093
8.931 10.419 12.022
8.879 10.358 11.952
8.826 10.298 11.882
8.774 10.237 11.811
8.722 10.176 11.741
8.670 10.115 11.671
8.618 10.054 11.601
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xa
0xb
0xc
0xd
0xe
0xf
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1a
0x1b
0x1c
0x1d
0x1e
8.565
8.513
8.461
8.409
8.356
8.304
8.252
8.200
8.148
9.993 11.530
9.932 11.460
9.871 11.390
9.810 11.319
9.749 11.249
9.688 11.179
9.627 11.108
9.566 11.038
9.505 10.968
Low-Voltage Sense
0.425 0.504
0x21
0.220
0.260 0.308
0.361
0.593
0.692
0.810
0.949
1.108
1.280
72
L-ASC10
In-System Programmable
Hardware Management Expander
Current Monitor Configuration Registers
The ASC configuration memory defines the operation of the current monitor (IMON1/HIMON) circuitry, described in
the Theory of Operation section. The low and high voltage current monitor trip points, glitch filter setting, and win-
dow mode are configurable over I2C. The IMON1 (low voltage) also includes a Low-Side bit, which configures the
low-side sense setting on IMON1.
The configuration registers are described in Table 37.
Table 37. Current Monitor Configuration Register Summary
Register
Address
Register Name
IMON1_Config0
IMON1_Config1
HIMON_Config0
HIMON_Config1
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
FAST_TH[2:0] GBP WM LSS
A_TH[1:0] B_TH[1:0] A_GAIN[1:0] B_GAIN[1:0]
FAST_TH[2:0]
A_TH[1:0] B_TH[1:0] A_GAIN[1:0] B_GAIN[1:0]
Reconfiguration Details
0x34
0
0
0x35
0x36
0x37
Master/Slave
(LOAD_CFG_REG supported)
GBP WM
X
0
0
A_TH[1:0], B_TH[1:0], A_GAIN[1:0], B_GAIN[1:0] – Threshold and Gain Setting for A and B Comparators
The A and B current monitor trip points are defined by the combination of the threshold and gain settings. Table 38
shows the trip point settings for both the IMON1 and HIMON current monitor circuits.
Table 38. Current Monitor Trip Points (Differential Voltage)
A_TH/B_TH[1:0]
GAIN[1:0]
00
01
10
11
(GAIN = 100V/V)
(GAIN = 50V/V)
(GAIN = 25V/V)
(GAIN = 10V/V)
00
01
10
11
8 mV
15.5 mV
20.5 mV
28.5 mV
39 mV
30.5 mV
40.5 mV
56.5 mV
77 mV
75 mV
100 mV
140 mV
190 mV
10.5 mV
14.5 mV
20 mV
GBP – Glitch Filter Bypass
Each of the current monitors include a glitch filter at each of the trip point comparator outputs as shown in Figure 8.
This glitch filter can be bypassed dependent on the GBP setting shown in Table 39.
Table 39. GBP Setting vs Glitch Bypass Behavior
GBP
Glitch Filter Setting
Glitch Filter On
0
1
Glitch Filter Bypassed
WM – Window Mode
Each of the current monitors include a selectable window mode, as described in Table 5. The window mode setting
is shown in Table 40.
Table 40. WM Setting vs Window Mode Value
WM
0
Window Mode
Off
On
1
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L-ASC10
In-System Programmable
Hardware Management Expander
LSS – Low Side Sense Mode
The IMON1 current monitor includes a low side sense mode, as shown in Figure 8. The low side sense settings are
shown in Table 41.
Table 41. LSS Setting vs Low Side Sensing Mode
LSS
0
Low Side Sense Mode
Disabled
1
Enabled
FAST_TH[2:0] - Fast Comparator Threshold
The fast trip point for both IMON1 and HIMON is set according to the FAST_TH[2:0] code. Table 42 shows the fast
trip point settings vs the FAST_THRESH code for both IMON1 and HIMON current monitor circuits.
Table 42. Fast Current Monitor Trip Points (Differential Voltage)
FAST_TH[2:0]
Trip Point
50 mV
000
001
010
011
100
101
110
111
100 mV
150 mV
200 mV
250 mV
300 mV
400 mV
500 mV
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L-ASC10
In-System Programmable
Hardware Management Expander
Temperature Monitor Configuration Registers
Table 43. Temperature Monitor Configuration Register Summary
Register
Address
Register Name
TMON1_Config0
TMON1_Config1
TMON1_Config2
TMON1_Config3
TMON1_Config4
TMON1_Config5
TMON1_Config6
TMON1_Config7
TMON1_Config8
TMON2_Config0
TMON2_Config1
TMON2_Config2
TMON2_Config3
TMON2_Config4
TMON2_Config5
TMON2_Config6
TMON2_Config7
TMON2_Config8
TMONint_Config0
TMONint_Config1
TMONint_Config2
TMONint_Config3
TMONint_Config4
TMONint_Config5
TMONint_Config6
TMONint_Config7
TMONint_Config8
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Reconfiguration Details
0x38
Ideality_Code[13:6]
Ideality_Code[5:0]
Off[8:1]
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
Cfg[1:0]
Th_A[8:2]
Off[0]
Th_A[1:0]
Th_B[2:0]
FilterB[3:0]
Th_B[8:3]
X
X
FLT
AVE[1:0]
FilterA[3:0]
X
X
HystA[6:0]
HystB[6:0]
Ideality_Code[13:6]
Ideality_Code[5:0]
Off[8:1]
Cfg[1:0]
Master-Only
(TMON circuit resets after
each time configuration
update)
Th_A[8:2]
Off[0]
Th_A[1:0]
Th_B[2:0]
FilterB[3:0]
Th_B[8:3]
X
X
FLT
AVE[1:0]
FilterA[3:0]
X
X
HystA[6:0]
HystB[6:0]
Ideality_Code[13:6]
Ideality_Code[5:0]
Off[8:1]
Cfg[1:0]
Th_A[8:2]
Off[0]
Th_A[1:0]
Th_B[2:0]
FilterB[3:0]
Th_B[8:3]
X
X
FLT
AVE[1:0]
FilterA[3:0]
X
X
HystA[6:0]
HystB[6:0]
The temperature monitor circuit (TMON) configuration registers can be updated over I2C. The definition and func-
tion of these parameters is described in the Temperature Monitor Inputs section. There are nine configuration reg-
isters per TMON channel (TMON1, TMON2, and TMON_int). The diode ideality factor, transducer configuration,
temperature offset, A and B monitor characteristics (threshold, filter, hysteresis) and measurement averaging and
fault behavior are all configurable according to the format in Table 43. A description of how to calculate each
parameter follows the register format. The temperature monitor circuit will reset each time a configuration parame-
ter is updated over I2C.
Ideality_Code[13:0] - Ideality Factor Setting
The Temperature Monitor inputs support a programmable ideality factor (emission coefficient) for interfacing to dif-
ferent remote transistor diodes. The programmable ideality factor is calculated based on a 14-bit code. The allowed
range of ideality factors is 0.9 to 2.0, values outside this range are not allowed. Calculating the code for a given ide-
ality factor is done using the following calculation:
Ideality_Code (14 bits, converted to binary) = ROUND (4572 / ideality factor)
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L-ASC10
In-System Programmable
Hardware Management Expander
Table 44 shows some common ideality factors and their corresponding codes.
Table 44. Ideality Factor vs Ideality_Code Setting
Ideality_Code[13:0]
Ideality Factor
0x08EE
2.0000
---------
---------
---------
0x11B6
0x11B7
0x11B8
1.0083
1.0082
1.0079
0x11C8
0x11C9
0x11CA
1.0044
1.0042
1.0039
0x11D9
0x11DA
0x11DB
0x11DC
0x11DD
0x11DE
0x11DF
1.0007
1.0004
1.0002
1.0000
0.9998
0.9996
0.9993
---------
0x13D8
0.9000
Cfg[1:0] - Temperature Monitor Diode Configuration
As described in the Temperature Monitor Inputs section, the TMON supports different transistor-based diode con-
figurations for connection to the ASC Temperature Monitors. The two bit value Tran_cfg[1:0], corresponds to the
supported configurations as shown in Table 45.
Table 45. Temperature Monitor Diode Configuration Settings
Cfg[1:0]
00
Diode Configuration
TMON disabled
01
Beta Compensated PNP
Differential PNP or NPN
Single-Ended (Not recommended)
10
11
Off[8:0] - Temperature Monitor Offset
The TMON supports a 9-bit programmable temperature offset, which is applied to the temperature measurement
for both readout and the A and B monitor comparison. The programmable offset range is from –64 oC to 63.75 oC,
o
with a resolution of 0.25 C. The offset is stored as a 2’s complement number, with the 9th bit as the signed bit.
Table 46 shows the settings associated with several different offset temperatures.
76
L-ASC10
In-System Programmable
Hardware Management Expander
Table 46. Temperature Monitor Offset Settings
Off[8:0]
0x0FF
0x0FE
Offset Temperature oC
63.75
63.50
-------------------------
------------------------
0x002
0x001
0x000
0x1FF
0x1FE
0.50
0.25
0.00
–0.25
–0.50
0x101
0x100
–63.75
–64.00
Th_A[8:0], Th_B[8:0] - Comparator Thresholds for A and B alarms
The TMON includes two individually programmable comparators, TMONA and TMONB. The 9-bit alarm thresholds
o
o
o
range for each of these monitors is –64 C to 155 C, with a resolution of 1 C. The thresholds are stored as 2’s
complement numbers, with the 9th bit as the signed bit. Values above 155 oC or below –64 oC are not valid thresh-
old settings. Table 47 shows the settings associated with several different threshold temperatures.
Table 47. Temperature Monitor Thresholds Settings
Th_A / Th_B[8:0]
0x09B
Threshold Temperature oC
155
154
0x09A
-------------------------
0x002
0x001
0x000
0x1FF
0x1FE
2
1
0
–1
–2
------------------------
0x1C1
0x1C0
–63
–64
FLT - Fault Reading Setting
The TMON circuit includes open and short fault detection circuitry for the remote diode channels. (The fault detect
is not applicable for the internal temperature monitor, TMON_INT). The 1-bit programmable fault setting deter-
mines the measurement readout behavior of both open and short faults. The readout values compared to the fault
setting is shown in Table 48.
Table 48. Temperature Monitor Fault Setting
Short Condition Reading
Open Condition Reading
FLT
°C
Code
0x3FF
0x401
°C
Code
0x401
0x3FF
0
1
255.75
–255.75
–255.75
255.75
77
L-ASC10
In-System Programmable
Hardware Management Expander
AVE[1:0] - Average Filter Coefficient
The TMON temperature measurement can be read out over I2C. The TMON circuit includes a programmable expo-
nential averaging filter that is applied before the measurement readout. The Average parameter can be pro-
grammed to three different averaging coefficients, as shown in Table 49.
Table 49. Temperature Monitor Measurement Average Settings
AVE[1:0]
Coefficient
00
01
10
11
1
8
16
N/A
FilterA[3:0] / FilterB[3:0] - Monitor Alarm Filter
The TMONA and TMONB comparators each support programmable monitor alarm filters. The depth of the alarm
filter can be programmed between 1 and 16, based on the Filter[3:0] setting. The relationship between the filter
code and the filter depth is given by the following equation:
DEPTH = Filter[3:0] + 1
HystA[3:0] / HystB[3:0] - Temperature Monitor Hysteresis
The TMONA and TMONB comparators each support programmable temperature hysteresis. The 7-bit hysteresis
range for each of these monitors is –64 oC to 63 oC, with a resolution of 1 oC. (The negative hysteresis range should
be applied to over-temperature comparisons, while the positive hysteresis should be applied to under-temperature
comparisons.) The hysteresis settings are stored as 2’s complement numbers, with the 7th bit as the signed bit.
Table 50 shows the settings associated with several different hysteresis temperatures.
Table 50. Temperature Monitor Hysteresis Settings
Hyst[6:0]
0x3F
Temperature Hysteresis oC
63
62
0x3E
-----------------
0x02
0x01
0x00
0x7F
0x7E
2
1
0
–1
–2
-----------------
0x41
0x40
–63
–64
78
L-ASC10
In-System Programmable
Hardware Management Expander
High Voltage Output (HVOUT) Configuration Registers
Table 51. High Voltage Output Configuration Register Summary
Register
Address
Register Name
HVOUT1_Config0
HVOUT1_Config1
HVOUT2_Config0
HVOUT2_Config1
HVOUT3_Config0
HVOUT3_Config1
HVOUT4_Config0
HVOUT4_Config1
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Reconfiguration Details
0x53
OCB
SW
1
I_SRC[1:0]
OD
I_SRC[1:0]
OD
I_SRC[1:0]
OD
I_SRC[1:0]
OD
I_SNK[1:0]
DUTY[3:0]
I_SNK[1:0]
DUTY[3:0]
I_SNK[1:0]
DUTY[3:0]
I_SNK[1:0]
DUTY[3:0]
VPP[1:0]
VPP[1:0]
VPP[1:0]
VPP[1:0]
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
FR
1
X
OCB
SW
FR
1
X
Master/Slave
(LOAD_CFG_REG supported)
OCB
SW
FR
1
X
OCB
SW
FR
X
The High Voltage Output pins (HVOUT) configuration registers can be updated over I2C. The definition and function
of these parameters is described in the High Voltage Outputs section. There are two configuration registers per
HVOUT (HVOUT1, HVOUT2, HVOUT3, HVOUT4). The open-drain/charge pump setting, charge pump voltage,
source and sink current, switched/static mode, and switched mode duty cycle and frequency are all configurable
according to the format in Table 51. A description of how to calculate each parameter follows the register format.
OCB - Output Control Block Source
The OCB parameter is used to select the control signal source for the HVOUT pin from either the Output Control
Block (OCB) or the ASC-I/F. Table 52 shows the available settings.
Table 52. OCB Setting vs HVOUT Source Selection
OCB
HVOUT Source
ASC-I/F Signal
OCB
0
1
I_SRC[1:0] - HVOUT Source Current
The I_SRC[1:0] setting is used to choose between the four supported source currents for the HVOUT in charge
pump mode. The available choices are shown in Table 53.
Table 53. HVOUT Source Current Settings
I_SRC[1:0]
Output Source Current
00
01
10
11
12.5 uA
25 uA
50 uA
100 uA
I_SNK[1:0] - HVOUT Sink Current
The I_SNK[1:0] setting is used to choose between the four supported sink currents for the HVOUT in charge pump
mode. The available choices are shown in Table 54.
79
L-ASC10
In-System Programmable
Hardware Management Expander
Table 54. HVOUT Sink Current Settings
I_SNK[1:0]
Output Sink Current
00
01
10
11
100 uA
250 uA
500 uA
3000 uA
VPP[1:0] - Charge Pump Output Voltage Settings
The VPP[1:0] setting is used to choose between the four programmable output voltage levels for the HVOUT in
charge pump mode. The available choices are shown in Table 55.
Table 55. HVOUT Output Voltage Settings
VPP[1:0]
Output Voltage
00
01
10
11
6V
8V
10V
12V
SW - Switched Output Setting
The SW parameter configures the HVOUT pin for either static drive mode (on or off) or switched mode (either
switched at the programmed frequency and duty, or off). Table 56 shows the available settings.
Table 56. SW Setting vs HVOUT Mode
SW
0
HVOUT Mode
On/Off
1
Switched
FR - Output Frequency Select (Switched Mode Only)
The FR parameter configures the output frequency of the HVOUT when the device is placed in switched mode.
Table 57 shows the available settings.
Table 57. FR Setting vs HVOUT Output Frequency (Switched Mode only)
FR
0
Frequency
31.25 kHz
15.625 kHz
1
OD - Open Drain Output Mode Setting
The OD parameter is used to configure the output mode of the device. Table 58 shows the available settings.
Table 58. OD Setting vs HVOUT Output Mode
OD
0
HVOUT Output Mode
Charge-Pump Mode
Open-Drain Mode
1
DUTY[3:0] - Duty Cycle Selection (Switched Mode Only)
The Duty_Cycle[3:0] setting is used to choose between the sixteen programmable duty cycles for the HVOUT in
switched mode. The available choices are shown in Table 59.
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L-ASC10
In-System Programmable
Hardware Management Expander
Table 59. HVOUT Switched Output Duty Cycle Settings
Duty_Cycle[3:0]
Duty Cycle%
6.25%
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
12.5%
18.75%
25%
31.25%
37.55%
43.75%
50.00%
56.25%
62.50%
68.75%
75.00%
81.25%
87.50%
93.75%
50.00%
81
L-ASC10
In-System Programmable
Hardware Management Expander
Output Control Block Configuration Registers
Table 60. Output Control Block Configuration Register Summary
Register
Address
Register Name
OCB_Config0
OCB_Config1
OCB_Config2
OCB_Config3
OCB_Config4
OCB_Config5
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Reconfiguration Details
0x5B
GPIO3_src[3:0]
HVOUT2_src[3:0]
HVOUT4_src[3:0]
GPIO2_src[2:0]
HVOUT1_src[3:0]
HVOUT3_src[3:0]
0x5C
0x5D
0x5E
0x5F
0x60
Master/Slave
(LOAD_CFG_REG supported)
X
X
X
X
X
IM_HCM_CTRL[2:0] HI_HCM_CTRL[2:0]
V6_HCM_CTRL[2:0] V5_HCM_CTRL[2:0]
HI_T H4i
H3i
H2i
H1i
G3i
G2i
The Output Control Block (OCB) configuration registers can be updated over I2C. The definition and function of
these parameters is described in the Output Control Block section. There are 6 total configuration registers for the
output control block. The settings in the six registers define the operation of the output control block output muxes,
the hysteretic control muxes, and the dynamic threshold management. Registers 0x5B-0x5D define the out control
muxes according to the format shown in Table 60.
OUTPUT_src[3:0] - Output Channel Source Signal Select
The output control source for each of the six OCB based outputs is defined by the four bit _src[3:0] code. The out-
puts selected by each code are shown in Table 61.
Table 61. Output Control Block – Output Source Signals
OUTPUT_src[3:0]
Source Signal
ASC-I/F
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
I2C
GPIO5
GPIO6
RESERVED
GPIO8
GPIO9
GPIO10
HIMON_F
IMON1_F
VMON_4A
VMON_9A
HIMON_HCM
IMON1_HCM
VMON5_HCM
VMON6_HCM
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In-System Programmable
Hardware Management Expander
HCM_CTRL - Hysteretic Mux Configuration for IMON1, HIMON, VMON6 and VMON5
Registers 0x5E and 0x5F define the control signal inputs for the 4 Hysteretic Control Muxes (HCM). The register
format is shown in Table 60. The control signals selected by the _HCM_CTRL[2:0] code are shown in Table 62.
Table 62. Output Control Block – Hysteretic Control Mux Settings
HCM_CTRL[2:0]
ASC-I/F Source Signal
GPIO2
000
001
010
011
100
101
110
111
GPIO3
HVOUT1
HVOUT2
HVOUT3
HVOUT4
N/A
N/A
H4i / H3i / H2i / H1i/ G3i / G2i - Output Invert Control
The OCB outputs can be inverted with respect to their control signals. As shown in Table 60, the register 0x60
defines the programmable invert option for each of the outputs.The invert setting parameter is shown in Table 63.
Table 63. H4i … G2i Setting vs OCB Output Behavior
H4i / H3i / H2i / H1i/ G3i / G2i
OCB Output
Normal
0
1
Inverted
HI_T - HIMON_A Threshold Source
Register 0x60 also defines the programmable threshold source select for the HIMON circuit. The threshold source
can be selected as either the configuration memory or the ASC-I/F, as shown in Table 64.
Table 64. HI_T Setting vs HIMONA Threshold Source
HI_T
HIMONA Threshold Source
Configuration Memory
ASC-I/F
0
1
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In-System Programmable
Hardware Management Expander
GPIO Input Configuration Registers
Table 65. GPIO Input Configuration Register Summary
Register
Address
Register Name
GPIO_Config0
GPIO_Config1
GPIO_Config2
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Reconfiguration Details
0x62
X
X
X
G4in
G8in
X
X
X
X
G3in
X
X
X
X
G2in
G6in
X
X
G1in
G5in
G9in
Master/Slave
(LOAD_CFG_REG supported)
0x63
0x64
X
G10in X
The GPIO pins can be configured as input or output. The GPIO configuration registers can be updated over I2C.
The registers at addresses 0x62, 0x63, and 0x64 include single configuration bit for each of the GPIO. When the
device is configured as an input, the GPIO pin is put into a Hi-Z state and a weak pulldown is enabled. The input
setting is described in Table 66. The input status can still be read at the pin, regardless of the Gxin setting. The for-
mat for registers 0x62, 0x63, and 0x64 is shown in Table 65.
Table 66. Gxin Setting vs GPIO Input Setting
Gxin
GPIO Setting
0
1
Output – Weak Pulldown Disabled
Input – Weak Pulldown Enabled
Write Protect and User Tag Configuration Register
Table 67. Write Protect and User Tag Configuration Register
Register
Address
Reconfiguration
Details
Register Name
Bit7 Bit6 Bit5 Bit4 Bit3
Bit2
Bit1 Bit0
0x66
WRITEPROTECT_USERTAG
X
X
X
X
X
UT_EN
WP[1:0]
Read Only
The Write Protect and User Tag modes are defined by the bit settings in register 0x66 (shown in Table 67). This
register cannot be written using the configuration register commands. It can only be overwritten in the EEPROM
memory.
UT_EN - User Tag Enable
The UT_EN bit configures the device for either User Tag Memory mode or Fault Logging mode, as described in
Table 68. The User Tag and Fault Log features are described in more details in the Fault Logging and User Tag
Memory section
Table 68. UT_EN vs Fault Log / User Tag Mode
UT_EN
Fault Log / User Tag Mode
0
1
Fault Log Enabled / User Tag Disabled
User Tag Enabled / Fault Log Disabled
WP[1:0] - Write Protect Setting
The write protect setting bits are defined in Table 69. The write protect function is described in detail later in the I2C
Write Protection section.
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Table 69. Write Protect Settings
WP[1:0]
00
Write Protect Settings
No protection
No protection
01
10
Protection based on GPIO1 level
I2C write disabled
11
User Electronic Signature (UES) Registers
Table 70. UES Memory Summary
Register
Address
Register Name
UES0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Reconfiguration Details
0x70
UES[7:0]
0x71
0x72
0x73
0x74
0x75
0x76
0x77
UES1
UES2
UES3
UES4
UES5
UES6
UES7
UES[15:8]
UES[23:16]
UES[31:24]
UES[39:32]
UES[47:40]
UES[55:48]
UES[63:56]
EEPROM Read Only
The ASC includes a User Electronic Signature feature in the EEPROM memory of the device. This consists of 64
bits that can be configured by the user to store unique data such as ID codes, revision numbers, or inventory con-
trol data. The UES code can only be written and readout using the EEPROM memory access commands. The UES
storage format is shown in Table 70.
Reserved Configuration Addresses
The configuration memory map includes several reserved addresses, which should not be read or written to. The
reserved addresses are shown in Table 71 below.
Table 71. Reserved Configuration Addresses
Register
Address
Register
Name
Reconfiguration
Details
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x61
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Do not read or write to
these addresses
0x65
0x67-0x6F
0x78-0xFF
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In-System Programmable
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Closed Loop Trim Register Access
The Trim and Margin block provides for I2C access to write closed loop trim profile 0 target values for each Trim
channel on-chip as shown in Table 72. The 12 bits of each closed trim setpoint register can be updated and read
back atomically using the dedicated instructions below.
Table 72. Closed Loop Trim Access Instructions
Instruction Code
Instruction Name
Read/Write
Description
0x41
TRIM1_CLT_P0_SET
R/W
Update and readback of TRIM1 closed loop
trim profile 0 setpoint register[11:0]
0x42
0x43
0x44
TRIM2_CLT_P0_SET
TRIM3_CLT_P0_SET
TRIM4_CLT_P0_SET
R/W
R/W
R/W
Update and readback of TRIM2 closed loop
trim profile 0 setpoint register[11:0]
Update and readback of TRIM3 closed loop
trim profile 0 setpoint register[11:0]
Update and readback of TRIM4 closed loop
trim profile 0 setpoint register[11:0]
The format for these instructions is shown in Figure 50 below.
Figure 50. TRIMx_CLT_P0_SET - I2C Instruction Format
SLAVE
ADDRESS
TRIM HIGH
BYTE
INSTRUCTION
CODE
TRIM LOW
BYTE
S
A[6:0]
W
A
0x4x
A
D[7:0]
A
D[11:8]
A
TRIM LOW
BYTE
TRIM HIGH
BYTE
SLAVE
ADDRESS
Sr
A[6:0]
R
A
D[7:0]
A
D[11:8]
NA P
The new trim target is latched in the hardware at the completion of the write sequence, the LOAD_CFG_REG com-
mand is not needed.
In Closed Loop Trim mode, the Trim targets are 12-bit positive numbers where each bit corresponds to 2 mV. See
Closed Loop Trim Configuration Registers for details on calculating the trim target voltage. In Manual mode, the
DAC targets are 8-bit signed numbers (low byte) where each bit corresponds to 2.5 mV (see the Margin/Trim DAC
Output Characteristics table) and the high byte is ignored. Both bytes have to be written for the new value to take
effect.
Measurement and Control Register Access
The measurement and control section of the ASC is accessed via two different I2C instructions. The
WRITE_MEAS_CTRL instruction is used to write the measurement selection for voltage and current measure-
ments, the selection for reading the monitor status, and the control selection for the output control block. The
READ_MEAS_CTRL is used to read the measurement result selected by the WRITE_MEAS_CTRL instruction.
The instructions are used to access the register set shown in Table 73. The instructions use the register addresses
in Table 73 and follow the format shown in Figure 51 for WRITE_MEAS_CTRL and Figure 52 for
READ_MEAS_CTRL.
Figure 51. WRITE_MEAS_CTRL - I2C Instruction Format
SLAVE
ADDRESS
INSTRUCTION
CODE
REGISTER
ADDRESS
DATA
[ADDRESS]
S
A[6:0]
W
A
0x51
A
R_A[7:0]
A
D[7:0]
A
P
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In-System Programmable
Hardware Management Expander
Figure 52. READ_MEAS_CTRL - I2C Instruction Format
DATA
[ADDRESS]
DATA
[ADDRESS +1]
SLAVE
ADDRESS
SLAVE
ADDRESS
INSTRUCTION
CODE
REGISTER
ADDRESS
S
A[6:0]
W
A
0x52
A
R_A[7:0]
A
Sr
A[6:0]
R
A
D0[7:0]
A
D1[7:0]
A*
P
Optional: Read up to 8
additional data bytes
* After final data byte read, master should NACK before issuing the STOP command
The measurement and control register address map is shown in Table 73. These register are used to read volt-
age and current measurements from the ADC, read temperature measurements from the TMON circuit, and con-
trol I/Os configured for I2C control. These registers should not be confused with the configuration registers, which
are accessed with a different set of instructions and comprise a completely separate 8-bit address space.
Table 73. Measurement and Control Register Overview
Register
Address
Register Name
adc_mux
Read/Write
Description
ADC Attenuator and SEL[4:0]
ADC Result [4:0] and status
ADC Result [12:5]
Value after POR
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0x00
R/W
R
0x01
adc_value_low
0x02
adc_value_high
R
0x03
imon_average_ctrl
imon_average_select
imon_average_result_low
imon_average_result_high
monitor_select
R/W
R/W
R
Average Control [3:0]
IMON MUX[1:0]
0x04
0x05
IMON moving average [7:0]
IMON moving average [9:8]
Monitor Select[3:0]
0x06
R
0x07
R/W
R
0x08
monitor_ record
Monitor Record[7:0]
0x09-0x6F
0x70
RESERVED
output_control_block
RESERVED
R/W
HVOUT1-4 and GPIO2-3 control
0000 0000
0x71-0x7F
0x80
tmon_meas_1_high
tmon_meas_1_low
tmon_meas_2_high
tmon_meas_2_low
tmon_meas_int_high
tmon_meas_int_low1
tmon_stat_a1
R
R
R
R
R
R
R
R
TMON_1 Measurement [15:8]
TMON_1 Measurement [7:5]
TMON_2 Measurement [15:8]
TMON_2 Measurement [7:5]
TMON_int Measurement [15:8]
TMON_int Measurement [7:5]
TMON_A Status [2:0]
1110 0000
0000 0000
1110 0000
0000 0000
1110 0000
0000 0000
0000 0000
0000 0000
0x81
0x82
0x83
0x84
0x85
0x86
0x87
tmon_stat_b
TMON_B Status [2:0]
0x88-0xFF
RESERVED
1. Any READ_MEAS_CTRL command which reads addresses 0x85 or 0x86 as the final data byte must be followed by an additional
READ_MEAS_CTRL command of a different address (such as 0x70) before issuing any other I2C read command.
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The registers shown in Figure 53 are provided for interfacing to the ADC.
Figure 53. ADC Registers
0x00 – ADC_MUX (Read/Write)
ATTEN
0
0
SEL4
SEL3
SEL2
SEL1
SEL0
b7
b6
b5
b4
b3
b2
b1
b0
0x01 – ADC_VALUE_LOW (Read)
D4
D3
D2
D1
D0
Pending
Active
Done
b7
b6
b5
b4
b3
b2
b1
b0
0x02 – ADC_VALUE_HIGH (Read)
D12
D11
D10
D9
D8
D7
D6
D5
b7
b6
b5
b4
b3
b2
b1
b0
To perform an A/D conversion, one must set the input attenuator and channel selector. For VMON input voltage
conversions, two input ranges may be set using the attenuator, 0-2.048 V and 0-5.9 V. For conversion of the
HVMON input voltage, the available attenuator ranges are 0-8.192 V and 0-13.2 V. These settings are shown in
Table 74.
Table 74. ADC Input Attenuator Control
VMON1-VMON9
HVMON
Full Scale Range
ATTEN(ADC_MUX.b7)
Resolution
Full Scale Range
0-2.048 V
Resolution
8mV
0
1
2 mV
6 mV
0-8.192
0-13.2
0-5.9 V
16mV
The input selector may be set to monitor any of the VMON input voltages, the VCCA supply voltage, or the IMON
differential voltages. The selectable input channels are shown in Table 75. Do not read or write to ADC_MUX selec-
tions not shown in the table.
Table 75. ADC Input Selection
SEL[4:0]
(ADC_MUX Selection)
Input Channel
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
HVMON
VCCA
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0C
0x10
0x13
IMON1
HIMON
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In-System Programmable
Hardware Management Expander
Writing a value to the ADC_MUX register using the WRITE_MEAS_CTRL instruction to set the input attenuator
and selector will automatically initiate a conversion. The PENDING bit will be set to 1 when a conversion is
requested but not yet active. The ACTIVE bit will be set to 1 when the requested conversion is the active conver-
sion. When the conversion is in process, the DONE bit (ADC_VALUE_LOW.b0) will be reset to 0. When the conver-
sion is complete, this bit will be set to 1. When the conversion is complete, the result may be read out of the ADC by
performing two I2C read operations using the READ_MEAS_CTRL instruction; one for ADC_VALUE_LOW, and
one for ADC_VALUE_HIGH. It is recommended that the I2C master load a second conversion instruction only after
the completion of the current conversion operation (Waiting for the DONE bit to be set to 1). The example flow
below shows the necessary instructions to complete an ADC read.
Voltage Monitor ADC Readout Over I2C
1. Perform an I2C Write Operation with Instruction 0x51, Register Address 0x00, and the ADC Channel and Atten-
uator setting from Table 75. This will initiate the ADC conversion.
2. Perform an I2C Read Operation with Instruction 0x52, Register Address 0x01 to check that the DONE bit is set.
Repeat if Register 0x01, bit 0 is not set to 1. Read ADC Data[4:0] for ADC low byte.
3. Perform an I2C Read Operation with Instruction 0x052, Register Address 0x02 to read ADC Data [12:5] for
ADC high byte
The Current Monitor (IMON1 and HIMON) averaging measurement hardware is also accessed through the I2C
interface. The IMON1/HIMON averaging is controlled by dedicated hardware and is managed separately from the
single conversion IMON1/HIMON access through the ADC registers. The IMON1/HIMON averaging registers are
shown in Figure 54.
Figure 54. IMON Average Control Registers
0x03 – IMON_AVG_CTRL (Read/Write)
HIMON
AVG_EN
IMON1
AVG_EN
SMPL_
INT_1
SMPL_
INT_0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0x04 – IMON_AVG_SELECT (Read/Write)
0
0
0
0
0
0
SEL1
SEL0
b7
b6
b5
b4
b3
b2
b1
b0
0x05 – IMON_AVG_RESULT_LOW (Read)
D7
D6
D5
D4
D3
D2
D1
D0
b7
b6
b5
b4
b3
b2
b1
b0
0x06 – IMON_AVG_RESULT_HIGH (Read)
0
0
0
0
0
0
D9
D8
b7
b6
b5
b4
b3
b2
b1
b0
To perform a moving average read, first enable the moving average for the given channel in the IMON_AVG_CTRL
register. When the averaging is enabled the averaging hardware will begin to compute a binary exponential
weighted moving average, as shown below:
CurrentMeasx
7
8
---------------------------------------------
--
CurrentAvex =
+ CurrentAvex – 1
8
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In-System Programmable
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The IMON_AVG_CTRL register is used to enable the averaging operation and set the sample period of the averag-
ing. The HIMON and IMON1 averaging operations are enabled independently by setting the HIMON_AVG_EN and
IMON1_AVG_EN respectively. Setting these bits to 1 enables the 1/8 moving averaging for that input channel. The
SMPL_PER[1:0] is used to select the sampling interval from the values shown in Table 76.
Table 76. IMON Average Sample Interval Values
SMPL_INT[1:0]
Sample Interval
1 ms
00
01
10
11
2 ms
4 ms
8 ms
Once the averaging is enabled, the IMON_AVG_SELECT register is used to select between the HIMON and
IMON1 average values for readout (see Table 77).
Table 77. Selected IMON Average Readout Channel
SELECT[1:0]
Channel
IMON1
00
01
10
11
Not Used
Not Used
HIMON
After writing to the IMON_AVG_SELECT register, the selected channels 10-bit moving average can be read out of
the IMON_AVG_RESULT_LOW and IMON_AVG_RESULT_HIGH registers. The value in the IMON_AVG_SELECT
register will remain active until overwritten by another I2C instruction (or power on reset). The updated 10-bit mov-
ing average for the previously selected channel can be readout from the result registers without re-writing the
SELECT register.
Current Monitor Moving Average Readout Over I2C
1. Perform an I2C Write Operation with Instruction 0x51, Register Address 0x03, and enable the HIMON averag-
ing and configure the sampling period. This will enable the HIMON averaging. See Table 76 and Table 77.
2. Moving average results are available immediately based on limited samples. Waiting additional sample periods
ensures that the averaging filter has time to settle. After enough time has elapsed, perform an I2C Write Opera-
tion with Instruction 0x51, Register Address 0x04, and select the HIMON channel for readout.
3. Perform an I2C Read Operation with Instruction 0x052, Register Address 0x05 to read
IMON_AVG_RESULT_LOW[7:0] for HIMON low byte.
4. Perform an I2C Read Operation with Instruction 0x052, Register Address 0x06 to read
IMON_AVG_RESULT_HIGH[9:8] for HIMON high byte.
The status of the voltage, current, and temperature monitor alarms, as well as the GPIO input status, can be read
out over I2C. Access to the alarm signals is controlled by the MONITOR_SELECT register. To read out the alarm or
GPIO status over I2C, write the applicable selection to the MONITOR_SELECT register as shown in Table 78. After
writing the corresponding value to the MONITOR_SELECT, you can read the monitor signal status from the
MONITOR_RECORD register. These registers are shown in Figure 55.
The MONITOR_SELECT also includes a valid bit. This bit is set to 1 once the MONITOR_RECORD register
includes the monitor signals selected in the MONITOR_SELECT register. The monitor signals are refreshed much
faster than the I2C access time, so normally the valid bit will read as 1. If the device is in safe state and ASC-I/F
communication has not started properly, the valid bit will read as 0. The MONITOR_RECORD register will continue
to include the latest status of the specified alarm signals, as specified in the MONITOR_SELECT register.
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In-System Programmable
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Figure 55. Monitor Signal Access Registers
0x07 – MONITOR_SELECT (Read/Write)
Valid
0
0
0
SEL3
SEL2
SEL1
SEL0
b7
b6
b5
b4
b3
b2
b1
b0
0x08 – MONITOR_RECORD (Read)
D7
D6
D5
D4
D3
D2
D1
D0
b7
b6
b5
b4
b3
b2
b1
b0
The register map of the monitor data is shown in Table 78 below. An example for how to read out selected data is
shown after the table.
Table 78. MONITOR_RECORD Byte Selection
MONITOR_
SELECT
[3:0]
MONITOR_RECORD[7:0]
D7
D6
D5
D4
D3
D2
D1
D0
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0
Fault_Log_ Full Fault_Log_Busy
0
0
X
1
X
1
AGOOD
GPIO3
GPIO10
GPIO2
GPIO9
GPIO1
GPIO8
HVOUT4
GPIO6
HVOUT2
GPIO5
HVOUT1
GPIO4
HIMON_b
HVOUT3
HIMON_a
VMON8_a
VMON4_a
TMON2_a
IMON1_b
VMON7_b
VMON3_b
TMON1_b
IMON1_a
VMON7_a
VMON3_a
TMON1_a
HVMON_b HVMON_a VMON9_b VMON9_a VMON8_b
VMON6_b VMON6_a VMON5_b VMON5_a VMON4_b
VMON2_b VMON2_a VMON1_b VMON1_a TMON2_b
TMONint_b TMONint_a
1
0
1
Monitor Record Readout Over I2C
1. Perform an I2C Write Operation with Instruction 0x51, Register Address 0x07, and write the selected data byte
for readout. This will populate the MONITOR_RECORD register, Address 0x08, with the latest sampled data of
the chosen bits as described in Table 78.
2. Perform an I2C Read Operation with Instruction 0x52, Register Address 0x08 to read the selected Monitor
Record.
The output signals for HVOUT1-4 and GPIO2-3 can be controlled via I2C instruction, dependent on their Output
Control Block configuration. The OUTPUT_CONTROL_BLOCK register (shown in Figure 56) is used to set the I2C
control input to the Output Control Block. Outputs which are not configured for I2C control will ignore the setting in
the I2C register. See the Output Control Block section for more details.
Figure 56. Output Control Block Register
0x70 – OUTPUT_CONTROL_BLOCK (Read/Write)
0
0
HVOUT4
HVOUT3
HVOUT2
HVOUT1
GPIO3
GPIO2
b7
b6
b5
b4
b3
b2
b1
b0
Several registers are provided for accessing the temperature monitor measurements. Each temperature monitor
channel has a TMON_MEAS_CHx_LO and TMON_MEAS_CHx_HI register for accessing the 11-bit temperature
reading (shown in Figure 57). Provided the temperature monitor is enabled, these registers are updated automati-
cally with the latest temperature reading. The update rate of the temperature reading is dependent on the number
of channels enabled (see the Temperature Monitors section for more details).
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The temperature measurement hardware will latch its latest reading after the TMON_MEAS_CHx_HIGH byte is
read over I2C. This will ensure that the corresponding TMON_MEAS_CHx_LOW byte is from the same measure-
ment as the TMON_MEAS_CHx_HIGH byte. The HIGH byte should be read first in the I2C transaction, followed by
the LOW byte. This will ensure the two bytes are from the same measurement reading.
Figure 57. Temperature Monitor Measurement Registers
0x80 – TMON_MEAS_CH1_HIGH (Read)
D10
D9
D8
D7
D6
D5
D4
D3
b7
b6
b5
b4
b3
b2
b1
b0
0x81 – TMON_MEAS_CH1_LOW (Read)
D2
D1
D0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0x82 – TMON_MEAS_CH2_HIGH (Read)
D10
D9
D8
D7
D6
D5
D4
D3
b7
b6
b5
b4
b3
b2
b1
b0
0x83 – TMON_MEAS_CH2_LOW (Read)
D2
D1
D0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
0x84 – TMON_MEAS_INT_HIGH (Read)
D10
D9
D8
D7
D6
D5
D4
D3
b7
b6
b5
b4
b3
b2
b1
b0
0x85 – TMON_MEAS_INT_LOW (Read)
D2
D1
D0
0
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
The format of the 11-bit temperature measurement is shown in Table 79 along with some example values. The
measurement format is 2-complement, with bit D10 used as the sign bit. The measurement resolution is 0.25 oC
per bit. Temperature monitor circuits which are reset or disabled will always readout –64oC.
Any READ_MEAS_CTRL command which reads addresses 0x85 or 0x86 as the final data byte must be followed
by an additional READ_MEAS_CTRL command of a different address (such as 0x70) before issuing any other I2C
read command.
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Table 79. Temperature Measurement Data Format
D[10:0]
0x3FF
0x26C
0x26B
Measured Temperature (oC)
160.00*
155.00
154.75
-------------------------
0x002
0x001
0x000
0x7FF
0x7FE
0.50
0.25
0.00
–0.25
–0.50
------------------------
0x701
0x700
–63.75
–64.00*
o
Note: Measurements above 160 C will limit to 0x3FF. There is no lower limit, although the TMON accuracy is
unguaranteed below –64 oC.
The temperature monitor alarm signals are also available to be read out over I2C directly. The A comparator alarm
signals for each temperature monitor can be read out from the TMON_STAT_A register while the B comparator
alarm signals can be read out from the TMON_STAT_B. The register format is shown in Figure 58.
Figure 58. Temperature Monitor Status Registers
0x86 – TMON_STAT_A (Read)
0
0
0
0
0
TMONINT_A TMON2_A
TMON1_A
b7
b6
b5
b4
b3
b2
b1
b0
0x87 – TMON_STAT_B (Read)
0
0
0
0
0
TMONINT_B TMON2_B
TMON1_B
b7
b6
b5
b4
b3
b2
b1
b0
Any READ_MEAS_CTRL command which reads addresses 0x85 or 0x86 as the final data byte must be followed
by an additional READ_MEAS_CTRL command of a different address (such as 0x70) before issuing any other I2C
read command.
93
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In-System Programmable
Hardware Management Expander
User Tag Memory Access
The I2C interface is used to access the User Tag memory feature of the ASC. The User Tag memory block consists
of a 7 byte User Tag register, a programming hardware block, and a 16 row x 7 byte EEPROM memory. The User
Tag memory block architecture is shown in Figure 59, along with the I2C access instructions.
The User Tag feature cannot be used when the ASC Fault Log is enabled. These features use the same memory
array and only one of the two features can be enabled at a given time. The User Tag instructions shown below are
only applicable for accessing the memory in User Tag mode. Access to the memory in Fault Log Mode should fol-
low the Fault Log instructions detailed in the next section.
Table 80 shows the User Tag access instructions. The instructions are used to access either the User Tag register
or the User Tag EEPROM memory block. Accessing the User Tag memory requires that the ASC is placed into pro-
gramming mode (see the ENABLE_PROG instruction). The format for each instruction is in the section that follows.
Table 80. User Tag Memory Access Instructions
Instruction
Code
0x61
0x62
0x63
0x64
Instruction Name
ERASE_USER_TAG_EEPROM
WRITE_USER_TAG_REG
READ_USER_TAG_REG
Read/Write
Description
W
W
R
Erase the User Tag EEPROM array
Write to the User Tag data register
Read out the contents of the User Tag data register
PROG_USER_TAG_EEPROM
W
Program the selected row of EEPROM bits with the
tag data register
0x65
READ_USER_TAG_EEPROM
R
Read out the selected row of User Tag EEPROM bits
Figure 59. User Tag Memory Architecture with I2C Instruction Access
USER TAG EEPROM
USER TAG REGISTER
7 BYTES
READ_USER_TAG_EEPROM
(ROW_ADDR[7:4])
WRITE_USER_TAG_REG
(BYTE0-BYTE7)
16 ROWS x
7 BYTES
Program Row
READ_USER_TAG_REG
(BYTE0-BYTE7)
PROG_USER_TAG_EEPROM
(ROW ADDR[7:4])
ERASE_USER_TAG_EEPROM
The ERASE_USER_TAG_EEPROM instruction is used to erase the entire User Tag EEPROM array. The User Tag
can only be erased as a full block. A row must be erased prior to programming it. The instruction format for
ERASE_USER_TAG_EEPROM is shown in Figure 60.
Figure 60. ERASE_USER_TAG_EEPROM - I2C Instruction Format
SLAVE
ADDRESS
INSTRUCTION
CODE
S
A[6:0]
W
A
0x61
A
P
The User Tag EEPROM is programmed in a two-step process. First the data which is to be programmed is written
into the User Tag register space, as shown in Figure 61. Up to 7 bytes (known as a data “row”) can be written into
the User Tag register space in a single write transaction. The WRITE_USER_TAG_REG instruction is used for writ-
ing the User Tag register space.
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Figure 61. WRITE_USER_TAG_REG - I2C Instruction Format
SLAVE
ADDRESS
INSTRUCTION
CODE
DATA
BYTE_0
DATA
BYTE_1
S
A[6:0]
W
A
0x62
A
D0[7:0]
A
D1[7:0]
A
P
Optional: Write up to 6
additional data bytes
The READ_USER_TAG_REG instruction is used to read out the User Tag register bytes as shown in Figure 62. Up
to 7 bytes can be read out from the User Tag register space in a single read transaction. The bytes are read back in
order from byte 0 to byte 6.
Figure 62. READ_USER_TAG_REG - I2C Instruction Format
DATA
BYTE_0
DATA
BYTE_1
SLAVE
ADDRESS
SLAVE
ADDRESS
INSTRUCTION
CODE
S
A[6:0]
W
A
0x63
A
Sr
A[6:0]
R
A
D0[7:0]
A
D1[7:0]
A*
P
Optional: Read up to 6
additional data bytes
* After final data byte read, master should NACK before issuing the STOP command
The second step of the User Tag programming is writing to the EEPROM from the User Tag registers. This is
accomplished using the PROGRAM_USER_TAG_EEPROM instruction. The data in the User Tag registers is cop-
ied by the programming block to the EEPROM row specified by the R_A[7:4] bits in the data byte as shown in
Figure 63. The 4-bit code corresponds to Row 0 to Row 15 in the User Tag EEPROM memory block, as shown in
the User Tag block diagram in Figure 59.
Figure 63. PROG_USER_TAG_EEPROM - I2C Instruction Format
SLAVE
ADDRESS
INSTRUCTION
CODE
ROW
ADDRESS*
S
A[6:0]
W
A
0x64
A
R_A[7:0]
A
P
Note: The Row Address R_A[7:0] contains the 4-bit address code in bits [7:4]. Bits [3:0] are always zero.
The READ_USER_TAG_EEPROM I2C instruction provides the mechanism to readback data stored in the User Tag
memory. The READ_USER_TAG_EEPROM is a two step read transaction operation shown in Figure 64. In the
first step, a write transaction is performed with the 0x65 instruction, and a 4-bit address code [7:4]. The address
code corresponds to Row 0 to Row 15 as shown in the User Tag block diagram in Figure 59. In the second step,
the row can be read out in 7 bytes, from byte 0 to byte 6, using a read transaction. The row address will auto-incre-
ment to support reading multiple rows in a single transaction. This means a single transaction can support reading
the entire user tag array, if the starting address of Row 0 is used. A stop condition will complete the read transac-
tion, this can be issued after any number of rows and bytes have been read.
Figure 64. READ_USER_TAG_EEPROM - I2C Instruction Format
DATA BYTE0
[ROW_ADDR]
DATA BYTE1
[ROW_ADDR]
SLAVE
ADDRESS
SLAVE
ADDRESS
INSTRUCTION
CODE
ROW
ADDRESS*
S
A[6:0]
W
A
0x65
A
R_A[7:0]
A
Sr
A[6:0]
R
A
D0[7:0]
A
D1[7:0]
A*
P
Optional: Read 6 additional bytes for complete record,
Read 112 data bytes (16 rows by 7 bytes) for the entire
fault log memory.
* After final data byte read, master should NACK before issuing the STOP command
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In-System Programmable
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User Tag Access Example
This example describes the steps necessary to program 7 Data Bytes to Row 4 of the EEPROM array:
1. Perform an I2C Write with the ENABLE_PROG instruction (0x04), with the 2-byte key code 0xE53D. This will
place the chip in programming mode, a required step for User Tag access.
2. (Optional) Perform an I2C Write with the ERASE_USER_TAG_EEPROM instruction (0x61). This is only
required if data has already been written to Row 4.
3. Perform an I2C Write with the WRITE_USER_TAG_REG instruction (0x62), with the 7 data bytes to be written.
4. Optional) Perform an I2C Read with the READ_USER_TAG_REG instruction (0x63) to confirm that the 7 Data
Bytes were properly written the USER_TAG_REGISTER.
5. Perform an I2C Write with the PROGRAM_USER_TAG_EEPROM instruction (0x64), with an R_A[0x40], row
address 4. This copies the data from the USER_TAG_REG into Row 4 of the USER_TAG_EEPROM array.
6. (Optional) Perform an I2C Read with the READ_USER_TAG_EEPROM instruction (0x65), with an address of
0x04. You can use this operation to verify the EEPROM programming.
7. Perform an I2C Write with the ENABLE_USER instruction (0x05). This operation will place the ASC back in
User Mode, in order to prevent accidental programming access.
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In-System Programmable
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Fault Log Memory Access
The ASC includes a fault logging block. The fault logging block consists of fault recording hardware, a volatile mem-
ory register which holds one 7 byte fault log record, a programming block, and a 16 row by 7 byte EEPROM mem-
ory for fault record storage. The fault logging block, including I2C access instructions is shown in Figure 65. The
fault logging block is described in detail in the fault log section.
The ASC Fault Log cannot be used when the user tag feature is enabled. These features use the same memory
array and only one of the two features can be enabled at a given time. The Fault Log instructions shown below are
only applicable for accessing the memory in Fault Log mode. Access to the memory in User Tag Mode should fol-
low the User Tag instructions detailed in the previous section.
Table 81 shows the Fault Log access instructions. The instructions are used to read out or erase either the fault log
register or the fault log EEPROM memory block. The format for each instruction is in the section that follows.
Writing fault logs to the EEPROM memory is triggered by the ASC-I/F. Faults can be recorded in either the fault log-
ging register or in the EEPROM (for more details see the Fault Log Section). The fault log recording hardware has
priority access to the fault log EEPROM memory, and needs to be disabled via the READ_FAULT_ENABLE
instruction prior to accessing the fault log via I2C. The fault log recording process also takes precedence over the
reconfiguration/programming of the device. If a fault log record process is active, the device will reject reconfigura-
tion requests. You can avoid that scenario by executing the READ_FAULT_ENABLE instruction prior to starting the
reconfiguration process.
The fault log instructions are summarized in Table 81 below, with individual instruction details in the following sec-
tion.
Table 81. Fault Log Access Instructions
Instruction Code
Instruction Name
ERASE_FAULT_EEPROM
READ_FAULT_VOLATILE_REG
READ_FAULT_ENABLE
Read/Write
Description
0x71
0x73
0x74
W
R
Erase the entire fault log memory
Read the fault log volatile register contents
R/W
Disables the fault log recording hardware
and enables the ERASE and READ instruc-
tions
0x75
0x76
READ_FAULT_RECORD_EEPROM
READ_ALL_FAULT_EEPROM
R
R
Read out the selected record of Fault Log
Array EEPROM bits
Reads out all records of the Fault Log
EEPROM Array
97
L-ASC10
In-System Programmable
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Figure 65. Fault Log Memory Block with I2C Access Instructions
ASC-I/F-Fault_Log_Mode
FAULT LOG EEPROM
FAULT LOG REGISTER
7 BYTES
I2C_READ_ALL_FAULT_EEPROM
ASC-I/F-Fault_Log_Trigger
ASC-I/F-Fault_Log_USER
16 ROWS x
7 BYTES
RECORD COPY TO
EEPROM*
I2C_READ_FAULT_RECORD_EEPROM
(RECORD ADD[7:4])
ASC-I/F
Fault_Log_Full
ASC-I/F
Fault_Log_Busy
I2C_READ_
FAULT_ENABLE
I2C_ERASE_FAULT_EEPROM
I2C_READ_FAULT_
VOLATILE_REG
* - Fault Log record programming number is automatically incremented each time a fault log is recorded in the memory.
The next programming row is recorded in the status register, accessed by the READ_STATUS I2C command.
The ERASE_FAULT_EEPROM instruction is used to erase the entire fault log EEPROM record storage. The ASC
must be in programming mode in order to execute this instruction (See the PROGRAM_MODE instruction). The
READ_FAULT_ENABLE instruction must also have been sent to the ASC in order to disable recording of new
faults. The format for the ERASE_FAULT_EEPROM is shown in Figure 66 below.
Figure 66. ERASE_FAULT_EEPROM - I2C Instruction Format
SLAVE
ADDRESS
INSTRUCTION
CODE
S
A[6:0]
W
A
0x71
A
P
The READ_FAULT_VOLATILE_REG instruction is used to read back the contents of the fault logging register. The
7 bytes are read back in order from Byte 0 to Byte 7. The READ_FAULT_ENABLE instruction must have been sent
to the ASC in order to disable recording of new faults, prior to executing a READ_FAULT_VOLATILE_REG instruc-
tion. The format is shown in Figure 67.
Figure 67. READ_FAULT_VOLATILE_REG - I2C Instruction Format
DATA
BYTE_0
DATA
BYTE_1
SLAVE
ADDRESS
SLAVE
ADDRESS
INSTRUCTION
CODE
S
A[6:0]
W
A
0x73
A
Sr
A[6:0]
R
A
D0[7:0]
A
D1[7:0]
A*
P
Optional: Read up to 6
additional data bytes
* After final data byte read, master should NACK before issuing the STOP command
The READ_FAULT_ENABLE instruction is used to disable the fault log recording hardware, and to enable the read-
back and erase of the fault logging memory block and fault log register. The READ_FAULT_ENABLE instruction is
a write instruction with readback. The first transaction is a write transaction, as shown in Figure 68 below. The
Address Byte with W=0 is sent, followed by the 0x74 instruction byte, followed by a keycode value of 0xAC. This
key code is required to enable reading out or erasing of faults and disable fault recording. Sending any other key-
code will disable reading and enable fault recording. Sending an incorrect keycode is the mechanism used to re-
enable fault log recording without resetting the device.
The second transaction is a read transaction, with the Address Byte with R=1 sent, followed by a readback of the
Fault Log Status Register. The Fault Log status register is described in Figure 69.
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In-System Programmable
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Figure 68. READ_FAULT_ENABLE - I2C Instruction Format
FAULT
STATUS_REG
SLAVE
ADDRESS
SLAVE
ADDRESS
INSTRUCTION
CODE
FAULT READ
ENABLE KEY
S
A[6:0]
W
A
0x74
A
0xAC
A
Sr
A[6:0]
R
A
R[7:0]
NA
P
Figure 69. Fault Log Status Register
Fault Log Status Register (Read Only)
REQ[1]
REQ[0]
EN[1]
EN[0]
0
0
0
0
b7
b6
b5
b4
b3
b2
b1
b0
The Fault Log status register is a read-only register which indicates the status of the fault log hardware. The regis-
ter bits indicate whether reading of fault logs is enabled or disabled. The possible readout combinations of the reg-
ister are shown in Table 82.
Table 82. Fault Log Status Details
REQ[1]
REQ[0]
EN[1]
EN[0]
Fault Log Status
0
0
1
0
0
1
0
1
0
0
1
0
ASC device is in safe state, or ERASEFAULT operation is active
Fault Logging is active, reading faults is disabled
Future fault logging is disabled and fault log read enable is requested.
Reading fault logs will be enabled pending completion of in progress fault
log recording or other EEPROM erase/program operation on-chip
1
1
1
1
Reading of fault logs via I2C is now enabled. Fault log recording is disabled
All other values
Invalid reading
The READ_FAULT_RECORD_EEPROM instruction provides the mechanism to readback fault log records stored
in the EEPROM memory. The READ_FAULT_RECORD_EEPROM is a two-step read transaction instruction, as
shown in Figure 70. In the first step, a write transaction is performed with the 0x75 instruction, and a 4-bit address
code [7:4]. The address code corresponds to fault log record 0 to 15, as shown in the fault log block diagram in
Figure 69. In the second step, the fault log record can be read out in 7 bytes, from byte 0 to byte 6, using a read
transaction. The record address will auto-increment to support reading multiple records in a single transaction. A
stop condition will complete the read transaction, this can be issued after any number of rows and bytes have been
read.The fault record is organized according to Table 14, in the Fault Logging and User Tag Memory section. This
means a single transaction can support reading the all 15 fault log memory records, if the starting address of
Record 0 is used.
The READ_FAULT_RECORD_EEPROM instruction will be ignored if the READ_FAULT_ENABLE instruction has
not been used to disable active fault recording.
Figure 70. READ_FAULT_RECORD_EEPROM - I2C Instruction Format
DATA BYTE0
[RECORD#]
DATA BYTE1
[RECORD#]
SLAVE
ADDRESS
SLAVE
ADDRESS
INSTRUCTION
CODE
RECORD*
NUMBER
S
A[6:0]
W
A
0x75
A
R_#[7:0]
A
Sr
A[6:0]
R
A
D0[7:0]
A
D1[7:0]
A**
P
Optional: Read 6 additional bytes for
complete record, Read 112 data bytes
(16 rows by 7 bytes) for the entire
fault log memory, depending on
starting row
*The Record Number R_#[7:0] contains the 4-bit record number code in bits [7:4]. Bits [3:0] are always zero.
** After final data byte read, master should NACK before issuing the STOP command
99
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In-System Programmable
Hardware Management Expander
The READ_ALL_FAULT_EEPROM is similar to the READ_FAULT_RECORD_EEPROM instruction and provides
an alternative mechanism for reading back fault log records stored in EEPROM memory. The
READ_ALL_FAULT_EEPROM instruction always starts the readback at Record 0 and does not support requesting
an individual fault log record request. During the read transaction, shown in step 2 of Figure 71, fault log row 0 can
be read out in 7 bytes. The row address will auto-increment to allow reading out the entire fault log array in a single
transaction. A stop condition will complete the read transaction, this can be issued after any number of rows and
bytes have been read. The READ_ALL_FAULT_EEPROM instruction will be ignored if the READ_FAULT_ENABLE
instruction has not been used to disable active fault recording.
Figure 71. READ_ALL_FAULT_EEPROM - I2C Instruction Format
DATA BYTE0
[RECORD # = 0]
DATA BYTE1
[RECORD # = 0]
SLAVE
ADDRESS
SLAVE
ADDRESS
INSTRUCTION
CODE
S
A[6:0]
W
A
0x76
A
Sr
A[6:0]
R
A
D0[7:0]
A
D1[7:0]
A*
P
Optional: Read 6 additional bytes for
complete record, Read 112 data bytes
(16 rows by 7 bytes) for the entire
fault log memory.
* After final data byte read, master should NACK before issuing the STOP command
Fault Log Memory Readout Example
This example describes the steps necessary to read the fault log EEPROM array over I2C. Note that the device
must be in fault logging mode or it will not respond to these instructions.
1. Perform an I2C Write with the READ_FAULT_ENABLE instruction (0x74), with the 1-byte key code 0xAC. Com-
plete the READ_FAULT_ENABLE operation by reading back the Fault Log Status Register. Repeat this opera-
tion until the Fault Log Status register reads as 0xF0 (Fault Log Reading is Enabled). When reading is enabled,
fault log recording will be disabled.
2. Perform an I2C Read with the READ_STATUS instruction (0x03). The ASC_STATUS_REGISTER_LO[7:4] bits
(FAULT_CNT[3:0]) are equal to the number of fault log records which have been written to the EEPROM mem-
ory array by the recording hardware. ASC_STATUS_REGISTER_LO[3] (FAULT_LOG_FULL) is set to 1 when
all sixteen records have been used for fault logging.
3. Perform an I2C READ with the READ_ALL_FAULT_EEPROM instruction (0x76). Read out the fault logs start-
ing at Record 0, Byte 0. Continue reading data until you reach the last populated fault record (given by
FAULT_CNT[3:0] in step 3), byte 6.
4. Perform an I2C Write with the READ_FAULT_ENABLE instruction (0x74), with any keycode besides 0xAC. This
disables fault log I2C access and returns the device to fault log recording mode. Repeat this operation until the
Fault Log Status register reads as 0x00 (Fault Log Recording is Enabled).
Fault Log Memory Erase Example
This example describes the steps necessary to erase the fault log EEPROM array. Note that the device must be in
fault logging mode or it will not respond to these instructions.
1. Perform an I2C Write with the ENABLE_PROGRAM instruction (0x04), with the 2-byte key code 0xE53D. This
will place the chip in programming mode, a required step to erase the fault log EEPROM array.
2. Perform an I2C Write with the READ_FAULT_ENABLE instruction (0x74), with the 1-byte key code 0xAC. Com-
plete the READ_FAULT_ENABLE operation by reading back the Fault Log Status Register. Repeat this opera-
tion until the Fault Log Status register reads as 0xF0 (Fault Log Reading is Enabled).
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In-System Programmable
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3. Perform an I2C Write with the ERASE_FAULT_EEPROM instruction (0x71). This will erase the fault log
EEPROM memory.
4. Perform an I2C Write with the READ_FAULT_ENABLE instruction (0x74), with any keycode besides 0xAC. This
disables fault log I2C access and return the device to fault log recording mode. Repeat this operation until the
Fault Log Status register reads as 0x00 (Fault Log Recording is Enabled).
5. Perform an I2C Write with the ENABLE_USER instruction (0x05). This operation places the ASC back in User
Mode in order to prevent accidental programming access.
I2C Write Protection
The ASC includes multiple protection mechanisms to prohibit accidental or incorrect access to the active device
configuration. The active device configuration access protections are set during the initial programming of the
device (also described in Table 69). There are three possible protection modes:
• I2C Configuration Write Enabled – The ASC configuration parameters can be freely overwritten by I2C commands
• I2C Configuration Write Disabled – The ASC configuration parameters cannot be overwritten by I2C instructions
• I2C Configuration Write Controlled by GPIO1 Pin State – The ASC configuration parameters can only be over-
written by I2C instructions when GPIO1 is pulled high by an external device (FPGA or Microcontroller)
These protection modes control the configuration access by the following I2C instructions: WRITE_CFG_REG,
WRITE_CFG_REG_wMASK, and TRIMx_CLT_P0_SET. This protection does not prevent EEPROM access
instructions. EEPROM access is protected by the ENABLE_PROG_MODE instruction and instruction key.
Figure 72 shows the typical configuration for working in the “Configuration Write Controlled by GPIO1 pin State”
protection mode.
Figure 72. I2C Write Protect by GPIO1
VDD
I2C_SDA
I2C_SCL
I2C_SDA
I2C_SCL
Platform
Manager 2
ASC1
GPIO1
PIOx
GPIO1
I2C Handler pulls PIOx high prior to
executing a configuration command
I2C_SDA
I2C_SCL
ASC2
GPIO1
The ASC device will still provide ACK bits in I2C write transmissions, even when the configuration write is disabled
(by either the GPIO1 state or configuration setting). Even though the device presents ACK bits, the configuration
memory will not be overwritten.
When using Write Protect by GPIO1 with WRITE_CFG_REG or WRITE_CFG_REG_wMASK, the GPIO1 signal
should be asserted before transmission of the 7-bit slave address. It should be de-asserted after the STOP or
RESTART signaling that marks the end of the write access. For TRIMx_CLT_P0_SET access, the GPIO1 signal
101
L-ASC10
In-System Programmable
Hardware Management Expander
should be asserted before transmission of the 7-bit slave address of the write phase. It should be de-asserted dur-
ing or after the transmission of the slave address at the start of the readback phase (See the Closed Loop Trim
Register Access section for more details).
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Pin Descriptions
Pin Function
VMON1
48-Pin QFN
Pin Type
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Digital I/O
Description
26
25
28
27
30
29
32
31
34
35
36
37
38
17
18
19
20
21
22
23
24
44
45
46
47
48
1
Voltage Monitor Input
VMON1GS
VMON2
VMON2GS
VMON3
VMON3GS
VMON4
VMON4GS
VMON5
VMON6
VMON7
VMON8
VMON9
HIMONP3
HIMONN_HVMON
IMON1P
IMON1N
TMON1P
TMON1N
TMON2P
TMON2N
GPIO1
Voltage Monitor Input Ground Sense
Voltage Monitor Input
Voltage Monitor Input Ground Sense
Voltage Monitor Input
Voltage Monitor Input Ground Sense
Voltage Monitor Input
Voltage Monitor Input Ground Sense
Voltage Monitor Input
Voltage Monitor Input
Voltage Monitor Input
Voltage Monitor Input
Voltage Monitor Input
12V Current Monitor Input Source
12V Current Monitor Input Return / Voltage Monitor Input
Low Voltage Current Monitor Input source
Low Voltage Current Monitor Input return
Temperature Monitor Input source
Temperature Monitor Input return
Temperature Monitor Input source
Temperature Monitor Input return
Digital Input/ Open Drain Output, reset Low
Digital Input/ Open Drain Output, reset Low
Digital Input/ Open Drain Output, reset Low
Digital Input/ Open Drain Output, reset Low
Digital Input/ Open Drain Output, reset Low
Digital Input/ Open Drain Output, reset Low
Digital Input/ Open Drain Output, reset Hi-Z
Digital Input/ Open Drain Output, reset Hi-Z
Digital Input/ Open Drain Output, reset Low
Current Source/ Open Drain Output, reset Low
Current Source/ Open Drain Output, reset Low
Current Source/ Open Drain Output, reset Low
Current Source/ Open Drain Output, reset Low
Trim DAC Output, reset Hi-Z
GPIO2
Digital I/O
GPIO3
Digital I/O
GPIO4
Digital I/O
GPIO5
GPIO62
GPIO82
Digital I/O
Digital I/O
11
12
13
2
Digital I/O
GPIO9
Digital I/O
GPIO10
HVOUT1
HVOUT2
HVOUT3
HVOUT4
TRIM1
Digital I/O
Analog/Digital Out
Analog/Digital Out
Analog/Digital Out
Analog/Digital Out
Analog Output
Analog Output
Analog Output
Analog Output
Digital I/O
3
9
10
39
40
41
42
43
15
14
16
7
TRIM2
Trim DAC Output, reset Hi-Z
TRIM3
Trim DAC Output, reset Hi-Z
TRIM4
RESETb1
Trim DAC Output, reset Hi-Z
Device reset (Active Low)
SCL
Digital Input
Digital I/O
Slave I2C Serial Clock input
SDA
Slave I2C Serial Data, Bi-directional pin
Resistor Input to set I2C address low bits
8 MHz ASC Clock Output (Tristate) CMOS
ASC Interface Data signal
I2C_ADDR
ASCCLK
RDAT
Analog Input
Digital Output
Digital Output
Digital Input
5
WDAT
4
ASC Interface Data Signal
103
L-ASC10
In-System Programmable
Hardware Management Expander
Pin Function
WRCLK
48-Pin QFN
Pin Type
Digital Input
Power
Description
6
33
8
ASC Interface Clock signal
VCCA
Main Power Supply
Power
GND
49
Power
Exposed die pad is the device ground
1. Do not connect any external drivers (push buttons, switches, or other devices) to the RESETb pins. See the Reset Requirements section for
more information.
2. GPIO7 is not bonded out.
3. When only using HIMONN_HVMON to measure voltage, connect HIMONP to the same source to prevent differential over-voltage.
104
L-ASC10
In-System Programmable
Hardware Management Expander
Device Pinout
Top View
1
2
GPIO6
HVOUT1
HVOUT2
WDAT
VMON7
VMON6
VMON5
VCCA
36
35
3
34
33
32
49 - GND (EXPOSED DIE PAD)
4
RDAT
5
VMON4
6
WRCLK
ASCCLK
VCCA
31
30
29
28
27
26
25
VMON4GS
VMON3
ASC
48-PIN QFN
7
8
VMON3GS
VMON2
HVOUT3
HVOUT4
GPIO8
9
10
11
12
VMON2GS
VMON1
GPIO9
VMON1GS
105
L-ASC10
In-System Programmable
Hardware Management Expander
Package Diagram
48-Pin QFN (Dimensions in mm)
TOP VIEW
BOTTOM VIEW
SIDE VIEW
SYMBOL
MIN.
0.80
0.00
NOM.
0.90
MAX.
1.00
0.05
NOTES: UNLESS OTHERWISE SPECIFIED
A
A1
A3
D
0.02
1.
2.
DIMENSIONS AND TOLERANCES
PER ANSI Y14.5M.
0.2 REF
7.0 BSC
5.40
7.0 BSC
5.40
0.20
ALL DIMENSIONS ARE IN MILLIMETERS.
D2
E
5.30
5.50
EXACT SHAPE AND SIZE OF THIS
FEATURE IS OPTIONAL.
E2
b
5.30
0.15
5.50
0.25
DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 mm FROM TERMINAL TIP.
e
L
0.50 BSC
0.40
APPLIES TO EXPOSED PORTION OF TERMINALS.
0.35
0.45
106
L-ASC10
In-System Programmable
Hardware Management Expander
Part Number Description
L-ASC10-1 SG48 I XX
Device Family
Shipping Method
Blank = Trays
Number of Rails
TR = Tape and Reel
Operating Temperature Range
Performance Grade
I = Industrial
1 = Standard
Package
SG48 = 48-pin Halogen-Free Package
Ordering Information
Halogen-Free Packaging
Part Number
Package
Pins
L-ASC10-1SG48I
Halogen-Free QFN
48
For Further Information
For more information on the Platform Manager 2 family of devices, consult the Platform Manager 2, MachXO2,
MachXO3, and ECP5 family data sheets along with related application and technical notes on the Lattice website.
• FPGA-DS-02012 (previously DS1044), ECP5 and ECP5-5G Family Data Sheet
• DS1035, MachXO2 Family Data Sheet
• FPGA-DS-02032 (previously DS1047), MachXO3 Family Data Sheet
• FPGA-DS-02036 (previously DS1043), Platform Manager 2 Family Data Sheet
• AN6094, Adding Scalable Power and Thermal Management to MachXO2 and MachXO3 Using L-ASC10
• AN6095, Adding Scalable Power and Thermal Management to ECP5 Using L-ASC10
• TN1225, Platform Manager 2 Hardware Checklist
• Platform Designer User Guide
Technical Support Assistance
Submit a technical support case through www.latticesemi.com/techsupport.
107
L-ASC10
In-System Programmable
Hardware Management Expander
Revision History
Date
Version
Section
Change Summary
June 2019
2.0
—
Clarified Closed Loop Trim mode and Bypass mode in several
sections.
Part Number Description Added Tape and Reel.
May 2019
1.9
1.8
Device Pinout
Added Top View label.
Package Diagrams
Correctly labeled Top and Bottom views.
Added Disclaimers section.
—
September 2018
—
Changed document number from DS1042 to FPGA-DS-02038.
Added LPTM21L to Figure 1.
Application Diagram
DC and Switching
Characteristics
Clarification added to Fault Log table.
Theory of Operation
Updated High Voltage Monitor section. Added information on
extending input voltage range.
Updated Calculation section.
— Added information on PGA settings under the Voltage at the
VMONx Pins subsection.
Updated System Connections section.
— Added reference to Figure 32 in the section introduction.
— Added Table 15.
— Indicated Platform Manager 2 LPTM21 in Figure 30 and
added note.
I2C Interface
Added LPTM21L row to Table 20.
Added note 3.
Pin Descriptions
For Further Information Added product names and updated document numbers.
June 2017
1.7
Multiple
Added references to MachXO3 and ECP5.
Theory of Operation
Added clarification to TrimCell Architecture section. Updated
Figure 26, TrimCell Architecture.
— Modified caption of Figure 31, System Connections - ASC and
MachXO2, or MachXO3.
— Added Figure 32, System Connections - ASC and ECP5.
May 2016
April 2015
1.6
1.5
I2C Interface
Updated Measurement and Control Register Access section to
address restrictions on READ_MEAS_CTRL command with
addresses 0x85 and 0x86.
Multiple
Deleted all references to LPTM20.
Theory of Operation
Updated System Connections section.
Modified the following figures to clarify I2C_ADDR pin usage:
— Figure 30, System Connections - ASC and Platform Manager 2
— Figure 31, System Connections - ASC and MachXO2,
MachXO3, or ECP5
I2C Interface
Updated ASC Configuration Registers section.
Updated Polarity bit setting in Table 23, POL Setting vs Closed
Loop Trim Polarity.
October 2014
1.4
I2C Interface
Updated Device Status and Mode Management section.
Revised Figure 39, READ_STATUS - I2C Instruction Format.
Package Diagram
Updated 48-Pin QFN (Dimensions in mm) diagram.
108
L-ASC10
In-System Programmable
Hardware Management Expander
Date
Version
Section
Change Summary
May 2014
01.3
—
Data sheet status changed from preliminary to final.
DC and Switching Charac- Specifications populated with characterization results.
teristics
Added ASC-I/F Timing section.
Multiple
Renamed IMON to IMON1.
Updated ASC-IF TRIM control signal names.
Removed IMON Hysteresis feature.
Expanded Output Control Block section.
Updated System Connections section.
Theory of Operation
I2C Interface
Corrected error in ADC Input Selection table for IMON1 and
HIMON SEL bits.
Updated VMON and IMON tables with final device trip points.
Added preliminary ESD Performance section.
March 2014
01.1
01.2
DS and Switching
Characteristics
Corrected formatting error on Page 27. Moved footnote after Fig-
ure 24, ASC Margin/Trim Block.
December 2013
01.0
Preliminary release.
Disclaimers
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its products
for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely with Buyer.
Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited test-
ing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice products
should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a situation
where personal injury, death, severe property or environmental damage may occur. The information provided in this document is proprietary to Lattice
Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice.
109
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