LA-ISPMACH4064V [LATTICE]
3.3V/1.8V In-System Programmable SuperFAST High Density PLDs; 3.3V / 1.8V在系统可编程超快高密度可编程逻辑器件
| 型号： | LA-ISPMACH4064V |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | 3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| 文件： | 总42页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LA-ispMACH 4000V/Z
Automotive Family
3.3V/1.8V In-System Programmable
TM
SuperFAST High Density PLDs
July 2008
Data Sheet DS1017
• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI
interfaces
• Hot-socketing
Features
■ High Performance
• f
= 168MHz maximum operating frequency
MAX
• Open-drain capability
• t = 7.5ns propagation delay
PD
• Input pull-up, pull-down or bus-keeper
• Programmable output slew rate
• 3.3V PCI compatible
• IEEE 1149.1 boundary scan testable
• 3.3V/2.5V/1.8V In-System Programmable
(ISP™) using IEEE 1532 compliant interface
• I/O pins with fast setup path
• Lead-free (RoHS) package
• Up to four global clock pins with programmable
clock polarity control
• Up to 80 PTs per output
■ Ease of Design
• Enhanced macrocells with individual clock,
reset, preset and clock enable controls
• Up to four global OE controls
• Individual local OE control per I/O pin
• Excellent First-Time-FitTM and refit
• Fast path, SpeedLockingTM Path, and wide-PT
path
Introduction
The high performance LA-ispMACH 4000V/Z automo-
tive family from Lattice offers a SuperFAST CPLD solu-
tion that is tested and qualified to the AEC-Q100
• Wide input gating (36 input logic blocks) for fast
counters, state machines and address decoders standard. The family is a blend of Lattice’s two most
popular architectures: the ispLSI® 2000 and ispMACH
■ Zero Power (LA-ispMACH 4000Z)
4A. Retaining the best of both families, the LA-ispMACH
• Typical static current 10µA (4032Z)
4000V/Z architecture focuses on significant innovations
• 1.8V core low dynamic power
to combine the highest performance with low power in a
• LA-ispMACH 4000Z operational down to 1.6V
flexible CPLD family.
■ AEC-Q100 Tested and Qualified
The LA-ispMACH 4000V/Z automotive family combines
high speed and low power with the flexibility needed for
ease of design. With its robust Global Routing Pool and
Output Routing Pool, this family delivers excellent First-
Time-Fit, timing predictability, routing, pin-out retention
and density migration.
• Automotive: -40 to 125°C ambient (T )
A
■ Easy System Integration
• Superior solution for power sensitive consumer
applications
• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
• Operation with 3.3V (4000V) or 1.8V (4000Z)
supplies
Table 1. LA-ispMACH 4000V Automotive Family Selection Guide
LA-ispMACH 4032V
LA-ispMACH 4064V
LA-ispMACH 4128V
Macrocells
32
30+2/32+4
7.5
64
128
I/O + Dedicated Inputs
30+2/32+4/64+10
64+10/92+4/96+4
t
(ns)
7.5
4.5
7.5
4.5
PD
t (ns)
4.5
S
t
f
(ns)
4.5
4.5
4.5
CO
(MHz)
168
168
3.3V
168
3.3V
MAX
Supply Voltage (V)
Pins/Package
3.3V
44-pin Lead-Free TQFP
48-pin Lead-Free TQFP
44-pin Lead-Free TQFP
48-pin Lead-Free TQFP
100-pin Lead-Free TQFP
100-pin Lead-Free TQFP
128-pin Lead-Free TQFP
144-pin Lead-Free TQFP
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
DS1017_02.3
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Table 2. LA-ispMACH 4000Z Automotive Family Selection Guide
LA-ispMACH 4032Z
LA-ispMACH 4064Z
LA-ispMACH 4128Z
Macrocells
32
64
32+4/64+10
7.5
128
64+10
7.5
I/O + Dedicated Inputs
32+4
t
(ns)
7.5
PD
t (ns)
4.5
4.5
4.5
S
t
f
(ns)
4.5
4.5
4.5
CO
(MHz)
168
1.8V
168
168
MAX
Supply Voltage (V)
Pins/Package
1.8V
1.8V
48-pin Lead-Free TQFP
48-pin Lead-Free TQFP
100-pin Lead-Free TQFP
100-pin Lead-Free TQFP
The LA-ispMACH 4000V/Z automotive family offers densities ranging from 32 to 128 macrocells.There are multiple
density-I/O combinations in Thin Quad Flat Pack (TQFP) packages ranging from 44 to 144 pins. Tables 1 and 2
show the macrocell, package and I/O options, along with other key parameters.
The LA-ispMACH 4000V/Z automotive family has enhanced system integration capabilities. It supports 3.3V (4000V
and 1.8V (4000Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely
driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The LA-
ispMACH 4000V/Z also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper
latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. The LA-ispMACH 4000V/Z
automotive family is in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1
boundary scan testing capability also allows product testing on automated test equipment. The 1532 interface sig-
nals TCK, TMS, TDI and TDO are referenced to VCC (logic core).
Overview
The LA-ispMACH 4000V/Z automotive devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks
(GLBs) interconnected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O
Blocks (IOBs), which contain multiple I/O cells. This architecture is shown in Figure 1.
Figure 1. Functional Block Diagram
I/O
Block
I/O
Block
16
36
16
36
Generic
Logic
Block
Generic
Logic
Block
ORP
ORP
16
16
I/O
Block
I/O
Block
16
36
16
36
Generic
Logic
Block
Generic
Logic
Block
ORP 16
16
ORP
2
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
The I/Os in the LA-ispMACH 4000V/Z automotive devices are split into two banks. Each bank has a separate I/O
power supply. Inputs can support a variety of standards independent of the chip or bank power supply. Outputs
support the standards compatible with the power supply provided to the bank. Support for a variety of standards
helps designers implement designs in mixed voltage environments. In addition, 5V tolerant inputs are specified
within an I/O bank that is connected to V
of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces.
CCO
LA-ispMACH 4000V/Z Automotive Architecture
There are a total of two GLBs in the LA-ispMACH 4032V/Z, increasing to 8 GLBs in the LA-ispMACH 4128V/Z.
Each GLB has 36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into
the GRP to be connected to the inputs of any other GLB on the device. Even if feedback signals return to the same
GLB, they still must go through the GRP. This mechanism ensures that GLBs communicate with each other with
consistent and predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them
to the associated I/O cells in the I/O block.
Generic Logic Block
The LA-ispMACH 4000V/Z Automotive GLB consists of a programmable AND array, logic allocator, 16 macrocells
and a GLB clock generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O
pins are decoupled from macrocells through the ORP. Figure 2 illustrates the GLB.
Figure 2. Generic Logic Block
To GRP
Clock
Generator
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
36 Inputs
from GRP
To
Product Term
Output Enable
Sharing
AND Array
The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are
used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con-
nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic
allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and
Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being
fed to the macrocells.
Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0.
There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND
Array.
3
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Figure 3. AND Array
In[0]
In[34]
In[35]
PT0
PT1
PT2
PT3
PT4
Cluster 0
PT75
PT76
PT77
PT78
PT79
Cluster 15
PT80 Shared PT Clock
PT81 Shared PT Initialization
PT82 Shared PTOE
Note:
Indicates programmable fuse.
Enhanced Logic Allocator
Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term
cluster is associated with a macrocell. The cluster size for the LA-ispMACH 4000V/Z automotive family is 4+1 (total
5) product terms. The software automatically considers the availability and distribution of product term clusters as it
fits the functions within a GLB. The logic allocator is designed to provide three speed paths: 5-PT fast bypass path,
20-PT Speed Locking path and an up to 80-PT path. The availability of these three paths lets designers trade tim-
ing variability for increased performance.
The enhanced Logic Allocator of the LA-ispMACH 4000V/Z automotive family consists of the following blocks:
• Product Term Allocator
• Cluster Allocator
• Wide Steering Logic
Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB.
Figure 4. Macrocell Slice
to to
n-1 n-2
from from
n-1 n-4
Fast 5-PT
Path
From
n-4
1-80
PTs
5-PT
n
To XOR (MC)
Cluster
to
n+1
from
n+2
from
n+1
To n+4
Individual Product
Term Allocator
Cluster
Allocator
SuperWIDE™
Steering Logic
4
Lattice Semiconductor
Product Term Allocator
LA-ispMACH 4000V/Z Automotive Family Data Sheet
The product term allocator assigns product terms from a cluster to either logic or control applications as required
by the design being implemented. Product terms that are used as logic are steered into a 5-input OR gate associ-
ated with the cluster. Product terms that used for control are steered either to the macrocell or I/O cell associated
with the cluster. Table 3 shows the available functions for each of the five product terms in the cluster. The OR gate
output connects to the associated I/O cell, providing a fast path for narrow combinatorial functions, and to the logic
allocator.
Table 3. Individual PT Steering
Product Term
PTn
Logic
Control
Logic PT
Logic PT
Logic PT
Logic PT
Logic PT
Single PT for XOR/OR
PTn+1
Individual Clock (PT Clock)
PTn+2
Individual Initialization or Individual Clock Enable (PT Initialization/CE)
Individual Initialization (PT Initialization)
PTn+3
PTn+4
Individual OE (PTOE)
Cluster Allocator
The cluster allocator allows clusters to be steered to neighboring macrocells, thus allowing the creation of functions
with more product terms. Table 4 shows which clusters can be steered to which macrocells. Used in this manner,
the cluster allocator can be used to form functions of up to 20 product terms. Additionally, the cluster allocator
accepts inputs from the wide steering logic. Using these inputs, functions up to 80 product terms can be created.
Table 4. Available Clusters for Each Macrocell
Macrocell
M0
Available Clusters
—
C0
C0
C1
C1
C2
C2
C3
M1
M2
C1
C2
C3
C4
M3
C2
C3
C4
C5
M4
C3
C4
C5
C6
M5
C4
C5
C6
C7
M6
C5
C6
C7
C8
M7
C6
C7
C8
C9
M8
C7
C8
C9
C10
C11
C12
C13
C14
C15
—
M9
C8
C9
C10
C11
C12
C13
C14
C15
—
M10
M11
M12
M13
M14
M15
C9
C10
C11
C12
C13
C14
C15
C10
C11
C12
C13
C14
—
Wide Steering Logic
The wide steering logic allows the output of the cluster allocator n to be connected to the input of the cluster alloca-
tor n+4. Thus, cluster chains can be formed with up to 80 product terms, supporting wide product term functions
and allowing performance to be increased through a single GLB implementation. Table 5 shows the product term
chains.
5
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Table 5. Product Term Expansion Capability
Expansion Chains
Chain-0
Macrocells Associated with Expansion Chain (with Wrap Around)
Max PT/Macrocell
M0 → M4 → M8 → M12 → M0
M1 → M5 → M9 → M13 → M1
M2 → M6 → M10 → M14 → M2
M3 → M7 → M11 → M15 → M3
75
80
75
70
Chain-1
Chain-2
Chain-3
Every time the super cluster allocator is used, there is an incremental delay of t
. When the super cluster alloca-
EXP
tor is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super clus-
ter is steered to M (n+4), then M (n) is ground).
Macrocell
The 16 macrocells in the GLB are driven by the 16 outputs from the logic allocator. Each macrocell contains a pro-
grammable XOR gate, a programmable register/latch, along with routing for the logic and control functions.
Figure 5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input
from the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable
delay in this path allows designers to choose between the fastest possible set-up time and zero hold time.
Figure 5. Macrocell
Power-up
Initialization
Shared PT Initialization
PT Initialization (optional)
PT Initialization/CE (optional)
Delay
From I/O Cell
R
P
From Logic Allocator
To ORP
To GRP
D/T/L
Q
CE
Block CLK0
Block CLK1
Block CLK2
Block CLK3
Single PT
PT Clock (optional)
Shared PT Clock
Enhanced Clock Multiplexer
The clock input to the flip-flop can select any of the four block clocks along with the shared PT clock, and true and
complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The
eight sources for the clock multiplexer are as follows:
• Block CLK0
• Block CLK1
• Block CLK2
6
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
• Block CLK3
• PT Clock
• PT Clock Inverted
• Shared PT Clock
• Ground
Clock Enable Multiplexer
Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the fol-
lowing four sources:
• PT Initialization/CE
• PT Initialization/CE Inverted
• Shared PT Clock
• Logic High
Initialization Control
The LA-ispMACH 4000V/Z automotive family architecture accommodates both block-level and macrocell-level set
and reset capability. There is one block-level initialization term that is distributed to all macrocell registers in a GLB.
At the macrocell level, two product terms can be “stolen” from the cluster associated with a macrocell to be used for
set/reset functionality. A reset/preset swapping feature in each macrocell allows for reset and preset to be
exchanged, providing flexibility.
Note that the reset/preset swapping selection feature affects power-up reset as well. All flip-flops power up to a
known state for predictable system initialization. If a macrocell is configured to SET on a signal from the block-level
initialization, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a
signal from the block-level initialization or is not configured for set/reset, then that macrocell will RESET on power-
up. To guarantee initialization values, the V rise must be monotonic, and the clock must be inactive until the reset
CC
delay time has elapsed.
GLB Clock Generator
Each LA-ispMACH 4000V/Z automotive device has up to four clock pins that are also routed to the GRP to be used
as inputs. These pins drive a clock generator in each GLB, as shown in Figure 6. The clock generator provides four
clock signals that can be used anywhere in the GLB.These four GLB clock signals can consist of a number of com-
binations of the true and complement edges of the global clock signals.
Figure 6. GLB Clock Generator
CLK0
Block CLK0
CLK1
Block CLK1
CLK2
Block CLK2
CLK3
Block CLK3
7
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Output Routing Pool (ORP)
The Output Routing Pool allows macrocell outputs to be connected to any of several I/O cells within an I/O block.
This provides greater flexibility in determining the pinout and allows design changes to occur without affecting the
pinout. The output routing pool also provides a parallel capability for routing macrocell-level OE product terms. This
allows the OE product term to follow the macrocell output as it is switched between I/O cells. Additionally, the out-
put routing pool allows the macrocell output or true and complement forms of the 5-PT bypass signal to bypass the
output routing multiplexers and feed the I/O cell directly. The enhanced ORP of the LA-ispMACH 4000V/Z family
consists of the following elements:
• Output Routing Multiplexers
• OE Routing Multiplexers
• Output Routing Pool Bypass Multiplexers
Figure 7 shows the structure of the ORP from the I/O cell perspective. This is referred to as an ORP slice. Each
ORP has as many ORP slices as there are I/O cells in the corresponding I/O block.
Figure 7. ORP Slice
OE Routing Multiplexer
From PTOE
To I/O
Cell
OE
ORP
Bypass
Multiplexer
5-PT Fast Path
From Macrocell
To I/O
Cell
Output
Output Routing Multiplexer
Output Routing Multiplexers
The details of connections between the macrocells and the I/O cells vary across devices and within a device
dependent on the maximum number of I/Os available. Tables 6-10 provide the connection details.
Table 6. ORP Combinations for I/O Blocks with 8 I/Os
I/O Cell
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Available Macrocells
M0, M1, M2, M3, M4, M5, M6, M7
M2, M3, M4, M5, M6, M7, M8, M9
M4, M5, M6, M7, M8, M9, M10, M11
M6, M7, M8, M9, M10, M11, M12, M13
M8, M9, M10, M11, M12, M13, M14, M15
M10, M11, M12, M13, M14, M15, M0, M1
M12, M13, M14, M15, M0, M1, M2, M3
M14, M15, M0, M1, M2, M3, M4, M5
8
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Table 7. ORP Combinations for I/O Blocks with 16 I/Os
I/O Cell
Available Macrocells
I/O 0
I/O 1
M0, M1, M2, M3, M4, M5, M6, M7
M1, M2, M3, M4, M5, M6, M7, M8
M2, M3, M4, M5, M6, M7, M8, M9
M3, M4, M5, M6, M7, M8, M9, M10
M4, M5, M6, M7, M8, M9, M10, M11
M5, M6, M7, M8, M9, M10, M11, M12
M6, M7, M8, M9, M10, M11, M12, M13
M7, M8, M9, M10, M11, M12, M13, M14
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
M8, M9, M10, M11, M12, M13, M14, M15
M9, M10, M11, M12, M13, M14, M15, M0
M10, M11, M12, M13, M14, M15, M0, M1
M11, M12, M13, M14, M15, M0, M1, M2
M12, M13, M14, M15, M0, M1, M2, M3
M13, M14, M15, M0, M1, M2, M3, M4
M14, M15, M0, M1, M2, M3, M4, M5
M15, M0, M1, M2, M3, M4, M5, M6
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
Table 8. ORP Combinations for I/O Blocks with 12 I/Os
I/O Cell
Available Macrocells
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
M0, M1, M2, M3, M4, M5, M6, M7
M1, M2, M3, M4, M5, M6, M7, M8
M2, M3, M4, M5, M6, M7, M8, M9
M4, M5, M6, M7, M8, M9, M10, M11
M5, M6, M7, M8, M9, M10, M11, M12
M6, M7, M8, M9, M10, M11, M12, M13
M8, M9, M10, M11, M12, M13, M14, M15
M9, M10, M11, M12, M13, M14, M15, M0
M10, M11, M12, M13, M14, M15, M0, M1
M12, M13, M14, M15, M0, M1, M2, M3
M13, M14, M15, M0, M1, M2, M3, M4
M14, M15, M0, M1, M2, M3, M4, M5
ORP Bypass and Fast Output Multiplexers
The ORP bypass and fast-path output multiplexer is a 4:1 multiplexer and allows the 5-PT fast path to bypass the
ORP and be connected directly to the pin with either the regular output or the inverted output. This multiplexer also
allows the register output to bypass the ORP to achieve faster t
.
CO
Output Enable Routing Multiplexers
The OE Routing Pool provides the corresponding local output enable (OE) product term to the I/O cell.
I/O Cell
The I/O cell contains the following programmable elements: output buffer, input buffer, OE multiplexer and bus
maintenance circuitry. Figure 8 details the I/O cell.
9
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Figure 8. I/O Cell
GOE 0
GOE 1
GOE 2
GOE 3
From ORP
VCC
VCCO
VCCO
*
*
*
From ORP
To Macrocell
To GRP
*Global fuses
Each output supports a variety of output standards dependent on the V
supplied to its I/O bank. Outputs can
CCO
also be configured for open drain operation. Each input can be programmed to support a variety of standards, inde-
pendent of the V
supplied to its I/O bank. The I/O standards supported are:
CCO
• LVTTL
• LVCMOS 1.8
• LVCMOS 3.3
• LVCMOS 2.5
• 3.3V PCI Compatible
All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, Pull-up Resistor or Pull-down
Resistor. A fourth option is to provide none of these. The selection is done on a global basis. The default in both
hardware and software is such that when the device is erased or if the user does not specify, the input structure is
configured to be a Pull-up Resistor.
Each LA-ispMACH 4000V/Z automotive device I/O has an individually programmable output slew rate control bit.
Each output can be individually configured for fast slew or slow slew. The typical edge rate difference between fast
and slow slew setting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will intro-
duce fewer reflections, less noise and keep ground bounce to a minimum. For designs with short traces or well ter-
minated lines, the fast slew rate can be used to achieve the highest speed.
Global OE Generation
Most LA-ispMACH 4000V/Z automotive family devices have a 4-bit wide Global OE Bus, except the LA-ispMACH
4032V and LA-ispMACH4032Z devices that have a 2-bit wide Global OE Bus. This bus is derived from a 4-bit inter-
nal global OE PT bus and two dual purpose I/O or GOE pins. Each signal that drives the bus can optionally be
inverted.
Each GLB has a block-level OE PT that connects to all bits of the Global OE PT bus with four fuses. Hence, for a
128-macrocell device (with 16 blocks), each line of the bus is driven from 8 OE product terms. Figures 9 and 10
show a graphical representation of the global OE generation.
10
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Figure 9. Global OE Generation for All Devices Except LA-ispMACH 4032V/Z
Internal Global OE
Global OE
PT Bus
(4 lines)
4-Bit
Global OE Bus
Shared PTOE
(Block 0)
Shared PTOE
(Block n)
Global
Fuses
GOE (0:3)
to I/O cells
Fuse connection
Hard wired
Figure 10. Global OE Generation for LA-ispMACH 4032V/Z
Internal Global OE
PT Bus
4-Bit
Global OE Bus
Global OE
(2 lines)
Shared PTOE
(Block 0)
Shared PTOE
(Block 1)
Global
Fuses
GOE (3:0)
to I/O cells
Fuse connection
Hard wired
Zero Power/Low Power and Power Management
The LA-ispMACH 4000V/Z automotive family is designed with high speed low power design techniques to offer
both high speed and low power. With an advanced E2 low power cell and non sense-amplifier design approach (full
CMOS logic approach), the LA-ispMACH 4000V/Z automotive family offers SuperFAST pin-to-pin speeds, while
simultaneously delivering low standby power without needing any “turbo bits” or other power management
schemes associated with a traditional sense-amplifier approach.
11
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
The zero power LA-ispMACH 4000Z is based on the 1.8V ispMACH 4000C family. With innovative circuit design
changes, the LA-ispMACH 4000Z family is able to achieve the industry’s “lowest static power”.
IEEE 1149.1-Compliant Boundary Scan Testability
All LA-ispMACH 4000V/Z automotive devices have boundary scan cells and are compliant to the IEEE 1149.1
standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan
path that can access all critical logic notes. Internal registers are linked internally, allowing test data to be shifted in
and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition,
these devices can be linked into a board-level serial scan path for more board-level testing. The test access port
operates with an LVCMOS interface that corresponds to the power supply voltage.
I/O Quick Configuration
To facilitate the most efficient board test, the physical nature of the I/O cells must be set before running any continu-
ity tests. As these tests are fast, by nature, the overhead and time that is required for configuration of the I/Os’
physical nature should be minimal so that board test time is minimized. The LA-ispMACH 4000V/Z automotive fam-
ily of devices allows this by offering the user the ability to quickly configure the physical nature of the I/O cells. This
quick configuration takes milliseconds to complete, whereas it takes seconds for the entire device to be pro-
grammed. Lattice's ispVM™ System programming software can either perform the quick configuration through the
PC parallel port, or can generate the ATE or test vectors necessary for a third-party test system.
IEEE 1532-Compliant In-System Programming
Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inven-
tory levels, higher quality and the ability to make in-field modifications. The LA-ispMACH 4000V/Z automotive
devices provide In-System Programming (ISP™) capability through the Boundary Scan Test Access Port. This
capability has been implemented in a manner that ensures that the port remains complaint to the IEEE 1149.1
standard. By using IEEE 1149.1 as the communication interface through which ISP is achieved, users get the ben-
efit of a standard, well-defined interface. All LA-ispMACH 4000V/Z automotive devices are also compliant with the
IEEE 1532 standard.
The LA-ispMACH 4000V/Z automotive devices can be programmed across the commercial temperature and volt-
age range. The PC-based Lattice software facilitates in-system programming of LA-ispMACH 4000V/Z automotive
devices. The software takes the JEDEC file output produced by the design implementation software, along with
information about the scan chain, and creates a set of vectors used to drive the scan chain. The software can use
these vectors to drive a scan chain via the parallel port of a PC. Alternatively, the software can output files in for-
mats understood by common automated test equipment. This equipment can then be used to program LA-
ispMACH 4000V/Z automotive devices during the testing of a circuit board.
User Electronic Signature
The User Electronic Signature (UES) allows the designer to include identification bits or serial numbers inside the
device, stored in E2CMOS memory.The LA-ispMACH 4000V/Z automotive device contains 32 UES bits that can be
configured by the user to store unique data such as ID codes, revision numbers or inventory control codes.
Security Bit
A programmable security bit is provided on the LA-ispMACH 4000V/Z automotive devices as a deterrent to unau-
thorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the pro-
grammed pattern by a device programmer, securing proprietary designs from competitors. Programming and
verification are also defeated by the security bit. The bit can only be reset by erasing the entire device.
Hot Socketing
The LA-ispMACH 4000V/Z automotive devices are well-suited for applications that require hot socketing capability.
Hot socketing a device requires that the device, during power-up and down, can tolerate active signals on the I/Os
12
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
and inputs without being damaged. Additionally, it requires that the effects of I/O pin loading be minimal on active
signals. The LA-ispMACH 4000V/Z automotive devices provide this capability for input voltages in the range 0V to
3.0V.
Density Migration
The LA-ispMACH 4000V/Z automotive family has been designed to ensure that different density devices in the
same package have the same pin-out. Furthermore, the architecture ensures a high success rate when performing
design migration from lower density parts to higher density parts. In many cases, it is possible to shift a lower utili-
zation design targeted for a high density device to a lower density device. However, the exact details of the final
resource utilization will impact the likely success in each case.
AEC-Q100 Tested and Qualified
The Automotive Electronics Council (AEC) consists of two committees: the Quality Systems Committee and the
Component Technical Committee. These committees are composed of representatives from sustaining and other
associate members. The AEC Component Technical Committee is the standardization body for establishing stan-
dards for reliable, high quality electronic components. In particular, the AEC-Q100 specification “Stress Test for
Qualification for Integrated Circuits” defines qualification and re-qualification requirements for electronic compo-
nents. Components meeting these specifications are suitable for use in the harsh automotive environment without
additional component-level qualification testing. Lattice's LA-ispMACH 4000V/Z and LA-MachXO devices com-
pleted and passed the requirements of the AEC-Q100 specification.
13
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Absolute Maximum Ratings1, 2, 3
LA-ispMACH 4000V (3.3V)
LA-ispMACH 4000Z (1.8V)
Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V . . . . . . . . . . . . . . . . -0.5 to 2.5V
CC
Output Supply Voltage (V
) . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . . . . . . . . -0.5 to 4.5V
CCO
Input or I/O Tristate Voltage Applied4, 5 . . . . . . . . . . . . . . . . . -0.5 to 5.5V . . . . . . . . . . . . . . . . -0.5 to 5.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C . . . . . . . . . . . . . . . -65 to 150°C
Junction Temperature (T ) with Power Applied . . . . . . . . . . -55 to 150°C . . . . . . . . . . . . . . . -55 to 150°C
j
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied.
2. Compliance with Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Undershoot of -2V and overshoot of (V (MAX) + 2V), up to a total pin voltage of 6.0V, is permitted for a duration of < 20ns.
IH
5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed.
Recommended Operating Conditions
Symbol
Parameter
Min.
3.0
Max.
3.6
Units
LA-ispMACH 4000V Supply Voltage
LA-ispMACH 4000Z Supply Voltage
V
V
V
C
V
1.7
1.61
1.9
CC
LA-ispMACH 4000Z, Extended Functional Voltage Operations
Ambient Temperature (Automotive)
1.9
T
-40
125
A
1. Devices operating at 1.6V can expect performance degradation up to 35%.
Erase Reprogram Specifications
Parameter
Min.
Max.
Units
Erase/Reprogram Cycle
1,000
—
Cycles
Note: Valid over commercial temperature range.
Hot Socketing Characteristics1,2,3
Symbol
Parameter
Condition
Min.
—
Typ.
30
Max.
150
Units
µA
0 ≤ V ≤ 3.0V, Tj = 105°C
IN
I
Input or I/O Leakage Current
DK
0 ≤ V ≤ 3.0V, Tj = 130°C
—
30
200
µA
IN
1. Insensitive to sequence of V or V
However, assumes monotonic rise/fall rates for V and V
provided (V - V
) ≤ 3.6V.
CCO
CC
CCO.
CC
CCO,
IN
2. 0 < V < V (MAX), 0 < V
< V (MAX).
CC
CC
CCO
CCO
3. I is additive to I , I or I . Device defaults to pull-up until fuse circuitry is active.
DK
PU PD
BH
14
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
I/O Recommended Operating Conditions
V
(V)1
CCO
Standard
Min.
3.0
Max.
3.6
LVTTL
LVCMOS 3.3
Extended LVCMOS 3.32
LVCMOS 2.5
LVCMOS 1.8
PCI 3.3
3.0
3.6
2.7
3.6
2.3
2.7
1.65
3.0
1.95
3.6
1. Typical values for V
are the average of the min. and max. values.
CCO
2. LA-ispMACH 4000Z only.
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
Input Leakage Current
(LA-ispMACH 4000Z)
1, 4
I , I
0 ≤ V < V
—
—
0.5
1
µA
IL IH
IN
CCO
3.6V < V ≤ 5.5V, T = 105°C
IN
CCO
j
—
—
—
—
—
20
50
µA
µA
µA
µA
µA
3.0V ≤ V
≤ 3.6V
Input High Leakage Current
(LA-ispMACH 4000V)
3.6V < V ≤ 5.5V, T = 130°C
1, 2
IN
CCO
j
I
—
IH
3.0V ≤ V
≤ 3.6V
Input High Leakage Current
(LA-ispMACH 4000Z)
V
< V ≤ 5.5V
—
10
CCO
IN
I/O Weak Pull-up Resistor Current
(LA-ispMACH 4000V)
0 ≤ V ≤ 0.7V
-30
-30
-200
-150
IN
CCO
CCO
I
PU
I/O Weak Pull-up Resistor Current
(LA-ispMACH 4000Z)
0 ≤ V ≤ 0.7V
IN
I
I
I
I
I
I/O Weak Pull-down Resistor Current V (MAX) ≤ V ≤ V (MIN)
30
30
-30
—
—
—
—
—
—
—
150
—
µA
µA
µA
µA
µA
V
PD
IL
IN
IH
Bus Hold Low Sustaining Current
Bus Hold High Sustaining Current
Bus Hold Low Overdrive Current
Bus Hold High Overdrive Current
Bus Hold Trip Points
V
V
= V (MAX)
IL
BHLS
BHHS
BHLO
BHHO
IN
IN
= 0.7 V
—
CCO
0V ≤ V ≤ V
150
-150
IN
BHT
V
≤ V ≤ V
CCO
—
BHT
IN
V
—
V
* 0.35
V
* 0.65
CCO
BHT
CCO
V
V
V
V
V
V
= 3.3V, 2.5V, 1.8V
—
—
—
—
—
—
—
—
—
—
—
—
CCO
C
C
C
I/O Capacitance3
8
6
6
pf
pf
pf
1
2
3
= 1.8V, V = 0 to V (MAX)
CC
IO
IH
= 3.3V, 2.5V, 1.8V
CCO
Clock Capacitance3
Global Input Capacitance3
= 1.8V, V = 0 to V (MAX)
CC
IO
IH
= 3.3V, 2.5V, 1.8V
CCO
= 1.8V, V = 0 to V (MAX)
CC
IO
IH
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not
measured with the output driver active. Bus maintenance circuits are disabled.
2. 5V tolerant inputs and I/O should only be placed in banks where 3.0V ≤ V
≤ 3.6V.
CCO
3. T = 25°C, f = 1.0MHz.
A
4. I excursions of up to 1.5µA maximum per pin above the spec limit may be observed for certain voltage conditions on no more than 10% of
IH
the device’s I/O pins.
15
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Supply Current, LA-ispMACH 4000V
Over Recommended Operating Conditions
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
LA-ispMACH 4032V
Operating Power Supply Current
Standby Power Supply Current
Vcc = 3.3V
—
—
11.8
11.3
—
—
mA
mA
ICC
Vcc = 3.3V
LA-ispMACH 4064V
Operating Power Supply Current
Standby Power Supply Current
LA-ispMACH 4128V
Operating Power Supply Current
Standby Power Supply Current
Vcc = 3.3V
Vcc = 3.3V
—
—
12
—
—
mA
mA
ICC
11.5
Vcc = 3.3V
Vcc = 3.3V
—
—
12
—
—
mA
mA
ICC
11.5
16
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Supply Current, LA-ispMACH 4000Z
Over Recommended Operating Conditions
Symbol
Parameter
Condition
Min. Typ. Max. Units
LA-ispMACH 4032Z
Vcc = 1.8V, T = 25°C
—
—
—
—
—
—
—
—
50
58
60
70
10
13
15
22
—
—
—
—
—
20
25
µA
µA
µA
µA
µA
µA
µA
µA
A
Vcc = 1.9V, T = 70°C
A
ICC1, 2, 3, 5
Operating Power Supply Current
Standby Power Supply Current
Vcc = 1.9V, T = 85°C
A
Vcc = 1.9V, T = 125°C
A
Vcc = 1.8V, T = 25°C
A
Vcc = 1.9V, T = 70°C
A
ICC4, 5
Vcc = 1.9V, T = 85°C
A
Vcc = 1.9V, T = 125°C
A
LA-ispMACH 4064Z
Vcc = 1.8V, T = 25°C
—
—
—
—
—
—
—
—
80
89
92
109
11
15
18
37
—
—
—
—
—
25
35
µA
µA
µA
µA
µA
µA
µA
µA
A
Vcc = 1.9V, T = 70°C
A
ICC1, 2, 3, 5
Operating Power Supply Current
Vcc = 1.9V, T = 85°C
A
Vcc = 1.9V, T = 125°C
A
Vcc = 1.8V, T = 25°C
A
Vcc = 1.9V, T = 70°C
A
ICC4, 5
Standby Power Supply Current
Vcc = 1.9V, T = 85°C
A
Vcc = 1.9V, T = 125°C
A
LA-ispMACH 4128Z
Vcc = 1.8V, T = 25°C
—
—
—
—
—
—
—
—
168
190
195
212
12
—
—
—
—
—
35
50
—
µA
µA
µA
µA
µA
µA
µA
µA
A
Vcc = 1.9V, T = 70°C
A
ICC1, 2, 3, 5
Operating Power Supply Current
Vcc = 1.9V, T = 85°C
A
Vcc = 1.9V, T = 125°C
A
Vcc = 1.8V, T = 25°C
A
Vcc = 1.9V, T = 70°C
16
A
ICC4, 5
Standby Power Supply Current
Vcc = 1.9V, T = 85°C
19
A
Vcc = 1.9V, T = 125°C
42
A
1. T = 25°C, frequency = 1.0 MHz.
A
2. Device configured with 16-bit counters.
3. I varies with specific device configuration and operating frequency.
CC
4. V
= 3.6V, V = 0V or V
bus maintenance turned off. V above V
will add transient current above the specified standby I
.
CC
CCO
IN
CCO,
IN
CCO
5. Includes V
current without output loading.
CCO
17
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
I/O DC Electrical Characteristics
Over Recommended Operating Conditions
V
V
1
1
IL
IH
V
V
I
I
OH
OL
OH
OL
Standard
LVTTL
Min (V)
Max (V)
Min (V)
Max (V) Max (V)
Min (V)
(mA) (mA)
0.40
V
V
V
V
V
V
V
V
V
V
- 0.40
8.0
0.1
8.0
0.1
8.0
0.1
2.0
0.1
2.0
0.1
1.5
1.5
-4.0
-0.1
-4.0
-0.1
-4.0
-0.1
-2.0
-0.1
-2.0
-0.1
-0.5
-0.5
CCO
CCO
CCO
CCO
CCO
CCO
CCO
CCO
CCO
CCO
-0.3
0.80
0.80
0.70
0.63
2.0
5.5
0.20
- 0.20
- 0.40
- 0.20
- 0.40
- 0.20
- 0.45
- 0.20
- 0.45
- 0.20
0.40
LVCMOS 3.3
LVCMOS 2.5
-0.3
-0.3
-0.3
-0.3
2.0
5.5
0.20
0.40
1.70
1.17
3.6
0.20
0.40
LVCMOS 1.8
(4000V)
3.6
0.20
0.40
LVCMOS 1.8
(4000Z)
0.35 * V
1.08
0.65 * V
1.5
3.6
CC
CC
0.20
PCI 3.3 (4000V)
PCI 3.3 (4000Z)
-0.3
-0.3
5.5
5.5
0.1 V
0.1 V
0.9 V
0.9 V
CCO
CCO
0.3 * 3.3 * (V / 1.8) 0.5 * 3.3 * (V / 1.8)
CC
CC
CCO
CCO
1. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of
the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND
connections or between the last GND in a bank and the end of a bank.
3.3V VCCO
2.5V VCCO
70
60
50
40
30
20
100
80
60
40
20
0
IOL
IOH
IOL
IOH
10
0
0
0.5
1.0
1.5
2.0
2.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
VO Output Voltage (V)
VO Output Voltage (V)
1.8V VCCO
60
50
IOL
IOH
40
30
20
10
0
0
0.5
1.0
1.5
2.0
VO Output Voltage (V)
18
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4000V/Z External Switching Characteristics
Over Recommended Operating Conditions
LA-ispMACH 4000V LA-ispMACH 4000Z
-75 -75
Parameter
Description1, 2, 3
Min.
Max.
Min.
Max.
Units
t
5-PT bypass combinatorial propagation delay
—
7.5
—
7.5
ns
PD
20-PT combinatorial propagation delay through macro-
cell
t
t
t
—
8.0
—
—
8.0
—
ns
ns
ns
PD_MC
S
GLB register setup time before clock
4.5
4.7
4.5
4.7
GLB register setup time before clock with T-type regis-
ter
—
—
ST
GLB register setup time before clock, input register
path
t
1.7
—
1.4
—
ns
SIR
t
t
t
t
GLB register setup time before clock with zero hold
GLB register hold time after clock
2.7
0.0
0.0
1.0
—
—
—
—
2.7
0.0
0.0
1.3
—
—
—
—
ns
ns
ns
ns
SIRZ
H
GLB register hold time after clock with T-type register
GLB register hold time after clock, input register path
HT
HIR
GLB register hold time after clock, input register path
with zero hold
t
0.0
—
0.0
—
ns
HIRZ
t
t
t
GLB register clock-to-output delay
External reset pin to output delay
External reset pulse duration
—
—
4.5
9.0
—
—
—
4.5
9.0
—
ns
ns
ns
CO
R
4.0
4.0
RW
Input to output local product term output enable/dis-
able
t
t
—
—
9.0
—
—
9.0
ns
ns
PTOE/DIS
Input to output global product term output enable/dis-
able
10.3
10.5
GPTOE/DIS
t
t
Global OE input to output enable/disable
Global clock width, high or low
—
7.0
—
—
7.0
—
ns
ns
GOE/DIS
3.3
3.3
CW
Global gate width low (for low transparent) or high (for
high transparent)
t
3.3
—
3.3
—
ns
GW
t
f
f
Input register clock width, high or low
Clock frequency with internal feedback
3.3
168
111
—
—
—
3.3
168
111
—
—
—
ns
WIR
4
MHz
MAX
(Ext.) Clock frequency with external feedback, [1/ (t + t )]
MHz
MAX
S
CO
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.
2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
Timing v.3.2
19
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Timing Model
The task of determining the timing through the LA-ispMACH 4000V/Z automotive family, like any CPLD, is relatively
simple. The timing model provided in Figure 11 shows the specific delay paths. Once the implementation of a given
function is determined either conceptually or from the software report file, the delay path of the function can easily
be determined from the timing model. The Lattice design tools report the timing delays based on the same timing
model for a particular design. Note that the internal timing parameters are given for reference only, and are not
tested. The external timing parameters are tested and guaranteed for every device. For more information on the
timing model and usage, please refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage
Guidelines.
Figure 11. LA-ispMACH 4000V/Z Automotive Timing Model
Routing/GLB Delays
From
Feedback
tPDb
tPDi
Feedback
Out
tFBK
tROUTE
tBLA
tMCELL
tEXP
tIN
tBUF
tIOO
tEN
DATA
IN
tORP
tIOI
Q
tINREG
tINDIO
tDIS
tGCLK_IN
tIOI
In/Out
Delays
SCLK
tPTCLK
tBCLK
C.E.
S/R
tPTSR
tBSR
Register/Latch
Delays
MC Reg.
tGPTOE
tPTOE
Control
Delays
tGOE
tIOI
OE
In/Out
Delays
Note: Italicized items are optional delay adders.
20
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4000V/Z Internal Timing Parameters
Over Recommended Operating Conditions
LA-ispMACH 4000V LA-ispMACH 4000Z
-75 -75
Parameter
Description
Input Buffer Delay
Min.
Max.
Min.
Max.
Units
In/Out Delays
t
t
t
t
t
t
—
—
—
—
—
—
1.50
6.04
2.28
1.50
0.96
0.96
—
—
—
—
—
—
1.80
4.30
2.15
1.30
2.70
2.70
ns
ns
ns
ns
ns
ns
IN
Global OE Pin Delay
GOE
GCLK_IN
BUF
EN
Global Clock Input Buffer Delay
Delay through Output Buffer
Output Enable Time
Output Disable Time
DIS
Routing/GLB Delays
t
t
t
t
t
t
Delay through GRP
—
—
—
—
—
—
2.26
1.45
0.96
0.00
2.24
1.24
—
—
—
—
—
—
2.50
1.00
1.00
0.05
1.90
1.00
ns
ns
ns
ns
ns
ns
ROUTE
MCELL
INREG
FBK
Macrocell Delay
Input Buffer to Macrocell Register Delay
Internal Feedback Delay
5-PT Bypass Propagation Delay
Macrocell Propagation Delay
PDb
PDi
Register/Latch Delays
t
t
t
t
t
t
t
t
D-Register Setup Time (Global Clock)
D-Register Setup Time (Product Term Clock)
T-Register Setup Time (Global Clock)
T-Register Setup Time (Product Term Clock)
D-Register Hold Time
1.57
1.32
1.77
1.32
2.93
2.93
1.57
1.45
—
—
—
—
—
—
—
—
1.35
2.45
1.55
2.75
3.15
3.15
0.75
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
S
S_PT
ST
ST_PT
H
T-Register Hold Time
HT
D-Input Register Setup Time (Global Clock)
SIR
D-Input Register Setup Time (Product Term
Clock)
SIR_PT
1.45
1.95
1.18
—
—
—
t
t
D-Input Register Hold Time (Global Clock)
1.18
1.18
—
—
ns
ns
HIR
D-Input Register Hold Time (Product Term
Clock)
HIR_PT
t
t
t
t
t
t
t
t
Register Clock to Output/Feedback MUX Time
Clock Enable Setup Time
—
0.67
—
—
1.05
—
ns
ns
ns
ns
ns
ns
ns
ns
COi
2.25
1.88
1.57
1.32
1.17
—
2.00
0.00
1.65
2.15
1.17
—
CES
CEH
SL
Clock Enable Hold Time
—
—
Latch Setup Time (Global Clock)
Latch Setup Time (Product Term Clock)
Latch Hold Time
—
—
—
—
SL_PT
HL
—
—
Latch Gate to Output/Feedback MUX Time
0.33
0.25
0.33
GOi
PDLi
Propagation Delay through Transparent Latch to
Output/Feedback MUX
—
—
0.25
t
Asynchronous Reset or Set to Output/Feedback
MUX Delay
0.28
1.67
—
—
ns
ns
SRi
—
—
0.28
1.67
t
Asynchronous Reset or Set Recovery Time
SRR
Control Delays
t
t
GLB PT Clock Delay
—
—
1.12
0.87
—
—
1.25
1.25
ns
ns
BCLK
Macrocell PT Clock Delay
PTCLK
21
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4000V/Z Internal Timing Parameters (Cont.)
Over Recommended Operating Conditions
LA-ispMACH 4000V LA-ispMACH 4000Z
-75 -75
Parameter
Description
GLB PT Set/Reset Delay
Min.
—
Max.
1.83
3.41
5.58
4.28
Min.
—
Max.
1.83
2.72
3.50
2.00
Units
ns
t
t
t
t
BSR
Macrocell PT Set/Reset Delay
Global PT OE Delay
—
—
ns
PTSR
—
—
ns
GPTOE
PTOE
Macrocell PT OE Delay
—
—
ns
Timing v.3.2
Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details.
22
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4000V/Z Timing Adders1
LA-ispMACH 4000V LA-ispMACH 4000Z
-75 -75
Adder Type
Base Parameter
Description
Input register delay
Min.
Max.
Min.
Max.
Units
Optional Delay Adders
t
t
t
t
t
t
—
—
—
—
1.00
0.33
0.05
0.05
—
—
—
—
1.30
0.50
0.40
0.05
ns
ns
ns
ns
INDIO
INREG
Product term expander delay
Output routing pool delay
EXP
MCELL
—
ORP
BLA
t
Additional block loading adder
ROUTE
t
Input Adjusters
IOI
LVTTL_in
LVCMOS33_in t , t
t , t
, t
Using LVTTL standard
—
—
—
—
—
0.60
0.60
0.60
0.00
0.60
—
—
—
—
—
0.60
0.60
0.60
0.00
0.60
ns
ns
ns
ns
ns
IN GCLK_IN GOE
, t
Using LVCMOS 3.3 standard
Using LVCMOS 2.5 standard
Using LVCMOS 1.8 standard
Using PCI compatible input
IN GCLK_IN GOE
LVCMOS25_in t , t
, t
IN GCLK_IN GOE
LVCMOS18_in t , t
, t
IN GCLK_IN GOE
PCI_in
t , t
, t
IN GCLK_IN GOE
t
Output Adjusters
IOO
LVTTL_out
t
, t , t
Output configured as TTL buffer
Output configured as 3.3V buffer
Output configured as 2.5V buffer
Output configured as 1.8V buffer
—
—
—
—
0.20
0.20
0.10
0.00
—
—
—
—
0.20
0.20
0.10
0.00
ns
ns
ns
ns
BUF EN DIS
LVCMOS33_out t
LVCMOS25_out t
LVCMOS18_out t
, t , t
BUF EN DIS
, t , t
BUF EN DIS
, t , t
BUF EN DIS
Output configured as PCI
compatible buffer
PCI_out
t
, t , t
—
—
0.20
1.00
—
—
0.20
1.00
ns
BUF EN DIS
Output configured for slow slew
rate
Slow Slew
t
, t
ns
BUF EN
Note: Open drain timing is the same as corresponding LVCMOS timing.
Timing v.3.2
1. Refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders.
23
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Boundary Scan Waveforms and Timing Specifications
Symbol
Parameter
Min.
40
20
20
8
Max.
—
Units
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
TCK [BSCAN test] clock cycle
BTCP
TCK [BSCAN test] pulse width high
—
ns
BTCH
BTCL
TCK [BSCAN test] pulse width low
—
ns
TCK [BSCAN test] setup time
—
ns
BTSU
BTH
TCK [BSCAN test] hold time
10
50
—
—
—
8
—
ns
TCK [BSCAN test] rise and fall time
—
mV/ns
ns
BRF
TAP controller falling edge of clock to valid output
TAP controller falling edge of clock to data output disable
TAP controller falling edge of clock to data output enable
BSCAN test Capture register setup time
10
10
10
—
BTCO
BTOZ
ns
ns
BTVO
BTCPSU
BTCPH
BTUCO
BTUOZ
BTUOV
ns
BSCAN test Capture register hold time
10
—
—
—
—
ns
BSCAN test Update reg, falling edge of clock to valid output
BSCAN test Update reg, falling edge of clock to output disable
BSCAN test Update reg, falling edge of clock to output enable
25
25
25
ns
ns
ns
24
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Power Consumption
LA-ispMACH 4000V
LA-ispMACH 4000Z
Typical I
vs. Frequency
Typical I
vs. Frequency
(Preliminary Information)
CC
CC
100
80
60
40
20
0
150
100
4128V
4064V
50
4128Z
4064Z
4032V
4032Z
0
0
0
50
100
150
200
250
300
50
100
150
200
250
300
350
400
Frequency (MHz)
Frequency (MHz)
Note: The devices are configured with the maximum number
Note: The devices are configured with the maximum number
of 16-bit counters, typical current at 3.3V, 2.5V, 25°C.
of 16-bit counters, typical current at 1.8V, 25°C.
Power Estimation Coefficients1
Device
A
B
LA-ispMACH 4032V
LA-ispMACH 4064V
LA-ispMACH 4128V
LA-ispMACH 4032Z
LA-ispMACH 4064Z
LA-ispMACH 4128Z
11.3
11.5
0.010
0.010
0.011
0.010
0.010
0.010
11.5
0.010
0.011
0.012
1. For further information about the use of these coefficients, refer to Technical Note
TN1005, Power Estimation in ispMACH 4000V/B/C/Z Devices.
25
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Switching Test Conditions
Figure 12 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 9.
Figure 12. Output Test Load, LVTTL and LVCMOS Standards
V
CCO
R
1
2
Test
Point
DUT
R
C
L
0213A/ispm4k
Table 9. Test Fixture Required Components
1
Test Condition
R
R
C
Timing Ref.
V
CCO
1
2
L
LVCMOS 3.3 = 1.5V
LVCMOS 3.3 = 3.0V
LVCMOS I/O, (L -> H, H -> L)
106Ω 106Ω
35pF
LVCMOS 2.5 = V
LVCMOS 1.8 = V
1.5V
/2
/2
LVCMOS 2.5 = 2.3V
CCO
CCO
LVCMOS 1.8 = 1.65V
LVCMOS I/O (Z -> H)
LVCMOS I/O (Z -> L)
LVCMOS I/O (H -> Z)
LVCMOS I/O (L -> Z)
∞
106Ω
∞
35pF
35pF
5pF
3.0V
3.0V
3.0V
3.0V
106Ω
∞
1.5V
106Ω
∞
V
V
- 0.3
OH
OL
106Ω
5pF
+ 0.3
1. C includes test fixtures and probe capacitance.
L
26
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Signal Descriptions
Signal Names
Description
TMS
Input – This pin is the IEEE 1149.1 Test Mode Select input, which is used to control
the state machine
TCK
Input – This pin is the IEEE 1149.1 Test Clock input pin, used to clock through the
state machine
TDI
Input – This pin is the IEEE 1149.1 Test Data In pin, used to load data
Output – This pin is the IEEE 1149.1 Test Data Out pin used to shift data out
TDO
GOE0/IO, GOE1/IO
These pins are configured to be either Global Output Enable Input or as general I/O
pins
GND
NC
Ground
Not Connected
V
The power supply pins for the logic core and JTAG port
These pins are configured to be either CLK input or as an input
The power supply pins for each I/O bank
CC
CLK0/I, CLK1/I, CLK2/I, CLK3/I
, V
V
CCO0 CCO1
Input/Output1 – These are the general purpose I/O used by the logic array. y is GLB
reference (alpha) and z is macrocell reference (numeric). z: 0-15
LA-ispMACH 4032V/Z
LA-ispMACH 4064V/Z
LA-ispMACH 4128V/Z
y: A-B
y: A-D
y: A-H
yzz
1. In some packages, certain I/Os are only available for use as inputs. See the signal connections table for details.
LA-ispMACH 4000V ORP Reference Table
4032V
4064V
4128V
Number of I/Os
301
2
32
2
302
4
32
4
64
4
64
8
923
96
8
Number of GLBs
8
Number of I/Os /GLB
Reference ORP Table
16
16
8
8
16
8
12
12
16 I/Os / GLB
8 I/Os / GLB
16 I/Os / GLB 8 I/Os /GLB
12 I/Os / GLB
1. 32-macrocell device, 44 TQFP: 2 GLBs have 15 out of 16 I/Os bonded out.
2. 64-macrocells device, 44 TQFP: 2 GLBs have 7 out of 8 I/Os bonded out.
3. 128-macrocell device, 128 TQFP: 4 GLBs have 11 out of 12 I/Os
LA-ispMACH 4000Z ORP Reference Table
4032Z
4064Z
4128Z
Number of I/Os
32
2
32
4
64
4
64
8
Number of GLBs
Number of I/Os / GLB
16
8
16
8
16 I/Os /
GLB
8 I/Os /
GLB
16 I/Os /
GLB
8 I/Os /
GLB
Reference ORP Table
27
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4000V/Z Power Supply and NC Connections1
Signal
44 TQFP2
48 TQFP2
100 TQFP2
128 TQFP2
144 TQFP2
36, 57, 108, 129
3, 19, 34, 47, 136
VCC
11, 33
12, 36
25, 40, 75, 90
32, 51, 96, 115
VCCO0
VCCO (Bank 0)
6
6
13, 33, 95
3, 17, 30, 41, 122
VCCO1
VCCO (Bank 1)
64, 75, 91, 106, 119
28
30
45, 63, 83
58, 67, 81, 94, 105
1, 33, 65, 97
GND
12, 34
5
13, 37
5
1, 26, 51, 76
7, 18, 32, 96
1, 37, 73, 109
10, 186, 27, 46, 127,
137
GND (Bank 0)
10, 24, 40, 113, 123
GND (Bank 1)
NC
55, 65, 82, 906, 99,
118
27
29
46, 57, 68, 82
None
49, 59, 74, 88, 104
None
None
None
17, 20, 38, 45, 72,
89, 92, 110, 117,
144
1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with
the bank shown.
2. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise.
28
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4032V and 4064V Logic Signal Connections: 44-Pin TQFP
LA-ispMACH 4032V
LA-ispMACH 4064V
Pin Number
Bank Number
GLB/MC/Pad
ORP
-
GLB/MC/Pad
ORP
-
1
-
TDI
TDI
2
0
0
0
0
0
0
0
0
-
A5
A^5
A^6
A^7
-
A10
A^5
A^6
A^7
-
3
A6
A12
4
A7
A14
5
GND (Bank 0)
GND (Bank 0)
6
VCCO (Bank 0)
-
VCCO (Bank 0)
-
7
A8
A9
A^8
A^9
A^10
-
B0
B2
B^0
B^1
B^2
-
8
9
A10
B4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
TCK
TCK
-
VCC
GND
A12
-
VCC
GND
B8
-
-
-
-
0
0
0
0
1
1
1
1
1
1
-
A^12
A^13
A^14
A^15
-
B^4
B^5
B^6
B^7
-
A13
B10
A14
B12
A15
B14
CLK2/I
B0
CLK2/I
C0
B^0
B^1
B^2
B^3
B^4
-
C^0
C^1
C^2
C^3
C^4
-
B1
C2
B2
C4
B3
C6
B4
C8
TMS
B5
TMS
C10
1
1
1
1
1
1
1
1
-
B^5
B^6
B^7
-
C^5
C^6
C^7
-
B6
C12
B7
C14
GND (Bank 1)
VCCO (Bank 1)
B8
GND (Bank 1)
VCCO (Bank 1)
D0
-
-
B^8
B^9
B^10
-
D^0
D^1
D^2
-
B9
D2
B10
D4
TDO
VCC
GND
B12
TDO
VCC
GND
D8
-
-
-
-
-
-
1
1
1
1
0
0
0
0
B^12
B^13
B^14
B^15
-
D^4
D^5
D^6
D^7
-
B13
D10
B14
D12
B15/GOE1
CLK0/I
A0/GOE0
A1
D14/GOE1
CLK0/I
A0/GOE0
A2
A^0
A^1
A^2
A^0
A^1
A^2
A2
A4
29
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4032V and 4064V Logic Signal Connections: 44-Pin TQFP
LA-ispMACH 4032V
LA-ispMACH 4064V
Pin Number
Bank Number
GLB/MC/Pad
ORP
A^3
A^4
GLB/MC/Pad
ORP
A^3
A^4
43
44
0
0
A3
A4
A6
A8
LA-ispMACH 4032V/Z and 4064V/Z Logic Signal Connections: 48-Pin TQFP
LA-ispMACH 4032V/Z
LA-ispMACH 4064V/Z
Pin Number
Bank Number
GLB/MC/Pad ORP
GLB/MC/Pad ORP
1
-
TDI
-
A^5
A^6
A^7
-
TDI
-
2
0
0
0
0
0
0
0
0
0
-
A5
A10
A^5
A^6
A^7
-
3
A6
A12
4
A7
A14
5
GND (Bank 0)
GND (Bank 0)
6
VCCO (Bank 0)
-
VCCO (Bank 0)
-
7
A8
A^8
A^9
A^10
A^11
-
B0
B^0
B^1
B^2
B^3
-
8
A9
B2
9
A10
B4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
A11
B6
TCK
TCK
-
VCC
-
VCC
GND
B8
-
-
GND
-
-
0
0
0
0
0
1
1
1
1
1
1
-
A12
A^12
A^13
A^14
A^15
-
B^4
B^5
B^6
B^7
-
A13
B10
A14
B12
A15
B14
CLK1/I
CLK1/I
CLK2/I
C0
CLK2/I
-
-
B0
B^0
B^1
B^2
B^3
B^4
-
C^0
C^1
C^2
C^3
C^4
-
B1
C2
B2
C4
B3
C6
B4
C8
TMS
TMS
C10
1
1
1
1
1
1
1
1
1
-
B5
B^5
B^6
B^7
-
C^5
C^6
C^7
-
B6
C12
B7
C14
GND (Bank 1)
GND (Bank 1)
VCCO (Bank 1)
D0
VCCO (Bank 1)
-
-
B8
B9
B^8
B^9
B^10
B^11
-
D^0
D^1
D^2
D^3
-
D2
B10
B11
TDO
D4
D6
TDO
30
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4032V/Z and 4064V/Z Logic Signal Connections: 48-Pin TQFP
LA-ispMACH 4032V/Z
LA-ispMACH 4064V/Z
Pin Number
Bank Number
GLB/MC/Pad ORP
GLB/MC/Pad ORP
36
37
38
39
40
41
42
43
44
45
46
47
48
-
VCC
GND
B12
-
VCC
GND
D8
-
-
-
-
1
1
1
1
1
0
0
0
0
0
0
B^12
B^13
B^14
B^15
-
D^4
D^5
D^6
D^7
-
B13
D10
B14
D12
B15/GOE1
CLK3/I
CLK0/I
A0/GOE0
A1
D14/GOE1
CLK3/I
CLK0/I
A0/GOE0
A2
-
-
A^0
A^1
A^2
A^3
A^4
A^0
A^1
A^2
A^3
A^4
A2
A4
A3
A6
A4
A8
LA-ispMACH 4064V/Z and 4128V/Z Logic Signal Connections: 100-Pin TQFP
LA-ispMACH 4064V/Z
LA-ispMACH 4128V/Z
Pin Number
Bank Number
GLB/MC/Pad ORP
GLB/MC/Pad ORP
1
2
-
GND
-
GND
-
-
TDI
-
TDI
-
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
A8
A^8
A^9
A^10
A^11
-
B0
B^0
B^1
B^2
B^3
-
4
A9
B2
5
A10
B4
6
A11
B6
7
GND (Bank 0)
GND (Bank 0)
8
A12
A^12
A^13
A^14
A^15
-
B8
B^4
B^5
B^6
B^7
-
9
A13
B10
10
11
12*
13
14
15
16
17
18
19
20
21
22
23*
24
A14
B12
A15
B13
I
I
VCCO (Bank 0)
-
VCCO (Bank 0)
-
B15
B^15
B^14
B^13
B^12
-
C14
C^7
C^6
C^5
C^4
-
B14
C12
B13
C10
B12
C8
GND (Bank 0)
GND (Bank 0)
B11
B10
B9
B^11
B^10
B^9
B^8
-
C6
C5
C4
C2
I
C^3
C^2
C^1
C^0
-
B8
I
TCK
-
TCK
-
31
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4064V/Z and 4128V/Z Logic Signal Connections: 100-Pin TQFP
LA-ispMACH 4064V/Z
LA-ispMACH 4128V/Z
Pin Number
25
Bank Number
GLB/MC/Pad ORP
GLB/MC/Pad ORP
-
VCC
-
-
VCC
-
26
-
GND
GND
-
27*
28
0
0
0
0
0
0
0
0
0
0
0
0
1
-
I
-
I
-
B7
B^7
B^6
B^5
B^4
-
D13
D^7
D^6
D^5
D^4
-
29
B6
D12
30
B5
D10
31
B4
D8
32
GND (Bank 0)
GND (Bank 0)
33
VCCO (Bank 0)
-
VCCO (Bank 0)
-
34
B3
B^3
B^2
B^1
B^0
-
D6
D^3
D^2
D^1
D^0
-
35
B2
D4
36
B1
D2
37
B0
D0
38
CLK1/I
CLK1/I
39
CLK2/I
-
CLK2/I
-
40
VCC
-
VCC
-
41
1
1
1
1
1
1
1
1
1
1
-
C0
C^0
C^1
C^2
C^3
-
E0
E^0
E^1
E^2
E^3
-
42
C1
E2
43
C2
E4
44
C3
E6
45
VCCO (Bank 1)
VCCO (Bank 1)
46
GND (Bank 1)
-
GND (Bank 1)
-
47
C4
C^4
C^5
C^6
C^7
-
E8
E^4
E^5
E^6
E^7
-
48
C5
E10
49
C6
E12
50
C7
E14
51
GND
GND
52
-
TMS
-
TMS
-
53
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C8
C^8
C^9
C^10
C^11
-
F0
F^0
F^1
F^2
F^3
-
54
C9
F2
55
C10
F4
56
C11
F6
57
GND (Bank 1)
GND (Bank 1)
58
C12
C^12
C^13
C^14
C^15
-
F8
F^4
F^5
F^6
F^7
-
59
C13
F10
60
C14
F12
61
C15
F13
62*
63
I
VCCO (Bank 1)
D15
I
-
VCCO (Bank 1)
-
64
D^15
D^14
D^13
D^12
G14
G12
G10
G8
G^7
G^6
G^5
G^4
65
D14
66
D13
67
D12
32
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4064V/Z and 4128V/Z Logic Signal Connections: 100-Pin TQFP
LA-ispMACH 4064V/Z
LA-ispMACH 4128V/Z
Pin Number
Bank Number
GLB/MC/Pad ORP
GLB/MC/Pad ORP
68
1
1
1
1
1
1
-
GND (Bank 1)
-
D^11
D^10
D^9
D^8
-
GND (Bank 1)
-
69
D11
G6
G^3
G^2
G^1
G^0
-
70
D10
G5
71
D9
G4
72
D8
G2
73*
I
I
74
TDO
-
TDO
-
75
-
VCC
-
VCC
-
76
-
GND
-
GND
-
77*
1
1
1
1
1
1
1
1
1
1
1
1
0
-
I
-
I
-
78
D7
D^7
D^6
D^5
D^4
-
H13
H^7
H^6
H^5
H^4
-
79
D6
H12
80
D5
H10
81
D4
H8
82
GND (Bank 1)
GND (Bank 1)
83
VCCO (Bank 1)
-
VCCO (Bank 1)
-
84
D3
D^3
D^2
D^1
D^0
-
H6
H4
H^3
H^2
H^1
H^0
-
85
D2
86
D1
H2
87
D0/GOE1
H0/GOE1
CLK3/I
CLK0/I
VCC
88
CLK3/I
89
CLK0/I
-
-
90
VCC
-
-
91
0
0
0
0
0
0
0
0
0
0
A0/GOE0
A^0
A^1
A^2
A^3
-
A0/GOE0
A2
A^0
A^1
A^2
A^3
-
92
A1
93
A2
A4
94
A3
A6
95
VCCO (Bank 0)
VCCO (Bank 0)
GND (Bank 0)
A8
96
GND (Bank 0)
-
-
97
A4
A5
A6
A7
A^4
A^5
A^6
A^7
A^4
A^5
A^6
A^7
98
A10
99
100
A12
A14
*This pin is input only.
33
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4128V Logic Signal Connections: 128-Pin TQFP
LA-ispMACH 4128V
Pin Number
Bank Number
GLB/MC/Pad
ORP
-
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GND
2
TDI
-
3
VCCO (Bank 0)
-
4
B0
B^0
B^1
B^2
B^3
B^4
B^5
-
5
B1
6
B2
7
B4
8
B5
9
B6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
GND (Bank 0)
B8
B^6
B^7
B^8
B^9
B^10
B^11
-
B9
B10
B12
B13
B14
VCCO (Bank 0)
C14
C^11
C^10
C^9
C^8
C^7
C^6
-
C13
C12
C10
C9
C8
GND (Bank 0)
C6
C^5
C^4
C^3
C^2
C^0
-
C5
C4
C2
C0
VCCO (Bank 0)
TCK
-
VCC
-
GND
-
D14
D^11
D^10
D^9
D^8
D^7
D^6
-
D13
D12
D10
D9
D8
GND (Bank 0)
VCCO (Bank 0)
D6
-
D^5
34
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4128V Logic Signal Connections: 128-Pin TQFP (Cont.)
LA-ispMACH 4128V
Pin Number
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
Bank Number
GLB/MC/Pad
ORP
D^4
D^3
D^2
D^1
D^0
-
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D5
D4
D2
D1
D0
CLK1/I
GND (Bank 1)
-
CLK2/I
-
VCC
-
E0
E^0
E^1
E^2
E^3
E^4
E^5
-
E1
E2
E4
E5
E6
VCCO (Bank 1)
GND (Bank 1)
-
E8
E^6
E^7
E^8
E^9
E^11
-
E9
E10
E12
E14
GND
TMS
-
VCCO (Bank 1)
-
F0
F^0
F^1
F^2
F^3
F^4
F^5
-
F1
F2
F4
F5
F6
GND (Bank 1)
F8
F^6
F^7
F^8
F^9
F^10
F^11
-
F9
F10
F12
F13
F14
VCCO (Bank 1)
G14
G^11
G^10
G^9
G^8
G13
G12
G10
35
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4128V Logic Signal Connections: 128-Pin TQFP (Cont.)
LA-ispMACH 4128V
Pin Number
86
Bank Number
GLB/MC/Pad
ORP
G^7
G^6
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
G9
87
G8
88
GND (Bank 1)
89
G6
G^5
G^4
G^3
G^2
G^0
-
90
G5
91
G4
92
G2
93
G0
94
VCCO (Bank 1)
95
TDO
-
96
VCC
-
97
GND
-
98
H14
H^11
H^10
H^9
H^8
H^7
H^6
-
99
H13
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
H12
H10
H9
H8
GND (Bank 1)
VCCO (Bank 1)
-
H6
H^5
H^4
H^3
H^2
H^1
H^0
-
H5
H4
H2
H1
H0/GOE1
CLK3/I
GND (Bank 0)
-
CLK0/I
-
VCC
-
A0/GOE0
A^0
A^1
A^2
A^3
A^4
A^5
-
A1
A2
A4
A5
A6
VCCO (Bank 0)
GND (Bank 0)
-
A8
A9
A^6
A^7
A^8
A^9
A^11
A10
A12
A14
36
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4128V Logic Signal Connections: 144-Pin TQFP
LA-ispMACH 4128V
Pin Number
Bank Number
GLB/MC/Pad
ORP
-
1
-
GND
2
-
TDI
-
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
VCCO (Bank 0)
-
4
B0
B^0
B^1
B^2
B^3
B^4
B^5
-
5
B1
6
B2
7
B4
8
B5
9
B6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
GND (Bank 0)
B8
B^6
B^7
B^8
B^9
B^10
B^11
-
B9
B10
B12
B13
B14
NC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
GND (Bank 0)1
-
VCCO (Bank 0)
-
NC
-
C14
C^11
C^10
C^9
C^8
C^7
C^6
-
C13
C12
C10
C9
C8
GND (Bank 0)
C6
C^5
C^4
C^3
C^2
C^1
C^0
-
C5
C4
C2
C1
C0
VCCO (Bank 0)
TCK
-
-
VCC
-
-
GND
NC
-
0
0
0
0
0
-
D14
D^11
D^10
D^9
D^8
D13
D12
D10
37
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4128V Logic Signal Connections: 144-Pin TQFP (Cont.)
LA-ispMACH 4128V
Pin Number
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
Bank Number
GLB/MC/Pad
ORP
D^7
D^6
-
0
0
0
0
0
0
0
0
0
0
0
0
1
1
-
D9
D8
NC
GND (Bank 0)
-
VCCO (Bank 0)
-
D6
D^5
D^4
D^3
D^2
D^1
D^0
-
D5
D4
D2
D1
D0
CLK1/I
GND (Bank 1)
-
CLK2/I
-
VCC
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
E0
E^0
E^1
E^2
E^3
E^4
E^5
-
E1
E2
E4
E5
E6
VCCO (Bank 1)
GND (Bank 1)
-
E8
E^6
E^7
E^8
E^9
E^10
E^11
-
E9
E10
E12
E13
E14
NC
GND
-
-
TMS
-
1
1
1
1
1
1
1
1
1
1
1
VCCO (Bank 1)
-
F0
F^0
F^1
F^2
F^3
F^4
F^5
-
F1
F2
F4
F5
F6
GND (Bank 1)
F8
F9
F^6
F^7
F^8
F10
38
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4128V Logic Signal Connections: 144-Pin TQFP (Cont.)
LA-ispMACH 4128V
Pin Number
86
Bank Number
GLB/MC/Pad
ORP
F^9
F^10
F^11
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
F12
87
F13
88
F14
89
NC
90
GND (Bank 1)1
-
91
VCCO (Bank 1)
-
92
NC
-
93
G14
G^11
G^10
G^9
G^8
G^7
G^6
-
94
G13
95
G12
96
G10
97
G9
98
G8
99
GND (Bank 1)
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
G6
G^5
G^4
G^3
G^2
G^1
G^0
-
G5
G4
G2
G1
G0
VCCO (Bank 1)
TDO
-
-
VCC
-
-
GND
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
NC
-
H14
H^11
H^10
H^9
H^8
H^7
H^6
-
H13
H12
H10
H9
H8
NC
GND (Bank 1)
VCCO (Bank 1)
H6
-
-
H^5
H^4
H^3
H^2
H^1
H^0
-
H5
H4
H2
H1
H0/GOE1
CLK3/I
GND (Bank 0)
CLK0/I
-
-
39
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
LA-ispMACH 4128V Logic Signal Connections: 144-Pin TQFP (Cont.)
LA-ispMACH 4128V
Pin Number
129
Bank Number
GLB/MC/Pad
ORP
-
-
VCC
130
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A0/GOE0
A^0
A^1
A^2
A^3
A^4
A^5
-
131
A1
132
A2
133
A4
134
A5
135
A6
136
VCCO (Bank 0)
137
GND (Bank 0)
-
138
A8
A^6
A^7
A^8
A^9
A^10
A^11
-
139
A9
140
A10
A12
A13
A14
NC2
141
142
143
144
1. For device migration considerations, these NC pins are GND pins for I/O banks in LA-ispMACH 4128V devices.
40
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Part Number Description
LA XXXX XX – XX XX XXX X
Device Family
Operating Temperature Range
E = Automotive
Device Number
Pin/Ball Count
4032 = 32 Macrocells
4064 = 64 Macrocells
4128 = 128 Macrocells
44 (1.0mm thickness)
48 (1.0mm thickness)
100
128
144
Power
Blank = Low Power
Z = Zero Power
Package
Supply Voltage
V = 3.3V
TN = Lead-free TQFP
C = 1.8V
Speed
75 = 7.5ns
Ordering Information
Pin/Ball
Device
Part Number
LA4032V-75TN48E
LA4032V-75TN44E
LA4064V-75TN100E
LA4064V-75TN48E
LA4064V-75TN44E
LA4128V-75TN144E
LA4128V-75TN128E
LA4128V-75TN100E
LA4032ZC-75TN48E
LA4064ZC-75TN100E
LA4064ZC-75TN48E
LA4128ZC-75TN100E
Macrocells Voltage
t
Package
Count
I/O
32
30
64
32
30
96
92
64
32
64
32
64
Grade
PD
32
32
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.8
1.8
1.8
1.8
7.5 Lead-free TQFP
7.5 Lead-free TQFP
7.5 Lead-free TQFP
7.5 Lead-free TQFP
7.5 Lead-free TQFP
7.5 Lead-free TQFP
7.5 Lead-free TQFP
7.5 Lead-free TQFP
7.5 Lead-free TQFP
7.5 Lead-free TQFP
7.5 Lead-free TQFP
7.5 Lead-free TQFP
48
E
E
E
E
E
E
E
E
E
E
E
E
LA4032V
44
64
100
48
LA4064V
LA4128V
64
64
44
128
128
128
32
144
128
100
48
LA4032Z
LA4064Z
LA4128Z
64
100
48
64
128
100
Automotive Disclaimer
Products are not designed, intended or warranted to be fail-safe and are not designed, intended or warranted for
use in applications related to the deployment of airbags. Further, products are not intended to be used, designed or
warranted for use in applications that affect the control of the vehicle unless there is a fail-safe or redundancy fea-
ture and also a warning signal to the operator of the vehicle upon failure. Use of products in such applications is
fully at the risk of the customer, subject to applicable laws and regulations governing limitations on product liability.
For Further Information
In addition to this data sheet, the following technical notes may be helpful when designing with the LA-ispMACH
4000V/Z automotive family:
• ispMACH 4000 Timing Model Design and Usage Guidelines (TN1004)
• ispMACH 4000V/B/C/Z Power Consumption (TN1005)
41
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
Revision History
Date
Version
01.0
Change Summary
April 2006
Initial release.
October 2006
March 2007
02.0
Added LA-ispMACH 4000Z support information throughout.
Updated ispMACH 4000 Introduction section.
02.1
Updated Signal Descriptions table.
September 2007
July 2008
02.2
02.3
DC Electrical Characteristics table, removed duplicate specifications.
Lowered the maximum supply current at 85°C to match the commercial product values.
Added automotive disclaimer.
42
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