LA-ISPPAC-POWR1014A-01TN48E [LATTICE]
Power Supply Management Circuit, Adjustable, 10 Channel, CMOS, PQFP48, LEAD FREE, TQFP-48;
| 型号： | LA-ISPPAC-POWR1014A-01TN48E |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | Power Supply Management Circuit, Adjustable, 10 Channel, CMOS, PQFP48, LEAD FREE, TQFP-48 |
| 文件： | 总51页 (文件大小：4501K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
LA-ispPAC-POWR1014/A
Automotive Family
In-System Programmable Power Supply Supervisor,
Reset Generator and Sequencing Controller
September 2013
Data Sheet DS1018
Features
Application Block Diagram
Monitor and Control Multiple Power Supplies
• Simultaneously monitors up to 10 power
supplies
Primary
Supply
3.3V
Primary
Supply
• Provides up to 14 output control signals
• Programmable digital and analog circuitry
2.5V
1.8V
Primary
Supply
AEC-Q100 Tested and Qualified
Embedded PLD for Sequence Control
• 24-macrocell CPLD implements both state
machines and combinatorial logic functions
Primary
Supply
POL#1
Embedded Programmable Timers
• Four independent timers
Primary
• 32µs to 2 second intervals for timing sequences
Supply
POL#N
Analog Input Monitoring
• 10 independent analog monitor inputs
• Two programmable threshold comparators per
analog input
Other Control/Supervisory
Signals
12 Digital
Outputs
2 MOSFET
Drivers
• Hardware window comparison
• 10-bit ADC for I2C monitoring (LA-ispPAC-
POWR1014A only)
CPLD
24 Macrocells
53 Inputs
ADC*
2
I C
Bus*
High-Voltage FET Drivers
• Power supply ramp up/down control
• Programmable current and voltage output
• Independently configurable for FET control or
digital output
2-Wire (I2C/SMBus™ Compatible) Interface
• Comparator status monitor
2
4 Digital
Inputs
I C
4 Timers
CPU
Interface
LA-ispPAC-POWR1014A
*LA-ispPAC-POWR1014A only.
Description
Lattice’s Power Manager II LA-ispPAC-POWR1014/A is
a general-purpose power-supply monitor and sequence
controller, incorporating both in-system programmable
logic and in-system programmable analog functions
implemented in non-volatile E2CMOS® technology. The
LA-ispPAC-POWR1014/A device provides 10 indepen-
dent analog input channels to monitor up to 10 power
supply test points. Each of these input channels has
two independently programmable comparators to sup-
port both high/low and in-bounds/out-of-bounds (win-
dow-compare) monitor functions. Four general-purpose
digital inputs are also provided for miscellaneous con-
trol functions.
• ADC readout
• Direct control of inputs and outputs
• Power sequence control
• Only available with LA-ispPAC-POWR1014A
3.3V Operation, Wide Supply Range 2.8V to
3.96V
• Automotive temperature range: -40°C to +105°C
• 48-pin TQFP package, lead-free option
Multi-Function JTAG Interface
• In-system programming
• Access to all I2C registers
• Direct input control
The LA-ispPAC-POWR1014/A provides 14 open-drain
digital outputs that can be used for controlling DC-DC
converters, low-drop-out regulators (LDOs) and opto-
couplers, as well as for supervisory and general-pur-
pose logic interface functions. Two of these outputs
(HVOUT1-HVOUT2) may be configured as high-voltage
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
www.latticesemi.com
5-1
DS1018_01.3
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
MOSFET drivers. In high-voltage mode these outputs can provide up to 8V for driving the gates of n-channel MOS-
FETs so that they can be used as high-side power switches controlling the supplies with a programmable ramp rate
for both ramp up and ramp down.
The LA-ispPAC-POWR1014/A incorporates a 24-macrocell CPLD that can be used to implement complex state
machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. The status
of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as
inputs by the CPLD array, and all digital outputs may be controlled by the CPLD. Four independently programmable
timers can create delays and time-outs ranging from 32µs to 2 seconds. The CPLD is programmed using Logi-
Builder™, an easy-to-learn language integrated into the PAC-Designer® software. Control sequences are written to
monitor the status of any of the analog input channel comparators or the digital inputs.
The on-chip 10-bit A/D converter is used to monitor the V
LA-ispPAC-POWR1014A device.
voltage through the I2C bus or JTAG interface of the
MON
The I2C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the V
MON
inputs, read back the status of each of the V
comparator and PLD outputs, control logic signals IN2 to IN4 and
MON
control the output pins (LA-ispPAC-POWR1014A only). The JTAG interface can be used to read out all I2C registers
during manufacturing.
Figure 5-1. LA-ispPAC-POWR1014/A Block Diagram
MEASUREMENT
ADC*
CONTROL LOGIC*
VMON1
VMON2
VMON3
VMON4
VMON5
HVOUT1
HVOUT2
VMON6
VMON7
VMON8
VMON9
CPLD
VMON10
OUT3/(SMBA*)
OUT4
OUT5
24 MACROCELLS
53 INPUTS
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
IN1
IN2
IN3
IN4
CLOCK
OSCILLATOR
TIMERS
(4)
I2C
INTERFACE
JTAG LOGIC
*LA-ispPAC-POWR1014A only.
5-2
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Pin Descriptions
Number
Name
Pin Type
Voltage Range
VCCINP1, 2
VCCINP1, 3
VCCINP1, 3
VCCINP1, 3
-0.3V to 5.87V4
-0.3V to 5.87V4
-0.3V to 5.87V4
-0.3V to 5.87V4
-0.3V to 5.87V4
-0.3V to 5.87V4
-0.3V to 5.87V4
-0.3V to 5.87V4
-0.3V to 5.87V4
-0.3V to 5.87V4
Ground
Description
PLD Logic Input 1 Registered by MCLK
PLD Logic Input 2 Registered by MCLK
PLD Logic Input 3 Registered by MCLK
PLD Logic Input 4 Registered by MCLK
Voltage Monitor 1 Input
44
IN1
IN2
IN3
IN4
Digital Input
46
Digital Input
Digital Input
Digital Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Ground
47
48
25
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
VMON10
26
Voltage Monitor 2 Input
27
Voltage Monitor 3 Input
28
Voltage Monitor 4 Input
32
Voltage Monitor 5 Input
33
Voltage Monitor 6 Input
34
Voltage Monitor 7 Input
35
Voltage Monitor 8 Input
36
Voltage Monitor 9 Input
37
Voltage Monitor 10 Input
Digital Ground
7, 31 GNDD5
30
GNDA5
41, 23 VCCD6
Ground
Ground
Analog Ground
Power
2.8V to 3.96V
2.8V to 3.96V
2.25V to 5.5V
2.25V to 3.6V
Core VCC, Main Power Supply
Analog Power Supply
29
45
20
VCCA6
VCCINP
VCCJ
Power
Power
VCC for IN[1:4] Inputs
Power
VCC for JTAG Logic Interface Pins
Alternate Programming
Supply
Alternate E2 Programming Supply; use only when
the Device is Not Powered by VCCD and VCCA
24
APS10
3.0V to 3.6V
0V to 8V
Open Drain Output7
Current Source/Sink
Open Drain Output7
Current Source/Sink
Open-Drain Output 1
15
HVOUT1
12.5µA to 100µA Source
100µA to 3000µA Sink
High-voltage FET Gate Driver 1
Open-Drain Output 2
0V to 8V
14
13
HVOUT2
12.5µA to 100µA Source
100µA to 3000µA Sink
High-voltage FET Gate Driver 2
Open-Drain Output 3, (SMBUS Alert Active Low,
LA-ispPAC-POWR1014A only).
SMBA_OUT3 Open Drain Output7
0V to 5.5V
12
11
10
9
OUT4
Open Drain Output7
Open Drain Output7
Open Drain Output7
Open Drain Output7
Open Drain Output7
Open Drain Output7
Open Drain Output7
Open Drain Output7
Open Drain Output7
Open Drain Output7
Open Drain Output7
Digital I/O
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 3.96V
Open-Drain Output 4
OUT5
Open-Drain Output 5
OUT6
Open-Drain Output 6
OUT7
Open-Drain Output 7
8
OUT8
Open-Drain Output 8
6
OUT9
Open-Drain Output 9
5
OUT10
OUT11
OUT12
OUT13
OUT14
RESETb8
Open-Drain Output 10
Open-Drain Output 11
Open-Drain Output 12
Open-Drain Output 13
Open-Drain Output 14
Device Reset (Active Low) - Internal pull-up
4
3
2
1
40
250kHz PLD Clock Output (Tristate), CMOS
Output - Internal pull-up
42
PLDCLK
Digital Output
0V to 3.96V
5-3
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Pin Descriptions (Cont.)
Number
Name
Pin Type
Voltage Range
0V to 3.96V
Description
8MHz Clock I/O (Tristate), CMOS Drive - Internal
Pull-up
43
MCLK
Digital I/O
21
22
16
TDO
TCK
TMS
Digital Output
Digital Input
Digital Input
0V to 5.5V
0V to 5.5V
0V to 5.5V
JTAG Test Data Out
JTAG Test Clock Input
JTAG Test Mode Select - Internal Pull-up
JTAG Test Data In, TDISEL pin = 1 - Internal
Pull-up
18
TDI
Digital Input
0V to 5.5V
JTAG Test Data In (Alternate), TDISEL Pin = 0 -
Internal Pull-up
17
19
39
ATDI
Digital Input
Digital Input
Digital Input
0V to 5.5V
0V to 5.5V
0V to 5.5V
TDISEL
SCL9, 11
Select TDI/ATDI Input - Internal Pull-up
I2C Serial Clock Input (LA-ispPAC-POWR1014A
Only)
I2C Serial Data, Bi-directional Pin, Open Drain
(LA-ispPAC-POWR1014A Only)
38
SDA9, 11
Digital I/O
0V to 5.5V
1. [IN1...IN4] are inputs to the PLD. The thresholds for these pins are referenced by the voltage on VCCINP. Unused INx inputs should be tied
to GNDD.
2. IN1 pin can also be controlled through JTAG interface.
3. [IN2..IN4] can also be controlled through I2C/SMBus interface (LA-ispPAC-POWR1014A only).
4. The VMON inputs can be biased independently from VCCA. Unused VMON inputs should be tied to GNDD.
5. GNDA and GNDD pins must be connected together on the circuit board.
6. VCCD and VCCA pins must be connected together on the circuit board.
7. Open-drain outputs require an external pull-up resistor to a supply.
8. The RESETb pin should only be used for cascading two or more LA-ispPAC-POWR1014/A devices.
9. These pins should be connected to GNDD (LA-ispPAC-POWR1014 device only).
10. The APS pin MUST be left floating when VCCD and VCCA are powered.
11. SCL should be tied high and SDA is don’t care when I2C registers are accessed through the JTAG interface.
5-4
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Absolute Maximum Ratings
Absolute maximum ratings are shown in the table below. Stresses beyond those listed may cause permanent dam-
age to the device. Functional operation of the device at these or any other conditions beyond those indicated in the
recommended operating conditions of this specification is not implied.
Symbol
Parameter
Conditions
Min.
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
Max.
4.5
4.5
6
Units
V
VCCD
VCCA
Core supply
Analog supply
V
VCCINP
VCCJ
APS
Digital input supply (IN[1:4])
JTAG logic supply
Alternate E2 programming supply
Digital input voltage (all digital I/O pins)
VMON input voltage
V
6
V
4
V
VIN
6
V
VMON
6
V
HVOUT[1:2]
13.3
6
V
VTRI
Voltage applied to tri-stated pins
OUT[3:14]
V
ISINKMAXTOTAL
Maximum sink current on any output
Storage temperature
23
150
125
mA
oC
oC
TS
TA
-65
-65
Ambient temperature
Recommended Operating Conditions
Symbol
Parameter
Conditions
Min.
2.8
Max.
3.96
5.5
Units
V
CCD, VCCA
Core supply voltage at pin
V
V
V
VCCINP
VCCJ
Digital input supply for IN[1:4] at pin
JTAG logic supply voltage at pin
2.25
2.25
3.6
No connect
Must be left floating
VCCD and VCCA powered
V
APS
Alternate E2 programming supply at pin
VCCD and VCCA not powered
3.0
-0.3
-0.3
-0.3
3.6
5.5
5.9
5.5
V
V
V
V
VIN
Input voltage at digital input pins
Input voltage at VMON pins
VMON
OUT[3:14] pins
VOUT
Open-drain output voltage
HVOUT[1:2] pins in open-drain
mode
-0.3
-40
13.0
85
V
Ambient temperature during
programming
TAPROG
oC
1
TA
Ambient temperature
Junction temperature
Power applied
Power applied
-40
-40
105
110
oC
oC
TJ
1. Device functionality guaranteed up to 125°C.
Analog Specifications
Symbol
Parameter
Core and analog supply current
VCCINP supply current
Conditions
Min.
Typ.
Max.
20
5
Units
mA
1
ICC
ICCINP
ICCJ
mA
JTAG supply current
1
mA
ICCPROG Core and analog supply current
1. Includes currents on VCCD and VCCA supplies.
During programming cycle
20
mA
5-5
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Voltage Monitors
Symbol
Parameter
Input resistance
Input capacitance
Conditions
Min.
Typ.
65
Max.
Units
k
pF
V
RIN
CIN
55
75
8
V
MON Range
Programmable trip-point range
0.075
70
5.867
80
VZ Sense
Near-ground sense threshold
75
mV
%
-40<TA<105°C
-40<TA<125°C
0.3
1.1
V
MON Accuracy
Absolute accuracy of any trip-point1
1.2
%
Hysteresis of any trip-point (relative to
setting)
HYST
1
%
1. Guaranteed by characterization across VCCA range, operating temperature, process.
High Voltage FET Drivers
Symbol
Parameter
Conditions
8V setting
Min.
7.6
Typ.
8
Max.
8.4
Units
V
VPP
Gate driver output voltage
6V setting
5.7
6
6.3
12.5
25
Gate driver source current
IOUTSRC
Four settings in software
µA
µA
(HIGH state)
50
100
3000
100
250
500
FAST OFF mode
1500
Gate driver sink current
(LOW state)
IOUTSINK
Controlled ramp settings
5-6
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
ADC Characteristics1
Symbol
Parameter
Conditions
Time from I2C request
Min.
Typ.
Max.
Units
Bits
µs
ADC resolution
Conversion time
10
TCONVERT
VIN
100
2.048
5.92
Programmable attenuator = 1
Programmable attenuator = 3
Programmable attenuator = 1
Programmable attenuator = 3
Programmable attenuator = 3
0
0
V
Input range full scale
V
2
6
mV
mV
%
ADC Step Size LSB
Eattenuator
Error due to attenuator
+/- 0.1
1. LA-ispPAC-POWR1014A only.
2. Maximum voltage is limited by VMONX pin (theoretical maximum is 6.144V).
ADC Error Budget Across Entire Operating Temperature Range1
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Measurement Range 600 mV - 2.048V,
Attenuator =1
-10
+/-4
10
mV
Total Measurement Error at
Any Voltage2
TADC Error
Measurement Range Zero to 600mV,
Attenuator = 1
+/-12
mV
1. LA-ispPAC-POWR1014A only.
2. Total error, guaranteed by characterization, includes INL, DNL, Gain, Offset, and PSR specifications of the ADC.
Power-On Reset
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
TRST
Delay from VTH to start-up state
100
µs
Delay from RESETb HIGH to PLDCLK rising
edge
TSTART
TGOOD
TBRO
5
10
500
5
µs
Power-on reset to valid VMON comparator
output and AGOOD is true.
µs
µs
Minimum duration brown out required to trig-
ger RESETb
1
TPOR
VTL
VTH
VT
Delay from brown out to reset state.
11
µs
V
Threshold below which RESETb is LOW1
Threshold above which RESETb is HIGH1
Threshold above which RESETb is valid1
2.3
2.7
0.8
V
V
Capacitive load on RESETb for master/slave
operation
CL
200
pF
1. Corresponds to VCCA and VCCD supply voltages.
5-7
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Figure 5-2. LA-ispPAC-POWR1014/A Power-On Reset
V
TH
T
T
BRO
POR
V
TL
VCC
V
T
T
RST
RESETb
MCLK
Start Up
State
Reset
State
PLDCLK
AGOOD (Internal)
T
START
Analog Calibration
T
GOOD
5-8
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
AC/Transient Characteristics
Over Recommended Operating Conditions
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Voltage Monitors
Propagation delay input to
output glitch filter OFF
tPD16
16
64
µs
µs
Propagation delay input to
output glitch filter ON
tPD64
Oscillators
fCLK
Internal master clock
7.6
7.2
8
8.4
8.8
MHz
frequency (MCLK)
Externally applied master
clock (MCLK)
fCLKEXT
MHz
kHz
fPLDCLK
PLDCLK output frequency fCLK = 8MHz
250
Timers
Range of programmable
fCLK = 8MHz
Timeout Range
0.032
-6.67
1966
ms
timers (128 steps)
Spacing between available
adjacent timer intervals
Resolution
Accuracy
13
%
%
Timer accuracy
fCLK = 8MHz
-12.5
5-9
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Digital Specifications
Over Recommended Operating Conditions
Symbol
IIL,IIH
Parameter
Conditions
Min.
Typ.
Max.
Units
Input leakage, no pull-up/pull-down
+/-10
µA
HVOUT[1:2] in open
drain mode and pulled
up to 8V
IOH-HVOUT Output leakage current
Input pull-up current (TMS, TDI,
35
70
100
µA
µA
IPU
TDISEL, ATDI, MCLK, PLDCLK,
RESETb)
TDI, TMS, ATDI,
TDISEL, 3.3V supply
0.8
0.7
TDI, TMS, ATDI,
TDISEL, 2.5V supply
VIL
Voltage input, logic low1
Voltage input, logic high1
V
SCL, SDA
30% VCCD
IN[1:4]
30% VCCINP
TDI, TMS, ATDI,
TDISEL, 3.3V supply
2.0
1.7
TDI, TMS, ATDI,
TDISEL, 2.5V supply
VIH
V
V
SCL, SDA
IN[1:4]
70% VCCD
VCCD
VCCINP
0.8
70% VCCINP
HVOUT[1:2] (open drain mode),
OUT[3:14]
ISINK = 10mA
ISINK = 20mA
VOL
VOH
0.8
TDO, MCLK, PLDCLK, SDA
TDO, MCLK, PLDCLK
ISINK = 4mA
0.4
ISRC = 4mA
VCCD - 0.4
67
V
2
ISINKTOTAL All digital outputs
mA
1. IN[1:4] referenced to VCCINP; TDO, TDI, TMS, ATDI, TDISEL referenced to VCCJ; SCL, SDA referenced to VCCD.
2. Sum of maximum current sink from all digital outputs combined. Reliable operation is not guaranteed if this value is exceeded.
5-10
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
I2C Port Characteristics1
100KHz
400KHz
Symbol
Definition
Min.
Max.
1002
Min.
Max.
4002
Units
kHz
us
FI2C
I2C clock/data rate
After start
TSU;STA
THD;STA
TSU;DAT
TSU;STO
THD;DAT
TLOW
4.7
4
0.6
0.6
100
0.6
0.3
1.3
0.6
After start
us
Data setup
Stop setup
250
4
ns
us
Data hold; SCL= Vih_min = 2.1V
Clock low period
0.3
4.7
4
3.45
10
0.9
10
us
us
THIGH
TF
Clock high period
us
Fall time; 2.25V to 0.65V
300
1000
35
300
300
35
ns
TR
Rise time; 0.65V to 2.25V
ns
TTIMEOUT
TPOR
Detect clock low timeout
25
500
4.7
25
500
1.3
ms
ms
us
Device must be operational after power-on reset
Bus free time between stop and start condition
TBUF
1. Applies to LA-ispPAC-POWR1014A only.
2. If FI2C is less than 50kHz, then the ADC DONE status bit is not guaranteed to be set after a valid conversion request is completed. In this
case, waiting for the TCONVERT minimum time after a convert request is made is the only way to guarantee a valid conversion is ready for
readout. When FI2C is greater than 50kHz, ADC conversion complete is ensured by waiting for the DONE status bit.
5-11
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Timing for JTAG Operations
Symbol
tISPEN
Parameter
Program enable delay time
Program disable delay time
High voltage discharge time, program
High voltage discharge time, erase
Falling edge of TCK to TDO active
Falling edge of TCK to TDO disable
Setup time
Conditions
Min.
10
30
30
200
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
—
Units
µs
tISPDIS
tHVDIS
tHVDIS
tCEN
tCDIS
tSU1
—
µs
—
µs
—
µs
10
10
—
ns
—
ns
5
ns
tH
Hold time
10
20
20
—
—
ns
tCKH
tCKL
fMAX
tCO
tPWV
tPWP
TCK clock pulse width, high
TCK clock pulse width, low
Maximum TCK clock frequency
Falling edge of TCK to valid output
Verify pulse width
—
ns
—
ns
25
10
—
MHz
ns
—
30
20
µs
Programming pulse width
—
ms
Figure 5-3. Erase (User Erase or Erase All) Timing Diagram
VIH
TMS
VIL
tSU1
tSU1
tGKL
tSU1
tSU1
tSU1
tGKL
tSU1
tH
tH
tH
tH
tH
tH
tCKH
tCKH
tCKH
tCKH
tCKH
VIH
VIL
TCK
tSU2
Specified by the Data Sheet
Run-Test/Idle (Discharge)
Update-IR
Run-Test/Idle (Erase)
Select-DR Scan
State
Figure 5-4. Programming Timing Diagram
VIH
TMS
VIL
tSU1
tH
tSU1
tCKL
tH
tSU1
tH
tCKH
tSU1
tH
tSU1
tCKL
tH
tCKH
tCKH
tPWP
tCKH
VIH
TCK
VIL
Update-IR
State
Update-IR
Run-Test/Idle (Program)
Select-DR Scan
5-12
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Figure 5-5. Verify Timing Diagram
VIH
TMS
VIL
tSU1
tH
tSU1
tCKL
tH
tSU1
tH
tSU1
tH
tSU1
tCKL
tH
tCKH
tPWV
tCKH
tCKH
tCKH
VIH
VIL
TCK
Update-IR
State
Update-IR
Run-Test/Idle (Program)
Select-DR Scan
Figure 5-6. Discharge Timing Diagram
tHVDIS (Actual)
VIH
TMS
VIL
tSU1
tH
tSU1
tCKL
tH
tSU1
tH
tCKH
tSU1
tH
tSU1
tCKL
tH
tCKH
tSU1
tH
tCKH
tPWP
tCKH
tPWV
tCKH
VIH
VIL
Actual
TCK
tPWV
Specified by the Data Sheet
Run-Test/Idle (Verify)
State
Update-IR
Run-Test/Idle (Erase or Program)
Select-DR Scan
Theory of Operation
Analog Monitor Inputs
The LA-ispPAC-POWR1014/A provides 10 independently programmable voltage monitor input circuits as shown in
Figure 5-7. Two individually programmable trip-point comparators are connected to an analog monitoring input.
Each comparator reference has 372 programmable trip points over the range of 0.672V to 5.867V. Additionally, a
75mV ‘zero-detect’ threshold is selectable which allows the voltage monitors to determine if a monitored signal has
dropped to ground level. This feature is especially useful for determining if a power supply’s output has decayed to
a substantially inactive condition after it has been switched off.
5-13
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Figure 5-7. LA-ispPAC-POWR1014/A Voltage Monitors
ispPAC-POWR1014/A
To ADC
(POWR1014A only)
Comp A/Window
Select
Comp A
VMONxA
Logic
VMONx
+
–
Signal
Trip Point A
Trip Point B
Glitch
Filter
PLD
Array
VMONxB
Comp B
Logic
+
–
Signal
Glitch
Filter
Window Control
Analog Input
Filtering
VMONx Status
2
I C Interface/JTAG
Interface Unit
(LA-POWR1014A
only)
Figure 5-7 shows the functional block diagram of one of the 10 voltage monitor inputs - ‘x’ (where x = 1...10). Each
voltage monitor can be divided into three sections: Analog Input, Window Control, and Filtering.
The voltage input is monitored by two individually programmable trip-point comparators, shown as CompA and
CompB. Table 5-1 shows all trip points and the range to which any comparator’s threshold can be set.
Each comparator outputs a HIGH signal to the PLD array if the voltage at its positive terminal is greater than its pro-
grammed trip point setting, otherwise it outputs a LOW signal.
A hysteresis of approximately 1% of the setpoint is provided by the comparators to reduce false triggering as a
result of input noise. The hysteresis provided by the voltage monitor is a function of the input divider setting.
Table 5-3 lists the typical hysteresis versus voltage monitor trip-point.
AGOOD Logic Signal
All the VMON comparators auto-calibrate immediately after a power-on reset event. During this time, the digital
glitch filters are also initialized. This process completion is signalled by an internally generated logic signal:
AGOOD. All logic using the VMON comparator logic signals must wait for the AGOOD signal to become active.
Programmable Over-Voltage and Under-Voltage Thresholds
Figure 5-8 (a) shows the power supply ramp-up and ramp-down voltage waveforms. Because of hysteresis, the
comparator outputs change state at different thresholds depending on the direction of excursion of the monitored
power supply.
5-14
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Figure 5-8. (a) Power Supply Voltage Ramp-up and Ramp-down Waveform and the Resulting Comparator
Output, (b) Corresponding to Upper and Lower Trip Points
UTP
LTP
(a)
(b)
Comparator Logic Output
During power supply ramp-up the comparator output changes from logic 0 to 1 when the power supply voltage
crosses the upper trip point (UTP). During ramp down the comparator output changes from logic state 1 to 0 when
the power supply voltage crosses the lower trip point (LTP). To monitor for over voltage fault conditions, the UTP
should be used. To monitor under-voltage fault conditions, the LTP should be used.
Tables 1 and 2 show both the under-voltage and over-voltage trip points, which are automatically selected in soft-
ware depending on whether the user is monitoring for an over-voltage condition or an under-voltage condition.
5-15
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Table 5-1. Trip Point Table Used For Over-Voltage Detection
Coarse Range Setting
Fine
Range
Setting
1
2
3
4
5
6
7
8
9
10
11
12
1
0.806
0.802
0.797
0.793
0.789
0.785
0.781
0.776
0.772
0.768
0.764
0.760
0.755
0.751
0.747
0.743
0.739
0.734
0.730
0.726
0.722
0.718
0.713
0.709
0.705
0.701
0.697
0.692
0.688
0.684
0.680
0.960
0.955
0.950
0.945
0.940
0.935
0.930
0.925
0.920
0.915
0.910
0.905
0.900
0.895
0.890
0.885
0.880
0.875
0.870
0.865
0.860
0.855
0.850
0.845
0.840
0.835
0.830
0.825
0.820
0.815
0.810
1.143
1.137
1.131
1.125
1.119
1.113
1.107
1.101
1.095
1.089
1.083
1.077
1.071
1.065
1.059
1.053
1.047
1.041
1.035
1.029
1.024
1.018
1.012
1.006
1.000
0.994
0.988
0.982
0.976
0.970
0.964
1.360
1.353
1.346
1.338
1.331
1.324
1.317
1.310
1.303
1.296
1.289
1.282
1.275
1.268
1.261
1.254
1.246
1.239
1.232
1.225
1.218
1.211
1.204
1.197
1.190
1.183
1.176
1.169
1.161
1.154
1.147
1.612
1.603
1.595
1.586
1.578
1.570
1.561
1.553
1.544
1.536
1.528
1.519
1.511
1.502
1.494
1.486
1.477
1.469
1.460
1.452
1.444
1.435
1.427
1.418
1.410
1.402
1.393
1.385
1.377
1.368
—
1.923
1.913
1.903
1.893
1.883
1.873
1.863
1.853
1.843
1.833
1.823
1.813
1.803
1.793
1.783
1.773
1.763
1.753
1.743
1.733
1.723
1.713
1.703
1.693
1.683
1.673
1.663
1.653
1.643
1.633
1.623
2.290
2.278
2.266
2.254
2.242
2.230
2.219
2.207
2.195
2.183
2.171
2.159
2.147
2.135
2.123
2.111
2.099
2.087
2.075
2.063
2.052
2.040
2.028
2.016
2.004
1.992
1.980
1.968
1.956
1.944
1.932
2.719
2.705
2.691
2.677
2.663
2.649
2.634
2.620
2.606
2.592
2.578
2.564
2.550
2.535
2.521
2.507
2.493
2.479
2.465
2.450
2.436
2.422
2.408
2.394
2.380
2.365
2.351
2.337
2.323
2.309
2.295
3.223
3.206
3.190
3.173
3.156
3.139
3.122
3.106
3.089
3.072
3.055
3.038
3.022
3.005
2.988
2.971
2.954
2.938
2.921
2.904
2.887
2.871
2.854
2.837
2.820
2.803
2.787
2.770
2.753
2.736
—
3.839
3.819
3.799
3.779
3.759
3.739
3.719
3.699
3.679
3.659
3.639
3.619
3.599
3.579
3.559
3.539
3.519
3.499
3.479
3.459
3.439
3.419
3.399
3.379
3.359
3.339
3.319
3.299
3.279
3.259
3.239
4.926
4.900
4.875
4.849
4.823
4.798
4.772
4.746
4.721
4.695
4.669
4.644
4.618
4.592
4.567
4.541
4.515
4.490
4.464
4.438
4.413
4.387
4.361
4.336
4.310
4.284
4.259
4.233
4.207
4.182
4.156
5.867
5.836
5.806
5.775
5.745
5.714
5.683
5.653
5.622
5.592
5.561
5.531
5.500
5.470
5.439
5.408
5.378
5.347
5.317
5.286
5.256
5.225
5.195
5.164
5.133
5.103
5.072
5.042
5.011
4.981
4.950
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Low-V
Sense
75mV
5-16
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Table 5-2. Trip Point Table Used For Under-Voltage Detection
Fine
Range
Setting
1
2
3
4
5
6
7
8
9
10
11
12
1
0.797
0.793
0.789
0.785
0.781
0.776
0.772
0.768
0.764
0.760
0.755
0.751
0.747
0.743
0.739
0.734
0.730
0.726
0.722
0.718
0.713
0.709
0.705
0.701
0.697
0.692
0.688
0.684
0.680
0.676
0.672
0.950
0.945
0.940
0.935
0.930
0.925
0.920
0.915
0.910
0.905
0.900
0.895
0.890
0.885
0.880
0.875
0.870
0.865
0.860
0.855
0.850
0.845
0.840
0.835
0.830
0.825
0.820
0.815
0.810
0.805
0.800
1.131
1.125
1.119
1.113
1.107
1.101
1.095
1.089
1.083
1.077
1.071
1.065
1.059
1.053
1.047
1.041
1.035
1.029
1.024
1.018
1.012
1.006
1.000
0.994
0.988
0.982
0.976
0.970
0.964
0.958
0.952
1.346
1.338
1.331
1.324
1.317
1.310
1.303
1.296
1.289
1.282
1.275
1.268
1.261
1.254
1.246
1.239
1.232
1.225
1.218
1.211
1.204
1.197
1.190
1.183
1.176
1.169
1.161
1.154
1.147
1.140
1.133
1.595
1.586
1.578
1.570
1.561
1.553
1.544
1.536
1.528
1.519
1.511
1.502
1.494
1.486
1.477
1.469
1.460
1.452
1.444
1.435
1.427
1.418
1.410
1.402
1.393
1.385
1.377
1.368
1.360
1.352
-
1.903
1.893
1.883
1.873
1.863
1.853
1.843
1.833
1.823
1.813
1.803
1.793
1.783
1.773
1.763
1.753
1.743
1.733
1.723
1.713
1.703
1.693
1.683
1.673
1.663
1.653
1.643
1.633
1.623
1.613
1.603
2.266
2.254
2.242
2.230
2.219
2.207
2.195
2.183
2.171
2.159
2.147
2.135
2.123
2.111
2.099
2.087
2.075
2.063
2.052
2.040
2.028
2.016
2.004
1.992
1.980
1.968
1.956
1.944
1.932
1.920
1.908
2.691
2.677
2.663
2.649
2.634
2.620
2.606
2.592
2.578
2.564
2.550
2.535
2.521
2.507
2.493
2.479
2.465
2.450
2.436
2.422
2.408
2.394
2.380
2.365
2.351
2.337
2.323
2.309
2.295
2.281
2.267
3.190
3.173
3.156
3.139
3.122
3.106
3.089
3.072
3.055
3.038
3.022
3.005
2.988
2.971
2.954
2.938
2.921
2.904
2.887
2.871
2.854
2.837
2.820
2.803
2.787
2.770
2.753
2.736
2.719
2.702
-
3.799
3.779
3.759
3.739
3.719
3.699
3.679
3.659
3.639
3.619
3.599
3.579
3.559
3.539
3.519
3.499
3.479
3.459
3.439
3.419
3.399
3.379
3.359
3.339
3.319
3.299
3.279
3.259
3.239
3.219
3.199
4.875
4.849
4.823
4.798
4.772
4.746
4.721
4.695
4.669
4.644
4.618
4.592
4.567
4.541
4.515
4.490
4.464
4.438
4.413
4.387
4.361
4.336
4.310
4.284
4.259
4.233
4.207
4.182
4.156
4.130
4.105
5.806
5.775
5.745
5.714
5.683
5.653
5.622
5.592
5.561
5.531
5.500
5.470
5.439
5.408
5.378
5.347
5.317
5.286
5.256
5.225
5.195
5.164
5.133
5.103
5.072
5.042
5.011
4.981
4.950
4.919
4.889
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Low-V
Sense
75mV
5-17
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Table 5-3. Comparator Hysteresis vs. Trip-Point
Trip-point Range (V)
Low Limit High Limit
0.672 0.806
Hysteresis (mV)
8
0.800
0.952
1.133
1.346
1.603
1.908
2.267
2.691
3.199
4.105
4.889
0.960
1.143
1.360
1.612
1.923
2.290
2.719
3.223
3.839
4.926
5.867
10
12
14
17
20
24
28
34
40
51
61
75 mV
0 (Disabled)
The window control section of the voltage monitor circuit is an AND gate (with inputs: an inverted COMPA “ANDed”
with COMPB signal) and a multiplexer that supports the ability to develop a ‘window’ function without using any of
the PLD’s resources. Through the use of the multiplexer, voltage monitor’s ‘A’ output may be set to report either the
status of the ‘A’ comparator, or the window function of both comparator outputs. The voltage monitor’s ‘A’ output
indicates whether the input signal is between or outside the two comparator thresholds. Important: This windowing
function is only valid in cases where the threshold of the ‘A’ comparator is set to a value higher than that of the ‘B’
comparator. Table 5-4 shows the operation of window function logic.
Table 5-4. Voltage Monitor Windowing Logic
Window
Input Voltage
Comp A
Comp B
(B and Not A)
Comment
Outside window, low
Inside window
V
IN < Trip-point B < Trip-point A
0
0
1
0
1
1
0
1
0
Trip-point B < VIN < Trip-point A
Trip-point B < Trip-point A < VIN
Outside window, high
Note that when the ‘A’ output of the voltage monitor circuit is set to windowing mode, the ‘B’ output continues to
monitor the output of the ‘B’ comparator. This can be useful in that the ‘B’ output can be used to augment the win-
dowing function by determining if the input is above or below the windowing range.
The third section in the LA-ispPAC-POWR1014/A’s input voltage monitor is a digital filter. When enabled, the com-
parator output will be delayed by a filter time constant of 64 µs, and is especially useful for reducing the possibility
of false triggering from noise that may be present on the voltages being monitored. When the filter is disabled, the
comparator output will be delayed by 16µs. In both cases, enabled or disabled, the filters also provide synchroniza-
tion of the input signals to the PLD clock. This synchronous sampling feature effectively eliminates the possibility of
race conditions from occurring in any subsequent logic that is implemented in the LA-ispPAC-POWR1014/A’s inter-
nal PLD logic.
The comparator status can be read from the I2C interface or JTAG interface (LA-ispPAC-POWR1014A only). For
details on the I2C/JTAG interfaces, please refer to the I2C/SMBUS Interface, and Accessing I2C Registers Through
JTAG sections of this data sheet.
5-18
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
VMON Voltage Measurement with the On-chip Analog to Digital Converter
(ADC, LA-ispPAC-POWR1014A Only)
The LA-ispPAC-POWR1014A has an on-chip analog to digital converter that can be used for measuring the volt-
ages at the VMON inputs.
Figure 5-9. ADC Monitoring VMON1 to VMON10
VMON1
VMON2
VMON3
Programmable
Digital Multiplier
Programmable Analog
Attenuator
ADC
MUX
To I2C Readout Register
(LA-ispPAC-POWR1014A Only)
ADC
x3 / x1
÷3 / ÷1
10
12
VMON10
VDDA
Internal
VREF- 2.048V
VCCINP
4
1
5
From I2 C ADC MUX Register
(LA-ispPAC-POWR1014A Only)
Figure 5-9 shows the ADC circuit arrangement within the LA-ispPAC-POWR1014A device. The ADC can measure
all analog input voltages through the multiplexer, ADC MUX. The programmable attenuator between the ADC mux
and the ADC can be configured as divided-by-3 or divided-by-1 (no attenuation). The divided-by-3 setting is used to
measure voltages from 0V to 6V range and divided-by-1 setting is used to measure the voltages from 0V to 2V
range.
A microcontroller can place a request for any VMON voltage measurement at any time through the I2C bus (LA-isp-
PAC-POWR1014A only). Upon the receipt of an I2C command, the ADC will be connected to the I2C selected
VMON through the ADC MUX. The ADC output is then latched into the I2C readout registers.
Calculation
The algorithm to convert the ADC code to the corresponding voltage takes into consideration the attenuation bit
value. In other words, if the attenuation bit is set, then the 10-bit ADC result is automatically multiplied by 3 to cal-
culate the actual voltage at that VMON input. Thus, the I2C readout register is 12 bits instead of 10 bits. The follow-
ing formula can always be used to calculate the actual voltage from the ADC code.
Voltage at the VMONx Pins
VMON = I2C Readout Register (12 bits1, converted to decimal) * 2mV
1Note: ADC_VALUE_HIGH (8 bits), ADC_VALUE_LOW (4 bits) read from I2C/SMBUS interface (LA-ispPAC-POWR1014A only).
5-19
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
PLD Block
Figure 5-10 shows the LA-ispPAC-POWR1014/A PLD architecture, which is derived from the Lattice's ispMACH™
4000 CPLD. The PLD architecture allows the flexibility in designing various state machines and control functions
used for power supply management. The AND array has 53 inputs and generates 123 product terms. These 123
product terms are divided into three groups of 41 for each of the generic logic blocks, GLB1, GLB2, and GLB3.
Each GLB is made up of eight macrocells. In total, there are 24 macrocells in the LA-ispPAC-POWR1014/A device.
The output signals of the LA-ispPAC-POWR1014/A device are derived from GLBs as shown in Figure 5-10. GLB3
generates timer control.
Figure 5-10. LA-ispPAC-POWR1014/A PLD Architecture
Global Reset
(Resetb pin)
AGOOD
IN[1:4]
GLB1
Generic Logic Block
8 Macrocell
41 PT
HVOUT[1..2],
OUT[3..8]
41
MCLK
Input
Register
4
GLB2
Generic Logic Block
8 Macrocell
41 PT
AND Array
53 Inputs
123 PT
OUT[9..14]
VMON[1-10]
41
Input
Register
20
4
GLB3
Generic Logic Block
8 Macrocell
41 PT
Output
Feedback
41
24
Timer0
18
Timer1
Timer2
Timer3
IRP
Timer Clock
PLD Clock
Macrocell Architecture
The macrocell shown in Figure 5-11 is the heart of the PLD. The basic macrocell has five product terms that feed
the OR gate and the flip-flop. The flip-flop in each macrocell is independently configured. It can be programmed to
function as a D-Type or T-Type flip-flop. Combinatorial functions are realized by bypassing the flip-flop. The polarity
control and XOR gates provide additional flexibility for logic synthesis. The flip-flop’s clock is driven from the com-
mon PLD clock that is generated by dividing the 8 MHz master clock by 32. The macrocell also supports asynchro-
nous reset and preset functions, derived from either product terms, the global reset input, or the power-on reset
signal. The resources within the macrocells share routing and contain a product term allocation array. The product
term allocation array greatly expands the PLD’s ability to implement complex logical functions by allowing logic to
be shared between adjacent blocks and distributing the product terms to allow for wider decode functions. All the
digital inputs are registered by MCLK and the VMON comparator outputs are registered by the PLD Clock to syn-
chronize them to the PLD logic.
5-20
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Figure 5-11. LA-ispPAC-POWR1014/A Macrocell Block Diagram
Global Reset
Power On Reset
Global Polarity Fuse for
Init Product Term
Block Init Product Term
Product Term Allocation
PT4
PT3
PT2
PT1
PT0
R
P
To PLD Output
D/T
Q
Polarity
CLK
Clock
Macrocell flip-flop provides
D, T, or combinatorial
output with polarity
Clock and Timer Functions
Figure 5-12 shows a block diagram of the LA-ispPAC-POWR1014/A’s internal clock and timer systems. The master
clock operates at a fixed frequency of 8MHz, from which a fixed 250kHz PLD clock is derived.
Figure 5-12. Clock and Timer System
PLD Clock
Timer 0
Timer 1
SW0
Internal
To/From
PLD
Oscillator
8MHz
32
Timer 2
Timer 3
SW1
SW2
MCLK
PLDCLK
The internal oscillator runs at a fixed frequency of 8 MHz. This signal is used as a source for the PLD and timer
clocks. It is also used for clocking the comparator outputs and clocking the digital filters in the voltage monitor cir-
cuits and ADC. The LA-ispPAC-POWR1014/A can be programmed to operate in three modes: Master mode,
5-21
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Standalone mode and Slave mode. Table 5-5 summarizes the operating modes of LA-ispPAC-POWR1014/A.
Table 5-5. LA-ispPAC-POWR1014/A Operating Modes
Timer
Operating Mode
SW0
SW1
Condition
Comments
Standalone
Closed
Open When only one LA-ispPAC-POWR1014/A is used. MCLK pin tristated
When more than one LA-ispPAC-POWR1014/A is
Closed used in a board, one of them should be configured MCLK pin outputs 8MHz clock
to operate in this mode.
Master
Slave
Closed
Open
When more than one LA-ispPAC-POWR1014/As is
used in a board. Other than the master, the rest of
Closed
MCLK pin is input
the LA-ispPAC-POWR1014/As should be pro-
grammed as slaves.
A divide-by-32 prescaler divides the internal 8MHz oscillator (or external clock, if selected) down to 250kHz for the
PLD clock and for the programmable timers. This PLD clock may be made available on the PLDCLK pin by closing
SW2. Each of the four timers provides independent timeout intervals ranging from 32µs to 1.96 seconds in 128
steps.
Digital Outputs
The LA-ispPAC-POWR1014/A provides 14 digital outputs, HVOUT[1:2] and OUT[3:14]. Outputs OUT[3:14] are per-
manently configured as open drain to provide a high degree of flexibility when interfacing to logic signals, LEDs,
opto-couplers, and power supply control inputs. The HVOUT[1:2] pins can be configured as either high voltage FET
drivers or open drain outputs. Each of these outputs may be controlled either from the PLD or from the I2C bus (LA-
ispPAC-POWR1014A only). The determination whether a given output is under PLD or I2C control may be made on
a pin-by-pin basis (see Figure 5-13). For further details on controlling the outputs through I2C, please see the I2C/
SMBUS Interface section of this data sheet.
Figure 5-13. Digital Output Pin Configuration
Digital Control
from PLD
OUTx
Pin
Digital Control from I2C Register
(LA-ispPAC-POWR1014A only)
High-Voltage Outputs
In addition to being usable as digital open-drain outputs, the LA-ispPAC-POWR1014/A’s HVOUT1-HVOUT2 output
pins can be programmed to operate as high-voltage FET drivers. Figure 5-14 shows the details of the HVOUT gate
drivers. Each of these outputs may be controlled from the PLD, or with the LA-ispPAC-POWR1014A, from the I2C
bus/JTAG interface (see Figure 5-14). For further details on controlling the outputs through I2C, please see the I2C/
SMBUS Interface, and Accessing I2C Registers Through JTAG sections of this data sheet.
5-22
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Figure 5-14. Basic Function Diagram for an Output in High Voltage MOSFET Gate Driver Mode
Charge Pump
(6 to 8V)
I
SOURCE
(12.5 to 100 µA)
+
-
Input
Supply
HVOUTx
Pin
I
Load
SINK
(100 to 500 µA)
+Fast Turn-off
(3000µA)
Digital Control
from PLD
2
Digital Control from I C Register
(LA-ispPAC-POWR1014A Only)
Figure 5-14 shows the HVOUT circuitry when programmed as a FET driver. In this mode the output either sources
current from a charge pump or sinks current. The maximum voltage that the output level at the pin will rise to is also
programmable. The HVOUT pin source current, which is programmable between 12.5 µA and 100 µA, is used to
control the FET turn-on rate. Similarly, the HVOUT sink current, which is programmable between 3000 µA and 100
µA, is used to control the turn-off rate.
Programmable Output Voltage Levels for HVOUT1- HVOUT2
There are four selectable steps for the output voltage of the FET drivers when in FET driver mode. The voltage that
the pin is capable of driving to can be programmed from 6V to 8V in 2V steps.
RESETb Signal, RESET Command via JTAG or I2C
Activating the RESETb signal (Logic 0 applied to the RESETb pin) or issuing a reset instruction via JTAG, or with
the LA-ispPAC-POWR1014A, I2C will force the outputs to the following states independent of how these outputs
have been configured in the PINS window:
• OUT3-14 will go high-impedance.
• HVOUT pins programmed for open drain operation will go high-impedance.
• HVOUT pins programmed for FET driver mode operation will pull down.
At the conclusion of the RESET event, these outputs will go to the states defined by the PINS window, and if a
sequence has been programmed into the device, it will be re-started at the first step. The analog calibration will be
re-done and consequently, the VMONs, and ADCs will not be operational until 500 microseconds (max.) after the
conclusion of the RESET event.
CAUTION: Activating the RESETb signal or issuing a RESET command through I2C or JTAG during the LA-isp-
PAC-POWR1014/A device operation, results in the device aborting all operations and returning to the power-on
reset state. The status of the power supplies which are being enabled by the LA-ispPAC-POWR1014/A will be
determined by the state of the outputs shown above.
I2C/SMBUS Interface (LA-ispPAC-POWR1014A Only)
I2C and SMBus are low-speed serial interface protocols designed to enable communications among a number of
devices on a circuit board. The LA-ispPAC-POWR1014A supports a 7-bit addressing of the I2C communications
protocol, as well as SMBTimeout and SMBAlert features of the SMBus, enabling it to easily integrated into many
types of modern power management systems. Figure 5-15 shows a typical I2C configuration, in which one or more
LA-ispPAC-POWR1014As are slaved to a supervisory microcontroller. SDA is used to carry data signals, while
5-23
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
SCL provides a synchronous clock signal. The SMBAlert line is only present in SMBus systems. The 7-bit I2C
address of the POWR1014A is fully programmable through the JTAG port.
Figure 5-15. LA-ispPAC-POWR1014A in I2C/SMBUS System
V+
SDA/SMDAT (DATA)
To Other
I2C
Devices
SCL/SMCLK (CLOCK)
SMBALERT
OUT3/
SMBA
OUT3/
SMBA
SDA
SCL
SDA
SCL
SDA
SCL
INTERRUPT
POWR1014A
(I2C SLAVE)
POWR1014A
(I2C SLAVE)
MICROPROCESSOR
(I2C MASTER)
In both the I2C and SMBus protocols, the bus is controlled by a single MASTER device at any given time. This mas-
ter device generates the SCL clock signal and coordinates all data transfers to and from a number of slave devices.
The LA-ispPAC-POWR1014A is configured as a slave device, and cannot independently coordinate data transfers.
Each slave device on a given I2C bus is assigned a unique address. The LA-ispPAC-POWR1014A implements the
7-bit addressing portion of the standard. Any 7-bit address can be assigned to the LA-ispPAC-POWR1014A device
by programming through JTAG. When selecting a device address, one should note that several addresses are
reserved by the I2C and/or SMBus standards, and should not be assigned to LA-ispPAC-POWR1014A devices to
assure bus compatibility. Table 5-6 lists these reserved addresses.
Table 5-6. I2C/SMBus Reserved Slave Device Addresses
Address
0000 000
0000 000
0000 001
0000 010
0000 011
0000 1xx
0001 000
0001 100
0101 000
0110 111
1100 001
1111 0xx
1111 1xx
R/W bit
I2C function Description
SMBus Function
General Call Address
0
1
x
x
x
x
x
x
x
x
x
x
x
General Call Address
Start Byte
Start Byte
CBUS Address
CBUS Address
Reserved
Reserved
Reserved
Reserved
HS-mode master code
HS-mode master code
SMBus Host
NA
NA
SMBus Alert Response Address
Reserved for ACCESS.bus
Reserved for ACCESS.bus
SMBus Device Default Address
10-bit addressing
Reserved
NA
NA
NA
10-bit addressing
Reserved
The LA-ispPAC-POWR1014A’s I2C/SMBus interface allows data to be both written to and read from the device. A
data write transaction (Figure 5-16) consists of the following operations:
1. Start the bus transaction
2. Transmit the device address (7 bits) along with a low write bit
5-24
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
3. Transmit the address of the register to be written to (8 bits)
4. Transmit the data to be written (8 bits)
5. Stop the bus transaction
To start the transaction, the master device holds the SCL line high while pulling SDA low. Address and data bits are
then transferred on each successive SCL pulse, in three consecutive byte frames of 9 SCL pulses. Address and
data are transferred on the first 8 SCL clocks in each frame, while an acknowledge signal is asserted by the slave
device on the 9th clock in each frame. Both data and addresses are transferred in a most-significant-bit-first format.
The first frame contains the 7-bit device address, with bit 8 held low to indicate a write operation. The second frame
contains the register address to which data will be written, and the final frame contains the actual data to be writ-
ten. Note that the SDA signal is only allowed to change when the SCL is low, as raising SDA when SCL is high sig-
nals the end of the transaction.
Figure 5-16. I2C Write Operation
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A6
A5
A4
A3
A2
A1
A0 R/W ACK
R7
R6
R5
R4
R3
R2
R1
R0 ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
SDA
START
DEVICE ADDRESS (7 BITS)
REGISTER ADDRESS (8 BITS)
WRITE DATA (8 BITS)
STOP
Note: Shaded Bits Asserted by Slave
Reading a data byte from the LA-ispPAC-POWR1014A requires two separate bus transactions (Figure 5-17). The
first transaction writes the register address from which a data byte is to be read. Note that since no data is being
written to the device, the transaction is concluded after the second byte frame. The second transaction performs
the actual read. The first frame contains the 7-bit device address with the R/W bit held High. In the second frame
the LA-ispPAC-POWR1014A asserts data out on the bus in response to the SCL signal. Note that the acknowledge
signal in the second frame is asserted by the master device and not the LA-ispPAC-POWR1014A.
Figure 5-17. I2C Read Operation
STEP 1: WRITE REGISTER ADDRESS FOR READ OPERATION
SCL
SDA
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A6
A5
A4
A3
A2
A1
A0 R/W ACK
R7
R6
R5
R4
R3
R2
R1
R0
ACK
START
DEVICE ADDRESS (7 BITS)
REGISTER ADDRESS (8 BITS)
STOP
STEP 2: READ DATA FROM THAT REGISTER
SCL
SDA
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A6
A5
A4
A3
A2
A1
A0
ACK
D7
D6
D5
D4
D3
D2
D1
D0 ACK
OPTIONAL
R/W
START
DEVICE ADDRESS (7 BITS)
READ DATA (8 BITS)
STOP
Note: Shaded Bits Asserted by Slave
The LA-ispPAC-POWR1014ALA-ispPAC-POWR1014A provides 17 registers that can be accessed through its I2C
interface. These registers provide the user with the ability to monitor and control the device’s inputs and outputs,
and transfer data to and from the device. Table 5-7 provides a summary of these registers.
5-25
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Table 5-7. I2C Control Registers1
Register
Address
Register
Name
Read/Write
Description
VMON input status Vmon[4:1]
VMON input status Vmon[8:5]
VMON input status Vmon[10:9]
Output status OUT[8:3], HVOUT[2:1]
Output status OUT[14:9]
Input status IN[4:1]
ADC D[3:0] and status
ADC D[9:4]
Value After POR2, 3
– – – – – – – –
– – – – – – – –
X X X X – – – –
– – – – – – – –
X X – – – – – –
X X X X – – – –
– – – – X X X 1
X X – – – – – –
X X X – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
0 0 0 0 0 1 0 0
X X 0 0 0 0 0 0
X X X X 0 0 0 X
N/A
0x00
0x01
0x02
0x03
0x04
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x11
0x12
vmon_status0
vmon_status1
vmon_status2
output_status0
output_status1
input_status
adc_value_low
adc_value_high
adc_mux
R
R
R
R
R
R
R
R
R/W
R
ADC Attenuator and MUX[3:0]
UES[7:0]
UES_byte0
UES_byte1
UES_byte2
UES_byte3
gp_output1
gp_output2
input_value
reset
R
UES[15:8]
R
UES[23:16]
R
UES[31:24]
R/W
R/W
R/W
W
GPOUT[8:1]
GPOUT[14:9]
PLD Input Register [4:2]
Resets device on write
1. These registers can also be accessed through the JTAG interface.
2. “X” = Non-functional bit (bits read out as 1’s).
3. “–” = State depends on device configuration or input status.
Several registers are provided for monitoring the status of the analog inputs. The three registers
VMON_STATUS[0:2] provide the ability to read the status of the VMON output comparators. The ability to read
both the ‘a’ and ‘b’ comparators from each VMON input is provided through the VMON input registers. Note that if
a VMON input is configured to window comparison mode, then the corresponding VMONxA register bit will reflect
the status of the window comparison.
Figure 5-18. VMON Status Registers
0x00 - VMON_STATUS0 (Read Only)
VMON4B
b7
VMON4A
b6
VMON3B
b5
VMON3A
b4
VMON2B
b3
VMON2A
b2
VMON1B
b1
VMON1A
b0
0x01 - VMON_STATUS1 (Read Only)
VMON8B
b7
VMON8A
b6
VMON7B
b5
VMON7A
b4
VMON6B
b3
VMON6A
b2
VMON5B
b1
VMON5A
b0
0x02 - VMON_STATUS2 (Read Only)
1
1
1
1
VMON10B VMON10A VMON9B
b3 b2 b1
VMON9A
b0
b7
b6
b5
b4
It is also possible to directly read the value of the voltage present on any of the VMON inputs by using the LA-isp-
PAC-POWR1014A’s ADC. Three registers provide the I2C interface to the ADC (Figure 5-19).
5-26
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Figure 5-19. ADC Interface Registers
0x07 - ADC_VALUE_LOW (Read Only)
1
1
1
DONE
b0
D3
b7
D2
b6
D1
b5
D0
b4
b3
b2
b1
0x08 - ADC_VALUE_HIGH (Read Only)
D11
b7
D10
b6
D9
b5
D8
b4
D7
b3
D6
b2
D5
b1
D4
b0
0x09 - ADC_MUX (Read/Write)
X
X
X
ATTEN
b4
SEL3
b3
SEL2
b2
SEL1
b1
SEL0
b0
b7
b6
b5
To perform an A/D conversion, one must set the input attenuator and channel selector. Two input ranges may be
set using the attenuator, 0 - 2.048V and 0 - 6.144V. Table 5-8 shows the input attenuator settings.
Table 5-8. ADC Input Attenuator Control
ATTEN (ADC_MUX.4)
Resolution
2mV
Full-Scale Range
2.048 V
0
1
6mV
6.144 V
The input selector may be set to monitor any one of the ten VMON inputs, the VCCA input, or the VCCINP input.
Table 5-9 shows the codes associated with each input selection.
Table 5-9. V
Address Selection Table
MON
Select Word
SEL2
SEL3
(ADC_MUX.3)
SEL1
SEL0
(ADC_MUX.2)
(ADC_MUX.1)
(ADC_MUX.0) Input Channel
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
VMON10
VCCA
VCCINP
Writing a value to the ADC_MUX register to set the input attenuator and selector will automatically initiate a conver-
sion. When the conversion is in process, the DONE bit (ADC_VALUE_LOW.0) will be reset to 0. When the conver-
sion is complete, this bit will be set to 1. When the conversion is complete, the result may be read out of the ADC by
performing two I2C read operations; one for ADC_VALUE_LOW, and one for ADC_VALUE_HIGH. It is recom-
mended that the I2C master load a second conversion command only after the completion of the current conversion
5-27
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
command (Waiting for the DONE bit to be set to 1). An alternative would be to wait for a minimum specified time
(see T
value in the specifications) and disregard checking the DONE bit.
CONVERT
Note that if the I2C clock rate falls below 50kHz (see F 2 note in specifications), the only way to insure a valid ADC
I C
CONVERT
conversion is to wait the minimum specified time (T
), as the operation of the DONE bit at clock rates lower
than that cannot be guaranteed. In other words, if the I2C clock rate is less than 50kHz, the DONE bit may or may
not assert even though a valid conversion result is available.
To insure every ADC conversion result is valid, preferred operation is to clock I2C at more than 50kHz and verify
DONE bit status or wait for the full T
time period between subsequent ADC convert commands. If an I2C
CONVERT
request is placed before the current conversion is complete, the DONE bit will be set to 1 only after the second
request is complete.
The status of the digital input lines may also be monitored and controlled through I2C commands. Figure 5-20
shows the I2C interface to the IN[1:4] digital input lines. The input status may be monitored by reading the
INPUT_STATUS register, while input values to the PLD array may be set by writing to the INPUT_VALUE register.
To be able to set an input value for the PLD array, the input multiplexer associated with that bit needs to be set to
the I2C register setting in E2CMOS memory otherwise the PLD will receive its input from the INx pin.
Figure 5-20. I2C Digital Input Interface
PLD Output/Input_Value Register Select
2
(E Configuration)
3
IN1
MUX
USERJTAG
Bit
2
PLD
Array
3
IN[2..4]
MUX
3
3
Input_Value
Input_Status
2
I C Interface Unit
0x06 - INPUT_STATUS (Read Only)
1
1
1
1
IN4
IN3
b2
IN2
b1
IN1
b0
b7
b6
b5
b4
b3
0x11 - INPUT_VALUE (Read/Write)
X
X
X
X
I4
I3
I2
X
b7
b6
b5
b4
b3
b2
b1
b0
The digital outputs may also be monitored and controlled through the I2C interface, as shown in Figure 5-21. The
status of any given digital output may be read by reading the contents of the associated OUTPUT_STATUS[1:0]
register. Note that in the case of the outputs, the status reflected by these registers reflects the logic signal used to
drive the pin, and does not sample the actual level present on the output pin. For example, if an output is set high
5-28
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
but is not pulled up, the output status bit corresponding with that pin will read ‘1’, but a high output signal will not
appear on the pin.
Digital outputs may also be optionally controlled directly by the I2C bus instead of by the PLD array. The outputs
may be driven either from the PLD output or from the contents of the GP_OUTPUT[1:0] registers with the choice
user-settable in E2CMOS memory. Each output may be independently set to output from the PLD or from the
GP_OUTPUT registers.
Figure 5-21. I2C Output Monitor and Control Logic
PLD Output/GP_Output Register Select
2
(E Configuration)
14
PLD
14
Output
Routing
Pool
14
HVOUT[1..2]
OUT[3..14]
MUX
14
14
GP_Output1
GP_Output2
Output_Status0
Output_Status1
2
I C Interface Unit
0x03 - OUTPUT_STATUS0 (Read Only)
OUT8
b7
OUT7
b6
OUT6
b5
OUT5
b4
OUT4
b3
OUT3
b2
HVOUT2
HVOUT1
b0
b1
0x04 - OUTPUT_STATUS1 (Read Only)
1
1
OUT14
b5
OUT13
b4
OUT12
b3
OUT11
b2
OUT10
b1
OUT9
b0
b7
b6
0x0E - GP_OUTPUT1 (Read/Write)
GP8
b7
GP7
b6
GP6
b5
GP5
b4
GP4
b3
GP3_ENb
b2
GP2
b1
GP1
b0
0x0F - GP_OUTPUT2 (Read/Write)
X
X
GP14
b5
GP13
b4
GP12
b3
GP11
b2
GP10
b1
GP9
b0
b7
b6
The UES word may also be read through the I2C interface, with the register mapping shown in Figure 5-22.
5-29
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Figure 5-22. I2C Register Mapping for UES Bits
0x0A - UES_BYTE0 (Read Only)
UES7
b7
UES6
b6
UES5
b5
UES4
b4
UES3
b3
UES2
b2
UES1
b1
UES0
b0
0x0B - UES_BYTE1 (Read Only)
UES15
b7
UES14
b6
UES13
b5
UES12
b4
UES11
b3
UES10
b2
UES9
b1
UES8
b0
0x0C - UES_BYTE2 (Read Only)
UES23
b7
UES22
b6
UES21
b5
UES20
b4
UES19
b3
UES18
b2
UES17
b1
UES16
b0
0x0D - UES_BYTE3 (Read Only)
UES31
b7
UES30
b6
UES29
b5
UES28
b4
UES27
b3
UES26
b2
UES25
b1
UES24
b0
The I2C interface also provides the ability to initiate reset operations. The LA-ispPAC-POWR1014A may be reset by
issuing a write of any value to the I2C RESET register (Figure 5-23). Note: The execution of the I2C reset command
is equivalent to toggling the Resetb pin of the chip. Refer to the Resetb Signal, RESET Command via JTAG or I2C
section of this data sheet for further information.
Figure 5-23. I2C Reset Register
0x12 - RESET (Write Only)
X
X
X
X
X
X
X
X
b7
b6
b5
b4
b3
b2
b1
b0
5-30
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
SMBus SMBAlert Function
The LA-ispPAC-POWR1014A provides an SMBus SMBAlert function so that it can request service from the bus
master when it is used as part of an SMBus system. This feature is supported as an alternate function of OUT3.
When the SMBAlert feature is enabled, OUT3 is controlled by a combination of the PLD output and the GP3_ENb
bit (Figure 5-24). Note: To enable the SMBAlert feature, the SMB_Mode (EECMOS bit) should be set in software.
Figure 5-24. LA-ispPAC-POWR1014/A SMBAlert Logic
PLD Output/GP_Output Register Select
2
(E Configuration)
OUT3/SMBA Mode Select
2
(E Configuration)
PLD
Output
Routing
Pool
MUX
OUT3/SMBA
MUX
GP3_ENb
SMBAlert
Logic
2
I C Interface Unit
The typical flow for an SMBAlert transaction is as follows (Figure 5-24):
1. GP3_ENb bit is forced (Via I2C write) to Low
2. LA-ispPAC-POWR1014A PLD Logic pulls OUT3/SMBA Low
3. Master responds to interrupt from SMBA line
4. Master broadcasts a read operation using the SMBus Alert Response Address (ARA)
5. LA-ispPAC-POWR1014A responds to read request by transmitting its device address
6. If transmitted device address matches LA-ispPAC-POWR1014A address, it sets GP3_ENb bit high.
This releases OUT3/SMBA.
Figure 5-25. SMBAlert Bus Transaction
SMBA
SCL
SDA
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
x
9
0
0
0
1
1
0
0
ACK
A6
A5
A4
A3
A2
A1
A0
ACK
R/W
SLAVE
ASSERTS
SMBA
SLAVE
RELEASES
SMBA
START
SLAVE ADDRESS (7 BITS)
STOP
ALERT RESPONSE ADDRESS
(0001 100)
Note: Shaded Bits Asserted by Slave
After OUT3/SMBA has been released, the bus master (typically a microcontroller) may opt to perform some service
functions in which it may send data to or read data from the LA-ispPAC-POWR1014A. As part of the service func-
tions, the bus master will typically need to clear whatever condition initiated the SMBAlert request, and will also
need to reset GP3_ENb to re-enable the SMBAlert function. For further information on the SMBus, the user should
consult the SMBus Standard.
5-31
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Software-Based Design Environment
Designers can configure the LA-ispPAC-POWR1014/A using PAC-Designer, an easy to use, Microsoft Windows
compatible program. Circuit designs are entered graphically and then verified, all within the PAC-Designer environ-
ment. Full device programming is supported using PC parallel port I/O operations and a download cable connected
to the serial programming interface pins of the LA-ispPAC-POWR1014/A. A library of configurations is included with
basic solutions and examples of advanced circuit techniques are available on the Lattice web site for downloading.
In addition, comprehensive on-line and printed documentation is provided that covers all aspects of PAC-Designer
operation. The PAC-Designer schematic window, shown in Figure 5-26, provides access to all configurable LA-isp-
PAC-POWR1014/A elements via its graphical user interface. All analog input and output pins are represented.
Static or non-configurable pins such as power, ground, and the serial digital interface are omitted for clarity. Any
element in the schematic window can be accessed via mouse operations as well as menu commands. When com-
pleted, configurations can be saved, simulated, and downloaded to devices.
Figure 5-26. PAC-Designer LA-ispPAC-POWR1014/A Design Entry Screen
In-System Programming
The LA-ispPAC-POWR1014/A is an in-system programmable device. This is accomplished by integrating all E2
configuration memory and control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compli-
ant serial JTAG interface at normal logic levels (see Figure 5-27). Once a device is programmed, all configuration
information is stored on-chip, in non-volatile E2CMOS memory cells. The specifics of the IEEE 1149.1 serial inter-
face and all LA-ispPAC-POWR1014/A instructions are described in the JTAG interface section of this data sheet.
5-32
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Figure 5-27. LA-ispPAC-POWR1014/A JTAG Interconnection Configuration Diagram
Board Power Supplies
are ON
JTAG Signal
Connector
APS
TDO
(N/C)
TDI
TDO
TDI
Other JTAG
Device(s)
LA-ispPAC-POWR
1014/A
TDI
ATDI
(N/C)
Programming
Cable
VCCJ
TCK
TMS
TDO
Programming LA-ispPAC-POWR1014/A: Alternate Method
Some applications require that the LA-ispPAC-POWR1014/A be programmed before turning the power on to the
entire circuit board. To meet such application needs, the LA-ispPAC-POWR1014/A provides an alternate program-
ming method which enables the programming of the LA-ispPAC-POWR1014/A device through the JTAG chain with
a separate power supply applied just to the programming section of the LA-ispPAC-POWR1014/A device with the
main power supply of the board turned off.
Three special purpose pins, APS, ATDI and TDISEL, enable programming of the un-programmed LA-ispPAC-
POWR1014/A under such circumstances. The APS pin powers just the programming circuitry of the LA-ispPAC-
POWR1014/A device. The ATDI pin provides an alternate connection to the JTAG header while bypassing all the
un-powered devices in the JTAG chain. TDISEL pin enables switching between the ATDI and the standard JTAG
signal TDI. When the internally pulled-up TDISEL = 1, standard TDI pin is enabled and when the TDISEL = 0, ATDI
is enabled.
In order to use this feature the JTAG signals of the LA-ispPAC-POWR1014/A are connected to the header as
shown in Figure 5-28. Note: The LA-ispPAC-POWR1014/A should be the last device in the JTAG chain.
5-33
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Figure 5-28. LA-ispPAC-POWR1014/A Alternate Configuration Diagram
Board Power Supplies
are OFF
D1
D2
JTAG Signal
Connector
APS
TDI
TDO
TDI
Other JTAG
Device(s)
LA-ispPAC-POWR
1014/A
TDI
TDO
ATDI
Programming
Cable
VCCJ
TCK
TMS
TDO
TDISEL
APS
(off board Power Supply)
Alternate TDI Selection Via JTAG Command
When the TDISEL pin held high and four consecutive IDCODE instructions are issued, LA-ispPAC-POWR1014/A
responds by making its active JTAG data input the ATDI pin. When ATDI is selected, data on its TDI pin is ignored
until the JTAG state machine returns to the Test-Logic-Reset state.
This method of selecting ATDI takes advantage of the fact that a JTAG device with an IDCODE register will auto-
matically load its unique IDCODE instruction into the Instruction Register after a Test-Logic-Reset. This JTAG
capability permits blind interrogation of devices so that their location in a serial chain can be identified without hav-
ing to know anything about them in advance. A blind interrogation can be made using only the TMS and TCLK con-
trol pins, which means TDI and TDO are not required for performing the operation. Figure 5-29 illustrates the logic
for selecting whether the TDI or ATDI pin is the active data input to LA-ispPAC-POWR1014/A.
5-34
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Figure 5-29. LA-ispPAC-POWR1014/A TDI/ATDI Pin Selection Diagram
TMS TCK
TDI
1
0
JTAG
TDO
ATDI
Test-Logic-Reset
SET
4 Consecutive
IDCODE Instructions
Loaded at Update-IR
TDISEL
Q
CLR
LA-ispPAC-POWR1014/A
Table 5-10 shows in truth table form the same conditions required to select either TDI or ATDI as in the logic dia-
gram found in Figure 5-29.
Table 5-10. LA-ispPAC-POWR1014/A ATDI/TDI Selection Table
Four Consecutive
IDCODE Commands
Loaded at Update-IR
JTAG State Machine
Test-Logic-Reset
Active JTAG
Data Input Pin
TDISEL Pin
H
H
L
No
Yes
X
Yes
No
X
ATDI (TDI Disabled)
TDI (ATDI Disabled)
ATDI (TDI Disabled)
Please refer to the Lattice application note AN6068, Programming the ispPAC-POWR1220AT8 in a JTAG Chain
Using ATDI. The application note includes specific SVF code examples and information on the use of Lattice
design tools to verify device operation in alternate TDI mode.
APS Alternate Programming Supply Pin
Because the APS pin directly powers the on-chip programming circuitry, the LA-ispPAC-POWR1014/A device can
be programmed by applying power to the APS pin (without powering the entire chip though the VCCD and VCCA
pins). In addition, to enable the on-chip JTAG interface circuitry, power should be applied to the VCCJ pin.
When the LA-ispPAC-POWR1014/A is using the APS pin, its VCCD and VCCA pins can be open or pulled low.
Additionally, other than JTAG I/O pins, all digital output pins are in Hi-Z state, HVOUT pins configured as MOSFET
driver are driven low, and all other inputs are ignored.
To switch the power supply back to VCCD and VCCA pins, one should turn the APS supply and VCCJ off before
turning the regular supplies on. When VCCD and VCCA are turned back on for normal operation, APS should be
left floating.
The APS pin should not be connected to the VCCD and VCCA pins.
5-35
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
User Electronic Signature
A user electronic signature (UES) feature is included in the E2CMOS memory of the LA-ispPAC-POWR1014/A.
This consists of 32 bits that can be configured by the user to store unique data such as ID codes, revision numbers
or inventory control data. The specifics of this feature are discussed in the IEEE 1149.1 serial interface section of
this data sheet.
Electronic Security
An electronic security “fuse” (ESF) bit is provided in every LA-ispPAC-POWR1014/A device to prevent unauthor-
ized readout of the E2CMOS configuration bit patterns. Once programmed, this cell prevents further access to the
functional user bits in the device. This cell can only be erased by reprogramming the device, so the original config-
uration cannot be examined once programmed. Usage of this feature is optional. The specifics of this feature are
discussed in the IEEE 1149.1 serial interface section of this data sheet.
Production Programming Support
Once a final configuration is determined, an ASCII format JEDEC file can be created using the PAC-Designer soft-
ware. Devices can then be ordered through the usual supply channels with the user’s specific configuration already
preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production
programming equipment, giving customers a wide degree of freedom and flexibility in production planning.
Evaluation Fixture (POWR1014A_B_EVN)
The board demonstrates proper layout techniques and can be used in real time to check circuit operation as part of
the design process. Input and output connections are provided to aid in the evaluation of the functionality imple-
mented in LA-ispPAC-POWR1014/A for a given application. (Figure 5-30).
Figure 5-30. Download from a PC
PAC-Designer
Software
Other
System
Circuitry
USB Cable
4
ispPAC-
POWR1014/A
Device
IEEE Standard 1149.1 Interface (JTAG)
Serial Port Programming Interface Communication with the LA-ispPAC-POWR1014/A is facilitated via an IEEE
1149.1 test access port (TAP). It is used by the LA-ispPAC-POWR1014/A as a serial programming interface. A brief
description of the LA-ispPAC-POWR1014/A JTAG interface follows. For complete details of the reference specifica-
tion, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990
(which now includes IEEE Std 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the LA-
ispPAC-POWR1014/A. The TAP controller is a state machine driven with mode and clock inputs. Given in the cor-
rect sequence, instructions are shifted into an instruction register, which then determines subsequent data input,
data output, and related operations. Device programming is performed by addressing the configuration register,
shifting data in, and then executing a program configuration instruction, after which the data is transferred to inter-
nal E2CMOS cells. It is these non-volatile cells that store the configuration or the LA-ispPAC-POWR1014/A. A set of
instructions are defined that access all data registers and perform other internal control operations. For compatibil-
5-36
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
ity between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are func-
tionally specified, but inclusion is strictly optional. Finally, there are provisions for optional data registers defined by
the manufacturer. The two required registers are the bypass and boundary-scan registers. Figure 5-31 shows how
the instruction and various data registers are organized in an LA-ispPAC-POWR1014/A.
Figure 5-31. LA-ispPAC-POWR1014/A TAP Registers
DATA REGISTER (123 BITS)
ADDRESS REGISTER (109 BITS)
UES REGISTER (32 BITS)
E2CMOS
NON-VOLATILE
MEMORY
IDCODE REGISTER (32 BITS)
CFG ADDRESS REGISTER (12 BITS)
2
I C DATA REGISTER (72 BITS)
2
I C CONTROL REGISTER (12 BITS)
CFG DATA REGISTER (56 BITS)
BYPASS REGISTER (1 BIT)
INSTRUCTION REGISTER (8 BITS)
TEST ACCESS PORT (TAP)
LOGIC
OUTPUT
LATCH
TDI
TCK
TMS
TDO
TAP Controller Specifics
The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine
whether an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists
of a small 16-state controller design. In a given state, the controller responds according to the level on the TMS
input as shown in Figure 5-32. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data
Out (TDO) becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-
Reset, Run- Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-
Register. But there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This
allows a reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the
power-on default state.
5-37
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Figure 5-32. TAP States
Test-Logic-Rst
1
0
0
1
1
1
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
Shift-DR
1
0
Shift-IR
1
0
0
1
1
Exit1-DR
0
Exit1-IR
0
Pause-DR
1
0
Pause-IR
1
0
0
0
Exit2-DR
Exit2-IR
1
1
Update-DR
Update-IR
1
0
1
0
Note: The value shown adjacent to each state transition in this figure
represents the signal present at TMS at the time of a rising edge at TCK.
When the correct logic sequence is applied to the TMS and TCK inputs, the TAP will exit the Test-Logic-Reset state
and move to the desired state. The next state after Test-Logic-Reset is Run-Test/Idle. Until a data or instruction shift
is performed, no action will occur in Run-Test/Idle (steady state = idle). After Run-Test/Idle, either a data or instruc-
tion shift is performed. The states of the Data and Instruction Register blocks are identical to each other differing
only in their entry points. When either block is entered, the first action is a capture operation. For the Data Regis-
ters, the Capture-DR state is very simple: it captures (parallel loads) data onto the selected serial data path (previ-
ously chosen with the appropriate instruction). For the Instruction Register, the Capture-IR state will always load
the IDCODE instruction. It will always enable the ID Register for readout if no other instruction is loaded prior to a
Shift-DR operation. This, in conjunction with mandated bit codes, allows a “blind” interrogation of any device in a
compliant IEEE 1149.1 serial chain. From the Capture state, the TAP transitions to either the Shift or Exit1 state.
Normally the Shift state follows the Capture state so that test data or status information can be shifted out or new
data shifted in. Following the Shift state, the TAP either returns to the Run-Test/Idle state via the Exit1 and Update
states or enters the Pause state via Exit1. The Pause state is used to temporarily suspend the shifting of data
through either the Data or Instruction Register while an external operation is performed. From the Pause state,
shifting can resume by reentering the Shift state via the Exit2 state or be terminated by entering the Run-Test/Idle
state via the Exit2 and Update states. If the proper instruction is shifted in during a Shift-IR operation, the next entry
into Run-Test/Idle initiates the test mode (steady state = test). This is when the device is actually programmed,
erased or verified. All other instructions are executed in the Update state.
Test Instructions
Like data registers, the IEEE 1149.1 standard also mandates the inclusion of certain instructions. It outlines the
function of three required and six optional instructions. Any additional instructions are left exclusively for the manu-
facturer to determine. The instruction word length is not mandated other than to be a minimum of two bits, with only
the BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respec-
tively). The LA-ispPAC-POWR1014/A contains the required minimum instruction set as well as one from the
optional instruction set. In addition, there are several proprietary instructions that allow the device to be configured
and verified. Table 5-11 lists the instructions supported by the LA-ispPAC-POWR1014/A JTAG Test Access Port
5-38
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
(TAP) controller:
Table 5-11. LA-ispPAC-POWR1014/A TAP Instruction Table
Command
Instruction
BULK_ERASE
Code
Comments
0000 0011
1111 1111
0001 0100
0010 0100
0000 0000
0001 0110
0001 1000
00011100
0001 1110
0010 1111
0001 0101
0000 1001
Bulk erase device
BYPASS
Bypass - connect TDO to TDI
Fast VPP discharge
DISCHARGE
ERASE_DONE_BIT
EXTEST
Erases ‘Done’ bit only
Bypass - connect TDO to TDI
Read contents of manufacturer ID code (32 bits)
Force all outputs to High-Z state, FET outputs pulled low
Sample/Preload. Default to bypass.
Disable program mode
IDCODE
OUTPUTS_HIGHZ
SAMPLE/PRELOAD
PROGRAM_DISABLE
PROGRAM_DONE_BIT
PROGRAM_ENABLE
PROGRAM_SECURITY
Programs the Done bit
Enable program mode
Program security fuse
Resets device (refer to the RESETb Signal, RESET Command via
JTAG or I2C section of this data sheet)
RESET
0010 0010
IN1_RESET_JTAG_BIT
IN1_SET_JTAG_BIT
CFG_ADDRESS
0001 0010
0001 0011
0010 1011
0010 1101
0010 1001
0010 1110
0010 1000
0000 0001
0000 0010
0010 0001
0010 0111
0000 0111
0000 1010
0010 1010
0001 1010
0001 0111
Reset the JTAG bit associated with IN1 pin to 0
Set the JTAG bit associated with IN1 pin to 1
Select non-PLD address register
CFG_DATA_SHIFT
CFG_ERASE
Non-PLD data shift
ERASE Just the Non PLD configuration
Non-PLD program
CFG_PROGRAM
CFG_VERIFY
VRIFY non-PLD fusemap data
PLD_ADDRESS_SHIFT
PLD_DATA_SHIFT
PLD_INIT_ADDR_FOR_PROG_INCR
PLD_PROG_INCR
PLD_PROGRAM
PLD_Address register (109 bits)
PLD_Data register (123 Bits)
Initialize the address register for auto increment
Program column register to E2 and auto increment address register
Program PLD data register to E2
PLD_VERIFY
Verifies PLD column data
PLD_VERIFY_INCR
UES_PROGRAM
UES_READ
Load column register from E2 and auto increment address register
Program UES bits into E2
Read contents of UES register from E2 (32 bits)
BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and
TDO and allows serial data to be transferred through the device without affecting the operation of the LA-ispPAC-
POWR1014/A. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (11111111).
The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI
and TDO. The LA-ispPAC-POWR1014/A has no boundary scan register, so for compatibility it defaults to the
BYPASS mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown
in Table 5-11.
The EXTEST (external test) instruction is required and would normally place the device into an external boundary
test mode while also enabling the boundary scan register to be connected between TDI and TDO. Again, since the
LA-ispPAC-POWR1014/A has no boundary scan logic, the device is put in the BYPASS mode to ensure specifica-
tion compatibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros (00000000).
5-39
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
The optional IDCODE (identification code) instruction is incorporated in the LA-ispPAC-POWR1014/A and leaves it
in its functional mode when executed. It selects the Device Identification Register to be connected between TDI
and TDO. The Identification Register is a 32-bit shift register containing information regarding the IC manufacturer,
device type and version code (Figure 5-33). Access to the Identification Register is immediately available, via a
TAP data scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for
this instruction is defined by Lattice as shown in Table 5-11.
Figure 5-33. LA-ispPAC-POWR1014/A ID Code
MSB
LSB
0001 0000 0001 0100 0101 / 0000 0100 001 / 1
0000 0000 0001 0100 0101 / 0000 0100 001 / 1
(LA-ispPAC-POWR1014)
(LA-ispPAC-POWR1014A)
Part Number
(20 bits)
JEDEC Manufacturer
Identity Code for
Lattice Semiconductor
00145h = LA-ispPAC-POWR1014A
10145h = LA-ispPAC-POWR1014
(11 bits)
Constant 1
(1 bit)
per 1149.1-1990
LA-ispPAC-POWR1014/A Specific Instructions
There are 25 unique instructions specified by Lattice for the LA-ispPAC-POWR1014/A. These instructions are pri-
marily used to interface to the various user registers and the E2CMOS non-volatile memory. Additional instructions
are used to control or monitor other features of the device. A brief description of each unique instruction is provided
in detail below, and the bit codes are found in Table 5-11.
PLD_ADDRESS_SHIFT – This instruction is used to set the address of the PLD AND/ARCH arrays for subsequent
program or read operations. This instruction also forces the outputs into the OUTPUTS_HIGHZ.
PLD_DATA_SHIFT – This instruction is used to shift PLD data into the register prior to programming or reading.
This instruction also forces the outputs into the OUTPUTS_HIGHZ.
PLD_INIT_ADDR_FOR_PROG_INCR – This instruction prepares the PLD address register for subsequent
PLD_PROG_INCR or PLD_VERIFY_INCR instructions.
PLD_PROG_INCR – This instruction programs the PLD data register for the current address and increments the
address register for the next set of data.
PLD_PROGRAM – This instruction programs the selected PLD AND/ARCH array column. The specific column is
preselected by using PLD_ADDRESS_SHIFT instruction. The programming occurs at the second rising edge of
the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE
instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ.
PROGRAM_SECURITY – This instruction is used to program the electronic security fuse (ESF) bit. Programming
the ESF bit protects proprietary designs from being read out. The programming occurs at the second rising edge of
the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE
instruction). This instruction also forces the outputs into the OUTPUTS_HIGHZ.
PLD_VERIFY – This instruction is used to read the content of the selected PLD AND/ARCH array column. This
specific column is preselected by using PLD_ADDRESS_SHIFT instruction. This instruction also forces the outputs
into the OUTPUTS_HIGHZ.
DISCHARGE – This instruction is used to discharge the internal programming supply voltage after an erase or pro-
gramming cycle and prepares LA-ispPAC-POWR1014/A for a read cycle. This instruction also forces the outputs
into the OUTPUTS_HIGHZ.
5-40
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
CFG_ADDRESS – This instruction is used to set the address of the CFG array for subsequent program or read
operations. This instruction also forces the outputs into the OUTPUTS_HIGHZ.
CFG_DATA_SHIFT – This instruction is used to shift data into the CFG register prior to programming or reading.
This instruction also forces the outputs into the OUTPUTS_HIGHZ.
CFG_ERASE – This instruction will bulk erase the CFG array. The action occurs at the second rising edge of TCK
in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE instruction).
This instruction also forces the outputs into the OUTPUTS_HIGHZ.
CFG_PROGRAM – This instruction programs the selected CFG array column. This specific column is preselected
by using CFG_ADDRESS instruction. The programming occurs at the second rising edge of the TCK in Run-Test-
Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE instruction). This
instruction also forces the outputs into the OUTPUTS_HIGHZ.
CFG_VERIFY – This instruction is used to read the content of the selected CFG array column. This specific col-
umn is preselected by using CFG_ADDRESS instruction. This instruction also forces the outputs into the
OUTPUTS_HIGHZ.
BULK_ERASE – This instruction will bulk erase all E2CMOS bits (CFG, PLD, UES, and ESF) in the LA-ispPAC-
POWR1014/A. The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruc-
tion also forces the outputs into the OUTPUTS_HIGHZ.
OUTPUTS_HIGHZ – This instruction turns off all of the open-drain output transistors. Pins that are programmed as
FET drivers will be placed in the active low state. This instruction is effective after Update-Instruction-Register
JTAG state.
PROGRAM_ENABLE – This instruction enables the programming mode of the LA-ispPAC-POWR1014/A. This
instruction also forces the outputs into the OUTPUTS_HIGHZ.
IDCODE – This instruction connects the output of the Identification Code Data Shift (IDCODE) Register to TDO
(Figure 5-34), to support reading out the identification code.
Figure 5-34. IDCODE Register
TDO
Bit
31
Bit
30
Bit
29
Bit
28
Bit
27
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
PROGRAM_DISABLE – This instruction disables the programming mode of the LA-ispPAC-POWR1014/A. The
Test-Logic-Reset JTAG state can also be used to cancel the programming mode of the LA-ispPAC-POWR1014/A.
UES_READ – This instruction both reads the E2CMOS bits into the UES register and places the UES register
between the TDI and TDO pins (as shown in Figure 5-31), to support programming or reading of the user electronic
signature bits.
Figure 5-35. UES Register
TDO
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
UES_PROGRAM – This instruction will program the content of the UES Register into the UES E2CMOS memory.
The device must already be in programming mode (PROGRAM_ENABLE instruction). This instruction also forces
the outputs into the OUTPUTS_HIGHZ.
ERASE_DONE_BIT – This instruction clears the ‘Done’ bit, which prevents the LA-ispPAC-POWR1014/A
sequence from starting.
5-41
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
PROGRAM_DONE_BIT – This instruction sets the ‘Done’ bit, which enables the LA-ispPAC-POWR1014/A
sequence to start.
RESET – This instruction resets the PLD sequence and output macrocells.
IN1_RESET_JTAG_BIT – This instruction clears the JTAG Register logic input ‘IN1.’ The PLD input has to be con-
figured to take input from the JTAG Register in order for this command to have effect on the sequence.
IN1_SET_JTAG_BIT – This instruction sets the JTAG Register logic input ‘IN1.’ The PLD input has to be configured
to take input from the JTAG Register in order for this command to have effect on the sequence.
PLD_VERIFY_INCR – This instruction reads out the PLD data register for the current address and increments the
address register for the next read.
Notes:
In all of the descriptions above, OUTPUTS_HIGHZ refers both to the instruction and the state of the digital output
pins, in which the open-drains are tri-stated and the FET drivers are pulled low.
Before any of the above programming instructions are executed, the respective E2CMOS bits need to be erased
using the corresponding erase instruction.
Accessing I2C Registers through JTAG (LA-ispPAC-POWR1014A Only)
I2C registers can be read or written through the JTAG interface of the LA-ispPAC-POWR1014A devices using the
two JTAG command codes shown in Table 5-12.
Table 5-12. JTAG Command Codes
Instruction
Command Code
0010 0101
Comments
I2C_DATA_REGISTER
I2C_CONTROL_REGISTER
Accessing I2C Data Register Through JTAG (72 Bits)
Controls Read and Write Functions of I2C Registers (12 Bits)
0010 0110
There are 12 bits in the I2C_Control_Register and 72 bits in the I2C_Data_Register packet. All I2C register con-
tents, except the UES bits, can be read out through the 72-bit I2C_Data_Register packet. All I2C write registers can
be written by shifting in a 72-bit I2C_Data_Register packet. The I2C_Control_Register bits are used to select the
I2C registers read as well as written.
The reading (shifting out) and writing (shifting in) of I2C_Data_Register and writing of the I2C_Control_Register
through the JTAG port follows the TAP states protocol shown in Figure 5-32.
5-42
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
I2C_Control_Register Structure
Figure 5-36 shows the functions of each of the 12-bit I2C_Control_Register bits.
Figure 5-36. I2C_Control_Register
Bit
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
1
0/1
X1
X0
Y1
Y0
Z1
Z0
0 – Read ADC_MUX (Register 0x09)
1 – Write ADC_MUX (Register 0x09)*
X1,X0
0
0
1
1
0 – Read INPUT VALUE (Register 0x11)*
1 – Read INPUT STATUS (Register 0x06)*
0 – Write INPUT_VALUE (Register 0x11)*
1 – Not Valid
Y1,Y0
0
0
1
1
0 – Read GP_OUTPUT1 (Register 0x0E)*
1 – Read OUTPUT_STATUS0 (Register 0x03)*
0 – Write GP_OUTPUT1 (Register 0x0E)*
1 – Not Valid
Z1,Z0
0
0
1
1
0 – Read GP_OUTPUT2 (Register 0x0F)*
1 – Read OUTPUT_STATUS1 (Register 0x04)*
0 – Write GP_OUTPUT2 (Register 0x0F)*
1 – Not Valid
2
*Equivalent I C port addresses are shown in parentheses.
I2C_Data_Register Packet Structure
The 72-bit I2C_Data_Register packet is divided into 9 bytes.
• Bytes 9-7 contain the VMON status
• Bytes 6-5 contain ADC result
• Byte 4 controls/reads ADC Mux and ADC Input Attenuator
• Byte 3 controls/reads input pins/ status
• Bytes 2-1 control/read output pins/status
VMON Status Registers
Byte 9, Byte 8 and Byte 7: Byte 9 is the most significant byte and is shifted out last, ending with bit 71, VMON1A.
These bytes consist of the status of VMONxA and VMONxB comparators corresponding to VMON1 through
VMON10 inputs. In the following tables, the number in the parenthesis indicates the bit position within the
I2C_Data_Register Packet. During the I2C_Data_Register write operation, the contents of these bytes are ignored
because the VMON staut registers are read only.
5-43
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Figure 5-37. VMON Status Registers
(0x00) – VMON_STATUS0 (Read Only) – Byte 9 (Most Significant)
VMON1A
(71)
VMON1B
(70)
VMON2A
(69)
VMON2B
(68)
VMON3A
(67)
VMON3B
(66)
VMON4A
(65)
VMON4B
(64)
(0x01) – VMON_STATUS1 (Read Only) – Byte 8
VMON5A
(63)
VMON5B
(62)
VMON6A
(61)
VMON6B
(60)
VMON7A
(59)
VMON7B
(58)
VMON8A
(57)
VMON8B
(56)
(0x02) – VMON_STATUS2 (Read Only) – Byte 7
VMON9A
(55)
VMON9B VMON10A VMON10B
(54) (53) (52)
1
(51)
1
(50)
1
(49)
1
(48)
ADC Interface Registers
Byte 6, Byte 5: These bytes contain 12-bit ADC measured values.
Figure 5-38. ADC Interface Registers, Bytes 6 and 5
(0x07) – ADC_Value_Low (Read Only) – Byte 6
X
(47)
1
(46)
1
(45)
1
(44)
D0
(43)
D1
(42)
D2
(41)
D3
(40)
(0x08) – ADC_Value_High (Read Only) – Byte 5
D4
(39)
D5
(38)
D6
(37)
D7
(36)
D8
(35)
D9
(34)
D10
(33)
D11
(32)
Byte 4: The I2C_Data_Register write operation action is determined by bit 6 of the I2C_Control_Register. When bit
6 of the I2C_Control_Register is set to 1, this byte selects the VMON input for routing to the ADC (4-bit ADC input
mux) and sets/clears the ADC attenuate mode. When the bit 6 of the I2C_Control_register is reset to 0, the con-
tents of the Byte 4 are ignored. During I2C_Data_Register read operation with bit 6 reset to 0 in the
I2C_Control_Register, byte 4 returns the 4-bit input mux setting and the attenuate bit setting. Refer to Tables 5-8
and 5-9 for the mux select and the attenuate bits decode value.
Figure 5-39. ADC Interface Registers, Byte 4
(0x09) – ADC_MUX (Read/ Write)
SEL0
(31)
SEL1
(30)
SEL2
(29)
SEL3
(28)
ATTEN
(27)
X
(26)
X
(25)
X
(24)
Digital Input Status and Input Value Register
Byte 3: I2C_Control_Register bits 5 and 4 control reading into and writing from Byte 3 of the I2C_Data_Register.
When bits 5 and 4 are set to 10b, the contents of Byte 3 are written into the input register bits during the
I2C_Data_Register write operation.
Figure 5-40. INPUT_VALUE Registers, Byte 3
(0x11) – INPUT_VALUE (Write Operation) – When I2C_Control_Register bit 5 =1, bit 4=0.
X
(23)
I2
(22)
I3
(21)
I4
(20)
1
(19)
1
(18)
1
(17)
1
(16)
5-44
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
During the I2C_Data_Register read operation - When I2C_Control_Register bit 5 = 0, and bit 4 = 0, the Byte 3
value will return INPUT_VALUE register.
(0x11) – INPUT_VALUE (Read operation) – When I2C_Control_Register Bit 5=0 and Bit 4=0
X
(23)
I2
(22)
I3
(21)
I4
(20)
1
(19)
1
(18)
1
(17)
1
(16)
During the I2C_Data_Register read operation - When I2C_Control_Register bit 5 = 0, and bit 4 = 1 Byte 3 value will
return INPUT_STATUS register.
(0x06) – INPUT_STATUS (Read operation) – When I2C_Control_Register Bit 5=0 and Bit 4=1
X
(23)
IN2
(22)
IN3
(21)
IN4
(20)
1
(19)
1
(18)
1
(17)
1
(16)
Output Status and GP_Output Registers
Byte 2, Byte 1: These bytes control the digital outputs and HVOUT outputs during the write operation. The Output
Status and GP_Output register association with the outputs are shown in Figure 5-21. During the write operation,
the Gp_Output 1 and Gp_Output 2 registers are written with values specified in Byte 2 and Byte 1, when the
I2C_Control_Register bits 3 and 2 are set to 0x10b and bits 1 and 0 are set to 0x10b. During the
I2C_Data_Register read operation (I2C_Control_Register bits 3 and 2 = 0x00b and bits 1 and 0 = 0x00b), Byte 2
and Byte 1 return the GP_Output registers. If I2C_Control_Register bits 3 and 2 = 0x01b and bits 1 and 0 = 0x01b,
Byte 2 and Byte 1 will return the OUTPUT STATUS registers.
Figure 5-41. Output Status and GP_Output Registers, Byte 2
(0x0E) – GP_OUTPUT1 (Write operation) – When I2C_Control_Register Bit 3 =1, Bit 2=0
GP1
(15)
GP2
(14)
GP3_ENb
(13)
GP4
(12)
GP5
(11)
GP6
(10)
GP7
(9)
GP8
(8)
(0x0E) – GP_OUTPUT1 (Read Operation) – When I2C_Control_Register Bit 3 =0, Bit 2=0
GP1
(15)
GP2
(14)
GP3_ENb
(13)
GP4
(12)
GP5
(11)
GP6
(10)
GP7
(9)
GP8
(8)
(0x03) – OUTPUT_STATUS0 (Read Operation) – When I2C_Control_Register Bit 3 =0, Bit 2=1
HVOUT1
(15)
HVOUT2
(14)
OUT3
(13)
OUT4
(12)
OUT5
(11)
OUT6
(10)
OUT7
(9)
OUT8
(8)
Figure 5-42. Output Status and GP_Output Registers, Byte 1
(0x0F) – GP_OUTPUT2 (Write Operation) – When I2C_Control_Register Bit 1=1, Bit 0=0
GP9
(7)
GP10
(6)
GP11
(5)
GP12
(4)
GP13
(3)
GP14
(2)
X
(1)
X
(0)
(0x0F) – GP_OUTPUT2 (Read Operation) – When I2C_Control_Register Bit 1=0, Bit 0=0
GP9
(7)
GP10
(6)
GP11
(5)
GP12
(4)
GP13
(3)
GP14
(2)
X
(1)
X
(0)
(0x04) – OUTPUT_STATUS1 (Read Operation) – When I2C_Control_Register Bit 1=0, Bit 0=1
OUT9
(7)
OUT10
(6)
OUT11
(5)
OUT12
(4)
OUT13
(3)
OUT14
(2)
1
(1)
1
(0)
5-45
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
JTAG Access Method Example
This example shows various steps required to measure the voltage applied to the VMON5 of the ispPAC-
POWR1014A device. These steps include transition through the TAP states shown in Figure 5-32. This example
assumes that 5V is applied to VMON5.
Figure 5-43. VMON5 JTAG Access Example
TRST ON;
TRST OFF;
! --- I2C Control Register
SIR
! --- Set Bit 6 for ADC_MUX Register Write
SDR 12 TDI (040);
8
TDI (26);
STATE IDLE;
! --- end I2C Control Register
! --- I2C Data Register Write ADC convert
SIR
8
TDI (25);
! --- Set ADC Attenuate
! --- Set VMON Select Bits [3:0] to VMON5
SDR
72 TDI (000000000028000000);
! --- Wait 100us for ADC conversion
RUNTEST 1000 TCK;
STATE IDLE;
! --- end I2C Data Register Write ADC Convert
! --- I2C Data Register Read
SDR
72 TDI(xxxxxxxxxxxxxxxxxx) TDO (xxxxxxxxxxxxxxxxxx);
STATE IDLE;
! --- end I2C Data Register Read
5-46
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Table 5-13 shows the bit values of 72-bit I2C_Data_Register packet after POR.
Table 5-13. I2C_Data_Register Packet Reset Values
Equivalent I2C
Register Address
Register Name
vmon_status0
vmon_status1
vmon_status2
Read/Write
Description
Value After POR1
- - - - - - - -
0x00
0x01
0x02
R
R
R
VMON input status Vmon[1:4]
VMON input status Vmon[5:8]
VMON input status Vmon[9:10]
- - - - - - - -
- - - - XXXX
Output status HVOUT[1:2],
OUT[3:8],
0x03
output_status0
R
- - - - - - - -
0x04
0x06
0x07
0x08
0x09
0x0E
0x0F
0x11
output_status1
input_status
adc_value_low
adc_value_high
adc_mux
R
R
Output status OUT[9:14]
Input Status IN[2:4]
ADC D[0:3]
XX - - - - - -
X - - - XXXX
XXXX - - - -
- - - - - - XX
0000 0XXX
0000 0100
0000 00XX
X 000 XXXX
R
R
ADC D[4:11]
R/W
R/W
R/W
R/W
ADC Mux[0:3] & Attenuator
GPOUT[1:8]
gp_ouput1
gp_ouput2
GPOUT[9:14]
Input_value
PLD Input Register [2:4]
1. “X” = Non-functional bit (bits read out as 1's).
“-“ = State depends on device configuration of input status.
5-47
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Package Diagrams
48-Pin TQFP (Dimensions in Millimeters)
PIN 1 INDICATOR
0.20 H A-B
D
D1
0.20 C A-B D
D
N
1
3.
A
E1
E
B
3.
e
D
3.
4X
8.
SEE DETAIL "A"
H
GAUGE PLANE
0.25
A
A2
A1
b
C
SEATING PLANE
0.08
M
C A-B D
0.08 C
0.20 MIN.
1.00 REF.
LEAD FINISH
0-7∞
b
L
c
c
1
DETAIL "A"
b
1
BASE METAL
SECTION B - B
SYMBOL
MIN.
-
NOM.
-
MAX.
1.60
0.15
1.45
A
NOTES:
A1
A2
D
0.05
1.35
-
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
1.40
9.00 BSC
7.00 BSC
9.00 BSC
7.00 BSC
0.60
DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H.
3.
D1
E
4. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1
DIMENSIONS.
E1
L
0.45
0.75
5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM
OF THE PACKAGE BY 0.15 MM.
N
48
6. SECTION B-B:
e
0.50 BSC
0.22
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP.
b
0.17
0.17
0.09
0.09
0.27
0.23
0.20
0.16
b1
c
0.20
7. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
TO THE LOWEST POINT ON THE PACKAGE BODY.
0.15
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8.
c1
0.13
5-48
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Part Number Description
LA-ispPAC-POWR1014X - 01TN48E
Device Family
Device Number
Operating Temperature Range
E = Automotive (-40oC to +105oC TA)
Package
ADC Support
TN = Lead-Free 48-pin TQFP
A = ADC present
Performance Grade
01 = Standard
LA-ispPAC-POWR1014/A Ordering Information
Lead-Free Packaging
Part Number
Package
Pins
48
LA-ispPAC-POWR1014A-01TN48E
LA-ispPAC-POWR1014-01TN48E
Lead-Free TQFP
Lead-Free TQFP
48
Package Options
OUT14
1
36
35
34
33
32
31
30
29
28
27
26
25
VMON9
OUT13
OUT12
OUT11
2
VMON8
VMON7
VMON6
3
4
OUT10
OUT9
GNDD
OUT8
OUT7
OUT6
OUT5
OUT4
5
6
VMON5
GNDD
LA-ispPAC-POWR1014A
48-Pin TQFP
GNDA
7
8
9
VCCA
VMON4
VMON3
VMON2
VMON1
10
11
12
5-49
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Package Options (Cont.)
OUT14
OUT13
OUT12
OUT11
1
36
35
34
33
32
31
30
29
28
27
26
25
VMON9
VMON8
VMON7
VMON6
2
3
4
OUT10
OUT9
GNDD
OUT8
OUT7
OUT6
OUT5
OUT4
5
6
VMON5
GNDD
LA-ispPAC-POWR1014
48-Pin TQFP
GNDA
7
8
9
VCCA
VMON4
VMON3
VMON2
VMON1
10
11
12
Automotive Disclaimer
Products are not designed, intended or warranted to be fail-safe and are not designed, intended or warranted for
use in applications related to the deployment of airbags. Further, products are not intended to be used, designed or
warranted for use in applications that affect the control of the vehicle unless there is a fail-safe or redundancy fea-
ture and also a warning signal to the operator of the vehicle upon failure. Use of products in such applications is
fully at the risk of the customer, subject to applicable laws and regulations governing limitations on product liability.
Technical Support Assistance
e-mail: isppacs@latticesemi.com
Internet: www.latticesemi.com
5-50
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
Revision History
Date
Version
Change Summary
January 2008
June 2008
01.0
01.1
Initial release.
Added timing diagram and timing parameters to “Power-On Reset” specifications.
Modified PLD Architecture figure to show input registers.
Updated I2C Control Registers table.
VCCPROG pin usage clarification added.
Added automotive disclaimer text section.
Updated document with new corporate logo.
June 2012
01.2
01.3
Added device performance at 125°C, recommended operating conditions and voltage
monitors.
Added “Accessing I2C Registers through JTAG (LA-ispPAC-POWR1014A Only)” section.
September 2013
Renamed VCCPROG pin APS. Added ADC Typical Error below 600mV.
Typographical correction: OUT5/SMBA changed to OUT3/SMBA (Figure 5-15).
Added the LA-ispPAC-POWR1014/A JTAG Interconnection Configuration Diagram
(Figure 5-27).
Changed the LA-ispPAC-POWR1014/A Alternate TDI Configuration Diagram figure to LA-
ispPAC-POWR1014/A Alternate Configuration Diagram (Figure 5-28).
Updated Technical Support Assistance information.
5-51
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