LAMXO640LUTSC-3FTN256E

LA-MachXO Automotive Family Data Sheet

DS1003 Version 01.5, November 2007

LA-MachXO Automotive Family Data Sheet

Introduction

April 2006

Data Sheet DS1003

• Programmable sysIO™ buffer supports wide

range of interfaces:

Features

■ Non-volatile, Inﬁnitely Reconﬁgurable

• Instant-on – powers up in microseconds

• Single chip, no external conﬁguration memory

required

− LVCMOS 3.3/2.5/1.8/1.5/1.2

− LVTTL

− PCI

− LVDS, Bus-LVDS, LVPECL, RSDS

• Excellent design security, no bit stream to

intercept

• Reconﬁgure SRAM based logic in milliseconds

• SRAM and non-volatile memory programmable

through JTAG port

■ sysCLOCK™ PLLs

• Up to two analog PLLs per device

• Clock multiply, divide, and phase shifting

■ System Level Support

• IEEE Standard 1149.1 Boundary Scan

• Onboard oscillator

• Supports background programming of

non-volatile memory

• Devices operate with 3.3V, 2.5V, 1.8V or 1.2V

power supply

• IEEE 1532 compliant in-system programming

■ AEC-Q100 Tested and Qualiﬁed

■ Sleep Mode

• Allows up to 100x static current reduction

■ TransFR™ Reconﬁguration (TFR)

Introduction

• In-ﬁeld logic update while system operates

The LA-MachXO automotive device family is optimized

to meet the requirements of applications traditionally

addressed by CPLDs and low capacity FPGAs: glue

logic, bus bridging, bus interfacing, power-up control,

and control logic. These devices bring together the best

features of CPLD and FPGA devices on a single chip in

AEC-Q100 tested and qualiﬁed versions.

■ High I/O to Logic Density

• 256 to 2280 LUT4s

• 73 to 271 I/Os with extensive package options

• Density migration supported

• Lead free/RoHS compliant packaging

■ Embedded and Distributed Memory

• Up to 27.6 Kbits sysMEM™ Embedded Block

RAM

The devices use look-up tables (LUTs) and embedded

block memories traditionally associated with FPGAs for

ﬂexible and efﬁcient logic implementation. Through non-

volatile technology, the devices provide the single-chip,

• Up to 7.5 Kbits distributed RAM

• Dedicated FIFO control logic

■ Flexible I/O Buffer

Table 1-1. LA-MachXO Automotive Family Selection Guide

Device

LAMXO256E/C

LAMXO640E/C

LAMXO1200E

LAMXO2280E

LUTs

256

640

1200

6.25

9.2

1

2280

7.5

27.6

3

Dist. RAM (Kbits)

EBR SRAM (Kbits)

2.0

6.0

0

Number of EBR SRAM Blocks (9 Kbits)

Voltage

0

V

1.2/1.8/2.5/3.3V

1.2

1

1.2

2

CC

Number of PLLs

0

Max. I/O

78

159

211

271

Packages

100-pin Lead-Free TQFP (14x14 mm)

144-pin Lead-Free TQFP (20x20 mm)

256-ball Lead-Free ftBGA (17x17 mm)

324-ball Lead-Free ftBGA (19x19 mm)

78

74

73

113

159

113

211

113

211

271

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

1-1

DS1003 Introduction_01.0

Introduction

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

high-security, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and

careful design will provide the high pin-to-pin performance also associated with CPLDs.

The ispLEVER^®design tools from Lattice allow complex designs to be efﬁciently implemented using the LA-

MachXO automotive family of devices. Popular logic synthesis tools provide synthesis library support for LA-

MachXO. The ispLEVER tools use the synthesis tool output along with the constraints from its ﬂoor planning tools

to place and route the design in the LA-MachXO device. The ispLEVER tool extracts the timing from the routing

and back-annotates it into the design for timing veriﬁcation.

1-2

LA-MachXO Automotive Family Data Sheet

Architecture

February 2007

Data Sheet DS1003

Architecture Overview

The LA-MachXO family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO).

Some devices in this family have sysCLOCK PLLs and blocks of sysMEM™ Embedded Block RAM (EBRs). Fig-

ures 2-1, 2-2, and 2-3 show the block diagrams of the various family members.

The logic blocks are arranged in a two-dimensional grid with rows and columns. The EBR blocks are arranged in a

column to the left of the logic array. The PIO cells are located at the periphery of the device, arranged into Banks.

The PIOs utilize a ﬂexible I/O buffer referred to as a sysIO interface that supports operation with a variety of inter-

face standards. The blocks are connected with many vertical and horizontal routing channel resources. The place

and route software tool automatically allocates these routing resources.

There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and the Programmable Functional

unit without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and register func-

tions. The PFF block contains building blocks for logic, arithmetic, ROM, and register functions. Both the PFU and

PFF blocks are optimized for ﬂexibility, allowing complex designs to be implemented quickly and effectively. Logic

blocks are arranged in a two-dimensional array. Only one type of block is used per row.

In the LA-MachXO family, the number of sysIO Banks varies by device. There are different types of I/O Buffers on

different Banks. See the details in later sections of this document. The sysMEM EBRs are large, dedicated fast

memory blocks; these blocks are found only in the larger devices. These blocks can be conﬁgured as RAM, ROM

or FIFO. FIFO support includes dedicated FIFO pointer and ﬂag “hard” control logic to minimize LUT use.

The LA-MachXO architecture provides up to two sysCLOCK™ Phase Locked Loop (PLL) blocks on larger devices.

These blocks are located at either end of the memory blocks. The PLLs have multiply, divide, and phase shifting

capabilities that are used to manage the frequency and phase relationships of the clocks.

Every device in the family has a JTAG Port that supports programming and conﬁguration of the device as well as

access to the user logic.The LA-MachXO devices are available for operation from 3.3V, 2.5V, 1.8V, and 1.2V power

supplies, providing easy integration into the overall system.

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

2-1

DS1003 Architecture_01.2

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Figure 2-1. Top View of the LA-MachXO1200 Device¹

PIOs Arranged into

sysIO Banks

Programmable

Functional Units

with RAM (PFUs)

sysMEM Embedded

Block RAM (EBR)

Programmable

Functional Units

without RAM (PFFs)

sysCLOCK

PLL

JTAG Port

1. Top view of the LA-MachXO2280 device is similar but with higher LUT count, two PLLs, and three EBR blocks.

Figure 2-2. Top View of the LA-MachXO640 Device

PIOs Arranged into

sysIO Banks

Programmable

Function Units

without RAM (PFFs)

Programmable

Function Units

with RAM (PFUs)

JTAG Port

2-2

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Figure 2-3. Top View of the LA-MachXO256 Device

Programmable Function

Units without RAM (PFFs)

JTAG Port

PIOs Arranged

into sysIO Banks

Programmable

Function

Units with

RAM (PFUs)

PFU Blocks

The core of the LA-MachXO devices consists of PFU and PFF blocks. The PFUs can be programmed to perform

Logic, Arithmetic, Distributed RAM, and Distributed ROM functions. PFF blocks can be programmed to perform

Logic, Arithmetic, and Distributed ROM functions. Except where necessary, the remainder of this data sheet will

use the term PFU to refer to both PFU and PFF blocks.

Each PFU block consists of four interconnected Slices, numbered 0-3 as shown in Figure 2-4. There are 53 inputs

and 25 outputs associated with each PFU block.

Figure 2-4. PFU Diagram

From

Routing

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

FCIN

FCO

Slice 3

Slice 0

Slice 1

Slice 2

D

FF/

D

FF/

D

FF/

Latch

To

Routing

Slice

Each Slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and

some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7, and

LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock

select, chip-select, and wider RAM/ROM functions. Figure 2-5 shows an overview of the internal logic of the Slice.

The registers in the Slice can be conﬁgured for positive/negative and edge/level clocks.

2-3

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

There are 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent Slice/PFU).

There are 7 outputs: 6 to the routing and one to the carry-chain (to the adjacent Slice/PFU). Table 2-1 lists the sig-

nals associated with each Slice.

Figure 2-5. Slice Diagram

To Adjacent Slice/PFU

Slice

OFX1

F1

A1

B1

C1

D1

CO

F

Fast Connection

to I/O Cell*

LUT4 &

CARRY

D

SUM

FF/

Latch

Q1

CI

To

From

Routing

M1

M0

OFX0

LUT

Expansion

Mux

Fast Connection

to I/O Cell*

CO

A0

B0

F0

C0

LUT4 &

CARRY

F

D0

OFX0

SUM

D

FF/

Latch

Q0

CI

Control Signals

selected and

inverted per

CE

CLK

LSR

Slice in routing

From Adjacent Slice/PFU

Notes:

Some inter-Slice signals are not shown.

* Only PFUs at the edges have fast connections to the I/O cell.

Table 2-1. Slice Signal Descriptions

Function

Input

Type

Signal Names

Description

Data signal

A0, B0, C0, D0 Inputs to LUT4

A1, B1, C1, D1 Inputs to LUT4

Input

Data signal

Input

Multi-purpose

Control signal

Inter-PFU signal

Data signals

Inter-PFU signal

M0/M1

CE

Multipurpose Input

Clock Enable

Input

LSR

Local Set/Reset

System Clock

Fast Carry In¹

Input

CLK

Input

FCIN

F0, F1

Q0, Q1

OFX0

OFX1

FCO

Output

LUT4 output register bypass signals

Register Outputs

Output of a LUT5 MUX

Output of a LUT6, LUT7, LUT8²MUX depending on the Slice

Fast Carry Out¹

1. See Figure 2-4 for connection details.

2. Requires two PFUs.

2-4

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Modes of Operation

Each Slice is capable of four modes of operation: Logic, Ripple, RAM, and ROM. The Slice in the PFF is capable of

all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks.

Table 2-2. Slice Modes

Logic

Ripple

RAM

SP 16x2

N/A

ROM

PFU Slice

PFF Slice

LUT 4x2 or LUT 5x1

2-bit Arithmetic Unit

ROM 16x1 x 2

Logic Mode: In this mode, the LUTs in each Slice are conﬁgured as 4-input combinatorial lookup tables (LUT4). A

LUT4 can have 16 possible input combinations. Any logic function with four inputs can be generated by program-

ming this lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger

lookup tables such as LUT6, LUT7, and LUT8 can be constructed by concatenating other Slices.

Ripple Mode: Ripple mode allows the efﬁcient implementation of small arithmetic functions. In ripple mode, the fol-

lowing functions can be implemented by each Slice:

• Addition 2-bit

• Subtraction 2-bit

• Add/Subtract 2-bit using dynamic control

• Up counter 2-bit

• Down counter 2-bit

• Ripple mode multiplier building block

• Comparator functions of A and B inputs

- A greater-than-or-equal-to B

- A not-equal-to B

- A less-than-or-equal-to B

Two additional signals, Carry Generate and Carry Propagate, are generated per Slice in this mode, allowing fast

arithmetic functions to be constructed by concatenating Slices.

RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x2-bit memory.

Through the combination of LUTs and Slices, a variety of different memories can be constructed.

The ispLEVER design tool supports the creation of a variety of different size memories. Where appropriate, the

software will construct these using distributed memory primitives that represent the capabilities of the PFU.

Table 2-3 shows the number of Slices required to implement different distributed RAM primitives. Figure 2-6 shows

the distributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices. One Slice

functions as the read-write port, while the other companion Slice supports the read-only port. For more information

on RAM mode in LA-MachXO devices, please see details of additional technical documentation at the end of this

data sheet.

Table 2-3. Number of Slices Required For Implementing Distributed RAM

SPR16x2

DPR16x2

Number of Slices

1

2

Note: SPR = Single Port RAM, DPR = Dual Port RAM

2-5

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Figure 2-6. Distributed Memory Primitives

SPR16x2

DPR16x2

AD0

AD1

AD2

AD3

RAD0

RAD1

RAD2

RAD3

WAD0

WAD1

WAD2

WAD3

DO0

DO1

DI0

DI1

WRE

DI0

DI1

WCK

WRE

RDO0

RDO1

WDO0

WDO1

CK

ROM16x1

AD0

AD1

AD2

AD3

DO0

ROM Mode:The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is

accomplished through the programming interface during conﬁguration.

PFU Modes of Operation

Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the

functionality possible at the PFU level.

Table 2-4. PFU Modes of Operation

Logic

Ripple

RAM

ROM

LUT 4x8 or

MUX 2x1 x 8

SPR16x2 x 4

DPR16x2 x 2

2-bit Add x 4

ROM16x1 x 8

LUT 5x4 or

MUX 4x1 x 4

SPR16x4 x 2

DPR16x4 x 1

2-bit Sub x 4

2-bit Counter x 4

2-bit Comp x 4

ROM16x2 x 4

ROM16x4 x 2

ROM16x8 x 1

LUT 6x 2 or

MUX 8x1 x 2

SPR16x8 x 1

LUT 7x1 or

MUX 16x1 x 1

Routing

There are many resources provided in the LA-MachXO devices to route signals individually or as buses with

related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing)

segments.

The inter-PFU connections are made with three different types of routing resources: x1 (spans two PFUs), x2

(spans three PFUs) and x6 (spans seven PFUs). The x1, x2, and x6 connections provide fast and efﬁcient connec-

tions in the horizontal and vertical directions.

2-6

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the

place and route tool is completely automatic, although an interactive routing editor is available to optimize the

design.

Clock/Control Distribution Network

The LA-MachXO automotive family of devices provides global signals that are available to all PFUs. These signals

consist of four primary clocks and four secondary clocks. Primary clock signals are generated from four 16:1 muxes

as shown in Figure 2-7 and Figure 2-8. The available clock sources for the LA-MachXO256 and LA-MachXO640

devices are four dual function clock pins and 12 internal routing signals. The available clock sources for the LA-

MachXO1200 and LA-MachXO2280 devices are four dual function clock pins, up to nine internal routing signals

and up to six PLL outputs.

Figure 2-7. Primary Clocks for LA-MachXO256 and LA-MachXO640 Devices

12

4

Primary Clock 0

Primary Clock 1

16:1

Primary Clock 2

Primary Clock 3

16:1

Routing Clock

Pads

2-7

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Figure 2-8. Primary Clocks for LA-MachXO1200 and LA-MachXO2280 Devices

Up to 9

Up to 6

4

Primary Clock 0

Primary Clock 1

16:1

Primary Clock 2

Primary Clock 3

16:1

Routing Clock

PLL

Pads Outputs

Four secondary clocks are generated from four 16:1 muxes as shown in Figure 2-9. Four of the secondary clock

sources come from dual function clock pins and 12 come from internal routing.

Figure 2-9. Secondary Clocks for LA-MachXO Devices

12

4

16:1

Secondary (Control)

Clocks

16:1

Routing Clock

Pads

2-8

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

sysCLOCK Phase Locked Loops (PLLs)

The LA-MachXO1200 and LA-MachXO2280 provide PLL support. The source of the PLL input divider can come

from an external pin or from internal routing. There are four sources of feedback signals to the feedback divider:

from CLKINTFB (internal feedback port), from the global clock nets, from the output of the post scalar divider, and

from the routing (or from an external pin).There is a PLL_LOCK signal to indicate that the PLL has locked on to the

input clock signal. Figure 2-10 shows the sysCLOCK PLL diagram.

The setup and hold times of the device can be improved by programming a delay in the feedback or input path of

the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either pro-

grammed during conﬁguration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after

adjustment and not relock until the t

parameter has been satisﬁed. Additionally, the phase and duty cycle block

LOCK

allows the user to adjust the phase and duty cycle of the CLKOS output.

The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated

with it: input clock divider, feedback divider, post scalar divider, and secondary clock divider. The input clock divider

is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal.The post

scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the fre-

quency range. The secondary divider is used to derive lower frequency outputs.

Figure 2-10. PLL Diagram

Dynamic Delay Adjustment

LOCK

RST

Input Clock

Divider

(CLKI)

Post Scalar

Divider

(CLKOP)

Phase/Duty

Select

Voltage

ConVtCroOlled

Oscillator

CLKOS

Delay

Adjust

CLKI

(from routing or

external pin)

CLKOP

CLKOK

Secondary

Clock

Divider

Feedback

Divider

(CLKFB)

CLKFB

(from Post Scalar

Divider output,

clock net,

(CLKOK)

routing/external

pin or CLKINTFB

port

CLKINTFB

(internal feedback)

Figure 2-11 shows the available macros for the PLL. Table 2-5 provides signal description of the PLL Block.

Figure 2-11. PLL Primitive

RST

CLKOP

CLKI

CLKFB

CLKOS

CLKOK

LOCK

DDA MODE

DDAIZR

EHXPLLC

DDAILAG

CLKINTFB

DDAIDEL[2:0]

2-9

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Table 2-5. PLL Signal Descriptions

Signal

I/O

Description

CLKI

I

Clock input from external pin or routing

PLL feedback input from PLL output, clock net, routing/external pin or internal feedback from

CLKINTFB port

CLKFB

RST

I

O

I

“1” to reset the input clock divider

CLKOS

PLL output clock to clock tree (phase shifted/duty cycle changed)

PLL output clock to clock tree (No phase shift)

PLL output to clock tree through secondary clock divider

“1” indicates PLL LOCK to CLKI

CLKOP

CLKOK

LOCK

CLKINTFB

DDAMODE

DDAIZR

DDAILAG

DDAIDEL[2:0]

Internal feedback source, CLKOP divider output before CLOCKTREE

Dynamic Delay Enable. “1”: Pin control (dynamic), “0”: Fuse Control (static)

Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on

Dynamic Delay Lag/Lead. “1”: Lag, “0”: Lead

I

Dynamic Delay Input

For more information on the PLL, please see details of additional technical documentation at the end of this data

sheet.

sysMEM Memory

The LA-MachXO1200 and LA-MachXO2280 devices contain sysMEM Embedded Block RAMs (EBRs). The EBR

consists of a 9-Kbit RAM, with dedicated input and output registers.

sysMEM Memory Block

The sysMEM block can implement single port, dual port, pseudo dual port, or FIFO memories. Each block can be

used in a variety of depths and widths as shown in Table 2-6.

Table 2-6. sysMEM Block Conﬁgurations

Memory Mode

Conﬁgurations

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

256 x 36

Single Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

True Dual Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

256 x 36

Pseudo Dual Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

256 x 36

FIFO

2-10

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Bus Size Matching

All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB

word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for

each port varies, this mapping scheme applies to each port.

RAM Initialization and ROM Operation

If desired, the contents of the RAM can be pre-loaded during device conﬁguration. By preloading the RAM block

during the chip conﬁguration cycle and disabling the write controls, the sysMEM block can also be utilized as a

ROM.

Memory Cascading

Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools

cascade memory transparently, based on speciﬁc design inputs.

Single, Dual, Pseudo-Dual Port and FIFO Modes

Figure 2-12 shows the ﬁve basic memory conﬁgurations and their input/output names. In all the sysMEM RAM

modes, the input data and address for the ports are registered at the input of the memory array. The output data of

the memory is optionally registered at the memory array output.

Figure 2-12. sysMEM Memory Primitives

ADA[12:0]

DIA[17:0]

CLKA

CEA

RSTA

WEA

CSA[2:0]

DOA[17:0]

ADB[12:0]

DIB[17:0]

CEB

CLKB

RSTB

WEB

CSB[2:0]

DOB[17:0]

AD[12:0]

DI[35:0]

CLK

DO[35:0]

CE

EBR

RST

WE

CS[2:0]

True Dual Port RAM

Single Port RAM

ADW[12:0]

DI[35:0]

CLKW

CEW

ADR[12:0]

DO[35:0]

AD[12:0]

CLK

DO[35:0]

CE

EBR

ROM

EBR

WE

RST

CS[2:0]

CER

RST

CS[2:0]

CLKR

Pseudo-Dual Port RAM

DO[35:0]

CLKR

RSTB

RE

RCE

FF

DI[35:0]

CLKW

RSTA

WE

EBR

CEW

AF

EF

AE

FIFO

2-11

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

The EBR memory supports three forms of write behavior for single or dual port operation:

1. Normal – data on the output appears only during the read cycle. During a write cycle, the data (at the current

address) does not appear on the output. This mode is supported for all data widths.

2. WriteThrough – a copy of the input data appears at the output of the same port.This mode is supported for all

data widths.

3. Read-Before-Write – when new data is being written, the old contents of the address appears at the output.

This mode is supported for x9, x18 and x36 data widths.

FIFO Conﬁguration

The FIFO has a write port with Data-in, CEW, WE and CLKW signals. There is a separate read port with Data-out,

RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The

Full and Almost Full ﬂags are registered with CLKW. The Empty and Almost Empty ﬂags are registered with CLKR.

The range of programming values for these ﬂags are in Table 2-7.

Table 2-7. Programmable FIFO Flag Ranges

Flag Name

Programming Range

1 to (up to 2^N-1)

1 to Full-1

Full (FF)

Almost Full (AF)

Almost Empty (AE)

Empty (EF)

1 to Full-1

0

N = Address bit width

The FIFO state machine supports two types of reset signals: RSTA and RSTB. The RSTA signal is a global reset

that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO ﬂags in their initial reset

state. The RSTB signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is in

the FIFO. In these applications it is important to keep careful track of when a packet is written into or read from the

FIFO.

Memory Core Reset

The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-

nously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B respec-

tively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both

ports are as shown in Figure 2-13.

2-12

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Figure 2-13. Memory Core Reset

SET

D

Q

Memory Core

Port A[17:0]

Port B[17:0]

L_CLR

Output Data

Latches

SET

D

Q

L_CLR

RSTA

RSTB

GSRN

Programmable Disable

For further information on the sysMEM EBR block, see the details of additional technical documentation at the end

of this data sheet.

EBR Asynchronous Reset

EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the

reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-14. The GSR input to the

EBR is always asynchronous.

Figure 2-14. EBR Asynchronous Reset (Including GSR) Timing Diagram

Reset

Clock

Enable

If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after

the EBR read and write clock inputs are in a steady state condition for a minimum of 1/f

(EBR clock). The reset

MAX

release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.

If an EBR is pre-loaded during conﬁguration, the GSR input must be disabled or the release of the GSR during

device Wake Up must occur before the release of the device I/Os becoming active.

These instructions apply to all EBR RAM, ROM and FIFO implementations. For the EBR FIFO mode, the GSR sig-

nal is always enabled and the WE and RE signals act like the clock enable signals in Figure 2-14. The reset timing

rules apply to the RPReset input vs the RE input and the RST input vs. the WE and RE inputs. Both RST and

RPReset are always asynchronous EBR inputs.

Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.

2-13

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

PIO Groups

On the LA-MachXO devices, PIO cells are assembled into two different types of PIO groups, those with four PIO

cells and those with six PIO cells. PIO groups with four IOs are placed on the left and right sides of the device while

PIO groups with six IOs are placed on the top and bottom. The individual PIO cells are connected to their respec-

tive sysIO buffers and PADs.

On all LA-MachXO devices, two adjacent PIOs can be joined to provide a complementary Output driver pair. The I/

O pin pairs are labeled as "T" and "C" to distinguish between the true and complement pins.

The LA-MachXO1200 and LA-MachXO2280 devices contain enhanced I/O capability. All PIO pairs on these larger

devices can implement differential receivers. In addition, half of the PIO pairs on the left and right sides of these

devices can be conﬁgured as LVDS transmit/receive pairs. PIOs on the top of these larger devices also provide PCI

support.

Figure 2-15. Group of Four Programmable I/O Cells

This structure is used on the

left and right of MachXO devices

PADA "T"

PIO A

PADB "C"

PIO B

Four PIOs

PADC "T"

PIO C

PADD "C"

PIO D

Figure 2-16. Group of Six Programmable I/O Cells

This structure is used on the top

and bottom of MachXO devices

PADA "T"

PIO A

PADB "C"

PIO B

PADC "T"

PIO C

Six PIOs

PADD "C"

PIO D

PADE "T"

PIO E

PADF "C"

PIO F

PIO

The PIO blocks provide the interface between the sysIO buffers and the internal PFU array blocks. These blocks

receive output data from the PFU array and a fast output data signal from adjacent PFUs. The output data and fast

2-14

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

output data signals are multiplexed and provide a single signal to the I/O pin via the sysIO buffer. Figure 2-17

shows the LA-MachXO PIO logic.

The tristate control signal is multiplexed from the output data signals and their complements. In addition a global

signal (TSALL) from a dedicated pad can be used to tristate the sysIO buffer.

The PIO receives an input signal from the pin via the sysIO buffer and provides this signal to the core of the device.

In addition there are programmable elements that can be utilized by the design tools to avoid positive hold times.

Figure 2-17. LA-MachXO PIO Block Diagram

From Routing

TS

TSALL

TO

sysIO

Buffer

Fast Output

Data signal

DO

PAD

1

Input

Data Signal

2

3

Programmable

Delay Elements

4⁺_-

Note: Buffer 1 tracks with V

Buffer 2 tracks with V

CCAUX

CCIO.

From Complementary

Pad

Buffer 3 tracks with internal 1.2V V

Buffer 4 is available in MachXO1200 and MachXO2280 devices only.

.

REF

sysIO Buffer

Each I/O is associated with a ﬂexible buffer referred to as a sysIO buffer. These buffers are arranged around the

periphery of the device in groups referred to as Banks. The sysIO buffers allow users to implement the wide variety

of standards that are found in today’s systems including LVCMOS, TTL, BLVDS, LVDS and LVPECL.

In the LA-MachXO devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are

powered using V

. In addition to the Bank V

supplies, the LA-MachXO devices have a V core logic power

CCIO

CCIO CC

supply, and a V

input buffers.

supply that powers up a variety of internal circuits including all the differential and referenced

CCAUX

LA-MachXO256 and LA-MachXO640 devices contain single-ended input buffers and single-ended output buffers

with complementary outputs on all the I/O Banks.

LA-MachXO1200 and LA-MachXO2280 devices contain two types of sysIO buffer pairs.

1. Top and Bottom sysIO Buffer Pairs

The sysIO buffer pairs in the top and bottom Banks of the device consist of two single-ended output drivers and

two sets of single-ended input buffers (for ratioed or absolute input levels). The I/O pairs on the top and bottom

2-15

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

of the devices also support differential input buffers. PCI clamps are available on the top Bank I/O buffers. The

PCI clamp is enabled after V , V , and V are at valid operating levels and the device has been con-

CC CCAUX

CCIO

ﬁgured.

The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive

side of the differential input buffer and the comp (complementary) pad is associated with the negative side of

the differential input buffer.

2. Left and Right sysIO Buffer Pairs

The sysIO buffer pairs in the left and right Banks of the device consist of two single-ended output drivers and

two sets of single-ended input buffers (supporting ratioed and absolute input levels). The devices also have a

differential driver per output pair. The referenced input buffer can also be conﬁgured as a differential input

buffer. In these Banks the two pads in the pair are described as “true” and “comp”, where the true pad is asso-

ciated with the positive side of the differential I/O, and the comp (complementary) pad is associated with the

negative side of the differential I/O.

Typical I/O Behavior During Power-up

The internal power-on-reset (POR) signal is deactivated when V and V

have reached satisfactory levels.

CC

CCAUX

After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure

that all V Banks are active with valid input logic levels to properly control the output logic states of all the I/O

CCIO

Banks that are critical to the application. The default conﬁguration of the I/O pins in a blank device is tri-state with a

weak pull-up to VCCIO. The I/O pins will maintain the blank conﬁguration until VCC, VCCAUX and VCCIO have

reached satisfactory levels at which time the I/Os will take on the user-conﬁgured settings.

The V and V

supply the power to the FPGA core fabric, whereas the V

supplies power to the I/O buff-

CC

CCAUX

CCIO

ers. In order to simplify system design while providing consistent and predictable I/O behavior, the I/O buffers

should be powered up along with the FPGA core fabric. Therefore, V supplies should be powered up before or

CCIO

together with the V and V

supplies

CC

CCAUX

Supported Standards

The LA-MachXO sysIO buffer supports both single-ended and differential standards. Single-ended standards can

be further subdivided into LVCMOS and LVTTL. The buffer supports the LVTTL, LVCMOS 1.2, 1.5, 1.8, 2.5, and

3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually conﬁgurable options for drive

strength, bus maintenance (weak pull-up, weak pull-down, bus-keeper latch or none) and open drain. BLVDS and

LVPECL output emulation is supported on all devices.The LA-MachXO1200 and LA-MachXO2280 support on-chip

LVDS output buffers on approximately 50% of the I/Os on the left and right Banks. Differential receivers for LVDS,

BLVDS and LVPECL are supported on all Banks of LA-MachXO1200 and LA-MachXO2280 devices. PCI support is

provided in the top Banks of the LA-MachXO1200 and LA-MachXO2280 devices. Table 2-8 summarizes the I/O

characteristics of the devices in the LA-MachXO family.

Tables 2-9 and 2-10 show the I/O standards (together with their supply and reference voltages) supported by the

LA-MachXO devices. For further information on utilizing the sysIO buffer to support a variety of standards please

see the details of additional technical documentation at the end of this data sheet.

2-16

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Table 2-8. I/O Support Device by Device

LA-MachXO256

LA-MachXO640

LA-MachXO1200

LA-MachXO2280

Number of I/O Banks

Type of Input Buffers

2

4

8

Single-ended

(all I/O Banks)

Single-ended

(all I/O Banks)

Single-ended

(all I/O Banks)

Single-ended

(all I/O Banks)

Differential Receivers

(all I/O Banks)

Differential Receivers

(all I/O Banks)

Single-ended buffers

with complementary

Single-ended buffers

with complementary

Single-ended buffers

with complementary

Single-ended buffers

with complementary

outputs (all I/O Banks) outputs (all I/O Banks) outputs (all I/O Banks) outputs (all I/O Banks)

Types of Output Buffers

Differential buffers with Differential buffers with

true LVDS outputs (50% true LVDS outputs (50%

on left and right side)

Differential Output

Emulation Capability

All I/O Banks

No

All I/O Banks

No

All I/O Banks

PCI Support

Top side only

Table 2-9. Supported Input Standards

VCCIO (Typ.)

Input Standard

3.3V

2.5V

1.8V

1.5V

1.2V

Single Ended Interfaces

LVTTL

√

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

√

LVCMOS12

PCI¹

√

Differential Interfaces

BLVDS², LVDS², LVPECL², RSDS²

√

1. Top Banks of LA-MachXO1200 and LA-MachXO2280 devices only.

2. LA-MachXO1200 and LA-MachXO2280 devices only.

2-17

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Table 2-10. Supported Output Standards

Output Standard

Single-ended Interfaces

LVTTL

Drive

V

(Typ.)

CCIO

4mA, 8mA, 12mA, 16mA

4mA, 8mA, 12mA, 14mA

4mA, 8mA

3.3

LVCMOS33

3.3

2.5

1.8

1.5

1.2

—

LVCMOS25

LVCMOS18

LVCMOS15

LVCMOS12

2mA, 6mA

LVCMOS33, Open Drain

LVCMOS25, Open Drain

LVCMOS18, Open Drain

LVCMOS15, Open Drain

LVCMOS12, Open Drain

PCI33³

4mA, 8mA, 12mA, 14mA

4mA, 8mA

—

2mA, 6mA

—

N/A

3.3

Differential Interfaces

LVDS^{1, 2}

BLVDS, RSDS²

N/A

2.5

3.3

LVPECL²

1. LA-MachXO1200 and LA-MachXO2280 devices have dedicated LVDS buffers.

2. These interfaces can be emulated with external resistors in all devices.

3. Top Banks of LA-MachXO1200 and LA-MachXO2280 devices only.

sysIO Buffer Banks

The number of Banks vary between the devices of this family. Eight Banks surround the two larger devices, the LA-

MachXO1200 and LA-MachXO2280 (two Banks per side). The LA-MachXO640 has four Banks (one Bank per

side). The smallest member of this family, the LA-MachXO256, has only two Banks.

Each sysIO buffer Bank is capable of supporting multiple I/O standards. Each Bank has its own I/O supply voltage

(V

) which allows it to be completely independent from the other Banks. Figure 2-18, Figure 2-18, Figure 2-20

CCIO

and Figure 2-21 shows the sysIO Banks and their associated supplies for all devices.

2-18

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Figure 2-18. LA-MachXO2280 Banks

1

35

1

36

1

Bank 0

Bank 1

V_CCIO2

GND

V_CCIO7

GND

34

1

34

1

V_CCIO6

GND

V_CCIO3

GND

33

1

33

Bank 5

Bank 4

31

1

35

Figure 2-19. LA-MachXO1200 Banks

1

24

1

30

1

Bank 0

Bank 1

V_CCIO2

GND

V_CCIO7

GND

26

1

26

1

V_CCIO6

GND

V_CCIO3

GND

28

1

28

Bank 5

Bank 4

20

1

29

2-19

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Figure 2-20. LA-MachXO640 Banks

1

42

1

Bank 0

V_CCO3

GND

V_CCO1

GND

40

1

40

37

Bank 2

Figure 2-21. LA-MachXO256 Banks

V_CCO0

GND

1

Bank 0

41

37

Bank 1

GND

V _CCO1

Hot Socketing

The LA-MachXO automotive devices have been carefully designed to ensure predictable behavior during power-

up and power-down. Leakage into I/O pins is controlled to within speciﬁed limits. This allows for easy integration

2-20

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

with the rest of the system. These capabilities make the LA-MachXO ideal for many multiple power supply and

hot-swap applications.

Sleep Mode

The LA-MachXO “C” devices (V

= 1.8/2.5/3.3V) have a sleep mode that allows standby current to be reduced

CC

dramatically during periods of system inactivity. Entry and exit to Sleep mode is controlled by the SLEEPN pin.

During Sleep mode, the logic is non-operational, registers and EBR contents are not maintained, and I/Os are tri-

stated. Do not enter Sleep mode during device programming or conﬁguration operation. In Sleep mode, power sup-

plies are in their normal operating range, eliminating the need for external switching of power supplies. Table 2-11

compares the characteristics of Normal, Off and Sleep modes.

Table 2-11. Characteristics of Normal, Off and Sleep Modes

Characteristic

SLEEPN Pin

Normal

High

Off

Sleep

Low

—

0

Static Icc

Typical <10mA

<10µA

Typical <100uA

<10µA

I/O Leakage

<1mA

Power Supplies VCC/VCCIO/VCCAUX

Logic Operation

Normal Range

User Deﬁned

Operational

Maintained

0

Normal Range

Non operational

Tri-state

Non Operational

Tri-state

I/O Operation

JTAG and Programming circuitry

EBR Contents and Registers

Non-operational

Non-maintained

Non-operational

Non-maintained

SLEEPN Pin Characteristics

The SLEEPN pin behaves as an LVCMOS input with the voltage standard appropriate to the VCC supply for the

device. This pin also has a weak pull-up, along with a Schmidt trigger and glitch ﬁlter to prevent false triggering. An

external pull-up to VCC is recommended when Sleep Mode is not used to ensure the device stays in normal oper-

ation mode. Typically, the device enters sleep mode several hundred nanoseconds after SLEEPN is held at a valid

low and restarts normal operation as speciﬁed in the Sleep Mode Timing table. The AC and DC speciﬁcations por-

tion of this data sheet shows a detailed timing diagram.

Oscillator

Every LA-MachXO device has an internal CMOS oscillator. The oscillator can be routed as an input clock to the

clock tree or to general routing resources. The oscillator frequency can be divided by internal logic. There is a ded-

icated programming bit to enable/disable the oscillator. The oscillator frequency ranges from 16MHz to 26MHz.

Conﬁguration and Testing

The following section describes the conﬁguration and testing features of the LA-MachXO automotive family of

devices.

IEEE 1149.1-Compliant Boundary Scan Testability

All LA-MachXO devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test

access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a

serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to

be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for veriﬁcation.The test

access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port shares its power supply with

one of the VCCIO Banks (LA-MachXO256: V

; LA-MachXO640: V

; LA-MachXO1200 and LA-

CCIO1

CCIO2

MachXO2280: V

) and can operate with LVCMOS3.3, 2.5, 1.8, 1.5, and 1.2 standards.

CCIO5

For more details on boundary scan test, please see information regarding additional technical documentation at

the end of this data sheet.

2-21

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Device Conﬁguration

All LA-MachXO devices contain a test access port that can be used for device conﬁguration and programming.

The non-volatile memory in the LA-MachXO can be conﬁgured in two different modes:

• In IEEE 1532 mode via the IEEE 1149.1 port. In this mode, the device is off-line and I/Os are controlled by

BSCAN registers.

• In background mode via the IEEE 1149.1 port. This allows the device to remain operational in user mode

while reprogramming takes place.

The SRAM conﬁguration memory can be conﬁgured in three different ways:

• At power-up via the on-chip non-volatile memory.

• After a refresh command is issued via the IEEE 1149.1 port.

• In IEEE 1532 mode via the IEEE 1149.1 port.

Figure 2-22 provides a pictorial representation of the different programming modes available in the LA-MachXO

devices. On power-up, the SRAM is ready to be conﬁgured with IEEE 1149.1 serial TAP port using IEEE 1532 pro-

tocols.

Leave Alone I/O

When using IEEE 1532 mode for non-volatile memory programming, SRAM conﬁguration, or issuing a refresh

command, users may specify I/Os as high, low, tristated or held at current value. This provides excellent ﬂexibility

for implementing systems where reconﬁguration or reprogramming occurs on-the-ﬂy.

TransFR (Transparent Field Reconﬁguration)

TransFR (TFR) is a unique Lattice technology that allows users to update their logic in the ﬁeld without interrupting

system operation using a single ispVM command. See Lattice technical note #TN1087, Minimizing System Inter-

ruption During Conﬁguration Using TransFR Technology, for details.

Security

The LA-MachXO automotive devices contain security bits that, when set, prevent the readback of the SRAM con-

ﬁguration and non-volatile memory spaces. Once set, the only way to clear the security bits is to erase the memory

space.

For more information on device conﬁguration, please see details of additional technical documentation at the end

of this data sheet.

AEC-Q100 Tested and Qualiﬁed

The Automotive Electronics Council (AEC) consists of two committees: the Quality Systems Committee and the

Component Technical Committee. These committees are composed of representatives from sustaining and other

associate members. The AEC Component Technical Committee is the standardization body for establishing stan-

dards for reliable, high quality electronic components. In particular, the AEC-Q100 speciﬁcation “Stress Test for

Qualiﬁcation for Integrated Circuits” deﬁnes qualiﬁcation and re-qualiﬁcation requirements for electronic compo-

nents. Components meeting these speciﬁcations are suitable for use in the harsh automotive environment without

additional component-level qualiﬁcation testing. Lattice's LA-ispMACH 4000V and LA-MachXO devices completed

and passed the requirements of the AEC-Q100 speciﬁcation.

2-22

Architecture

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Figure 2-22. LA-MachXO Conﬁguration and Programming

ISP 1149.1 TAP Port

Port

Background

1532

Mode

Configure in milliseconds

Program in seconds

Power-up

Refresh

Non-Volatile

Memory Space

SRAM Memory

Space

Download in

microseconds

Density Shifting

The LA-MachXO family has been designed to enable density migration in the same package. Furthermore, the

architecture ensures a high success rate when performing design migration from lower density parts to higher den-

sity parts. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a

lower density device. However, the exact details of the ﬁnal resource utilization will impact the likely success in

each case.

2-23

LA-MachXO Automotive Family Data Sheet

DC and Switching Characteristics

November 2007

Data Sheet DS1003

Absolute Maximum Ratings^{1, 2, 3}

LCMXO E (1.2V)

LCMXO C (1.8V/2.5V/3.3V)

Supply Voltage V . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V . . . . . . . . . . . . . . . -0.5 to 3.75V

CC

Supply Voltage V

. . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V

CCAUX

Output Supply Voltage V

. . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V

CCIO

I/O Tristate Voltage Applied ⁴. . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V

Dedicated Input Voltage Applied⁴. . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 4.25V

Storage Temperature (ambient). . . . . . . . . . . . . . . -65 to 150°C . . . . . . . . . . . . . . . -65 to 150°C

Junction Temp. (Tj) . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C . . . . . . . . . . . . . . . . . . . +125°C

1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

2. Compliance with the Lattice Thermal Management document is required.

3. All voltages referenced to GND.

4. Overshoot and undershoot of -2V to (V

+ 2) volts is permitted for a duration of <20ns.

IHMAX

Recommended Operating Conditions¹

Symbol

Parameter

Min.

1.14

1.71

3.135

1.14

-40

Max.

1.26

Units

V

Core Supply Voltage for 1.2V Devices

V

CC

Core Supply Voltage for 1.8V/2.5V/3.3V Devices

Auxiliary Supply Voltage

3.465

125

V

3

V

t

V

CCAUX

2

I/O Driver Supply Voltage

V

CCIO

Junction Temperature Automotive Operation

Junction Temperature, Flash Programming, Automotive

^oC

JAUTO

t

-40

125

JFLASHAUTO

1. Like power supplies must be tied together. For example, if V

and V are both 2.5V, they must also be the same supply. 3.3V V

CC CCIO

CCIO

and 1.2V V

should be tied to V

or 1.2V V respectively.

CCIO

CCAUX CC

2. See recommended voltages by I/O standard in subsequent table.

3. V must reach minimum V value before V reaches 2.5V.

CC

CCAUX

LA-MachXO256 and LA-MachXO640 Hot Socketing Speciﬁcations^{1, 2, 3}

Symbol

Parameter

Condition

Min.

Typ.

Max

Units

I

Input or I/O leakage Current

0 ≤ V ≤ V (MAX)

—

+/-1000

µA

DK

IN

IH

1. Insensitive to sequence of V

V

and V

. However, assumes monotonic rise/fall rates for V

V

and V

CC, CCAUX,

CCIO

CC, CCAUX, CCIO.

2. 0 ≤ V ≤ V (MAX), 0 ≤ V

≤ V

(MAX) and 0 ≤ V

≤ V

(MAX).

CC

CCIO

CCAUX

3. I is additive to I

I

or I

.

DK

PU, PD

BH

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

3-1

DS1003 DC and Switching_01.3

DC and Switching Characteristics

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO1200 and LA-MachXO2280 Hot Socketing Speciﬁcations^{1, 2, 3, 4}

Symbol

Non-LVDS General Purpose sysIOs

Input or I/O Leakage Current

LVDS General Purpose sysIOs

Parameter

Condition

Min.

Typ.

Max.

Units

I

0 ≤ V ≤ V (MAX.)

—

+/-1000

µA

DK

IN

IH

V

≤ V

—

+/-1000

—

µA

IN

CCIO

I

Input or I/O Leakage Current

DK_LVDS

> V

35

mA

CCIO

1. Insensitive to sequence of V

V

and V

. However, assumes monotonic rise/fall rates for V

V

and V

CC, CCAUX,

CCIO

CC, CCAUX, CCIO.

2. 0 ≤ V ≤ V (MAX), 0 ≤ V

≤ V

(MAX), and 0 ≤ V

≤ V

(MAX).

CC

CCIO

CCAUX

3. I is additive to I

I

or I

.

DK

PU, PW

BH

4. LVCMOS and LVTTL only.

DC Electrical Characteristics

Over Recommended Operating Conditions

Symbol

Parameter

Condition

- 0.2V)

CCIO

Min.

Typ.

Max.

Units

µA

V

0 ≤ V ≤ (V

—

10

40

IN

1, 4, 5

I

Input or I/O Leakage

IL, IH

(V

- 0.2V) < V ≤ 3.6V

—

CCIO

IN

CCIO

I

I/O Active Pull-up Current

0 ≤ V ≤ 0.7 V

-30

30

-150

150

—

PU

IN

I/O Active Pull-down Current

Bus Hold Low sustaining current

Bus Hold High sustaining current

V

(MAX) ≤ V ≤ V (MAX)

IN IH

PD

IL

= V (MAX)

30

BHLS

BHHS

BHLO

IN

IL

= 0.7V

-30

—

CCIO

Bus Hold Low Overdrive current 0 ≤ V ≤ V (MAX)

150

-150

IN

IH

Bus Hold High Overdrive current 0 ≤ V ≤ V (MAX)

—

BHHO

IN

IH

3

V

Bus Hold trip Points

I/O Capacitance²

0 ≤ V ≤ V (MAX)

V

(MAX)

V

(MIN)

BHT

IN

IH

IL

IH

V

= 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,

CCIO

CC

C1

C2

—

8

—

pf

= Typ., V = 0 to V (MAX)

IO

IH

V

= 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,

Dedicated Input Capacitance²

CCIO

CC

= Typ., V = 0 to V (MAX)

IO

IH

1. Input or I/O leakage current is measured with the pin conﬁgured as an input or as an I/O with the output driver tri-stated. It is not measured

with the output driver active. Bus maintenance circuits are disabled.

2. T 25°C, f = 1.0MHz

A

3. Please refer to V and V in the sysIO Single-Ended DC Electrical Characteristics table of this document.

IL

IH

4. Not applicable to SLEEPN pin.

5. When V is higher than V , a transient current typically of 30ns in duration or less with a peak current of 6mA can occur on the high-to-

IH

CCIO

low transition. For LA-MachXO1200 and LA-MachXO2280 true LVDS output pins, V must be less than or equal to V

.

IH

CCIO

3-2

DC and Switching Characteristics

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Supply Current (Sleep Mode)^{1, 2}

Symbol

Parameter

Device

Typ.³

12

1

Max.

25

Units

µA

LCMXO256C

LCMXO640C

LCMXO256C

LCMXO640C

I

Core Power Supply

CC

25

µA

15

µA

I

Auxiliary Power Supply

Bank Power Supply⁴

CCAUX

1

25

µA

All LCMXO ‘C’ Devices

2

30

µA

CCIO

1. Assumes all inputs are conﬁgured as LVCMOS and held at the VCCIO or GND.

2. Frequency = 0MHz.

3. T = 25°C, power supplies at nominal voltage.

A

4. Per Bank.

Supply Current (Standby)^{1, 2, 3, 4}

Over Recommended Operating Conditions

Symbol

Parameter

Device

LCMXO256C

Typ.⁵

7

Units

mA

LCMXO640C

LCMXO256E

LCMXO640E

LCMXO1200E

LCMXO2280E

LCMXO256E/C

LCMXO640E/C

LCMXO1200E

LCMXO2280E

All devices

9

4

I

Core Power Supply

CC

6

10

12

5

7

Auxiliary Power Supply

= 3.3V

I

CCAUX

V

12

13

2

CCAUX

Bank Power Supply⁶

CCIO

1. For further information on supply current, please see details of additional technical documentation at the end of this data sheet.

2. Assumes all outputs are tristated, all inputs are conﬁgured as LVCMOS and held at V

or GND.

CCIO

3. Frequency = 0MHz.

4. User pattern = blank.

5. T = 25^oC, power supplies at nominal voltage.

J

6. Per Bank. V

= 2.5V. Does not include pull-up/pull-down.

CCIO

3-3

DC and Switching Characteristics

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Initialization Supply Current^{1, 2, 3, 4}

Over Recommended Operating Conditions

Symbol

Parameter

Device

Typ.⁵

13

17

10

14

18

20

10

13

24

25

2

Units

mA

LCMXO256C

LCMXO640C

LCMXO256E

LCMXO640E

LCMXO1200E

LCMXO2280E

LCMXO256E/C

LCMXO640E/C

LCMXO1200E

LCMXO2280E

All devices

I

Core Power Supply

CC

Auxiliary Power Supply

I

CCAUX

V

= 3.3V

CCAUX

Bank Power Supply⁶

CCIO

1. For further information on supply current, please see details of additional technical documentation at the end of this data sheet.

2. Assumes all I/O pins are held at V

3. Frequency = 0MHz.

or GND.

CCIO

4. Typical user pattern.

5. T = 25^oC, power supplies at nominal voltage.

J

6. Per Bank, V

= 2.5V. Does not include pull-up/pull-down.

CCIO

3-4

DC and Switching Characteristics

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Programming and Erase Flash Supply Current^{1, 2, 3, 4}

Symbol

Parameter

Device

LCMXO256C

Typ.⁵

9

Units

mA

LCMXO640C

LCMXO256E

LCMXO640E

LCMXO1200E

LCMXO2280E

LCMXO256E/C

LCMXO640E/C

LCMXO1200E

LCMXO2280E

All devices

11

6

I

Core Power Supply

CC

8

12

14

8

10

15

16

2

Auxiliary Power Supply

I

CCAUX

V

= 3.3V

CCAUX

Bank Power Supply⁶

CCIO

1. For further information on supply current, please see details of additional technical documentation at the end of this data sheet.

2. Assumes all I/O pins are held at V

3. Typical user pattern.

or GND.

CCIO

4. JTAG programming is at 25MHz.

5. T = 25°C, power supplies at nominal voltage.

J

6. Per Bank. V

= 2.5V. Does not include pull-up/pull-down.

CCIO

3-5

DC and Switching Characteristics

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

sysIO Recommended Operating Conditions

V

(V)

CCIO

Standard

LVCMOS 3.3

LVCMOS 2.5

LVCMOS 1.8

LVCMOS 1.5

LVCMOS 1.2

LVTTL

PCI³

LVDS^{1, 2}

LVPECL¹

BLVDS¹

Min.

3.135

2.375

1.71

Typ.

3.3

2.5

1.8

1.5

1.2

3.3

2.5

3.3

2.5

Max.

3.465

2.625

1.89

1.425

1.14

1.575

1.26

3.135

2.375

3.135

2.375

3.465

2.625

3.465

2.625

RSDS¹

1. Inputs on chip. Outputs are implemented with the addition of external resistors.

2. MachXO1200 and MachXO2280 devices have dedicated LVDS buffers

3. Input on the top bank of the MachXO1200 and MachXO2280 only.

3-6

DC and Switching Characteristics

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

sysIO Single-Ended DC Electrical Characteristics

V

IH

1

IL

Input/Output

Standard

V

Max.

V

Min.

I

OH

OL

OH

(V)

OL

Min. (V) Max. (V)

Min. (V)

Max. (V)

(V)

(mA)

-14, -12, -8, -4

-0.1

0.4

0.2

0.4

0.2

0.4

0.2

0.4

0.2

0.4

0.2

0.4

0.2

0.4

0.2

V

- 0.4 16, 12, 8, 4

CCIO

LVCMOS 3.3

-0.3

0.8

0.7

2.0

1.7

3.6

- 0.2

0.1

16

2.4

-16

LVTTL

-0.3

3.6

V

- 0.4

- 0.2

12, 8, 4

0.1

-12, -8, -4

-0.1

CCIO

- 0.4 16, 12, 8, 4

- 0.2 0.1

- 0.4 16, 12, 8, 4

-14, -12, -8, -4

-0.1

LVCMOS 2.5

LVCMOS 1.8

LVCMOS 1.5

-0.3

3.6

-14, -12, -8, -4

-0.1

0.35V

0.65V

CCIO

- 0.2

- 0.4

- 0.2

- 0.4

- 0.2

- 0.4

- 0.2

0.1

8, 4

0.1

6, 2

0.1

6, 2

0.1

1.5

-8, -4

0.35V

0.65V

CCIO

-0.1

-6, -2

LVCMOS 1.2

(“C” Version)

0.42

0.78

-0.1

-6, -2

LVCMOS 1.2

(“E” Version)

-0.3

0.35V

0.65V

3.6

CC

-0.1

PCI

0.3V

0.5V

0.1V

0.9V

-0.5

CCIO

1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O Bank and the end of an I/O Bank, as

shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between Bank GND connections or

between the last GND in a Bank and the end of a Bank.

3-7

DC and Switching Characteristics

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

sysIO Differential Electrical Characteristics

LVDS

Over Recommended Operating Conditions

Parameter

Symbol

Parameter Description

Input Voltage

Test Conditions

Min.

0

Typ.

—

Max.

2.4

Units

V

INP, INM

Differential Input Threshold

Input Common Mode Voltage

Input current

+/-100

—

mV

V

THD

100mV ≤ V

V

/2

1.2

—

1.8

THD

V

200mV ≤ V

350mV ≤ V

Power on

1.9

V

CM

2.0

V

THD

I

—

+/-10

1.60

—

µA

V

IN

V

Output high voltage for V or V

R = 100 Ohm

—

1.38

1.03

350

OH

OL

OD

OP

OM

T

Output low voltage for V or V

R = 100 Ohm

0.9V

250

V

OP

OM

T

Output voltage differential

(V - V ), R = 100 Ohm

450

mV

OP

OM

T

Change in V between high and

low

OD

ΔV

—

50

mV

OD

V

Output voltage offset

(V - V )/2, R = 100 Ohm

1.125

—

1.25

—

1.375

50

V

OS

OP

OM

T

ΔV

Change in V between H and L

mV

OS

V

= 0V Driver outputs

OD

I

Output short circuit current

—

6

mA

OSD

shorted

LVDS Emulation

LA-MachXO automotive devices can support LVDS outputs via emulation (LVDS25E), in addition to the LVDS sup-

port that is available on-chip on certain devices. The output is emulated using complementary LVCMOS outputs in

conjunction with resistors across the driver outputs on all devices. The scheme shown in Figure 3-1 is one possible

solution for LVDS standard implementation. Resistor values in Figure 3-1 are industry standard values for 1% resis-

tors.

Figure 3-1. LVDS Using External Resistors (LVDS25E)

VCCIO = 2.5

158

8mA

Zo = 100

+

100

VCCIO = 2.5

8mA

140

-

158

On-chip

Off-chip

On-chip

Emulated

LVDS

Buffer

Note: All resistors are 1%.

The LVDS differential input buffers are available on certain devices in the LA-MachXO family.

3-8

DC and Switching Characteristics

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Table 3-1. LVDS DC Conditions

Over Recommended Operating Conditions

Parameter

Description

Typical

20

Units

Ω

Z

Output impedance

OUT

R

Driver series resistor

Driver parallel resistor

Receiver termination

Output high voltage

Output low voltage

294

Ω

S

121

Ω

P

100

Ω

T

V

1.43

1.07

0.35

1.25

100

V

OH

OL

OD

CM

BACK

V

Output differential voltage

Output common mode voltage

Back impedance

V

Z

Ω

I

DC output current

3.66

mA

DC

BLVDS

The LA-MachXO automotive family supports the BLVDS standard through emulation. The output is emulated using

complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. The

input standard is supported by the LVDS differential input buffer on certain devices. BLVDS is intended for use

when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is

one possible solution for bi-directional multi-point differential signals.

Figure 3-2. BLVDS Multi-point Output Example

Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential

2.5V

16mA

2.5V

16mA

80

45-90 ohms

80

2.5V

16mA

2.5V

16mA

80

. . .

+

-

+

-

2.5V

16mA

2.5V

16mA

3-9

DC and Switching Characteristics

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Table 3-2. BLVDS DC Conditions¹

Over Recommended Operating Conditions

Nominal

Symbol

Description

Output impedance

Zo = 45 Zo = 90

Units

ohm

V

Z

100

45

100

90

OUT

R

Left end termination

Right end termination

Output high voltage

TLEFT

TRIGHT

OH

45

90

V

1.375

1.125

0.25

1.25

11.2

1.48

1.02

0.46

1.25

10.2

Output low voltage

V

OL

Output differential voltage

Output common mode voltage

DC output current

V

OD

V

CM

I

mA

DC

1. For input buffer, see LVDS table.

LVPECL

The LA-MachXO automotive family supports the differential LVPECL standard through emulation. This output stan-

dard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver

outputs on all the devices. The LVPECL input standard is supported by the LVDS differential input buffer on certain

devices. The scheme shown in Figure 3-3 is one possible solution for point-to-point signals.

Figure 3-3. Differential LVPECL

V_CCIO= 3.3V

100 ohms

16mA

+

V_CCIO= 3.3V

150 ohms

100 ohms

-

100 ohms

Off-chip

16mA

Transmission line, Zo = 100 ohm differential

Off-chip

On-chip

Table 3-3. LVPECL DC Conditions¹

Over Recommended Operating Conditions

Symbol

Description

Output impedance

Nominal

100

Units

Z

ohm

V

OUT

R

Driver parallel resistor

Receiver termination

Output high voltage

Output low voltage

150

P

T

100

V

2.03

1.27

0.76

1.65

85.7

12.7

OH

V

OL

Output differential voltage

Output common mode voltage

Back impedance

V

OD

V

CM

Z

ohm

mA

BACK

I

DC output current

DC

1. For input buffer, see LVDS table.

3-10

DC and Switching Characteristics

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

For further information on LVPECL, BLVDS and other differential interfaces please see details of additional techni-

cal documentation at the end of the data sheet.

RSDS

The LA-MachXO automotive family supports the differential RSDS standard. The output standard is emulated

using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs on all the

devices. The RSDS input standard is supported by the LVDS differential input buffer on certain devices. The

scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation. Use LVDS25E mode with

suggested resistors for RSDS operation. Resistor values in Figure 3-4 are industry standard values for 1% resis-

tors.

Figure 3-4. RSDS (Reduced Swing Differential Standard)

VCCIO = 2.5V

294

8mA

Zo = 100

+

VCCIO = 2.5V

121

100

-

294

8mA

On-chip

Off-chip

On-chip

Emulated

RSDS Buffer

Table 3-4. RSDS DC Conditions

Parameter

Description

Typical

20

Units

ohm

V

Z

Output impedance

OUT

R

Driver series resistor

Driver parallel resistor

Receiver termination

Output high voltage

Output low voltage

294

S

121

P

100

T

V

1.35

1.15

0.20

1.25

101.5

3.66

OH

OL

OD

CM

BACK

V

Output differential voltage

Output common mode voltage

Back impedance

V

Z

ohm

mA

I

DC output current

DC

3-11

DC and Switching Characteristics

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Typical Building Block Function Performance¹

Pin-to-Pin Performance (LVCMOS25 12mA Drive)

Function

Basic Functions

-3 Timing

Units

16-bit decoder

4:1 MUX

9.4

6.3

7.1

ns

16:1 MUX

Register-to-Register Performance

Function

Basic Functions

16:1 MUX

-3 Timing

Units

348

209

277

143

MHz

16-bit adder

16-bit counter

64-bit counter

Embedded Memory Functions (1200 and 2280 Devices Only)

256x36 Single Port RAM

512x18 True-Dual Port RAM

Distributed Memory Functions

16x2 Single Port RAM

203

MHz

310

229

186

224

194

MHz

64x2 Single Port RAM

128x4 Single Port RAM

32x2 Pseudo-Dual Port RAM

64x4 Pseudo-Dual Port RAM

1. The above timing numbers are generated using the ispLEVER design tool. Exact performance may vary with device and

tool version. The tool uses internal parameters that have been characterized but are not tested on every device.

Rev. A 0.19

Derating Logic Timing

Logic Timing provided in the following sections of the data sheet and the ispLEVER design tools are worst case

numbers in the operating range. Actual delays may be much faster.The ispLEVER design tool from Lattice can pro-

vide logic timing numbers at a particular temperature and voltage.

3-12

DC and Switching Characteristics

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO External Switching Characteristics¹

Over Recommended Operating Conditions

-3

Parameter

Description

Device

Min. Max. Units

General I/O Pin Parameters (Using Global Clock without PLL)¹

LCMXO256

LCMXO640

—

1.8

1.5

4.9

5.1

5.6

5.7

6.1

—

ns

t

f

t

Best Case t Through 1 LUT

PD

LCMXO1200

LCMXO2280

LCMXO256

LCMXO640

LCMXO1200

LCMXO2280

LCMXO256

LCMXO640

ns

Best Case Clock to Output - From PFU

Clock to Data Setup - To PFU

CO

ns

—

ns

SU

LCMXO1200 1.6

LCMXO2280 1.5

—

ns

—

ns

LCMXO256

LCMXO640

-0.3

-0.1

—

ns

—

ns

Clock to Data Hold - To PFU

H

LCMXO1200 0.0

LCMXO2280 -0.4

—

ns

—

ns

LCMXO256

LCMXO640

LCMXO1200

LCMXO2280

LCMXO256

LCMXO640

LCMXO1200

LCMXO2280

—

500

240

260

MHz

ps

Clock Frequency of I/O and PFU Register

Global Clock Skew Across Device

MAX_IO

ps

SKEW_PRI

ps

1. General timing numbers based on LVCMOS2.5V, 12 mA.

Rev. A 0.19

3-13

DC and Switching Characteristics

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO Internal Timing Parameters¹

Over Recommended Operating Conditions

-3

Parameter

Description

Min. Max. Units

PFU/PFF Logic Mode Timing

t

LUT4 delay (A to D inputs to F output)

LUT6 delay (A to D inputs to OFX output)

Set/Reset to output of PFU

—

0.39

0.62

1.26

—

ns

LUT4_PFU

LUT6_PFU

LSR_PFU

SUM_PFU

HM_PFU

—

Clock to Mux (M0,M1) input setup time

Clock to Mux (M0,M1) input hold time

Clock to D input setup time

0.15

-0.07

0.18

-0.04

—

SUD_PFU

HD_PFU

Clock to D input hold time

—

Clock to Q delay, D-type register conﬁguration

Clock to Q delay latch conﬁguration

D to Q throughput delay when latch is enabled

0.56

0.74

0.77

CK2Q_PFU

LE2Q_PFU

LD2Q_PFU

—

PFU Dual Port Memory Mode Timing

t

Clock to Output

—

0.56

—

ns

CORAM_PFU

SUDATA_PFU

HDATA_PFU

Data Setup Time

-0.25

0.39

-0.65

0.99

-0.30

0.47

Data Hold Time

—

Address Setup Time

Address Hold Time

—

SUADDR_PFU

HADDR_PFU

SUWREN_PFU

HWREN_PFU

—

Write/Read Enable Setup Time

Write/Read Enable Hold Time

—

PIO Input/Output Buffer Timing

t

Input Buffer Delay

Output Buffer Delay

—

1.06

1.80

ns

IN_PIO

OUT_PIO

EBR Timing (1200 and 2280 Devices Only)

Clock to output from Address or Data with no output

register

t

—

3.14

ns

CO_EBR

t

Clock to output from EBR output Register

Setup Data to EBR Memory

—

0.75

—

ns

COO_EBR

-0.37

0.57

-0.37

0.57

-0.23

0.36

0.27

-0.18

SUDATA_EBR

HDATA_EBR

SUADDR_EBR

HADDR_EBR

SUWREN_EBR

HWREN_EBR

SUCE_EBR

Hold Data to EBR Memory

—

Setup Address to EBR Memory

Hold Address to EBR Memory

—

Setup Write/Read Enable to EBR Memory

Hold Write/Read Enable to EBR Memory

Clock Enable Setup Time to EBR Output Register

Clock Enable Hold Time to EBR Output Register

—

HCE_EBR

Reset To Output Delay Time from EBR Output Regis-

ter

t

—

1.44

ns

RSTO_EBR

PLL Parameters (1200 and 2280 Devices Only)

t

Reset Recovery to Rising Clock

Reset Signal Setup Time

—

1.00

—

ns

RSTREC

1.00

RSTSU

1. Internal parameters are characterized but not tested on every device.

Rev. A 0.19

3-14

DC and Switching Characteristics

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO Family Timing Adders^{1, 2, 3}

Over Recommended Operating Conditions

Buffer Type

Input Adjusters

Description

-3

Units

LVDS25⁴

BLVDS25⁴

LVPECL33⁴

LVDS

0.61

0.59

0.01

0.00

0.10

0.19

0.56

0.01

ns

BLVDS

LVPECL

LVTTL

LVTTL33

LVCMOS33

LVCMOS 3.3

LVCMOS 2.5

LVCMOS 1.8

LVCMOS 1.5

LVCMOS 1.2

PCI

LVCMOS25

LVCMOS18

LVCMOS15

LVCMOS12

PCI33⁴

Output Adjusters

LVDS25E

LVDS25⁴

LVDS 2.5 E

-0.18

-0.30

-0.04

0.05

0.08

-0.01

0.70

0.05

0.08

-0.01

0.70

0.07

0.13

0.00

0.47

0.15

0.06

-0.08

0.09

0.22

0.07

0.36

0.07

2.59

ns

LVDS 2.5

BLVDS25

BLVDS 2.5

LVPECL33

LVPECL 3.3

LVTTL33_4mA

LVTTL33_8mA

LVTTL33_12mA

LVTTL33_16mA

LVCMOS33_4mA

LVCMOS33_8mA

LVCMOS33_12mA

LVCMOS33_14mA

LVCMOS25_4mA

LVCMOS25_8mA

LVCMOS25_12mA

LVCMOS25_14mA

LVCMOS18_4mA

LVCMOS18_8mA

LVCMOS18_12mA

LVCMOS18_14mA

LVCMOS15_4mA

LVCMOS15_8mA

LVCMOS12_2mA

LVCMOS12_6mA

PCI33⁴

LVTTL 4mA drive

LVTTL 8mA drive

LVTTL 12mA drive

LVTTL 16mA drive

LVCMOS 3.3 4mA drive

LVCMOS 3.3 8mA drive

LVCMOS 3.3 12mA drive

LVCMOS 3.3 14mA drive

LVCMOS 2.5 4mA drive

LVCMOS 2.5 8mA drive

LVCMOS 2.5 12mA drive

LVCMOS 2.5 14mA drive

LVCMOS 1.8 4mA drive

LVCMOS 1.8 8mA drive

LVCMOS 1.8 12mA drive

LVCMOS 1.8 14mA drive

LVCMOS 1.5 4mA drive

LVCMOS 1.5 8mA drive

LVCMOS 1.2 2mA drive

LVCMOS 1.2 6mA drive

PCI33

1. Timing adders are characterized but not tested on every device.

2. LVCMOS timing is measured with the load speciﬁed in Switching Test Conditions table.

3. All other standards tested according to the appropriate speciﬁcations.

4. I/O standard only available in LCMXO1200 and LCMXO2280 devices.

Rev. A 0.19

3-15

DC and Switching Characteristics

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

sysCLOCK PLL Timing

Over Recommended Operating Conditions

Parameter

Descriptions

Input Clock Frequency (CLKI, CLKFB)

Conditions

Min.

25

Max.

420

210

840

—

Units

MHz

f

IN

Output Clock Frequency (CLKOP, CLKOS)

K-Divider Output Frequency (CLKOK)

PLL VCO Frequency

25

OUT

OUT2

VCO

PFD

0.195

420

25

Phase Detector Input Frequency

AC Characteristics

t

Output Clock Duty Cycle

Default duty cycle selected³

45

—

55

0.05

+/-120

0.02

+/-200

—

%

UI

DT

PH

4

Output Phase Accuracy

Fout ≥ 100MHz

—

ps

1

t

Output Clock Period Jitter

OPJIT

Fout < 100MHz

—

UIPP

ps

t

Input Clock to Output Clock Skew

Output Clock Pulse Width

PLL Lock-in Time

Divider ratio = integer

At 90% or 10%³

—

SK

1

ns

W

2

—

150

450

+/-200

10

µs

LOCK

PA

Programmable Delay Unit

Input Clock Period Jitter

External Feedback Delay

Input Clock High Time

Input Clock Low Time

RST Pulse Width

100

—

ps

IPJIT

—

ns

FBKDLY

HI

90% to 90%

10% to 10%

0.5

10

—

ns

—

ns

LO

—

ns

RST

1. Jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock.

2. Output clock is valid after t for PLL reset and dynamic delay adjustment.

LOCK

3. Using LVDS output buffers.

4. CLKOS as compared to CLKOP output.

Rev. A 0.19

LA-MachXO “C” Sleep Mode Timing

Symbol

Parameter

Device

Min.

—

Typ.

Max

Units

t

SLEEPN Low to Power Down

All

—

400

600

—

ns

µs

ns

PWRDN

LCMXO256

LCMXO640

All

—

SLEEPN High to Power Up

PWRUP

—

t

SLEEPN Pulse Width

400

—

WSLEEPN

SLEEPN Pulse Rejection

All

100

WAWAKE

Rev. A 0.19

Power Down Mode

I/O

t_PWRUP

t_PWRDN

SLEEPN

t_WSLEEPNor t_WAWAKE

3-16

DC and Switching Characteristics

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Flash Download Time

Symbol

Parameter

LCMXO256

Min.

—

Typ.

—

Max.

0.4

Units

ms

Minimum V or V

(later of the two supplies)

to Device I/O Active

CC

CCAUX

LCMXO640

LCMXO1200

LCMXO2280

—

0.6

ms

t

REFRESH

—

0.8

ms

—

1.0

ms

JTAG Port Timing Speciﬁcations

Over Recommended Operating Conditions

Symbol

Parameter

Min.

—

40

20

8

Max.

Units

MHz

ns

f

t

TCK [BSCAN] clock frequency

25

—

10

—

25

MAX

TCK [BSCAN] clock pulse width

BTCP

TCK [BSCAN] clock pulse width high

ns

BTCPH

BTCPL

BTS

TCK [BSCAN] clock pulse width low

ns

TCK [BSCAN] setup time

ns

TCK [BSCAN] hold time

10

50

—

8

ns

BTH

TCK [BSCAN] rise/fall time

mV/ns

ns

BTRF

TAP controller falling edge of clock to output valid

TAP controller falling edge of clock to output disabled

TAP controller falling edge of clock to output enabled

BSCAN test capture register setup time

BTCO

ns

BTCODIS

BTCOEN

BTCRS

BTCRH

BUTCO

BTUODIS

BTUPOEN

ns

BSCAN test capture register hold time

25

—

ns

BSCAN test update register, falling edge of clock to output valid

BSCAN test update register, falling edge of clock to output disabled

BSCAN test update register, falling edge of clock to output enabled

ns

Rev. A 0.19

Figure 3-5. JTAG Port Timing Waveforms

TMS

TDI

t

BTH

BTS

t

BTCP

t

BTCPL

BTCPH

TCK

TDO

t

BTCODIS

t

BTCO

BTCOEN

Valid Data

t

BTCRH

t

BTCRS

Data to be

captured

from I/O

Data Captured

t

BTUPOEN

BUTCO

BTUODIS

Data to be

driven out

to I/O

Valid Data

3-17

DC and Switching Characteristics

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Switching Test Conditions

Figure 3-6 shows the output test load that is used for AC testing. The speciﬁc values for resistance, capacitance,

voltage, and other test conditions are shown in Figure 3-5.

Figure 3-6. Output Test Load, LVTTL and LVCMOS Standards

V_T

R1

DUT

Test Point

CL

Table 3-5. Test Fixture Required Components, Non-Terminated Interfaces

Test Condition

R

C

Timing Ref.

V

T

1

L

LVTTL, LVCMOS 3.3 = 1.5V

—

LVCMOS 2.5 = V

LVCMOS 1.8 = V

LVCMOS 1.5 = V

LVCMOS 1.2 = V

/2

CCIO

LVTTL and LVCMOS settings (L -> H, H -> L)

0pF

∞

LVTTL and LVCMOS 3.3 (Z -> H)

LVTTL and LVCMOS 3.3 (Z -> L)

Other LVCMOS (Z -> H)

V

OL

1.5

V

OH

V

/2

V

OL

CCIO

188

Other LVCMOS (Z -> L)

V

OH

CCIO

LVTTL + LVCMOS (H -> Z)

LVTTL + LVCMOS (L -> Z)

V

- 0.15

V

OL

OH

V

OH

OL

Note: Output test conditions for all other interfaces are determined by the respective standards.

3-18

LA-MachXO Automotive Family Data Sheet

Pinout Information

November 2007

Data Sheet DS1003

Signal Descriptions

Signal Name

I/O

Descriptions

General Purpose

[Edge] indicates the edge of the device on which the pad is located. Valid edge designa-

tions are L (Left), B (Bottom), R (Right), T (Top).

[Row/Column Number] indicates the PFU row or the column of the device on which the

PIO Group exists. When Edge is T (Top) or (Bottom), only need to specify Row Number.

When Edge is L (Left) or R (Right), only need to specify Column Number.

P[Edge] [Row/Column

Number]_[A/B/C/D/E/F]

[A/B/C/D/E/F] indicates the PIO within the group to which the pad is connected.

I/O

Some of these user programmable pins are shared with special function pins. When not

used as special function pins, these pins can be programmed as I/Os for user logic.

During conﬁguration of the user-programmable I/Os, the user has an option to tri-state the

I/Os and enable an internal pull-up resistor. This option also applies to unused pins (or

those not bonded to a package pin). The default during conﬁguration is for user-program-

mable I/Os to be tri-stated with an internal pull-up resistor enabled.

Global RESET signal (active low). Dedicated pad, when not in use it can be used as an I/O

pin.

GSRN

TSALL

I

TSALL is a dedicated pad for the global output enable signal. When TSALL is high all the

outputs are tristated. It is a dual function pin. When not in use, it can be used as an I/O pin.

NC

—

No connect.

GND

GND - Ground. Dedicated pins.

VCC - The power supply pins for core logic. Dedicated pins.

V

CC

VCCAUX - the Auxiliary power supply pin. This pin powers up a variety of internal circuits

including all the differential and referenced input buffers. Dedicated pins.

—

CCAUX

CCIOx

V

- The power supply pins for I/O Bank x. Dedicated pins.

CCIO

Sleep Mode pin - Active low sleep pin. When this pin is held high, the device operates nor-

SLEEPN¹

I

mally. This pin has a weak internal pull-up, but when unused, an external pull-up to V is

CC

recommended. When driven low, the device moves into Sleep mode after a speciﬁed time.

PLL and Clock Functions (Used as user programmable I/O pins when not used for PLL or clock pins)

Reference clock (PLL) input Pads: [LOC] indicates location. Valid designations are ULM

(Upper PLL) and LLM (Lower PLL). T = true and C = complement.

[LOC][0]_PLL[T, C]_IN

—

Optional feedback (PLL) input Pads: [LOC] indicates location. Valid designations are ULM

(Upper PLL) and LLM (Lower PLL). T = true and C = complement.

[LOC][0]_PLL[T, C]_FB

PCLK [n]_[1:0]

—

Primary Clock Pads, n per side.

Test and Programming (Dedicated pins)

TMS

TCK

TDI

I

Test Mode Select input pin, used to control the 1149.1 state machine.

Test Clock input pin, used to clock the 1149.1 state machine.

I

Test Data input pin, used to load data into the device using an 1149.1 state machine.

Output pin -Test Data output pin used to shift data out of the device using 1149.1.

TDO

O

1. Applies to LA-MachXO “C” devices only. NC for “E” devices.

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

4-1

DS1003 Pinouts_01.3

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Pin Information Summary

LAMXO256C/E

LAMXO640C/E

Pin Type

100 TQFP

144 TQFP

256 ftBGA

Single Ended User I/O

Differential Pair User I/O¹

78

38

6

74

17

6

113

159

43

79

Muxed

6

TAP

4

Dedicated (Total Without Supplies)

5

4

VCC

2

4

2

VCCAUX

1

2

Bank0

3

2

4

Bank1

3

2

4

VCCIO

Bank2

—

8

2

4

Bank3

2

4

GND

NC

10

0

12

18

0

52

Bank0

41/20

37/18

—

18/5

21/4

14/2

21/6

29/10

30/11

24/9

30/13

42/21

40/20

36/18

40/20

Bank1

Single Ended/Differential I/O

per Bank

Bank2

Bank3

1. These devices support emulated LVDS outputs. LVDS inputs are not supported.

LAMXO1200E

LAMXO2280E

Pin Type

100 TQFP

144 TQFP

256 ftBGA

100 TQFP

144 TQFP

256 ftBGA

324 ftBGA

Single Ended User I/O

Differential Pair User I/O¹

73

27

6

113

48

6

211

73

30

6

113

47

6

211

271

105

134

Muxed

6

TAP

4

Dedicated (Total Without Supplies)

5

VCC

4

2

4

6

VCCAUX

2

Bank0

1

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

1

2

1

2

1

2

1

2

1

2

1

2

VCCIO

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

GND

NC

8

12

0

18

8

12

0

18

24

0

Bank0

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

10/3

8/2

10/4

11/5

8/3

5/2

10/3

11/5

14/6

15/7

14/5

10/4

15/6

26/13

28/14

26/13

28/14

27/13

22/11

28/14

26/13

9/3

10/4

11/5

8/3

5/2

10/4

11/5

13/6

16/7

15/7

14/4

10/4

15/6

24/12

30/15

26/13

28/14

29/14

20/10

28/14

26/13

34/17

36/18

34/17

35/17

30/15

34/17

Single Ended/Differential I/O

per Bank

1. These devices support on-chip LVDS buffers for left and right I/O Banks.

4-2

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Power Supply and NC

Signal

100 TQFP¹

144 TQFP¹

VCC

LAMXO256/640: 35, 90

LAMXO1200/2280: 17, 35, 66, 91

21, 52, 93, 129

VCCIO0

LAMXO256: 60, 74, 92

LAMXO640: 80, 92

LAMXO1200/2280: 94

LAMXO640: 117, 135

LAMXO1200/2280: 135

VCCIO1

VCCIO2

VCCIO3

LAMXO256: 10, 24, 41

LAMXO640: 60, 74

LAMXO640: 82, 98

LAMXO1200/2280: 117

LAMXO1200/2280: 80

LAMXO256: None

LAMXO640: 29, 41

LAMXO1200/2280: 70

LAMXO640: 38, 63

LAMXO1200/2280: 98

LAMXO256: None

LAMXO640: 10, 24

LAMXO1200/2280: 56

LAMXO640: 10, 26

LAMXO1200/2280: 82

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCAUX

GND²

LAMXO256/640: None

LAMXO1200/2280: 44

LAMXO640: None

LAMXO1200/2280: 63

LAMXO256/640: None

LAMXO1200/2280: 27

LAMXO640: None

LAMXO1200/2280: 38

LAMXO256/640: None

LAMXO1200/2280: 20

LAMXO640: None

LAMXO1200/2280: 26

LAMXO256/640: None

LAMXO1200/2280: 6

LAMXO640: None

LAMXO1200/2280: 10

LAMXO256/640: 88

LAMXO1200/2280: 36, 90

53, 128

LAMXO256: 40, 84, 62, 75, 93, 12, 25, 42

LAMXO640: 40, 84, 81, 93, 62, 75, 30, 42, 12, 25

LAMXO1200/2280: 9, 41, 59, 83, 100, 76, 50, 26

16, 59, 88, 123, 118, 136, 83, 99, 37, 64, 11, 27

NC³

1. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise.

2. All grounds must be electrically connected at the board level. For fpBGA and ftBGA packages, the total number of GND balls is less than the actual number of

GND logic connections from the die to the common package GND plane.

3. NC pins should not be connected to any active signals, VCC or GND.

4-3

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Power Supply and NC (Cont.)

Signal

256 ftBGA¹

324 ftBGA¹

F14, G11, G9, H7, L7, M9

G8, G7

VCC

G7, G10, K7, K10

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

LAMXO640: F8, F7, F9, F10

LAMXO1200/2280: F8, F7

LAMXO640: H11, G11, K11, J11

LAMXO1200/2280: F9, F10

G12, G10

J12, H12

L12, K12

M12, M11

M8, R9

LAMXO640: L9, L10, L8, L7

LAMXO1200/2280: H11, G11

LAMXO640: K6, J6, H6, G6

LAMXO1200/2280: K11, J11

LAMXO640: None

LAMXO1200/2280: L9, L10

LAMXO640: None

LAMXO1200/2280: L8, L7

LAMXO640: None

LAMXO1200/2280: K6, J6

M7, K7

LAMXO640: None

LAMXO1200/2280: H6, G6

H6, J7

VCCAUX

GND²

T9, A8

M10, F9

A1, A16, F11, G8, G9, H7, H8, H9, H10, J7, J8, J9, E14, F16, H10, H11, H8, H9, J10, J11, J4, J8, J9,

J10, K8, K9, L6, T1, T16

K10, K11, K17, K8, K9, L10, L11, L8, L9, N2, P14,

P5, R7

NC³

LAMXO640: E4, E5, F5, F6, C3, C2, G4, G5, H4, H5, —

K5, K4, M5, M4, P2, P3, N5, N6, M7, M8, N10, N11,

R15, R16, P15, P16, M11, L11, N12, N13, M13, M12,

K12, J12, F12, F13, E12, E13, D13, D14, B15, A15,

C14, B14, E11, E10, E7, E6, D4, D3, B3, B2

LAMXO1200: None

LAMXO2280: None

1. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally.

2. All grounds must be electrically connected at the board level. For fpBGA and ftBGA packages, the total number of GND balls is less than the actual number of

GND logic connections from the die to the common package GND plane.

3. NC pins should not be connected to any active signals, VCC or GND.

4-4

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO256 and LA-MachXO640 Logic Signal Connections:

100 TQFP

LAMXO256

LAMXO640

Ball

Dual

Ball

Dual

Pin Number Function

Bank

1

-

Function

Differential

Function

Bank

3

2

-

Function

Differential

1

PL2A

PL2B

PL3A

PL3B

PL3C

PL3D

PL4A

PL4B

PL5A

VCCIO1

PL5B

GNDIO1

PL5C

PL5D

PL6A

PL6B

PL7A

PL7B

PL7C

PL7D

PL8A

PL8B

PL9A

VCCIO1

GNDIO1

TMS

T

C

T

C

T

C

T

C

T

PL2A

PL2C

PL2B

T

2

3

C

T

4

PL2D

PL3A

5

6

PL3B

C

T

7

PL3C

PL3D

PL4A

8

C

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

VCCIO3

PL4C

GNDIO3

PL4D

PL5B

C

T

C

T

C

T

C

T

C

T

C

T

C

GSRN

TSALL

GSRN

TSALL

PL7B

PL8C

PL8D

PL9A

T

C

PL9C

PL10A

PL10C

PL11A

PL11C

VCCIO3

GNDIO3

TMS

TCK

TMS

TCK

PL9B

TCK

C

PB2C

TCK

PB2A

PB2B

TDO

T

VCCIO2

GNDIO2

TDO

C

TDO

TDI

TDO

TDI

PB2C

TDI

T

PB4C

TDI

PB2D

VCC

C

PB4E

VCC

PB3A

PB3B

PB3C

PB3D

GND

1

-

PCLK1_1**

PCLK1_0**

T

C

T

PB5B

PB5D

PB6B

PB6C

GND

2

-

PCLK2_1**

PCLK2_0**

C

VCCIO1

1

VCCIO2

2

4-5

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO256 and LA-MachXO640 Logic Signal Connections:

100 TQFP (Cont.)

LAMXO256

LAMXO640

Ball

Dual

Ball

Dual

Pin Number Function

Bank

1

-

Function

Differential

Function

Bank

2

-

Function

Differential

42

43

44

45

46

47

48*

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

GNDIO1

PB4A

PB4B

PB4C

PB4D

PB5A

SLEEPN

PB5C

PB5D

PR9B

PR9A

PR8B

PR8A

PR7D

PR7C

PR7B

PR7A

PR6B

VCCIO0

PR6A

GNDIO0

PR5D

PR5C

PR5B

PR5A

PR4B

PR4A

PR3D

PR3C

PR3B

PR3A

PR2B

VCCIO0

GNDIO0

PR2A

PT5C

PT5B

GNDIO2

PB8B

T

C

T

PB8C

T

PB8D

C

PB9A

PB9C

T

SLEEPN

PB9D

SLEEPN

1

0

T

C

T

2

1

0

C

PB9F

PR11D

PR11B

PR11C

PR11A

PR10D

PR10C

PR10B

PR10A

PR9D

C

T

C

T

C

T

C

T

C

T

C

T

C

VCCIO1

PR9B

T

GNDIO1

PR7B

C

T

C

T

C

T

C

T

C

T

C

PR6C

PR6B

PR5D

PR5B

PR4D

PR4B

PR3D

PR3B

PR2D

PR2B

VCCIO1

GNDIO1

PT9F

T

C

T

PT9E

C

T

PT9C

PT5A

PT9A

PT4F

C

T

VCCIO0

GNDIO0

PT7E

PT4E

PT4D

C

4-6

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO256 and LA-MachXO640 Logic Signal Connections:

100 TQFP (Cont.)

LAMXO256

LAMXO640

Ball

Dual

Function

Ball

Function

Dual

Function

Pin Number Function

Bank

Differential

Bank

Differential

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

PT4C

GND

0

-

T

PT7A

GND

0

-

PT4B

PT4A

PT3D

VCCAUX

PT3C

VCC

0

-

PCLK0_1**

PCLK0_0**

C

T

PT6B

PT5B

PT5A

VCCAUX

PT4F

0

-

PCLK0_1**

PCLK0_0**

C

T

C

0

-

T

0

-

VCC

PT3B

VCCIO0

GNDIO0

PT3A

PT2F

0

C

PT3F

0

VCCIO0

GNDIO0

PT3B

PT3A

PT2F

T

C

T

C

T

C

T

C

T

PT2E

PT2D

PT2C

PT2B

PT2A

C

T

PT2E

PT2B

PT2C

PT2A

C

T

* NC for “E” devices.

** Primary clock inputs are single-ended.

4-7

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO1200 and LA-MachXO2280 Logic Signal Connections:

100 TQFP

LAMXO1200

LAMXO2280

Ball

Dual

Ball

Dual

Number

Function

Bank

7

-

Function

Differential

Function

Bank

7

-

Function

Differential

1

PL2A

PL2B

T

C

T

PL2A

PL2B

LUM0_PLLT_FB_A

LUM0_PLLC_FB_A

LUM0_PLLT_IN_A

LUM0_PLLC_IN_A

T

C

T

2

3

PL3C

4

PL3D

C

PL3D

C

5

PL4B

6

VCCIO7

PL6A

VCCIO7

PL7A

7

T*

8

PL6B

GSRN

C*

PL7B

GSRN

C*

9

GND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

PL7C

7

6

-

T

C

T

PL9C

7

6

-

T

C

T

PL7D

PL9D

PL8C

PL10C

PL10D

PL11C

PL13A

PL13B

VCC

PL8D

C

PL9C

PL10A

PL10B

VCC

T*

C*

PL11B

PL11C

VCCIO6

PL13C

PL14A

PL14B

PL15A

PL15B

6

PL14D

PL14C

VCCIO6

PL16C

PL17A

PL17B

PL18A

PL18B

6

C

T

TSALL

LLM0_PLLT_FB_A

LLM0_PLLC_FB_A

LLM0_PLLT_IN_A

LLM0_PLLC_IN_A

T*

C*

T*

C*

LLM0_PLLT_FB_A

LLM0_PLLC_FB_A

LLM0_PLLT_IN_A

LLM0_PLLC_IN_A

T*

C*

T*

C*

GNDIO6

GNDIO5

GNDIO6

GNDIO5

26**

-

27

28

29

30

31

32

33

34

35

36

37

38

39

40

VCCIO5

TMS

5

-

VCCIO5

TMS

5

-

TMS

TCK

TMS

TCK

PB3B

PB4A

PB4B

TDO

PB3B

PB4A

PB4B

TDO

T

C

TDO

TDI

TDO

TDI

VCC

VCCAUX

PB6E

PB6F

PB7B

PB7F

-

VCCAUX

PB8E

PB8F

PB10F

PB10B

-

5

4

T

5

4

T

C

PCLK4_1***

PCLK4_0***

PCLK4_1***

PCLK4_0***

4-8

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO1200 and LA-MachXO2280 Logic Signal Connections:

100 TQFP (Cont.)

LAMXO1200

LAMXO2280

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank

Differential

Bank

Differential

41

42

43

44

45

46

47

48

49

GND

PB9A

-

GND

PB12A

PB12B

VCCIO4

PB13A

PB13B

NC

-

4

-

T

4

-

T

PB9B

C

VCCIO4

PB10A

PB10B

NC

T

C

NC

PB11A

PB11B

4

T

PB16A

PB16B

4

T

C

GNDIO3

GNDIO4

GNDIO3

GNDIO4

50**

-

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

PR16B

PR15B

PR15A

PR14B

PR14A

VCCIO3

PR12B

PR12A

GND

3

-

PR19B

PR18B

PR18A

PR17B

PR17A

VCCIO3

PR15B

PR15A

GND

3

-

C*

T*

C*

T*

C*

T*

C*

T*

C*

T*

C*

T*

PR10B

PR10A

PR9B

3

2

-

C*

T*

C*

T*

C*

T*

PR13B

PR13A

PR11B

PR11A

PR10B

PR10A

VCC

3

2

-

C*

T*

C*

T*

C*

T*

PR9A

PR8B

PR8A

VCC

PR6C

PR6B

2

PR8C

2

C*

T*

PR8B

C*

T*

PR6A

PR8A

VCCIO2

PR4D

PR4B

VCCIO2

PR5D

C*

T*

C

PR5B

C*

T*

C*

T*

PR4A

PR5A

PR2B

PR3B

PR2A

T

PR3A

GNDIO1

GNDIO2

GNDIO1

GNDIO2

76**

-

77

78

79

PT11C

PT11B

PT11A

1

PT15C

PT14B

PT14A

1

C

T

C

T

4-9

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO1200 and LA-MachXO2280 Logic Signal Connections:

100 TQFP (Cont.)

LAMXO1200

LAMXO2280

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank

Differential

Bank

Differential

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

VCCIO1

PT9E

PT9A

GND

1

-

VCCIO1

PT12D

PT12C

GND

1

-

C

T

PT8B

PT8A

PT7D

PT6F

1

0

-

C

T

PT11B

PT11A

PT10B

PT9B

1

0

-

C

T

PCLK1_1***

PCLK1_0***

PCLK1_1***

PCLK1_0***

PT6D

PT6C

VCCAUX

VCC

C

T

PT8F

C

T

PT8E

VCCAUX

VCC

-

PT5B

PT4B

VCCIO0

PT3D

PT3C

PT3B

PT2B

PT2A

0

PT6D

0

PT6F

VCCIO0

PT4B

C

T

C

T

PT4A

PT3B

C

T

PT2B

C

T

PT2A

GNDIO0

GNDIO7

GNDIO0

GNDIO7

100**

-

*Supports true LVDS outputs.

**Double bonded to the pin.

*** Primary clock inputs are single-ended.

4-10

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal

Connections: 144 TQFP

LAMXO640

LAMXO1200

LAMXO2280

Ball

Dual

Function

Ball

Dual

Function

Ball

Dual

Function

Number Function Bank

Differential Function Bank

Differential

1

PL2A

PL2C

PL2B

3

-

T

PL2A

PL2B

7

-

T

C

PL2A

PL2B

7

-

LUM0_PLLT_FB_A

LUM0_PLLC_FB_A

T

C

2

3

C

T

PL3A

T*

C*

T

PL3A

T*

C*

T

4

PL3A

PL3B

5

PL2D

PL3B

C

T

PL3C

LUM0_PLLT_IN_A

LUM0_PLLC_IN_A

6

PL3D

C

PL3D

C

7

PL3C

PL3D

PL4A

T*

C*

PL4A

T*

C*

8

C

PL4B

9

PL4C

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

VCCIO3

GNDIO3

PL4D

PL5A

VCCIO7

GNDIO7

PL5C

VCCIO7

GNDIO7

PL6C

T

PL6A

T*

PL7A

T*

PL5B

GSRN

C

PL6B

GSRN

C*

PL7B

GSRN

C*

PL5D

GND

PL6D

PL7D

GND

PL6C

PL6D

PL7A

3

-

T

C

T

PL7C

7

6

-

T

C

PL9C

7

6

-

T

C

PL7D

PL9D

PL10A

PL10B

VCC

T*

C*

PL13A

PL13B

VCC

T*

C*

PL7B

C

VCC

PL8A

3

2

T

PL11A

PL11B

PL11C

PL12B

VCCIO6

GNDIO6

PL13D

PL14A

PL14B

PL14C

PL14D

PL15A

PL15B

PL16A

PL16B

GNDIO5

VCCIO5

TMS

6

5

T*

PL13D

PL14D

PL14C

PL15B

VCCIO6

GNDIO6

PL16D

PL17A

PL17B

PL17C

PL17D

PL18A

PL18B

PL19A

PL19B

GNDIO5

VCCIO5

TMS

6

5

PL8B

C

C*

C

T

PL8C

PL9C

VCCIO3

GNDIO3

PL9D

PL10A

PL10B

PL10C

PL11A

PL10D

PL11C

PL11B

PL11D

GNDIO2

VCCIO2

TMS

TSALL

T

C

T

LLM0_PLLT_FB_A

LLM0_PLLC_FB_A

T*

C*

T

LLM0_PLLT_FB_A

LLM0_PLLC_FB_A

T*

C*

T

C

T

C

T

LLM0_PLLT_IN_A

LLM0_PLLC_IN_A

T*

C*

T

LLM0_PLLT_IN_A

LLM0_PLLC_IN_A

T*

C*

T

C

TMS

TCK

TMS

TCK

TMS

TCK

PB2C

PB3A

TCK

PB2C

PB2D

TCK

T

PB2A

PB2B

TCK

T

C

PB3B

PB3C

PB3D

PB4A

TDO

C

T

C

T

PB3A

PB3B

PB4A

PB4B

TDO

T

C

T

PB3A

PB3B

PB4A

PB4B

TDO

T

C

T

C

TDO

PB4B

PB4C

PB4D

C

T

PB4D

PB5A

PB5B

PB4D

PB5A

PB5B

T

C

4-11

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal

Connections: 144 TQFP (Cont.)

LAMXO640

LAMXO1200

LAMXO2280

Ball

Dual

Function

Ball

Dual

Function

Ball

Dual

Function

Number Function Bank

Differential Function Bank

Differential

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70**

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

TDI

VCC

2

-

TDI

VCC

5

-

TDI

VCC

5

-

TDI

VCCAUX

PB5A

-

VCCAUX

PB6F

-

VCCAUX

PB8F

-

2

-

T

5

4

-

5

4

-

PB5B

PCLKT2_1***

PCLKT2_0***

C

PB7B

PCLK4_1***

PCLK4_0***

PB10F

PB10C

PB10D

PB10B

GND

PCLK4_1***

PCLK4_0***

PB5D

PB6A

PB7C

T

PB7D

C

PB6B

C

PB7F

GND

PB7C

PB7E

2

-

PB9A

4

-

T

PB12A

PB12B

PB12E

VCCIO4

GNDIO4

PB13A

PB13B

PB13C

PB13D

PB14D

NC

4

-

T

PB9B

C

PB8A

PB9E

VCCIO2

GNDIO2

PB8C

PB8D

PB9A

VCCIO4

GNDIO4

PB10A

PB10B

PB10C

PB10D

PB10F

NC

T

C

T

C

T

C

T

C

T

PB9C

PB9B

C

SLEEPN

PB9D

PB9F

SLEEPN

2

1

-

C

PB11C

PB11D

PR16B

PR16A

PR15B

PR15A

PR14D

PR14C

PR14B

PR14A

PR13D

VCCIO3

GNDIO3

PR12B

PR12A

PR11B

PR11A

GND

4

3

-

T

C

PB16C

PB16D

PR20B

PR20A

PR19B

PR19A

PR17D

PR17C

PR17B

PR17A

PR16D

VCCIO3

GNDIO3

PR15B

PR15A

PR14B

PR14A

GND

4

3

-

T

C

T

PR11D

PR11B

PR11C

PR10D

PR11A

PR10B

PR10C

PR10A

PR9D

VCCIO1

GNDIO1

PR9A

PR8C

PR8A

PR7D

GND

C

T

C

T

C

T

C

T

C*

T*

C

T

C

T

C*

T*

C*

T*

C*

T*

C*

T*

C*

T*

C*

T*

PR7B

PR7A

PR6D

PR6C

VCC

1

-

C

T

C

T

PR10B

PR10A

PR8B

3

2

-

C*

T*

C*

T*

PR13B

PR13A

PR10B

PR10A

VCC

3

2

-

C*

T*

C*

T*

PR8A

VCC

PR5D

PR5B

PR4D

PR4B

VCCIO1

GNDIO1

PR4A

1

PR6B

2

C*

T*

C*

T*

PR8B

2

C*

T*

C*

T*

PR6A

PR8A

PR5B

PR7B

C

T

PR5A

PR7A

VCCIO2

GNDIO2

PR4C

VCCIO2

GNDIO2

PR5C

4-12

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal

Connections: 144 TQFP (Cont.)

LAMXO640

LAMXO1200

LAMXO2280

Ball

Dual

Function

Ball

Dual

Function

Ball

Dual

Function

Number Function Bank

Differential Function Bank

Differential

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

PR3D

PR3C

PR3B

PR2D

PR3A

PR2B

PR2C

PR2A

PT9F

PT9D

PT9E

PT9B

PT9C

PT9A

PT8C

PT8B

VCCIO0

GNDIO0

PT8A

PT7E

PT7C

PT7A

GND

1

0

-

C

T

C

T

C

T

C

T

C

T

PR4B

PR4A

PR3D

PR3C

PR3B

PR3A

PR2B

PR2A

PT11D

PT11C

PT11B

PT11A

PT10F

PT10E

PT10D

PT10C

VCCIO1

GNDIO1

PT9F

2

1

-

C*

T*

C

T

PR5B

PR5A

PR4D

PR4C

PR4B

PR4A

PR3B

PR3A

PT16D

PT16C

PT16B

PT16A

PT15D

PT15C

PT14B

PT14A

VCCIO1

GNDIO1

PT12F

PT12E

PT12D

PT12C

GND

2

1

-

C*

T*

C

T

C*

T*

C

T

C*

T*

C*

T*

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

PT9E

PT9B

PT9A

GND

PT6B

PT6A

PT5C

PT5B

VCCAUX

VCC

0

-

PCLK0_1***

PCLK0_0***

C

T

PT7D

PT7B

1

0

-

PCLK1_1***

PCLK1_0***

PT10B

PT9D

1

-

PCLK1_1***

PCLK1_0***

C

T

C

T

PT7A

PT9C

PT6F

PT9B

VCCAUX

VCC

VCCAUX

VCC

-

PT4D

PT4B

PT4A

PT3F

PT3D

VCCIO0

GNDIO0

PT3B

PT2F

PT3A

PT2D

PT2E

PT2B

PT2C

PT2A

0

PT5D

PT5C

PT5B

0

C

T

C

T

PT7B

0

C

T

C

T

PT7A

PT6D

PT5A

PT6E

T

PT4B

PT6F

C

VCCIO0

GNDIO0

PT3D

PT3C

PT3B

VCCIO0

GNDIO0

PT4B

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

PT4A

PT3B

PT3A

PT2D

PT2C

PT2B

PT2D

C

T

PT2C

PT2B

C

T

PT2A

*Supports true LVDS outputs.

**NC for “E” devices.

***Primary clock inputs arer single-ended.

4-13

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal

Connections: 256 ftBGA

LAMXO640

LAMXO1200

LAMXO2280

Ball

Dual

Function

Ball

Dual

Function

Ball

Dual

Function

Number Function Bank

Differential Number Function Bank

Differential

GND

GNDIO3

3

GND GNDIO7

VCCIO7 VCCIO7

7

-

GND GNDIO7

VCCIO7 VCCIO7

7

-

VCCIO3 VCCIO3

E4

E5

F5

F6

F3

F4

E3

E2

C3

C2

B1

C1

NC

E4

E5

F5

F6

F3

F4

E3

E2

C3

C2

B1

C1

PL2A

PL2B

PL3A

PL3B

PL3C

PL3D

PL4A

PL4B

PL4C

PL4D

PL5A

PL5B

T

C

E4

E5

F5

F6

F3

F4

E3

E2

C3

C2

B1

C1

PL2A

PL2B

PL3A

PL3B

PL3C

PL3D

PL4A

PL4B

PL4C

PL4D

PL5A

PL5B

LUM0_PLLT_FB_A

LUM0_PLLC_FB_A

T

C

NC

T**

C**

T

T**

C**

T

NC

PL3A

PL3B

PL2C

PL2D

NC

3

T

C

T

LUM0_PLLT_IN_A

LUM0_PLLC_IN_A

C

T**

C**

T

T**

C**

T

C

NC

C

PL2A

PL2B

3

T

T**

C**

T**

C**

C

VCCIO3 VCCIO3

VCCIO7 VCCIO7

GND

D2

D1

F2

G2

E1

F1

G4

G5

GND

G3

H3

H4

H5

-

GNDIO3

PL3C

PL3D

PL5A

PL5B

PL4A

PL4B

NC

GND

D2

GNDIO7

PL5C

PL5D

PL6A

PL6B

PL6C

PL6D

PL7A

PL7B

GND

D2

GNDIO7

PL6C

PL6D

PL7A

PL7B

PL7C

PL7D

PL8A

PL8B

GND

T

C

T

C

T

C

D1

F2

T**

C**

T

F2

T**

C**

T

GSRN

C

T

G2

E1

GSRN

G2

E1

GSRN

C

F1

C

F1

C

G4

G5

GND

G3

H3

T**

C**

G4

G5

GND

G3

H3

T**

C**

NC

GND

PL4C

PL4D

NC

-

3

T

PL7C

PL7D

PL8A

PL8B

7

6

T

PL8C

PL8D

PL9A

PL9B

7

6

T

C

H4

T**

C**

H4

T**

C**

NC

H5

-

VCCIO7 VCCIO7

-

GND

G1

H1

H2

J2

GNDIO7

PL8C

PL8D

PL9A

GND

G1

H1

H2

J2

GNDIO7

PL10C

PL10D

PL11A

PL11B

PL11C

PL11D

PL12A

G1

H1

H2

J2

PL5C

PL5D

PL6A

PL6B

PL7C

PL7D

PL6C

-

3

T

C

T

C

T

C

T

C

T

C

T**

C**

T

T**

C**

T

PL9B

J3

PL9C

PL9D

PL10A

J3

K3

J1

K3

J1

C

K3

J1

C

T**

-

VCCIO6 VCCIO6

-

GND

K1

K2

L2

GNDIO6

PL10B

PL10C

PL10D

PL11A

PL11B

PL11D

PL11C

PL12A

PL12B

PL12C

PL12D

GND

K1

K2

L2

GNDIO6

PL12B

PL12C

PL12D

PL13A

PL13B

PL14D

PL14C

PL15A

PL15B

PL15C

PL15D

K1

K2

L2

L1

M1

P1

N1

L3

M3

M2

N2

PL6D

PL9A

PL9B

PL7A

PL7B

PL8D

PL8C

PL10A

PL10B

PL9C

PL9D

3

C

T

C

T

C

T

C

T

C

C**

T

C**

T

C

L1

T**

C**

C

L1

T**

C**

C

M1

P1

N1

L3

M1

P1

N1

L3

TSALL

T

TSALL

T

T**

C**

T

T**

C**

T

M3

M2

N2

M3

M2

N2

C

VCCIO3 VCCIO3

GND GNDIO3

VCCIO6 VCCIO6

GND GNDIO6

VCCIO6 VCCIO6

GND GNDIO6

4-14

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal

Connections: 256 ftBGA (Cont.)

LAMXO640

LAMXO1200

LAMXO2280

Ball

Dual

Function

Ball

Dual

Function

Ball

Dual

Function

Number Function Bank

Differential Number Function Bank

Differential

J4

J5

PL8A

PL8B

PL11A

PL11B

-

3

-

T

C

T

J4

J5

PL13A

PL13B

PL13C

PL13D

-

6

-

T**

C**

T

J4

J5

PL16A

PL16B

PL16C

PL16D

GND

6

-

T**

C**

T

R1

R2

-

R1

R2

-

R1

R2

GND

K5

K4

L5

C

K5

K4

L5

L4

M5

M4

N4

N3

NC

K5

K4

L5

L4

M5

M4

N4

N3

PL14A

PL14B

PL14C

PL14D

PL15A

PL15B

PL16A

PL16B

6

5

-

LLM0_PLLT_FB_A

LLM0_PLLC_FB_A

T**

C**

T

PL17A

PL17B

PL17C

PL17D

PL18A

PL18B

PL19A

PL19B

6

5

-

LLM0_PLLT_FB_A

LLM0_PLLC_FB_A

T**

C**

T

NC

PL10C

PL10D

NC

3

T

C

L4

C

LLM0_PLLT_IN_A

LLM0_PLLC_IN_A

T**

C**

T

M5

M4

N4

N3

LLM0_PLLT_IN_A

LLM0_PLLC_IN_A

T**

C**

T

NC

PL11C

PL11D

3

2

T

C

VCCIO3 VCCIO3

VCCIO6 VCCIO6

GND

GNDIO3

GNDIO2

GND

GNDIO6

GNDIO5

GND

GNDIO6

GNDIO5

VCCIO2 VCCIO2

VCCIO5 VCCIO5

P4

P2

P3

N5

R3

N6

T2

TMS

NC

TMS

TCK

P4

P2

P3

N5

R3

N6

T2

TMS

PB2A

PB2B

PB2C

TCK

TMS

TCK

P4

P2

P3

N5

R3

N6

T2

TMS

PB2A

PB2B

PB2C

TCK

TMS

TCK

T

C

T

C

T

NC

TCK

2

NC

PB2D

PB3A

PB3B

PB3C

PB3D

PB4A

PB4B

PB4C

TDO

C

T

C

T

C

T

C

T

PB2D

PB3A

PB3B

PB3C

PB3D

PB4A

PB4B

PB4C

TDO

C

T

C

T

C

T

C

T

PB2A

PB2B

PB2C

PB2D

PB3A

PB3B

PB3C

TDO

2

T

C

T

C

T

C

T

T3

R4

R5

P5

P6

T5

R4

R5

P5

P6

T5

R4

R5

P5

P6

T5

M6

T4

TDO

M6

T4

TDO

M6

T4

TDO

PB3D

PB4A

GNDIO2

C

T

PB4D

PB5A

GNDIO5

C

T

PB4D

PB5A

GNDIO5

C

T

R6

GND

R6

GND

R6

GND

VCCIO2 VCCIO2

VCCIO5 VCCIO5

T6

N7

T8

T7

M7

M8

T9

R7

R8

-

PB4B

TDI

C

T6

N7

T8

T7

M7

M8

T9

R7

R8

PB5B

TDI

C

T6

N7

T8

T7

M7

M8

T9

R7

R8

PB5B

TDI

C

TDI

PB4C

PB4D

NC

T

PB5C

PB5D

PB6A

PB6B

VCCAUX

PB6C

PB6D

T

C

T

PB6A

PB6B

PB7C

PB7D

VCCAUX

PB8C

PB8D

T

C

T

C

NC

C

VCCAUX

PB4E

PB4F

-

2

T

5

4

T

5

4

T

C

VCCIO5 VCCIO5

-

GND

P7

GNDIO5

PB6E

PB6F

PB7A

PB7B

PB7D

PB7C

PB7F

GND

P7

GNDIO5

PB9A

P7

P8

N8

N9

P10

P9

M9

PB5C

PB5D

PB5A

PB5B

PB7B

PB7A

PB6B

2

T

C

T

C

T

C

T

P8

PB9B

N8

PB10E

PB10F

PB10D

PB10C

PB10B

PCLK2_1****

PCLK2_0****

C

T

N9

PCLK4_1****

PCLK4_0****

4-15

C

T

N9

PCLK4_1****

PCLK4_0****

C

T

P10

P9

P10

P9

C

M9

C

M9

C

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal

Connections: 256 ftBGA (Cont.)

LAMXO640

LAMXO1200

LAMXO2280

Ball

Dual

Function

Ball

Dual

Function

Ball

Dual

Function

Number Function Bank

Differential Number Function Bank

Differential

-

VCCIO4 VCCIO4

4

-

VCCIO4 VCCIO4

4

-

GND

M10

R9

GNDIO4

PB7E

PB8A

PB8B

PB8C

PB8D

PB8E

PB8F

GND

M10

R9

GNDIO4

PB10A

PB11C

PB11D

PB12A

PB12B

PB12C

PB12D

M10

R9

PB6A

PB6C

PB6D

PB7C

PB7D

NC

2

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

R10

T10

T11

N10

N11

R10

T10

T11

N10

N11

R10

T10

T11

N10

N11

NC

VCCIO2 VCCIO2

2

-

VCCIO4 VCCIO4

GND

R11

R12

P11

P12

T13

T12

R13

R14

GND

T14

T15

GNDIO2

PB7E

PB7F

PB8A

PB8B

PB8C

PB8D

PB9A

PB9B

GND

R11

R12

P11

P12

T13

T12

R13

R14

GND

T14

T15

P13

P14

R15

R16

P15

P16

GNDIO4

PB9A

GND

R11

R12

P11

P12

T13

T12

R13

R14

GND

T14

T15

P13

P14

R15

R16

P15

P16

GNDIO4

PB13A

PB13B

PB13C

PB13D

PB14A

PB14B

PB14C

PB14D

GND

T

C

T

C

T

C

T

PB9B

PB9C

PB9D

PB9E

C

T

C

T

C

T

C

T

PB9F

C

T

C

T

PB10A

PB10B

GND

C

-

PB9C

PB9D

2

-

T

PB10C

PB10D

NC

4

-

T

PB15A

PB15B

NC

4

-

T

C

P13*** SLEEPN

SLEEPN

P14

R15

R16

P15

P16

PB9F

NC

2

PB10F

PB11A

PB11B

PB11C

PB11D

4

3

PB15D

PB16A

PB16B

PB16C

PB16D

4

3

T

C

T

C

T

NC

C

VCCIO2 VCCIO2

2

1

VCCIO4 VCCIO4

GND

GNDIO2

GNDIO1

GND

GNDIO4

GNDIO3

GND

GNDIO4

GNDIO3

VCCIO1 VCCIO1

VCCIO3 VCCIO3

M11

L11

N12

N13

M13

M12

N14

N15

L13

L12

M14

NC

M11

L11

N12

N13

M13

M12

N14

N15

L13

L12

M14

PR16B

PR16A

PR15B

PR15A

PR14D

PR14C

PR14B

PR14A

PR13D

PR13C

PR13B

C

T

M11

L11

N12

N13

M13

M12

N14

N15

L13

L12

M14

PR20B

PR20A

PR18B

PR18A

PR17D

PR17C

PR17B

PR17A

PR16D

PR16C

PR16B

C

T

NC

C**

T**

C

C**

T**

C

NC

T

PR11D

PR11C

PR11B

PR11A

PR10B

1

C

T

C**

T**

C

C**

T**

C

T

C

C**

VCCIO1 VCCIO1

VCCIO3 VCCIO3

GND

L14

N16

M16

M15

L15

L16

K16

K13

GNDIO1

PR10A

PR10D

PR10C

PR9D

GND

L14

N16

M16

M15

L15

L16

K16

K13

GNDIO3

PR13A

PR12D

PR12C

PR12B

PR12A

PR11D

PR11C

PR11B

GND

L14

N16

M16

M15

L15

L16

K16

K13

GNDIO3

PR16A

PR15D

PR15C

PR15B

PR15A

PR14D

PR14C

PR14B

T

C

T

T**

C

T**

C

T

C

T

C**

T**

C

C**

T**

C

PR9C

PR9B

C

T

PR9A

T

PR8D

C

C**

4-16

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal

Connections: 256 ftBGA (Cont.)

LAMXO640

LAMXO1200

LAMXO2280

Ball

Dual

Function

Ball

Dual

Function

Ball

Dual

Function

Number Function Bank

Differential Number Function Bank

Differential

J13

GND

K14

J14

K15

J15

-

PR8C

GND

PR8B

PR8A

PR7D

PR7C

-

1

-

T

J13

GND

K14

J14

PR11A

GND

3

-

T**

J13

GND

K14

J14

PR14A

GND

3

-

T**

1

C

T

C

T

PR10D

PR10C

PR10B

PR10A

GNDIO3

3

2

-

C

T

PR13D

PR13C

PR13B

PR13A

GNDIO3

3

2

-

C

T

K15

J15

C**

T**

K15

J15

C**

T**

GND

-

VCCIO3 VCCIO3

K12

J12

J16

H16

H15

G15

H14

G14

GND

NC

K12

J12

PR9D

PR9C

PR9B

PR9A

PR8D

PR8C

PR8B

PR8A

GNDIO2

C

T

K12

J12

PR11D

PR11C

PR11B

PR11A

PR10D

PR10C

PR10B

PR10A

GNDIO2

C

T

NC

PR7B

PR7A

PR6B

PR6A

PR5D

PR5C

GNDIO1

1

-

C

T

C

T

C

T

J16

C**

T**

C

J16

C**

T**

C

H16

H15

G15

H14

G14

GND

H16

H15

G15

H14

G14

GND

T

C**

T**

C**

T**

VCCIO1 VCCIO1

VCCIO2 VCCIO2

H13

H12

G13

G12

G16

F16

F15

E15

E16

D16

PR6D

PR6C

PR4D

PR4C

PR5B

PR5A

PR4B

PR4A

PR3B

PR3A

C

T

C

T

C

T

C

T

C

T

H13

H12

G13

G12

G16

F16

F15

E15

E16

D16

PR7D

PR7C

PR7B

PR7A

PR6D

PR6C

PR6B

PR6A

PR5D

PR5C

C

T

H13

H12

G13

G12

G16

F16

F15

E15

E16

D16

PR9D

PR9C

PR9B

PR9A

PR7D

PR7C

PR7B

PR7A

PR6D

PR6C

C

T

C**

T**

C

C**

T**

C

T

C**

T**

C

C**

T**

C

T

VCCIO1 VCCIO1

VCCIO2 VCCIO2

GND

D15

C15

C16

B16

F14

E14

-

GNDIO1

PR2D

PR2C

PR2B

PR2A

PR3D

PR3C

-

GND

D15

C15

C16

B16

F14

E14

-

GNDIO2

PR5B

PR5A

PR4D

PR4C

PR4B

PR4A

-

GND

D15

C15

C16

B16

F14

E14

GND

F12

F13

E12

E13

D13

D14

GNDIO2

PR6B

PR6A

PR5D

PR5C

PR5B

PR5A

GND

C

T

C

T

C

T

C**

T**

C

C**

T**

C

T

C**

T**

C**

T**

F12

F13

E12

E13

D13

D14

NC

F12

F13

E12

E13

D13

D14

PR3D

PR3C

PR3B

PR3A

PR2B

PR2A

2

1

C

T

PR4D

PR4C

PR4B

PR4A

PR3B

PR3A

2

1

C

NC

T

NC

C**

T**

C

C**

T**

C**

T**

NC

T

VCCIO0 VCCIO0

0

VCCIO2 VCCIO2

GND

GNDIO0

GND

GNDIO2

GNDIO1

GND

GNDIO2

GNDIO1

VCCIO0 VCCIO0

VCCIO1 VCCIO1

B15

A15

C14

B14

C13

B13

NC

B15

A15

C14

B14

C13

B13

PT11D

PT11C

PT11B

PT11A

PT10F

PT10E

C

T

C

T

C

T

B15

A15

C14

B14

C13

B13

PT16D

PT16C

PT16B

PT16A

PT15D

PT15C

C

T

C

T

C

T

NC

PT9F

PT9E

0

C

T

4-17

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal

Connections: 256 ftBGA (Cont.)

LAMXO640

LAMXO1200

LAMXO2280

Ball

Dual

Function

Ball

Dual

Function

Ball

Dual

Function

Number Function Bank

Differential Number Function Bank

Differential

E11

E10

D12

D11

A14

A13

C12

C11

-

NC

E11

E10

D12

D11

A14

A13

C12

C11

PT10D

PT10C

PT10B

PT10A

PT9F

1

-

C

T

C

T

C

T

C

T

E11

E10

D12

D11

A14

A13

C12

C11

PT15B

PT15A

PT14D

PT14C

PT14B

PT14A

PT13D

PT13C

1

-

C

T

C

T

C

T

C

T

PT9D

PT9C

PT7F

PT7E

PT8B

PT8A

-

0

C

T

C

T

C

T

PT9E

PT9D

PT9C

VCCIO1 VCCIO1

-

GND

B12

B11

A12

A11

GND

B10

B9

GNDIO1

PT9B

PT9A

PT8F

PT8E

GND

B12

B11

A12

A11

GND

B10

B9

GNDIO1

PT12D

PT12C

PT12B

PT12A

GND

B12

B11

A12

A11

GND

B10

B9

PT7B

PT7A

PT7D

PT7C

GND

PT5D

PT5C

PT8D

PT8C

-

0

-

C

T

C

T

C

T

C

T

C

T

C

T

0

C

T

C

T

PT8D

PT8C

PT8B

PT8A

1

0

-

C

T

C

T

PT11B

PT11A

PT10F

PT10E

1

0

-

C

T

C

T

D10

D9

D10

D9

D10

D9

-

VCCIO1 VCCIO1

-

GND

C10

C9

GNDIO1

PT7F

PT7E

PT7D

PT7C

PT7B

PT7A

PT6F

PT6E

GND

C10

C9

GNDIO1

PT10D

PT10C

PT10B

PT10A

PT9D

C10

C9

PT6D

PT6C

PT6B

PT6A

PT9B

PT9A

PT5B

PT5A

0

-

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

A9

PCLK0_1****

PCLK0_0****

A9

PCLK1_1****

PCLK1_0****

A9

PCLK1_1****

PCLK1_0****

A10

E9

A10

E9

A10

E9

E8

PT9C

D7

PT9B

D8

PT9A

VCCIO0 VCCIO0

GND

C8

B8

A8

A7

A6

B7

B6

C6

C7

A5

A4

E7

E6

B5

B4

D5

D6

C4

C5

-

GNDIO0

PT4F

PT4E

VCCAUX

PT4D

PT4C

PT4B

PT4A

PT3C

PT3D

PT3E

PT3F

NC

GND

C8

B8

A8

A7

A6

B7

B6

C6

C7

A5

A4

E7

E6

B5

B4

D5

D6

C4

C5

-

GNDIO0

PT6D

PT6C

VCCAUX

PT6B

PT6A

PT5F

PT5E

PT5C

PT5D

PT5A

PT5B

PT4C

PT4D

PT3F

PT3E

PT3D

PT3C

PT4A

PT4B

-

GND

C8

B8

A8

A7

A6

B7

B6

C6

C7

A5

A4

E7

E6

B5

B4

D5

D6

C4

C5

GND

D4

D3

GNDIO0

PT8D

PT8C

VCCAUX

PT7D

PT7C

PT7B

PT7A

PT6A

PT6B

PT6C

PT6D

PT6E

PT6F

PT5D

PT5C

PT5B

PT5A

PT4A

PT4B

GND

C

T

C

T

C

T

0

C

T

C

T

C

T

C

0

-

C

T

C

T

C

T

C

T

C

T

C

T

C

0

-

C

T

C

T

C

T

C

T

C

T

C

T

C

NC

PT3B

PT3A

PT2D

PT2C

PT2E

PT2F

-

0

-

C

T

C

T

C

D4

D3

NC

D4

D3

PT2D

PT2C

0

C

T

PT3D

PT3C

0

C

T

NC

4-18

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO640, LA-MachXO1200 and LA-MachXO2280 Logic Signal

Connections: 256 ftBGA (Cont.)

LAMXO640

LAMXO1200

LAMXO2280

Ball

Dual

Function

Ball

Dual

Function

Ball

Dual

Function

Number Function Bank

Differential Number Function Bank

Differential

A3

A2

B3

B2

PT2B

PT2A

NC

0

C

T

A3

A2

B3

B2

PT3B

PT3A

PT2B

PT2A

0

-

C

T

C

T

A3

A2

B3

B2

PT3B

PT3A

PT2D

PT2C

0

-

C

T

C

T

NC

VCCIO0 VCCIO0

0

-

VCCIO0 VCCIO0

GND

A1

GNDIO0

GND

A1

GNDIO0

GND

A1

GNDIO0

GND

A16

F11

G8

G9

H7

GND

-

A16

F11

G8

G9

H7

GND

-

A16

F11

G8

G9

H7

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

H8

GND

-

H8

GND

-

H8

GND

-

H9

GND

-

H9

GND

-

H9

GND

-

H10

J7

GND

-

H10

J7

GND

-

H10

J7

GND

-

GND

-

GND

-

GND

-

J8

GND

-

J8

GND

-

J8

GND

-

J9

GND

-

J9

GND

-

J9

GND

-

J10

K8

GND

-

J10

K8

GND

-

J10

K8

GND

-

GND

-

GND

-

GND

-

K9

GND

-

K9

GND

-

K9

GND

-

L6

GND

-

L6

GND

-

L6

GND

-

T1

GND

-

T1

GND

-

T1

GND

-

T16

G7

G10

K7

GND

-

T16

G7

G10

K7

GND

-

T16

G7

G10

K7

GND

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

K10

H6

VCC

-

K10

H6

VCC

-

K10

H6

VCC

-

VCCIO3

VCCIO2

VCCIO1

VCCIO0

3

2

1

0

VCCIO7

VCCIO6

VCCIO5

VCCIO4

VCCIO3

VCCIO2

VCCIO1

VCCIO0

7

6

5

4

3

2

1

0

VCCIO7

VCCIO6

VCCIO5

VCCIO4

VCCIO3

VCCIO2

VCCIO1

VCCIO0

7

6

5

4

3

2

1

0

G6

K6

G6

K6

G6

K6

J6

L8

L7

L9

L10

K11

J11

H11

G11

F9

L10

K11

J11

H11

G11

F9

L10

K11

J11

H11

G11

F9

F10

F8

F10

F8

F10

F8

F7

* LCMXO640 only.

** Supports true LVDS outputs.

*** NC for “E” devices.

**** Primary clock inputs are single-ended.

4-19

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO2280 Logic Signal Connections: 324 ftBGA

LAMXO2280

Ball Number

GND

VCCIO7

D4

Ball Function

GNDIO7

VCCIO7

PL2A

Bank

7

-

Dual Function

Differential

LUM0_PLLT_FB_A

LUM0_PLLC_FB_A

T

C

F5

PL2B

B3

PL3A

T*

C*

T

C3

PL3B

E4

PL3C

LUM0_PLLT_IN_A

LUM0_PLLC_IN_A

G6

PL3D

C

A1

PL4A

T*

C*

T

B1

PL4B

F4

PL4C

VCC

E3

VCC

PL4D

7

-

C

T*

C*

T

D2

PL5A

D3

PL5B

G5

PL5C

F3

PL5D

C

C2

PL6A

T*

VCCIO7

GND

C1

VCCIO7

GNDIO7

PL6B

C*

T

H5

PL6C

G4

PL6D

C

E2

PL7A

T*

C*

T

D1

PL7B

GSRN

J6

PL7C

H4

PL7D

C

F2

PL8A

T*

C*

E1

PL8B

GND

J3

GND

PL8C

7

T

C

J5

PL8D

G3

PL9A

T*

C*

T

H3

PL9B

K3

PL9C

K5

PL9D

C

F1

PL10A

VCCIO7

GNDIO7

PL10B

PL10C

PL10D

T*

VCCIO7

GND

G1

C*

T

K4

K6

C

4-20

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.)

LAMXO2280

Ball Number

G2

Ball Function

PL11A

PL11B

PL11C

PL11D

PL12A

VCCIO6

GNDIO6

PL12B

PL12C

PL12D

PL13A

PL13B

PL13C

VCC

Bank

6

-

Dual Function

Differential

T*

C*

T

H2

L3

L5

C

H1

T*

VCCIO6

GND

J2

C*

T

L4

L6

C

K2

T*

C*

T

K1

J1

VCC

L2

PL13D

PL14D

PL14C

PL14B

PL14A

PL15A

PL15B

PL15C

PL15D

VCCIO6

GNDIO6

PL16A

PL16B

PL16C

PL16D

GND

6

-

C

M5

M3

TSALL

T

L1

C*

T*

C*

T

M2

M1

N1

M6

M4

C

VCCIO6

GND

P1

T*

C*

T

P2

N3

N4

C

GND

T1

PL17A

PL17B

PL17C

PL17D

PL18A

PL18B

PL19A

PL19B

PL20A

VCCIO6

GNDIO6

GNDIO5

VCCIO5

6

5

LLM0_PLLT_FB_A

LLM0_PLLC_FB_A

T*

C*

T

R1

P3

N5

C

R3

LLM0_PLLT_IN_A

LLM0_PLLC_IN_A

T*

C*

T

R2

P4

N6

C

U1

T

VCCIO6

GND

VCCIO5

4-21

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.)

LAMXO2280

Ball Number

T2

Ball Function

PL20B

TMS

Bank

6

5

-

Dual Function

Differential

C

P6

TMS

V1

PB2A

PB2B

PB2C

TCK

T

C

T

U2

T3

N7

TCK

R4

PB2D

PB3A

PB3B

VCC

C

T

R5

T4

C

VCC

R6

PB3C

PB3D

PB4A

PB4B

PB4C

TDO

5

-

T

C

T

C

T

P7

U3

T5

V2

N8

TDO

V3

PB4D

PB5A

GNDIO5

VCCIO5

PB5B

PB5C

PB5D

TDI

C

T

T6

GND

VCCIO5

U4

C

T

P8

T7

C

V4

TDI

R8

PB6A

PB6B

PB6C

PB6D

PB7A

VCC

T

C

T

C

T

N9

U5

V5

U6

VCC

V6

PB7B

PB7C

PB7D

PB8A

PB8B

VCCAUX

PB8C

PB8D

VCCIO5

GNDIO5

PB8E

PB8F

PB9A

5

-

C

T

P9

T8

C

T

U7

V7

C

M10

U8

5

4

T

V8

C

VCCIO5

GND

T9

T

C

T

U9

V9

4-22

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.)

LAMXO2280

Ball Number

V10

Ball Function

PB9B

Bank

4

-

Dual Function

PCLK4_1**

Differential

C

T

N10

PB9C

R10

PB9D

C

T

P10

PB10F

PB10E

PB10D

PB10C

PB10B

VCCIO4

GNDIO4

PB10A

PB11A

PB11B

GND

T10

U10

C

T

V11

U11

PCLK4_0**

C

VCCIO4

GND

T11

T

C

U12

R11

GND

T12

PB11C

PB11D

PB12A

PB12B

PB12C

PB12D

PB12E

VCCIO4

GNDIO4

PB12F

PB13A

PB13B

PB13C

PB13D

PB14A

PB14B

PB14C

GND

4

-

T

C

T

C

T

C

T

P11

V12

V13

R12

N11

U13

VCCIO4

GND

V14

C

T

C

T

C

T

C

T

T13

P12

R13

N12

V15

U14

V16

GND

T14

PB14D

PB15A

PB15B

NC

4

-

C

T

U15

V17

C

P13

T15

PB15D

PB16A

PB16B

PB16C

PB16D

VCCIO4

GNDIO4

4

U16

T

C

T

V18

N13

R14

C

VCCIO4

GND

4-23

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.)

LAMXO2280

Ball Number

GND

VCCIO3

P15

Ball Function

GNDIO3

VCCIO3

PR20B

PR20A

PR19B

PR19A

PR18B

PR18A

PR17D

PR17C

PR17B

VCC

Bank

3

-

Dual Function

Differential

C

T

N14

N15

C

M13

R15

T

C*

T*

C

T16

N16

M14

U17

T

C*

VCC

U18

PR17A

PR16D

PR16C

PR16B

VCCIO3

GNDIO3

PR16A

PR15D

PR15C

PR15B

PR15A

PR14D

PR14C

PR14B

PR14A

GND

3

-

T*

C

R17

R16

T

P16

C*

VCCIO3

GND

P17

T*

C

L13

M15

T17

T

C*

T*

C

T18

L14

L15

T

R18

C*

T*

P18

GND

K15

PR13D

PR13C

PR13B

PR13A

PR12D

PR12C

PR12B

PR12A

GNDIO3

VCCIO3

PR11D

PR11C

PR11B

PR11A

PR10D

3

2

C

T

K13

N17

C*

T*

C

N18

K16

K14

T

M16

L16

C*

T*

GND

VCCIO3

J16

C

T

J14

M17

L17

C*

T*

C

J15

4-24

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.)

LAMXO2280

Ball Number

J13

Ball Function

PR10C

PR10B

PR10A

GNDIO2

VCCIO2

PR9D

Bank

2

-

Dual Function

Differential

T

M18

L18

C*

T*

GND

VCCIO2

H16

C

T

H14

PR9C

K18

PR9B

C*

T*

C

J18

PR9A

J17

PR8D

VCC

H18

VCC

PR8C

2

-

T

C*

T*

C

H17

PR8B

G17

PR8A

H13

PR7D

H15

PR7C

T

G18

PR7B

C*

T*

C

F18

PR7A

G14

PR6D

G16

PR6C

T

VCCIO2

GND

E18

VCCIO2

GNDIO2

PR6B

C*

T*

C

F17

PR6A

G13

PR5D

G15

PR5C

T

E17

PR5B

C*

T*

E16

PR5A

GND

F15

GND

PR4D

2

1

C

T

E15

PR4C

D17

PR4B

C*

T*

C

D18

PR4A

B18

PR3D

C18

PR3C

T

C16

PR3B

C*

T*

C

D16

PR3A

C17

PR2B

D15

PR2A

T

VCCIO2

GND

VCCIO1

VCCIO2

GNDIO2

GNDIO1

VCCIO1

4-25

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.)

LAMXO2280

Ball Number

E13

Ball Function

PT16D

PT16C

PT16B

PT16A

PT15D

PT15C

PT15B

PT15A

VCC

Bank

1

-

Dual Function

Differential

C

T

C

T

C

T

C

T

C15

F13

D14

A18

B17

A16

A17

VCC

D13

F12

PT14D

PT14C

PT14B

PT14A

PT13D

PT13C

PT13B

PT13A

VCCIO1

GNDIO1

PT12F

PT12E

PT12D

PT12C

PT12B

PT12A

PT11D

GND

1

-

C

T

C

T

C

T

C

T

C14

E12

C13

B16

B15

A15

VCCIO1

GND

B14

C

T

A14

D12

F11

C

T

B13

C

T

A13

C12

GND

B12

C

PT11C

PT11B

PT11A

PT10F

PT10E

VCCIO1

GNDIO1

PT10D

PT10C

PT10B

PT10A

PT9D

1

0

T

C

T

C

T

E11

D11

C11

A12

VCCIO1

GND

F10

C

T

D10

B11

PCLK1_1***

PCLK1_0***

C

T

A11

E10

C

T

C10

D9

PT9C

PT9B

C

T

E9

PT9A

B10

PT8F

C

4-26

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.)

LAMXO2280

Ball Number

A10

VCCIO0

GND

A9

Ball Function

PT8E

Bank

0

-

Dual Function

Differential

T

VCCIO0

GNDIO0

PT8D

PT8C

PT8B

C

T

C9

B9

C

F9

VCCAUX

PT8A

A8

0

-

T

C

T

B8

PT7D

PT7C

VCC

C8

VCC

A7

PT7B

0

-

C

T

B7

PT7A

A6

PT6A

T

B6

PT6B

C

T

D8

PT6C

PT6D

PT6E

F8

C

T

C7

E8

PT6F

C

D7

PT5D

VCCIO0

GNDIO0

PT5C

PT5B

VCCIO0

GND

E7

T

C

T

C

T

C

T

A5

C6

PT5A

B5

PT4A

A4

PT4B

D6

PT4C

PT4D

PT4E

F7

B4

GND

C5

GND

PT4F

0

-

C

T

F6

PT3D

PT3C

PT3B

E5

E6

C

T

D5

PT3A

A3

PT2D

PT2C

PT2B

C

T

C4

A2

C

T

B2

PT2A

VCCIO0

GND

E14

VCCIO0

GNDIO0

GND

4-27

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.)

LAMXO2280

Ball Number

F16

H10

H11

H8

Ball Function

GND

Bank

Dual Function

Differential

-

GND

-

GND

-

H9

GND

-

J10

J11

J4

GND

-

GND

-

GND

-

J8

GND

-

J9

GND

-

K10

K11

K17

K8

GND

-

GND

-

GND

-

GND

-

K9

GND

-

L10

L11

L8

GND

-

GND

-

GND

-

L9

GND

-

N2

GND

-

P14

P5

GND

-

GND

-

R7

GND

-

F14

G11

G9

VCC

-

VCC

-

VCC

-

H7

VCC

-

L7

VCC

-

M9

VCC

-

H6

VCCIO7

VCCIO6

VCCIO5

VCCIO4

VCCIO3

VCCIO2

VCCIO1

7

6

5

4

3

2

1

J7

M7

K7

M8

R9

M12

M11

L12

K12

J12

H12

G12

G10

4-28

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

LA-MachXO2280 Logic Signal Connections: 324 ftBGA (Cont.)

LAMXO2280

Ball Number

Ball Function

VCCIO0

Bank

Dual Function

Differential

G8

0

G7

VCCIO0

* Supports true LVDS outputs.

** Primary clock inputs are single-ended.

4-29

Pinout Information

LA-MachXO Automotive Family Data Sheet

Lattice Semiconductor

Thermal Management

Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal

characteristics of a system, Lattice speciﬁes a maximum allowable junction temperature in all device data sheets.

Designers must complete a thermal analysis of their speciﬁc design to ensure that the device and package do not

exceed the junction temperature limits. Refer to the Thermal Management document to ﬁnd the device/package

speciﬁc thermal values.

For Further Information

For further information regarding Thermal Management, refer to the following located on the Lattice website at

www.latticesemi.com.

• Thermal Management document

• Technical Note TN1090 - Power Estimation and Management for MachXO Devices

• Power Calculator tool included with Lattice’s ispLEVER design tool, or as a standalone download from

www.latticesemi.com/software

4-30

LA-MachXO Automotive Family Data Sheet

Ordering Information

April 2006

Data Sheet DS1003

Part Number Description

LAMXO XXXX X – X XXXXXX X

Device Family

LA-MachXO Automotive Crossover PLD

Grade

E = Automotive

Logic Capacity

256 LUTs = 256

640 LUTs = 640

1200 LUTs = 1200

2280 LUTs = 2280

Package

TN100 = 100-pin Lead-Free TQFP

TN144 = 144-pin Lead-Free TQFP

FTN256 = 256-ball Lead-Free ftBGA

FTN324 = 324-ball Lead-Free ftBGA

Supply Voltage

C = 1.8V/2.5V/3.3V

E = 1.2V

Speed

3 = -3 Speed Grade

Note: Parts dual marked as described.

Ordering Information

Part Number

LUTs

Supply Voltage

1.8V/2.5V/3.3V

1.2V

I/Os

78

Grade

-3

Package

Pins

100

144

256

100

144

256

100

144

256

100

144

256

324

Temp.

AUTO

LAMXO256C-3TN100E

LAMXO640C-3TN100E

LAMXO640C-3TN144E

LAMXO640C-3FTN256E

LAMXO256E-3TN100E

LAMXO640E-3TN100E

LAMXO640E-3TN144E

LAMXO640E-3FTN256E

LAMXO1200E-3TN100E

LAMXO1200E-3TN144E

LAMXO1200E-3FTN256E

LAMXO2280E-3TN100E

LAMXO2280E-3TN144E

LAMXO2280E-3FTN256E

LAMXO2280E-3FTN324E

256

Lead-Free TQFP

Lead-Free ftBGA

Lead-Free TQFP

Lead-Free ftBGA

Lead-Free TQFP

Lead-Free ftBGA

Lead-Free TQFP

Lead-Free ftBGA

640

74

-3

640

113

159

78

-3

640

-3

256

-3

640

1.2V

74

-3

640

1.2V

113

159

73

-3

640

1.2V

-3

1200

2280

1.2V

-3

1.2V

113

211

73

-3

1.2V

-3

1.2V

-3

1.2V

113

211

271

-3

1.2V

-3

1.2V

-3

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

5-1

DS1003 Ordering Information_01.0

LA-MachXO Automotive Family Data Sheet

Supplemental Information

November 2007

Data Sheet DS1003

For Further Information

A variety of technical notes for the LA-MachXO family are available on the Lattice web site at www.latticesemi.com.

• MachXO sysIO Usage Guide (TN1091)

• MachXO sysCLOCK PLL Design and Usage Guide (TN1089)

• MachXO Memory Usage Guide (TN1092)

• Power Estimation and Management for MachXO Devices (TN1090)

• MachXO JTAG Programming and Conﬁguration User’s Guide (TN1086)

• Minimizing System Interruption During Conﬁguration Using TransFR Technology (TN1087)

• MachXO Density Migration (TN1097)

• IEEE 1149.1 Boundary Scan Testability in Lattice Devices

For further information on interface standards refer to the following web sites:

• JEDEC Standards (LVTTL, LVCMOS): www.jedec.org

• PCI: www.pcisig.com

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

6-1

DS1003 Further Information_01.1

LA-MachXO Automotive Family Data Sheet

Revision History

November 2007

Data Sheet DS1003

Revision History

Date

Version

Section

—

Change Summary

April 2006

May 2006

01.0

Initial release.

01.1

Pinout Information

Removed [LOC][0]_PLL_RST from Signal Descriptions table.

PCLK footnote added to appropriate pins in Logic Signal Connections

tables.

November 2006

01.2

DC and Switching

Characteristics

Corrections to MachXO “C” Sleep Mode Timing table - value for

t

(400ns) changed from max. to min. Value for t

WSLEEPN

WAWAKE

(100ns) changed from min. to max.

Added Flash Download Time table.

EBR Asynchronous Reset section added.

December 2006

01.3

Architecture

Pinout Information

Architecture

Power Supply and NC table: Pin/Ball orientation footnotes added.

Updated EBR Asynchronous Reset section.

February 2007

November 2007

01.4

01.5

DC and Switching

Characteristics

Updated sysIO Single-Ended DC Electrical Characteristics table.

Added JTAG Port Timing Waveforms diagram.

Added Thermal Management text section.

Updated title list.

Pinout Information

Supplemental

Information

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

7-1


型号：	LAMXO640LUTSC-3FTN256E
厂家：	LATTICE SEMICONDUCTOR
描述：	LA-MachXO Automotive Family Data Sheet LA-汽车的MachXO系列数据手册石英晶振
文件：	总77页 (文件大小：875K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LAMXO640LUTSC-3FTN256E [LATTICE]

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